mirror of https://github.com/ARMmbed/mbed-os.git
L1 ST CUBE V1.8.1
bcostm
parent
c8bd08f60e
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d8aa587782
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;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
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;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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;* File Name : startup_stm32l152xc.s
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;* Author : MCD Application Team
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;* Version : V2.2.0
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;* Date : 01-July-2016
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;* Version : 21-April-2017
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;* Date : V2.2.1
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;* Description : STM32L152XC Devices vector for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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@ -16,7 +16,7 @@
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* COPYRIGHT(c) 2016 STMicroelectronics
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;* COPYRIGHT(c) 2017 STMicroelectronics
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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@ -1,8 +1,8 @@
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;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
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;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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;* File Name : startup_stm32l152xc.s
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;* Author : MCD Application Team
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;* Version : V2.2.0
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;* Date : 01-July-2016
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;* Version : 21-April-2017
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;* Date : V2.2.1
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;* Description : STM32L152XC Devices vector for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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@ -16,7 +16,7 @@
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* COPYRIGHT(c) 2016 STMicroelectronics
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;* COPYRIGHT(c) 2017 STMicroelectronics
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file startup_stm32l152xc.s
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* @author MCD Application Team
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* @version V2.2.0
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* @date 01-July-2016
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* @brief STM32L152XC Devices vector table for
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* Atollic toolchain.
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* This module performs:
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@ -17,7 +15,7 @@
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -1,8 +1,8 @@
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;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
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;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
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;* File Name : startup_stm32l152xc.s
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;* Author : MCD Application Team
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;* Version : V2.2.0
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;* Date : 01-July-2016
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;* Version : 21-April-2017
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;* Date : V2.2.1
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;* Description : STM32L152XC Devices vector for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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@ -16,7 +16,7 @@
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32l152xc.h
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* @author MCD Application Team
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* @version V2.2.0
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* @date 01-July-2016
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32L1xx devices.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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@ -454,21 +452,27 @@ typedef struct
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typedef struct
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{
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__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
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__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
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__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
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__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
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__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
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__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
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__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
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__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
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uint32_t RESERVED1; /*!< Reserved, 0x18 */
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__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
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__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
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__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
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__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
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__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
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__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
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__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
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__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
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__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
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__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
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__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
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__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
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__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
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__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
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__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
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__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
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__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
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__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
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__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
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__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
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__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
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__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
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__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
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__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
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__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
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__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
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__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
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} RI_TypeDef;
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/**
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@ -3586,56 +3590,56 @@ typedef struct
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#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
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/****************** Bit definition for GPIO_AFRL register ********************/
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#define GPIO_AFRL_AFRL0_Pos (0U)
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#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
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#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
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#define GPIO_AFRL_AFRL1_Pos (4U)
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#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
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#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
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#define GPIO_AFRL_AFRL2_Pos (8U)
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#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
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#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
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#define GPIO_AFRL_AFRL3_Pos (12U)
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#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
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#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
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#define GPIO_AFRL_AFRL4_Pos (16U)
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#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
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#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
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#define GPIO_AFRL_AFRL5_Pos (20U)
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#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
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#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
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#define GPIO_AFRL_AFRL6_Pos (24U)
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#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
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#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
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#define GPIO_AFRL_AFRL7_Pos (28U)
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#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
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#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
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#define GPIO_AFRL_AFSEL0_Pos (0U)
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#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
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#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
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#define GPIO_AFRL_AFSEL1_Pos (4U)
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#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
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#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
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#define GPIO_AFRL_AFSEL2_Pos (8U)
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#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
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#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
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#define GPIO_AFRL_AFSEL3_Pos (12U)
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#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
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#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
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#define GPIO_AFRL_AFSEL4_Pos (16U)
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#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
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#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
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#define GPIO_AFRL_AFSEL5_Pos (20U)
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#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
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#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
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#define GPIO_AFRL_AFSEL6_Pos (24U)
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#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
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#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
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#define GPIO_AFRL_AFSEL7_Pos (28U)
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#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
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#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
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/****************** Bit definition for GPIO_AFRH register ********************/
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#define GPIO_AFRH_AFRH0_Pos (0U)
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#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
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#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
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#define GPIO_AFRH_AFRH1_Pos (4U)
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#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
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#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
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#define GPIO_AFRH_AFRH2_Pos (8U)
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#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
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#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
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#define GPIO_AFRH_AFRH3_Pos (12U)
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#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
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#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
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#define GPIO_AFRH_AFRH4_Pos (16U)
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#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
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#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
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#define GPIO_AFRH_AFRH5_Pos (20U)
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#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
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#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
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#define GPIO_AFRH_AFRH6_Pos (24U)
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#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
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#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
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#define GPIO_AFRH_AFRH7_Pos (28U)
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#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
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#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
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#define GPIO_AFRH_AFSEL8_Pos (0U)
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#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
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#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
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#define GPIO_AFRH_AFSEL9_Pos (4U)
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#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
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#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
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#define GPIO_AFRH_AFSEL10_Pos (8U)
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#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
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#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
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#define GPIO_AFRH_AFSEL11_Pos (12U)
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#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
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#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
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#define GPIO_AFRH_AFSEL12_Pos (16U)
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#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
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#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
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#define GPIO_AFRH_AFSEL13_Pos (20U)
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#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
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#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
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#define GPIO_AFRH_AFSEL14_Pos (24U)
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#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
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#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
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#define GPIO_AFRH_AFSEL15_Pos (28U)
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#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
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#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
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/****************** Bit definition for GPIO_BRR register *********************/
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#define GPIO_BRR_BR_0 (0x00000001U)
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#define RTC_CR_COSEL_Pos (19U)
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#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
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#define RTC_CR_COSEL RTC_CR_COSEL_Msk
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#define RTC_CR_BCK_Pos (18U)
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#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
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#define RTC_CR_BCK RTC_CR_BCK_Msk
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#define RTC_CR_BKP_Pos (18U)
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#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
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#define RTC_CR_BKP RTC_CR_BKP_Msk
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#define RTC_CR_SUB1H_Pos (17U)
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#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
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#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
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#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
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#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
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/* Legacy defines */
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#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
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#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
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#define RTC_CR_BCK RTC_CR_BKP
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/******************** Bits definition for RTC_ISR register ******************/
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#define RTC_ISR_RECALPF_Pos (16U)
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#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
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#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
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#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
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#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
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#define RI_HYSCR3_PF_Pos (16U)
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#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */
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#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */
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#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */
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#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */
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#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */
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#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */
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#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */
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#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */
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#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */
|
||||
#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */
|
||||
#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */
|
||||
#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */
|
||||
#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */
|
||||
#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */
|
||||
#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */
|
||||
#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
|
||||
#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
|
||||
#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
|
||||
/******************** Bit definition for RI_HYSCR4 register ********************/
|
||||
#define RI_HYSCR4_PG_Pos (0U)
|
||||
#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */
|
||||
#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR1 register ********************/
|
||||
#define RI_ASMR1_PA_Pos (0U)
|
||||
|
|
@ -6454,6 +6502,132 @@ typedef struct
|
|||
#define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR4 register ********************/
|
||||
#define RI_ASMR4_PF_Pos (0U)
|
||||
#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR4 register ********************/
|
||||
#define RI_CMR4_PF_Pos (0U)
|
||||
#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR4 register ********************/
|
||||
#define RI_CICR4_PF_Pos (0U)
|
||||
#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR5 register ********************/
|
||||
#define RI_ASMR5_PG_Pos (0U)
|
||||
#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR5 register ********************/
|
||||
#define RI_CMR5_PG_Pos (0U)
|
||||
#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR5 register ********************/
|
||||
#define RI_CICR5_PG_Pos (0U)
|
||||
#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Timers (TIM) */
|
||||
|
|
@ -8631,24 +8805,58 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for SCB_CFSR register *******************/
|
||||
/*!< MFSR */
|
||||
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
|
||||
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
|
||||
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
|
||||
/*!< BFSR */
|
||||
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
|
||||
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
|
||||
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
|
||||
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
|
||||
/*!< UFSR */
|
||||
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
|
||||
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
|
||||
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
|
||||
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
|
||||
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
||||
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
||||
|
||||
/******************* Bit definition for SCB_HFSR register *******************/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -18,7 +16,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -122,7 +120,7 @@
|
|||
*/
|
||||
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l151xc.s
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief STM32L151XC Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -17,7 +15,7 @@
|
|||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L152XC Devices vector for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l151xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L1xx devices.
|
||||
|
|
@ -16,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -439,21 +437,27 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
|
||||
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
|
||||
__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
|
||||
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
|
||||
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
|
||||
__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
|
||||
} RI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -3569,56 +3573,56 @@ typedef struct
|
|||
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRL register ********************/
|
||||
#define GPIO_AFRL_AFRL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
|
||||
#define GPIO_AFRL_AFRL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
|
||||
#define GPIO_AFRL_AFRL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
|
||||
#define GPIO_AFRL_AFRL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
|
||||
#define GPIO_AFRL_AFRL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
|
||||
#define GPIO_AFRL_AFRL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
|
||||
#define GPIO_AFRL_AFRL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
|
||||
#define GPIO_AFRL_AFRL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
|
||||
#define GPIO_AFRL_AFSEL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
|
||||
#define GPIO_AFRL_AFSEL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
|
||||
#define GPIO_AFRL_AFSEL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
|
||||
#define GPIO_AFRL_AFSEL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
|
||||
#define GPIO_AFRL_AFSEL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
|
||||
#define GPIO_AFRL_AFSEL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
|
||||
#define GPIO_AFRL_AFSEL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
|
||||
#define GPIO_AFRL_AFSEL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRH register ********************/
|
||||
#define GPIO_AFRH_AFRH0_Pos (0U)
|
||||
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
|
||||
#define GPIO_AFRH_AFRH1_Pos (4U)
|
||||
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
|
||||
#define GPIO_AFRH_AFRH2_Pos (8U)
|
||||
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
|
||||
#define GPIO_AFRH_AFRH3_Pos (12U)
|
||||
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
|
||||
#define GPIO_AFRH_AFRH4_Pos (16U)
|
||||
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
|
||||
#define GPIO_AFRH_AFRH5_Pos (20U)
|
||||
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
|
||||
#define GPIO_AFRH_AFRH6_Pos (24U)
|
||||
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
|
||||
#define GPIO_AFRH_AFRH7_Pos (28U)
|
||||
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
|
||||
#define GPIO_AFRH_AFSEL8_Pos (0U)
|
||||
#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
|
||||
#define GPIO_AFRH_AFSEL9_Pos (4U)
|
||||
#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
|
||||
#define GPIO_AFRH_AFSEL10_Pos (8U)
|
||||
#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
|
||||
#define GPIO_AFRH_AFSEL11_Pos (12U)
|
||||
#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
|
||||
#define GPIO_AFRH_AFSEL12_Pos (16U)
|
||||
#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
|
||||
#define GPIO_AFRH_AFSEL13_Pos (20U)
|
||||
#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
|
||||
#define GPIO_AFRH_AFSEL14_Pos (24U)
|
||||
#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
|
||||
#define GPIO_AFRH_AFSEL15_Pos (28U)
|
||||
#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_BRR register *********************/
|
||||
#define GPIO_BRR_BR_0 (0x00000001U)
|
||||
|
|
@ -4830,9 +4834,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -4885,6 +4889,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -6114,6 +6123,45 @@ typedef struct
|
|||
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
|
||||
#define RI_HYSCR3_PF_Pos (16U)
|
||||
#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */
|
||||
#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */
|
||||
#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */
|
||||
#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */
|
||||
#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */
|
||||
#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */
|
||||
#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */
|
||||
#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */
|
||||
#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */
|
||||
#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */
|
||||
#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */
|
||||
#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */
|
||||
#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */
|
||||
#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */
|
||||
#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */
|
||||
#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
|
||||
#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
|
||||
#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
|
||||
/******************** Bit definition for RI_HYSCR4 register ********************/
|
||||
#define RI_HYSCR4_PG_Pos (0U)
|
||||
#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */
|
||||
#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR1 register ********************/
|
||||
#define RI_ASMR1_PA_Pos (0U)
|
||||
|
|
@ -6304,6 +6352,132 @@ typedef struct
|
|||
#define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR4 register ********************/
|
||||
#define RI_ASMR4_PF_Pos (0U)
|
||||
#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR4 register ********************/
|
||||
#define RI_CMR4_PF_Pos (0U)
|
||||
#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR4 register ********************/
|
||||
#define RI_CICR4_PF_Pos (0U)
|
||||
#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR5 register ********************/
|
||||
#define RI_ASMR5_PG_Pos (0U)
|
||||
#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR5 register ********************/
|
||||
#define RI_CMR5_PG_Pos (0U)
|
||||
#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR5 register ********************/
|
||||
#define RI_CICR5_PG_Pos (0U)
|
||||
#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Timers (TIM) */
|
||||
|
|
@ -8481,24 +8655,58 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for SCB_CFSR register *******************/
|
||||
/*!< MFSR */
|
||||
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
|
||||
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
|
||||
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
|
||||
/*!< BFSR */
|
||||
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
|
||||
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
|
||||
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
|
||||
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
|
||||
/*!< UFSR */
|
||||
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
|
||||
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
|
||||
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
|
||||
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
|
||||
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
||||
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
||||
|
||||
/******************* Bit definition for SCB_HFSR register *******************/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -18,7 +16,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -121,7 +119,7 @@
|
|||
*/
|
||||
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L152XE Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L152XE Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l152xe.s
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief STM32L152XE Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -17,7 +15,7 @@
|
|||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xe.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L152XE Devices vector for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l152xe.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L1xx devices.
|
||||
|
|
@ -16,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -463,27 +461,27 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
|
||||
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
|
||||
__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
|
||||
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
|
||||
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
|
||||
__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
|
||||
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
|
||||
__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
|
||||
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
|
||||
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
|
||||
__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
|
||||
} RI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -3656,56 +3654,56 @@ typedef struct
|
|||
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRL register ********************/
|
||||
#define GPIO_AFRL_AFRL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
|
||||
#define GPIO_AFRL_AFRL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
|
||||
#define GPIO_AFRL_AFRL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
|
||||
#define GPIO_AFRL_AFRL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
|
||||
#define GPIO_AFRL_AFRL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
|
||||
#define GPIO_AFRL_AFRL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
|
||||
#define GPIO_AFRL_AFRL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
|
||||
#define GPIO_AFRL_AFRL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
|
||||
#define GPIO_AFRL_AFSEL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
|
||||
#define GPIO_AFRL_AFSEL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
|
||||
#define GPIO_AFRL_AFSEL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
|
||||
#define GPIO_AFRL_AFSEL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
|
||||
#define GPIO_AFRL_AFSEL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
|
||||
#define GPIO_AFRL_AFSEL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
|
||||
#define GPIO_AFRL_AFSEL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
|
||||
#define GPIO_AFRL_AFSEL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRH register ********************/
|
||||
#define GPIO_AFRH_AFRH0_Pos (0U)
|
||||
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
|
||||
#define GPIO_AFRH_AFRH1_Pos (4U)
|
||||
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
|
||||
#define GPIO_AFRH_AFRH2_Pos (8U)
|
||||
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
|
||||
#define GPIO_AFRH_AFRH3_Pos (12U)
|
||||
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
|
||||
#define GPIO_AFRH_AFRH4_Pos (16U)
|
||||
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
|
||||
#define GPIO_AFRH_AFRH5_Pos (20U)
|
||||
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
|
||||
#define GPIO_AFRH_AFRH6_Pos (24U)
|
||||
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
|
||||
#define GPIO_AFRH_AFRH7_Pos (28U)
|
||||
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
|
||||
#define GPIO_AFRH_AFSEL8_Pos (0U)
|
||||
#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
|
||||
#define GPIO_AFRH_AFSEL9_Pos (4U)
|
||||
#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
|
||||
#define GPIO_AFRH_AFSEL10_Pos (8U)
|
||||
#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
|
||||
#define GPIO_AFRH_AFSEL11_Pos (12U)
|
||||
#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
|
||||
#define GPIO_AFRH_AFSEL12_Pos (16U)
|
||||
#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
|
||||
#define GPIO_AFRH_AFSEL13_Pos (20U)
|
||||
#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
|
||||
#define GPIO_AFRH_AFSEL14_Pos (24U)
|
||||
#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
|
||||
#define GPIO_AFRH_AFSEL15_Pos (28U)
|
||||
#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_BRR register *********************/
|
||||
#define GPIO_BRR_BR_0 (0x00000001U)
|
||||
|
|
@ -5078,9 +5076,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -5133,6 +5131,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -6419,7 +6422,6 @@ typedef struct
|
|||
#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
|
||||
#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
|
||||
#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
|
||||
|
||||
/******************** Bit definition for RI_HYSCR4 register ********************/
|
||||
#define RI_HYSCR4_PG_Pos (0U)
|
||||
#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
|
||||
|
|
@ -8933,24 +8935,58 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for SCB_CFSR register *******************/
|
||||
/*!< MFSR */
|
||||
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
|
||||
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
|
||||
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
|
||||
/*!< BFSR */
|
||||
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
|
||||
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
|
||||
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
|
||||
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
|
||||
/*!< UFSR */
|
||||
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
|
||||
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
|
||||
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
|
||||
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
|
||||
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
||||
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
||||
|
||||
/******************* Bit definition for SCB_HFSR register *******************/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -18,7 +16,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -122,7 +120,7 @@
|
|||
*/
|
||||
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l151xc.s
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief STM32L151XC Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -17,7 +15,7 @@
|
|||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l151xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L1xx devices.
|
||||
|
|
@ -16,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -439,21 +437,27 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
|
||||
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
|
||||
__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
|
||||
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
|
||||
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
|
||||
__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
|
||||
} RI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -3569,56 +3573,56 @@ typedef struct
|
|||
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRL register ********************/
|
||||
#define GPIO_AFRL_AFRL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
|
||||
#define GPIO_AFRL_AFRL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
|
||||
#define GPIO_AFRL_AFRL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
|
||||
#define GPIO_AFRL_AFRL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
|
||||
#define GPIO_AFRL_AFRL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
|
||||
#define GPIO_AFRL_AFRL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
|
||||
#define GPIO_AFRL_AFRL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
|
||||
#define GPIO_AFRL_AFRL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
|
||||
#define GPIO_AFRL_AFSEL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
|
||||
#define GPIO_AFRL_AFSEL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
|
||||
#define GPIO_AFRL_AFSEL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
|
||||
#define GPIO_AFRL_AFSEL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
|
||||
#define GPIO_AFRL_AFSEL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
|
||||
#define GPIO_AFRL_AFSEL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
|
||||
#define GPIO_AFRL_AFSEL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
|
||||
#define GPIO_AFRL_AFSEL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRH register ********************/
|
||||
#define GPIO_AFRH_AFRH0_Pos (0U)
|
||||
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
|
||||
#define GPIO_AFRH_AFRH1_Pos (4U)
|
||||
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
|
||||
#define GPIO_AFRH_AFRH2_Pos (8U)
|
||||
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
|
||||
#define GPIO_AFRH_AFRH3_Pos (12U)
|
||||
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
|
||||
#define GPIO_AFRH_AFRH4_Pos (16U)
|
||||
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
|
||||
#define GPIO_AFRH_AFRH5_Pos (20U)
|
||||
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
|
||||
#define GPIO_AFRH_AFRH6_Pos (24U)
|
||||
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
|
||||
#define GPIO_AFRH_AFRH7_Pos (28U)
|
||||
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
|
||||
#define GPIO_AFRH_AFSEL8_Pos (0U)
|
||||
#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
|
||||
#define GPIO_AFRH_AFSEL9_Pos (4U)
|
||||
#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
|
||||
#define GPIO_AFRH_AFSEL10_Pos (8U)
|
||||
#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
|
||||
#define GPIO_AFRH_AFSEL11_Pos (12U)
|
||||
#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
|
||||
#define GPIO_AFRH_AFSEL12_Pos (16U)
|
||||
#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
|
||||
#define GPIO_AFRH_AFSEL13_Pos (20U)
|
||||
#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
|
||||
#define GPIO_AFRH_AFSEL14_Pos (24U)
|
||||
#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
|
||||
#define GPIO_AFRH_AFSEL15_Pos (28U)
|
||||
#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_BRR register *********************/
|
||||
#define GPIO_BRR_BR_0 (0x00000001U)
|
||||
|
|
@ -4830,9 +4834,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -4885,6 +4889,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -6114,6 +6123,45 @@ typedef struct
|
|||
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
|
||||
#define RI_HYSCR3_PF_Pos (16U)
|
||||
#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */
|
||||
#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */
|
||||
#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */
|
||||
#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */
|
||||
#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */
|
||||
#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */
|
||||
#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */
|
||||
#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */
|
||||
#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */
|
||||
#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */
|
||||
#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */
|
||||
#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */
|
||||
#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */
|
||||
#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */
|
||||
#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */
|
||||
#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
|
||||
#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
|
||||
#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
|
||||
/******************** Bit definition for RI_HYSCR4 register ********************/
|
||||
#define RI_HYSCR4_PG_Pos (0U)
|
||||
#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */
|
||||
#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR1 register ********************/
|
||||
#define RI_ASMR1_PA_Pos (0U)
|
||||
|
|
@ -6304,6 +6352,132 @@ typedef struct
|
|||
#define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR4 register ********************/
|
||||
#define RI_ASMR4_PF_Pos (0U)
|
||||
#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR4 register ********************/
|
||||
#define RI_CMR4_PF_Pos (0U)
|
||||
#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR4 register ********************/
|
||||
#define RI_CICR4_PF_Pos (0U)
|
||||
#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR5 register ********************/
|
||||
#define RI_ASMR5_PG_Pos (0U)
|
||||
#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR5 register ********************/
|
||||
#define RI_CMR5_PG_Pos (0U)
|
||||
#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR5 register ********************/
|
||||
#define RI_CICR5_PG_Pos (0U)
|
||||
#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Timers (TIM) */
|
||||
|
|
@ -8481,24 +8655,58 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for SCB_CFSR register *******************/
|
||||
/*!< MFSR */
|
||||
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
|
||||
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
|
||||
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
|
||||
/*!< BFSR */
|
||||
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
|
||||
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
|
||||
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
|
||||
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
|
||||
/*!< UFSR */
|
||||
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
|
||||
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
|
||||
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
|
||||
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
|
||||
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
||||
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
||||
|
||||
/******************* Bit definition for SCB_HFSR register *******************/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -18,7 +16,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -134,7 +132,7 @@
|
|||
*/
|
||||
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l151xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* COPYRIGHT(c) 2016 STMicroelectronics
|
||||
;* COPYRIGHT(c) 2017 STMicroelectronics
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file startup_stm32l151xc.s
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief STM32L151XC Devices vector table for
|
||||
* Atollic toolchain.
|
||||
* This module performs:
|
||||
|
|
@ -17,7 +15,7 @@
|
|||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -1,8 +1,8 @@
|
|||
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
|
||||
;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
|
||||
;* File Name : startup_stm32l152xc.s
|
||||
;* Author : MCD Application Team
|
||||
;* Version : V2.2.0
|
||||
;* Date : 01-July-2016
|
||||
;* Version : 21-April-2017
|
||||
;* Date : V2.2.1
|
||||
;* Description : STM32L152XC Devices vector for EWARM toolchain.
|
||||
;* This module performs:
|
||||
;* - Set the initial SP
|
||||
|
|
@ -16,7 +16,7 @@
|
|||
;* priority is Privileged, and the Stack is set to Main.
|
||||
;********************************************************************************
|
||||
;*
|
||||
;* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
;* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
;*
|
||||
;* Redistribution and use in source and binary forms, with or without modification,
|
||||
;* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l151xc.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for STM32L1xx devices.
|
||||
|
|
@ -16,7 +14,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -439,21 +437,27 @@ typedef struct
|
|||
typedef struct
|
||||
{
|
||||
__IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
|
||||
__IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
|
||||
__IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
uint32_t RESERVED1; /*!< Reserved, 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
|
||||
__IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
|
||||
__IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
|
||||
__IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
|
||||
__IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
|
||||
__IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
|
||||
__IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
|
||||
__IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
|
||||
__IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
|
||||
__IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
|
||||
__IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
|
||||
__IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
|
||||
__IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
|
||||
__IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
|
||||
__IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
|
||||
__IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
|
||||
__IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
|
||||
__IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
|
||||
} RI_TypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -3569,56 +3573,56 @@ typedef struct
|
|||
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRL register ********************/
|
||||
#define GPIO_AFRL_AFRL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
|
||||
#define GPIO_AFRL_AFRL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
|
||||
#define GPIO_AFRL_AFRL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
|
||||
#define GPIO_AFRL_AFRL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
|
||||
#define GPIO_AFRL_AFRL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
|
||||
#define GPIO_AFRL_AFRL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
|
||||
#define GPIO_AFRL_AFRL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
|
||||
#define GPIO_AFRL_AFRL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
|
||||
#define GPIO_AFRL_AFSEL0_Pos (0U)
|
||||
#define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
|
||||
#define GPIO_AFRL_AFSEL1_Pos (4U)
|
||||
#define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
|
||||
#define GPIO_AFRL_AFSEL2_Pos (8U)
|
||||
#define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
|
||||
#define GPIO_AFRL_AFSEL3_Pos (12U)
|
||||
#define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
|
||||
#define GPIO_AFRL_AFSEL4_Pos (16U)
|
||||
#define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
|
||||
#define GPIO_AFRL_AFSEL5_Pos (20U)
|
||||
#define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
|
||||
#define GPIO_AFRL_AFSEL6_Pos (24U)
|
||||
#define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
|
||||
#define GPIO_AFRL_AFSEL7_Pos (28U)
|
||||
#define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_AFRH register ********************/
|
||||
#define GPIO_AFRH_AFRH0_Pos (0U)
|
||||
#define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
|
||||
#define GPIO_AFRH_AFRH1_Pos (4U)
|
||||
#define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
|
||||
#define GPIO_AFRH_AFRH2_Pos (8U)
|
||||
#define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
|
||||
#define GPIO_AFRH_AFRH3_Pos (12U)
|
||||
#define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
|
||||
#define GPIO_AFRH_AFRH4_Pos (16U)
|
||||
#define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
|
||||
#define GPIO_AFRH_AFRH5_Pos (20U)
|
||||
#define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
|
||||
#define GPIO_AFRH_AFRH6_Pos (24U)
|
||||
#define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
|
||||
#define GPIO_AFRH_AFRH7_Pos (28U)
|
||||
#define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
|
||||
#define GPIO_AFRH_AFSEL8_Pos (0U)
|
||||
#define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
|
||||
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
|
||||
#define GPIO_AFRH_AFSEL9_Pos (4U)
|
||||
#define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
|
||||
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
|
||||
#define GPIO_AFRH_AFSEL10_Pos (8U)
|
||||
#define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
|
||||
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
|
||||
#define GPIO_AFRH_AFSEL11_Pos (12U)
|
||||
#define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
|
||||
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
|
||||
#define GPIO_AFRH_AFSEL12_Pos (16U)
|
||||
#define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
|
||||
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
|
||||
#define GPIO_AFRH_AFSEL13_Pos (20U)
|
||||
#define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
|
||||
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
|
||||
#define GPIO_AFRH_AFSEL14_Pos (24U)
|
||||
#define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
|
||||
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
|
||||
#define GPIO_AFRH_AFSEL15_Pos (28U)
|
||||
#define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
|
||||
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
|
||||
|
||||
/****************** Bit definition for GPIO_BRR register *********************/
|
||||
#define GPIO_BRR_BR_0 (0x00000001U)
|
||||
|
|
@ -4830,9 +4834,9 @@ typedef struct
|
|||
#define RTC_CR_COSEL_Pos (19U)
|
||||
#define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
|
||||
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
|
||||
#define RTC_CR_BCK_Pos (18U)
|
||||
#define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BCK RTC_CR_BCK_Msk
|
||||
#define RTC_CR_BKP_Pos (18U)
|
||||
#define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
|
||||
#define RTC_CR_BKP RTC_CR_BKP_Msk
|
||||
#define RTC_CR_SUB1H_Pos (17U)
|
||||
#define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
|
||||
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
|
||||
|
|
@ -4885,6 +4889,11 @@ typedef struct
|
|||
#define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
|
||||
#define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
|
||||
|
||||
/* Legacy defines */
|
||||
#define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
|
||||
#define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
|
||||
#define RTC_CR_BCK RTC_CR_BKP
|
||||
|
||||
/******************** Bits definition for RTC_ISR register ******************/
|
||||
#define RTC_ISR_RECALPF_Pos (16U)
|
||||
#define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
|
||||
|
|
@ -6114,6 +6123,45 @@ typedef struct
|
|||
#define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
|
||||
#define RI_HYSCR3_PF_Pos (16U)
|
||||
#define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */
|
||||
#define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */
|
||||
#define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */
|
||||
#define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */
|
||||
#define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */
|
||||
#define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */
|
||||
#define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */
|
||||
#define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */
|
||||
#define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */
|
||||
#define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */
|
||||
#define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */
|
||||
#define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */
|
||||
#define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */
|
||||
#define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */
|
||||
#define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */
|
||||
#define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
|
||||
#define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
|
||||
#define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
|
||||
/******************** Bit definition for RI_HYSCR4 register ********************/
|
||||
#define RI_HYSCR4_PG_Pos (0U)
|
||||
#define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */
|
||||
#define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR1 register ********************/
|
||||
#define RI_ASMR1_PA_Pos (0U)
|
||||
|
|
@ -6304,6 +6352,132 @@ typedef struct
|
|||
#define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR4 register ********************/
|
||||
#define RI_ASMR4_PF_Pos (0U)
|
||||
#define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR4 register ********************/
|
||||
#define RI_CMR4_PF_Pos (0U)
|
||||
#define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR4 register ********************/
|
||||
#define RI_CICR4_PF_Pos (0U)
|
||||
#define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */
|
||||
#define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_ASMR5 register ********************/
|
||||
#define RI_ASMR5_PG_Pos (0U)
|
||||
#define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CMR5 register ********************/
|
||||
#define RI_CMR5_PG_Pos (0U)
|
||||
#define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************** Bit definition for RI_CICR5 register ********************/
|
||||
#define RI_CICR5_PG_Pos (0U)
|
||||
#define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */
|
||||
#define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */
|
||||
#define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */
|
||||
#define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */
|
||||
#define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */
|
||||
#define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */
|
||||
#define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */
|
||||
#define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */
|
||||
#define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */
|
||||
#define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */
|
||||
#define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */
|
||||
#define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */
|
||||
#define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */
|
||||
#define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */
|
||||
#define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */
|
||||
#define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */
|
||||
#define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */
|
||||
#define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* Timers (TIM) */
|
||||
|
|
@ -8481,24 +8655,58 @@ typedef struct
|
|||
|
||||
/******************* Bit definition for SCB_CFSR register *******************/
|
||||
/*!< MFSR */
|
||||
#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
|
||||
#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
|
||||
#define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
|
||||
#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
|
||||
#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
|
||||
#define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
|
||||
#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
|
||||
#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
|
||||
#define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
|
||||
#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
|
||||
#define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
|
||||
#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
|
||||
#define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
|
||||
/*!< BFSR */
|
||||
#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
|
||||
#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
|
||||
#define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
|
||||
#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
|
||||
#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
|
||||
#define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
|
||||
#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
|
||||
#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
|
||||
#define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
|
||||
#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
|
||||
#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
|
||||
#define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
|
||||
#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
|
||||
#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
|
||||
#define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
|
||||
#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
|
||||
#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
|
||||
#define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
|
||||
/*!< UFSR */
|
||||
#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
|
||||
#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
|
||||
#define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
|
||||
#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
|
||||
#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
|
||||
#define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
|
||||
#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
|
||||
#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
|
||||
#define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
|
||||
#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
|
||||
#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
|
||||
#define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
|
||||
#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
|
||||
#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
|
||||
#define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
|
||||
#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
|
||||
#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
|
||||
#define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
|
||||
|
||||
/******************* Bit definition for SCB_HFSR register *******************/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS STM32L1xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
|
|
@ -18,7 +16,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -121,7 +119,7 @@
|
|||
*/
|
||||
#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file system_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@
|
|||
******************************************************************************
|
||||
* @file stm32_hal_legacy.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains aliases definition for the STM32Cube HAL constants
|
||||
* macros and functions maintained for legacy purpose.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -138,6 +136,9 @@
|
|||
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
|
||||
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
|
||||
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
|
||||
#if defined(STM32L0)
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#endif
|
||||
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
|
||||
|
|
@ -240,9 +241,9 @@
|
|||
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
|
||||
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
|
||||
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
|
||||
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
|
||||
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
|
||||
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
|
||||
#define DAC_WAVE_NONE 0x00000000U
|
||||
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
|
||||
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
|
||||
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
|
||||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
|
@ -264,7 +265,6 @@
|
|||
#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
|
||||
#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
|
||||
#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
|
||||
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
|
||||
#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
|
||||
#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
|
||||
#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
|
||||
|
|
@ -355,6 +355,7 @@
|
|||
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
|
||||
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
|
||||
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -380,7 +381,7 @@
|
|||
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32L4) || defined(STM32F7)
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
|
||||
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
|
||||
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
|
||||
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
|
||||
|
|
@ -455,6 +456,78 @@
|
|||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
|
||||
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
|
||||
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
|
||||
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
|
||||
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
|
||||
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
|
||||
|
||||
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
|
||||
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
|
||||
|
||||
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
|
||||
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
|
||||
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
|
||||
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
|
||||
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
|
||||
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
|
||||
|
||||
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
|
||||
#endif /* STM32H7 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -668,7 +741,6 @@
|
|||
#define FORMAT_BCD RTC_FORMAT_BCD
|
||||
|
||||
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
|
||||
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
|
||||
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
|
||||
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
|
|
@ -676,9 +748,6 @@
|
|||
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
|
||||
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
|
||||
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
|
||||
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
|
||||
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
|
||||
|
||||
|
|
@ -852,6 +921,8 @@
|
|||
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
|
||||
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
|
||||
|
||||
#define __DIV_LPUART UART_DIV_LPUART
|
||||
|
||||
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
|
||||
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
|
||||
|
||||
|
|
@ -913,48 +984,48 @@
|
|||
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
|
||||
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
|
||||
|
||||
#define ETH_MMCCR ((uint32_t)0x00000100U)
|
||||
#define ETH_MMCRIR ((uint32_t)0x00000104U)
|
||||
#define ETH_MMCTIR ((uint32_t)0x00000108U)
|
||||
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
|
||||
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
|
||||
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
|
||||
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
|
||||
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
|
||||
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
|
||||
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
|
||||
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
|
||||
#define ETH_MMCCR 0x00000100U
|
||||
#define ETH_MMCRIR 0x00000104U
|
||||
#define ETH_MMCTIR 0x00000108U
|
||||
#define ETH_MMCRIMR 0x0000010CU
|
||||
#define ETH_MMCTIMR 0x00000110U
|
||||
#define ETH_MMCTGFSCCR 0x0000014CU
|
||||
#define ETH_MMCTGFMSCCR 0x00000150U
|
||||
#define ETH_MMCTGFCR 0x00000168U
|
||||
#define ETH_MMCRFCECR 0x00000194U
|
||||
#define ETH_MMCRFAECR 0x00000198U
|
||||
#define ETH_MMCRGUFCR 0x000001C4U
|
||||
|
||||
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -976,7 +1047,7 @@
|
|||
* @}
|
||||
*/
|
||||
|
||||
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
||||
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
|
||||
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
|
|
@ -1001,7 +1072,7 @@
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* STM32L4xx || STM32F7*/
|
||||
#endif /* STM32L4 || STM32F7*/
|
||||
|
||||
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
|
||||
* @{
|
||||
|
|
@ -1186,6 +1257,9 @@
|
|||
* @{
|
||||
*/
|
||||
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
|
||||
#define HAL_LTDC_Relaod HAL_LTDC_Reload
|
||||
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
|
||||
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -1227,6 +1301,7 @@
|
|||
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
|
||||
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
|
||||
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
|
||||
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
|
||||
|
||||
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
|
||||
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
|
||||
|
|
@ -1308,7 +1383,6 @@
|
|||
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
|
||||
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
|
||||
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
|
||||
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
|
||||
#define __HAL_ADC_JSQR ADC_JSQR
|
||||
|
||||
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
|
||||
|
|
@ -1621,7 +1695,11 @@
|
|||
|
||||
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
|
||||
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
|
||||
#if defined(STM32F1)
|
||||
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
|
||||
#else
|
||||
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
|
||||
#endif /* STM32F1 */
|
||||
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
|
||||
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
|
||||
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
|
||||
|
|
@ -1781,20 +1859,20 @@
|
|||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
|
||||
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
|
||||
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
|
||||
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
|
||||
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
|
||||
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
|
||||
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
|
||||
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
|
||||
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
|
||||
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
|
||||
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
|
||||
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
|
||||
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
|
||||
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
|
||||
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
|
||||
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
|
||||
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
|
||||
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
|
||||
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
|
||||
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
|
||||
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
|
||||
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
|
||||
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
|
||||
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
|
||||
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
|
||||
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
|
||||
|
|
@ -1811,7 +1889,7 @@
|
|||
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
|
||||
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
|
||||
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
|
||||
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
|
||||
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
|
||||
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
|
||||
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
|
||||
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
|
||||
|
|
@ -2227,26 +2305,26 @@
|
|||
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
|
||||
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
|
||||
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
|
||||
#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
|
||||
#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
|
||||
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
|
||||
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
|
||||
#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
|
||||
#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
|
||||
#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
|
||||
#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
|
||||
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
|
||||
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
|
||||
#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
|
||||
#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
|
||||
#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
|
||||
#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
|
||||
#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
|
||||
#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
|
||||
#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
|
||||
#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
|
||||
#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
|
||||
#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
|
||||
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
|
||||
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
|
||||
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
|
||||
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
|
||||
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
|
||||
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
|
||||
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
|
||||
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
|
||||
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
|
||||
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
|
||||
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
|
||||
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
|
||||
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
|
||||
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
|
||||
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
|
||||
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
|
||||
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
|
||||
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
|
||||
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
|
||||
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
|
||||
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
|
||||
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
|
||||
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
|
||||
|
|
@ -2406,7 +2484,6 @@
|
|||
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
|
||||
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
|
||||
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
|
||||
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
|
||||
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
|
||||
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
|
||||
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
|
||||
|
|
@ -2439,8 +2516,6 @@
|
|||
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
|
||||
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
|
||||
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
|
||||
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
|
||||
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
|
||||
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
|
||||
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
|
||||
|
|
@ -2462,8 +2537,6 @@
|
|||
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
|
||||
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
|
||||
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
|
||||
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
|
||||
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
|
||||
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
|
||||
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
|
||||
|
|
@ -2635,6 +2708,30 @@
|
|||
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32H7)
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
|
||||
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
|
||||
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
|
||||
#endif
|
||||
|
||||
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
|
||||
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
|
||||
|
||||
|
|
@ -2648,10 +2745,22 @@
|
|||
|
||||
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
|
||||
|
||||
#if defined(STM32L0)
|
||||
#define RCC_IT_LSECSS RCC_IT_CSSLSE
|
||||
#define RCC_IT_CSS RCC_IT_CSSHSE
|
||||
#endif
|
||||
#define RCC_IT_CSSLSE RCC_IT_LSECSS
|
||||
#define RCC_IT_CSSHSE RCC_IT_CSS
|
||||
|
||||
#define RCC_PLLMUL_3 RCC_PLL_MUL3
|
||||
#define RCC_PLLMUL_4 RCC_PLL_MUL4
|
||||
#define RCC_PLLMUL_6 RCC_PLL_MUL6
|
||||
#define RCC_PLLMUL_8 RCC_PLL_MUL8
|
||||
#define RCC_PLLMUL_12 RCC_PLL_MUL12
|
||||
#define RCC_PLLMUL_16 RCC_PLL_MUL16
|
||||
#define RCC_PLLMUL_24 RCC_PLL_MUL24
|
||||
#define RCC_PLLMUL_32 RCC_PLL_MUL32
|
||||
#define RCC_PLLMUL_48 RCC_PLL_MUL48
|
||||
|
||||
#define RCC_PLLDIV_2 RCC_PLL_DIV2
|
||||
#define RCC_PLLDIV_3 RCC_PLL_DIV3
|
||||
#define RCC_PLLDIV_4 RCC_PLL_DIV4
|
||||
|
||||
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
|
||||
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
|
||||
|
|
@ -2676,7 +2785,10 @@
|
|||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32WB) || defined(STM32G0)
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
#endif
|
||||
|
||||
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
|
||||
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
|
||||
|
|
@ -2768,10 +2880,22 @@
|
|||
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
|
||||
#define DfsdmClockSelection Dfsdm1ClockSelection
|
||||
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
|
||||
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
|
||||
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
|
||||
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
|
||||
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
|
||||
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -2789,8 +2913,10 @@
|
|||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (STM32G0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
|
||||
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
|
||||
|
||||
|
|
@ -2851,7 +2977,7 @@
|
|||
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
|
||||
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
|
||||
|
||||
#if defined(STM32F4)
|
||||
#if defined(STM32F4) || defined(STM32F2)
|
||||
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
|
||||
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
|
||||
#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
|
||||
|
|
@ -2902,6 +3028,14 @@
|
|||
#define SDIO_IRQn SDMMC1_IRQn
|
||||
#define SDIO_IRQHandler SDMMC1_IRQHandler
|
||||
#endif
|
||||
|
||||
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
|
||||
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
|
||||
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
|
||||
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
|
||||
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -3090,6 +3224,7 @@
|
|||
* @{
|
||||
*/
|
||||
#define __HAL_LTDC_LAYER LTDC_LAYER
|
||||
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief HAL module driver.
|
||||
* This is the common part of the HAL initialization
|
||||
*
|
||||
|
|
@ -23,7 +21,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -75,15 +73,15 @@
|
|||
* @brief STM32L1xx HAL Driver version number
|
||||
*/
|
||||
#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L1xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||
#define __STM32L1xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
|
||||
|(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\
|
||||
|(__STM32L1xx_HAL_VERSION_RC))
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
#define IDCODE_DEVID_MASK (0x00000FFFU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains all the functions prototypes for the HAL
|
||||
* module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_adc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
|
|
@ -256,7 +254,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -309,18 +307,18 @@
|
|||
/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
|
||||
/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */
|
||||
/* Unit: ms */
|
||||
#define ADC_ENABLE_TIMEOUT ((uint32_t) 2)
|
||||
#define ADC_DISABLE_TIMEOUT ((uint32_t) 2)
|
||||
#define ADC_ENABLE_TIMEOUT (2U)
|
||||
#define ADC_DISABLE_TIMEOUT (2U)
|
||||
|
||||
/* Delay for ADC stabilization time. */
|
||||
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
|
||||
/* Unit: us */
|
||||
#define ADC_STAB_DELAY_US ((uint32_t) 3)
|
||||
#define ADC_STAB_DELAY_US (3U)
|
||||
|
||||
/* Delay for temperature sensor stabilization time. */
|
||||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
||||
/* Unit: us */
|
||||
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
|
||||
#define ADC_TEMPSENSOR_DELAY_US (10U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file containing functions prototypes of ADC HAL library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -201,36 +199,36 @@ typedef struct
|
|||
* @brief HAL ADC state machine: ADC states definition (bitfields)
|
||||
*/
|
||||
/* States of ADC global scope */
|
||||
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
|
||||
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
|
||||
#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
|
||||
#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
|
||||
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
|
||||
#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
|
||||
|
||||
/* States of ADC errors */
|
||||
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
|
||||
#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
|
||||
|
||||
/* States of ADC group regular */
|
||||
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
|
||||
#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
|
||||
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on STM32L1 device: End Of Sampling flag raised */
|
||||
#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
|
||||
#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
|
||||
#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32L1 device: End Of Sampling flag raised */
|
||||
|
||||
/* States of ADC group injected */
|
||||
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
|
||||
#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
|
||||
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
|
||||
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
|
||||
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
|
||||
#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
|
||||
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
|
||||
|
||||
/* States of ADC analog watchdogs */
|
||||
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
|
||||
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
|
||||
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
|
||||
#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
|
||||
#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
|
||||
#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
|
||||
|
||||
/* States of ADC multi-mode */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
|
||||
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -267,11 +265,11 @@ typedef struct
|
|||
/** @defgroup ADC_Error_Code ADC Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
|
||||
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
|
||||
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
|
||||
enable/disable, erroneous state */
|
||||
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
|
||||
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
|
||||
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
|
||||
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -279,7 +277,7 @@ typedef struct
|
|||
/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
|
||||
#define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
|
||||
#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
|
||||
#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
|
||||
/**
|
||||
|
|
@ -289,7 +287,7 @@ typedef struct
|
|||
/** @defgroup ADC_Resolution ADC Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */
|
||||
#define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
|
||||
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */
|
||||
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */
|
||||
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */
|
||||
|
|
@ -300,7 +298,7 @@ typedef struct
|
|||
/** @defgroup ADC_Data_align ADC Data_align
|
||||
* @{
|
||||
*/
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
|
||||
#define ADC_DATAALIGN_RIGHT (0x00000000U)
|
||||
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -309,7 +307,7 @@ typedef struct
|
|||
/** @defgroup ADC_Scan_mode ADC Scan mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
|
||||
#define ADC_SCAN_DISABLE (0x00000000U)
|
||||
#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -318,7 +316,7 @@ typedef struct
|
|||
/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
|
||||
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
|
||||
|
|
@ -345,7 +343,7 @@ typedef struct
|
|||
#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
|
||||
#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
|
||||
#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
|
||||
#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
|
||||
#define ADC_SOFTWARE_START (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -353,7 +351,7 @@ typedef struct
|
|||
/** @defgroup ADC_EOCSelection ADC EOCSelection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
|
||||
#define ADC_EOC_SEQ_CONV (0x00000000U)
|
||||
#define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -366,7 +364,7 @@ typedef struct
|
|||
/* feature limited to enable or disable settings: */
|
||||
/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
|
||||
|
||||
#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
|
||||
#define ADC_AUTOWAIT_DISABLE (0x00000000U)
|
||||
#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
|
||||
#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
|
||||
#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
|
||||
|
|
@ -382,7 +380,7 @@ typedef struct
|
|||
/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
|
||||
* @{
|
||||
*/
|
||||
#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
|
||||
#define ADC_AUTOPOWEROFF_DISABLE (0x00000000U)
|
||||
#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */
|
||||
#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
|
||||
#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
|
||||
|
|
@ -395,13 +393,13 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
|
||||
#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
|
||||
#define ADC_CHANNELS_BANK_A (0x00000000U)
|
||||
#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
|
||||
|
||||
#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
|
||||
((BANK) == ADC_CHANNELS_BANK_B) )
|
||||
#else
|
||||
#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
|
||||
#define ADC_CHANNELS_BANK_A (0x00000000U)
|
||||
|
||||
#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
|
||||
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
|
|
@ -414,7 +412,7 @@ typedef struct
|
|||
*/
|
||||
/* Note: Depending on devices, some channels may not be available on package */
|
||||
/* pins. Refer to device datasheet for channels availability. */
|
||||
#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
|
||||
#define ADC_CHANNEL_0 (0x00000000U) /* Channel different in bank A and bank B */
|
||||
#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
|
||||
#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
|
||||
#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
|
||||
|
|
@ -467,7 +465,7 @@ typedef struct
|
|||
/** @defgroup ADC_sampling_times ADC sampling times
|
||||
* @{
|
||||
*/
|
||||
#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /*!< Sampling time 4 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_4CYCLES (0x00000000U) /*!< Sampling time 4 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */
|
||||
#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
|
||||
|
|
@ -554,35 +552,35 @@ typedef struct
|
|||
/** @defgroup ADC_regular_rank ADC rank into regular group
|
||||
* @{
|
||||
*/
|
||||
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
|
||||
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
|
||||
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
|
||||
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
|
||||
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
|
||||
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
|
||||
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
|
||||
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
|
||||
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
|
||||
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
|
||||
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
|
||||
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
|
||||
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
|
||||
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
|
||||
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
|
||||
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
|
||||
#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
|
||||
#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
|
||||
#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
|
||||
#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
|
||||
#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
|
||||
#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
|
||||
#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
|
||||
#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
|
||||
#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
|
||||
#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
|
||||
#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
|
||||
#define ADC_REGULAR_RANK_1 (0x00000001U)
|
||||
#define ADC_REGULAR_RANK_2 (0x00000002U)
|
||||
#define ADC_REGULAR_RANK_3 (0x00000003U)
|
||||
#define ADC_REGULAR_RANK_4 (0x00000004U)
|
||||
#define ADC_REGULAR_RANK_5 (0x00000005U)
|
||||
#define ADC_REGULAR_RANK_6 (0x00000006U)
|
||||
#define ADC_REGULAR_RANK_7 (0x00000007U)
|
||||
#define ADC_REGULAR_RANK_8 (0x00000008U)
|
||||
#define ADC_REGULAR_RANK_9 (0x00000009U)
|
||||
#define ADC_REGULAR_RANK_10 (0x0000000AU)
|
||||
#define ADC_REGULAR_RANK_11 (0x0000000BU)
|
||||
#define ADC_REGULAR_RANK_12 (0x0000000CU)
|
||||
#define ADC_REGULAR_RANK_13 (0x0000000DU)
|
||||
#define ADC_REGULAR_RANK_14 (0x0000000EU)
|
||||
#define ADC_REGULAR_RANK_15 (0x0000000FU)
|
||||
#define ADC_REGULAR_RANK_16 (0x00000010U)
|
||||
#define ADC_REGULAR_RANK_17 (0x00000011U)
|
||||
#define ADC_REGULAR_RANK_18 (0x00000012U)
|
||||
#define ADC_REGULAR_RANK_19 (0x00000013U)
|
||||
#define ADC_REGULAR_RANK_20 (0x00000014U)
|
||||
#define ADC_REGULAR_RANK_21 (0x00000015U)
|
||||
#define ADC_REGULAR_RANK_22 (0x00000016U)
|
||||
#define ADC_REGULAR_RANK_23 (0x00000017U)
|
||||
#define ADC_REGULAR_RANK_24 (0x00000018U)
|
||||
#define ADC_REGULAR_RANK_25 (0x00000019U)
|
||||
#define ADC_REGULAR_RANK_26 (0x0000001AU)
|
||||
#define ADC_REGULAR_RANK_27 (0x0000001BU)
|
||||
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
|
||||
#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
|
||||
#define ADC_REGULAR_RANK_28 (0x0000001CU)
|
||||
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -591,7 +589,7 @@ typedef struct
|
|||
/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
|
||||
#define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
|
||||
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
|
||||
|
|
@ -663,7 +661,7 @@ typedef struct
|
|||
/* (used internally by HAL driver. To not use into HAL structure parameters) */
|
||||
|
||||
/* External triggers of regular group for ADC1 */
|
||||
#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
|
||||
#define ADC_EXTERNALTRIG_T9_CC2 (0x00000000U)
|
||||
#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
|
||||
#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
|
||||
#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
|
||||
|
|
@ -1200,19 +1198,19 @@ typedef struct
|
|||
*
|
||||
*/
|
||||
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
|
||||
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) )
|
||||
((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= (0x00FFU))) || \
|
||||
(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= (0x003FU))) )
|
||||
|
||||
|
||||
#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
|
||||
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
|
||||
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U)))
|
||||
#else
|
||||
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
|
||||
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U)))
|
||||
#endif
|
||||
|
||||
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
|
||||
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_adc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Analog to Digital Convertor (ADC)
|
||||
* peripheral:
|
||||
|
|
@ -25,7 +23,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -75,19 +73,19 @@
|
|||
/* ADC conversion cycles (unit: ADC clock cycles) */
|
||||
/* (selected sampling time + conversion time of 12 ADC clock cycles, with */
|
||||
/* resolution 12 bits) */
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ((uint32_t) 16)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ((uint32_t) 21)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ((uint32_t) 28)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ((uint32_t) 36)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ((uint32_t) 60)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES ((uint32_t)108)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5 ( 16U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES ( 21U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES ( 28U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES ( 36U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES ( 60U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES (108U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES (204U)
|
||||
#define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES (396U)
|
||||
|
||||
/* Delay for temperature sensor stabilization time. */
|
||||
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
|
||||
/* Unit: us */
|
||||
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
|
||||
#define ADC_TEMPSENSOR_DELAY_US (10U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_adc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of ADC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -140,10 +138,10 @@ typedef struct
|
|||
/** @defgroup ADCEx_injected_rank ADCEx rank into injected group
|
||||
* @{
|
||||
*/
|
||||
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
|
||||
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
|
||||
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
|
||||
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
|
||||
#define ADC_INJECTED_RANK_1 (0x00000001U)
|
||||
#define ADC_INJECTED_RANK_2 (0x00000002U)
|
||||
#define ADC_INJECTED_RANK_3 (0x00000003U)
|
||||
#define ADC_INJECTED_RANK_4 (0x00000004U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -151,7 +149,7 @@ typedef struct
|
|||
/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
|
||||
* @{
|
||||
*/
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
|
||||
|
|
@ -175,7 +173,7 @@ typedef struct
|
|||
#define ADC_EXTERNALTRIGINJECCONV_T9_TRGO ADC_EXTERNALTRIGINJEC_T9_TRGO
|
||||
#define ADC_EXTERNALTRIGINJECCONV_T10_CC1 ADC_EXTERNALTRIGINJEC_T10_CC1
|
||||
#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
|
||||
#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000010)
|
||||
#define ADC_INJECTED_SOFTWARE_START (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -197,7 +195,7 @@ typedef struct
|
|||
|
||||
/* List of external triggers of injected group for ADC1: */
|
||||
/* (used internally by HAL driver. To not use into HAL structure parameters) */
|
||||
#define ADC_EXTERNALTRIGINJEC_T9_CC1 ((uint32_t) 0x00000000)
|
||||
#define ADC_EXTERNALTRIGINJEC_T9_CC1 (0x00000000U)
|
||||
#define ADC_EXTERNALTRIGINJEC_T9_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_0))
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)( ADC_CR2_JEXTSEL_1 ))
|
||||
#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)( ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
|
||||
|
|
@ -333,7 +331,7 @@ typedef struct
|
|||
((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
|
||||
#else
|
||||
#define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) \
|
||||
((uint32_t)0x00000000)
|
||||
(0x00000000U)
|
||||
#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
|
||||
#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
|
||||
|
|
@ -517,7 +515,7 @@ typedef struct
|
|||
/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
|
||||
#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief COMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the COMP peripheral:
|
||||
|
|
@ -92,7 +90,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -192,13 +190,13 @@
|
|||
/* - Comparator 2: delay minimum of 800 CPU cycles. Wait loop takes 3 CPU */
|
||||
/* cycles per iteration, therefore total wait iterations */
|
||||
/* number must be initialized at 266 iterations. */
|
||||
#define COMP1_START_DELAY_CPU_CYCLES ((uint32_t)106)
|
||||
#define COMP2_START_DELAY_CPU_CYCLES ((uint32_t)266)
|
||||
#define COMP1_START_DELAY_CPU_CYCLES (106U)
|
||||
#define COMP2_START_DELAY_CPU_CYCLES (266U)
|
||||
|
||||
/* Comparator status "locked": to update COMP handle state (software lock */
|
||||
/* only on COMP of STM32L1xx devices) by bitfield: */
|
||||
/* states HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_BUSY_LOCKED. */
|
||||
#define COMP_STATE_BIT_LOCK ((uint32_t) 0x00000010)
|
||||
#define COMP_STATE_BIT_LOCK (0x00000010U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of COMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_comp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of COMP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief HAL configuration file.
|
||||
* @brief HAL configuration template file.
|
||||
* This file should be copied to the application folder and renamed
|
||||
* to stm32l1xx_hal_conf.h.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -33,14 +33,14 @@
|
|||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_HAL_CONF_H
|
||||
#define __STM32L1xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
|
@ -48,9 +48,9 @@ extern "C" {
|
|||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_MODULE_ENABLED
|
||||
#define HAL_ADC_MODULE_ENABLED
|
||||
#define HAL_COMP_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
|
|
@ -84,14 +84,14 @@ extern "C" {
|
|||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT ((uint32_t)200) /*!< Time out for HSE start up, in ms */
|
||||
#define HSE_STARTUP_TIMEOUT (200U) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
|
|
@ -99,177 +99,189 @@ extern "C" {
|
|||
* This value is the default MSI range value after Reset.
|
||||
*/
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#define MSI_VALUE (2097000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#define HSI_VALUE (16000000U) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
|
||||
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Time out for LSE start up value in ms.
|
||||
*/
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
#define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY ((uint32_t)0x000F) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define PREFETCH_ENABLE 1
|
||||
#define INSTRUCTION_CACHE_ENABLE 0
|
||||
#define DATA_CACHE_ENABLE 0
|
||||
*/
|
||||
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY (0x000FU) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0U
|
||||
#define PREFETCH_ENABLE 1U
|
||||
#define INSTRUCTION_CACHE_ENABLE 0U
|
||||
#define DATA_CACHE_ENABLE 0U
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/*#define USE_FULL_ASSERT 1*/
|
||||
/*#define USE_FULL_ASSERT 1U*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_rcc.h"
|
||||
#include "stm32l1xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_gpio.h"
|
||||
#include "stm32l1xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_dma.h"
|
||||
#include "stm32l1xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_cortex.h"
|
||||
#include "stm32l1xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_adc.h"
|
||||
#include "stm32l1xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_comp.h"
|
||||
#include "stm32l1xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_crc.h"
|
||||
#include "stm32l1xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_cryp.h"
|
||||
#include "stm32l1xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_dac.h"
|
||||
#include "stm32l1xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_flash.h"
|
||||
#include "stm32l1xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_sram.h"
|
||||
#include "stm32l1xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
#include "stm32l1xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_i2c.h"
|
||||
#include "stm32l1xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_i2s.h"
|
||||
#include "stm32l1xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_iwdg.h"
|
||||
#include "stm32l1xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LCD_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_lcd.h"
|
||||
#include "stm32l1xx_hal_lcd.h"
|
||||
#endif /* HAL_LCD_MODULE_ENABLED */
|
||||
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_opamp.h"
|
||||
#include "stm32l1xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_pwr.h"
|
||||
#include "stm32l1xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_rtc.h"
|
||||
#include "stm32l1xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
#include "stm32l1xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_spi.h"
|
||||
#include "stm32l1xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_tim.h"
|
||||
#include "stm32l1xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_uart.h"
|
||||
#include "stm32l1xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_usart.h"
|
||||
#include "stm32l1xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_irda.h"
|
||||
#include "stm32l1xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_smartcard.h"
|
||||
#include "stm32l1xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_wwdg.h"
|
||||
#include "stm32l1xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32l1xx_hal_pcd.h"
|
||||
#include "stm32l1xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/* ALL MBED targets use same stm32_assert.h */
|
||||
// ALL MBED targets use same stm32_assert.h
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
//#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
//void assert_failed(uint8_t* file, uint32_t line);
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CORTEX HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
@ -23,29 +21,8 @@
|
|||
This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M3 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
|
||||
function according to the following table.
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
|
||||
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
|
@ -93,7 +70,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -120,6 +97,30 @@
|
|||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
Additional Tables: CORTEX_NVIC_Priority_Table
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
|
|
@ -292,6 +293,40 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/**
|
||||
* @brief Enable the MPU.
|
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged accessto the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
|
||||
|
||||
/* Ensure MPU setting take effects */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the MPU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
|
||||
/* Disable the MPU and clear the control register*/
|
||||
MPU->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cortex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CORTEX HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -108,16 +106,16 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -125,8 +123,8 @@ typedef struct
|
|||
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
|
||||
* @{
|
||||
*/
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
|
||||
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -136,10 +134,11 @@ typedef struct
|
|||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
|
||||
* @{
|
||||
*/
|
||||
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
|
||||
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
|
||||
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
|
||||
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
|
||||
#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
|
||||
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
|
||||
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
|
||||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -386,40 +385,6 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/**
|
||||
* @brief Disables the MPU
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Disable fault exceptions */
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
|
||||
/* Disable the MPU */
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the MPU
|
||||
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged accessto the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Enable fault exceptions */
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -449,6 +414,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
|||
*/
|
||||
/* Peripheral Control functions ***********************************************/
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CRC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
|
||||
|
|
@ -32,7 +30,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CRC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cryp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CRYP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
@ -70,7 +68,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cryp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CRYP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -143,7 +141,7 @@ typedef struct
|
|||
/** @defgroup CRYP_Data_Type CRYP Data Type
|
||||
* @{
|
||||
*/
|
||||
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
|
||||
#define CRYP_DATATYPE_32B (0x00000000U)
|
||||
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0
|
||||
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1
|
||||
#define CRYP_DATATYPE_1B AES_CR_DATATYPE
|
||||
|
|
@ -161,7 +159,7 @@ typedef struct
|
|||
*/
|
||||
#define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
|
||||
|
||||
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000000)
|
||||
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT (0x00000000U)
|
||||
#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT (AES_CR_MODE)
|
||||
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT (AES_CR_CHMOD_0)
|
||||
#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cryp_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief CRYPEx HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
@ -13,7 +11,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cryp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of CRYPEx HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital to Analog Converter (DAC) peripheral:
|
||||
|
|
@ -173,7 +171,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DAC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -129,7 +127,7 @@ typedef struct
|
|||
/** @defgroup DAC_trigger_selection DAC trigger selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_TRIGGER_T7_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
|
|
@ -146,7 +144,7 @@ typedef struct
|
|||
/** @defgroup DAC_output_buffer DAC output buffer
|
||||
* @{
|
||||
*/
|
||||
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
|
||||
#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
|
||||
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
|
||||
|
||||
/**
|
||||
|
|
@ -156,8 +154,8 @@ typedef struct
|
|||
/** @defgroup DAC_Channel_selection DAC Channel selection
|
||||
* @{
|
||||
*/
|
||||
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
|
||||
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
|
||||
#define DAC_CHANNEL_1 (0x00000000U)
|
||||
#define DAC_CHANNEL_2 (0x00000010U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -166,9 +164,9 @@ typedef struct
|
|||
/** @defgroup DAC_data_alignement DAC data alignement
|
||||
* @{
|
||||
*/
|
||||
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
|
||||
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
|
||||
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
|
||||
#define DAC_ALIGN_12B_R (0x00000000U)
|
||||
#define DAC_ALIGN_12B_L (0x00000004U)
|
||||
#define DAC_ALIGN_8B_R (0x00000008U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -307,11 +305,11 @@ typedef struct
|
|||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
|
||||
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
|
||||
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
|
||||
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
|
||||
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
|
||||
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dac_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief DAC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of DAC extension peripheral:
|
||||
|
|
@ -25,7 +23,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dac_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DAC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -65,7 +63,7 @@
|
|||
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
|
|
@ -77,7 +75,7 @@
|
|||
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
|
||||
|
|
@ -121,8 +119,8 @@
|
|||
/** @defgroup DACEx_wave_generation DACEx wave generation
|
||||
* @{
|
||||
*/
|
||||
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
|
||||
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
|
||||
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
|
||||
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains HAL common defines, enumeration, macros and
|
||||
* structures definitions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief DMA HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
|
|
@ -72,7 +70,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of DMA HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -167,11 +165,11 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_Error_Code DMA Error Code
|
||||
* @{
|
||||
*/
|
||||
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000004) /*!< no ongoing transfer */
|
||||
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100) /*!< Not supported mode */
|
||||
#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
|
||||
#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoing transfer */
|
||||
#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
|
||||
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -179,14 +177,14 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_request DMA request
|
||||
* @{
|
||||
*/
|
||||
#define DMA_REQUEST_0 ((uint32_t)0x00000000)
|
||||
#define DMA_REQUEST_1 ((uint32_t)0x00000001)
|
||||
#define DMA_REQUEST_2 ((uint32_t)0x00000002)
|
||||
#define DMA_REQUEST_3 ((uint32_t)0x00000003)
|
||||
#define DMA_REQUEST_4 ((uint32_t)0x00000004)
|
||||
#define DMA_REQUEST_5 ((uint32_t)0x00000005)
|
||||
#define DMA_REQUEST_6 ((uint32_t)0x00000006)
|
||||
#define DMA_REQUEST_7 ((uint32_t)0x00000007)
|
||||
#define DMA_REQUEST_0 (0x00000000U)
|
||||
#define DMA_REQUEST_1 (0x00000001U)
|
||||
#define DMA_REQUEST_2 (0x00000002U)
|
||||
#define DMA_REQUEST_3 (0x00000003U)
|
||||
#define DMA_REQUEST_4 (0x00000004U)
|
||||
#define DMA_REQUEST_5 (0x00000005U)
|
||||
#define DMA_REQUEST_6 (0x00000006U)
|
||||
#define DMA_REQUEST_7 (0x00000007U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -195,7 +193,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
|
||||
#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
|
||||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
|
||||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
|
||||
|
||||
|
|
@ -207,7 +205,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
* @{
|
||||
*/
|
||||
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
|
||||
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
|
||||
#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -216,7 +214,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
* @{
|
||||
*/
|
||||
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
|
||||
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
|
||||
#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -224,7 +222,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
|
||||
#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment: Byte */
|
||||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
|
||||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */
|
||||
/**
|
||||
|
|
@ -234,7 +232,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_Memory_data_size DMA Memory data size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
|
||||
#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment: Byte */
|
||||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
|
||||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */
|
||||
/**
|
||||
|
|
@ -244,7 +242,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_mode DMA mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
|
||||
#define DMA_NORMAL (0x00000000U) /*!< Normal mode */
|
||||
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -253,7 +251,7 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_Priority_level DMA Priority level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
|
||||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
|
||||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
|
||||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
|
||||
|
|
@ -275,34 +273,34 @@ typedef struct __DMA_HandleTypeDef
|
|||
/** @defgroup DMA_flag_definitions DMA flag definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
#define DMA_FLAG_GL1 (0x00000001U)
|
||||
#define DMA_FLAG_TC1 (0x00000002U)
|
||||
#define DMA_FLAG_HT1 (0x00000004U)
|
||||
#define DMA_FLAG_TE1 (0x00000008U)
|
||||
#define DMA_FLAG_GL2 (0x00000010U)
|
||||
#define DMA_FLAG_TC2 (0x00000020U)
|
||||
#define DMA_FLAG_HT2 (0x00000040U)
|
||||
#define DMA_FLAG_TE2 (0x00000080U)
|
||||
#define DMA_FLAG_GL3 (0x00000100U)
|
||||
#define DMA_FLAG_TC3 (0x00000200U)
|
||||
#define DMA_FLAG_HT3 (0x00000400U)
|
||||
#define DMA_FLAG_TE3 (0x00000800U)
|
||||
#define DMA_FLAG_GL4 (0x00001000U)
|
||||
#define DMA_FLAG_TC4 (0x00002000U)
|
||||
#define DMA_FLAG_HT4 (0x00004000U)
|
||||
#define DMA_FLAG_TE4 (0x00008000U)
|
||||
#define DMA_FLAG_GL5 (0x00010000U)
|
||||
#define DMA_FLAG_TC5 (0x00020000U)
|
||||
#define DMA_FLAG_HT5 (0x00040000U)
|
||||
#define DMA_FLAG_TE5 (0x00080000U)
|
||||
#define DMA_FLAG_GL6 (0x00100000U)
|
||||
#define DMA_FLAG_TC6 (0x00200000U)
|
||||
#define DMA_FLAG_HT6 (0x00400000U)
|
||||
#define DMA_FLAG_TE6 (0x00800000U)
|
||||
#define DMA_FLAG_GL7 (0x01000000U)
|
||||
#define DMA_FLAG_TC7 (0x02000000U)
|
||||
#define DMA_FLAG_HT7 (0x04000000U)
|
||||
#define DMA_FLAG_TE7 (0x08000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
|
|
@ -140,7 +138,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -239,10 +237,10 @@ extern void FLASH_PageErase(uint32_t PageAddress);
|
|||
* Call the HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
*
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: Specifies the address to be programmed.
|
||||
* @param Data: Specifies the data to be programmed
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
|
|
@ -281,10 +279,10 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint
|
|||
/**
|
||||
* @brief Program word at a specified address with interrupt enabled.
|
||||
*
|
||||
* @param TypeProgram: Indicate the way to program at a specified address.
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address: Specifies the address to be programmed.
|
||||
* @param Data: Specifies the data to be programmed
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
|
|
@ -321,7 +319,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
|
|||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0;
|
||||
uint32_t addresstmp = 0U;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
|
|
@ -371,7 +369,7 @@ void HAL_FLASH_IRQHandler(void)
|
|||
pFlash.NbPagesToErase--;
|
||||
|
||||
/* Check if there are still pages to erase */
|
||||
if(pFlash.NbPagesToErase != 0)
|
||||
if(pFlash.NbPagesToErase != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Page;
|
||||
/*Indicate user which sector has been erased */
|
||||
|
|
@ -630,7 +628,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
|
@ -670,7 +668,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
|||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0;
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of Flash HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -57,7 +55,7 @@
|
|||
/** @addtogroup FLASH_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U) /* 50 s */
|
||||
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -66,7 +64,7 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_TYPEPROGRAM(_VALUE_) (((_VALUE_) == FLASH_TYPEPROGRAM_WORD))
|
||||
#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
|
||||
|
||||
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
|
||||
((__LATENCY__) == FLASH_LATENCY_1))
|
||||
|
|
@ -85,9 +83,9 @@
|
|||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_PROC_NONE = 0,
|
||||
FLASH_PROC_PAGEERASE = 1,
|
||||
FLASH_PROC_PROGRAM = 2,
|
||||
FLASH_PROC_NONE = 0U,
|
||||
FLASH_PROC_PAGEERASE = 1U,
|
||||
FLASH_PROC_PROGRAM = 2U,
|
||||
} FLASH_ProcedureTypeDef;
|
||||
|
||||
/**
|
||||
|
|
@ -139,10 +137,9 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#ifndef FLASH_SIZE
|
||||
#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U)
|
||||
#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U)
|
||||
#define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */
|
||||
#endif
|
||||
#define FLASH_PAGE_SIZE ((uint32_t)256U) /*!< FLASH Page Size in bytes */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -151,7 +148,7 @@ typedef struct
|
|||
/** @defgroup FLASH_Type_Program FLASH Type Program
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -160,7 +157,7 @@ typedef struct
|
|||
/** @defgroup FLASH_Latency FLASH Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_LATENCY_0 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
|
||||
|
||||
/**
|
||||
|
|
@ -170,7 +167,7 @@ typedef struct
|
|||
/** @defgroup FLASH_Interrupts FLASH Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
|
||||
/**
|
||||
|
|
@ -206,21 +203,21 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PDKEY1 ((uint32_t)0x04152637U) /*!< Flash power down key1 */
|
||||
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
|
||||
#define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */
|
||||
#define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1
|
||||
to unlock the RUN_PD bit in FLASH_ACR */
|
||||
|
||||
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */
|
||||
#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
|
||||
#define FLASH_PEKEY1 (0x89ABCDEFU) /*!< Flash program erase key1 */
|
||||
#define FLASH_PEKEY2 (0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
|
||||
to unlock the write access to the FLASH_PECR register and
|
||||
data EEPROM */
|
||||
|
||||
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */
|
||||
#define FLASH_PRGKEY2 ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
|
||||
#define FLASH_PRGKEY1 (0x8C9DAEBFU) /*!< Flash program memory key1 */
|
||||
#define FLASH_PRGKEY2 (0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
|
||||
to unlock the program memory */
|
||||
|
||||
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */
|
||||
#define FLASH_OPTKEY2 ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
|
||||
#define FLASH_OPTKEY1 (0xFBEAD9C8U) /*!< Flash option key1 */
|
||||
#define FLASH_OPTKEY2 (0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
|
||||
unlock the write access to the option byte block */
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -307,8 +304,6 @@ typedef struct
|
|||
* @param __FLAG__ specifies the FLASH flags to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
|
||||
* @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag
|
||||
* @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode
|
||||
* @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag
|
||||
* @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
|
||||
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended FLASH HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
@ -38,7 +36,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -205,7 +203,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t
|
|||
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
uint32_t address = 0;
|
||||
uint32_t address = 0U;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
|
@ -222,7 +220,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
|
|||
assert_param(IS_NBPAGES(pEraseInit->NbPages));
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
|
||||
|
||||
#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX)
|
||||
/* Check on which bank belongs the 1st address to erase */
|
||||
|
|
@ -230,7 +228,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
|
|||
{
|
||||
/* BANK1 */
|
||||
/* Check that last page to erase still belongs to BANK1 */
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK1_END)
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)
|
||||
{
|
||||
/* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not
|
||||
continuous */
|
||||
|
|
@ -243,7 +241,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
|
|||
{
|
||||
/* BANK2 */
|
||||
/* Check that last page to erase still belongs to BANK2 */
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK2_END)
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)
|
||||
{
|
||||
/* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not
|
||||
continuous */
|
||||
|
|
@ -300,7 +298,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
|
|||
*/
|
||||
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* If procedure already ongoing, reject the next one */
|
||||
if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
|
|
@ -312,7 +310,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
|||
assert_param(IS_NBPAGES(pEraseInit->NbPages));
|
||||
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
|
@ -323,7 +321,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
|||
{
|
||||
/* BANK1 */
|
||||
/* Check that last page to erase still belongs to BANK1 */
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK1_END)
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)
|
||||
{
|
||||
/* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not
|
||||
continuous */
|
||||
|
|
@ -336,7 +334,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
|||
{
|
||||
/* BANK2 */
|
||||
/* Check that last page to erase still belongs to BANK2 */
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK2_END)
|
||||
if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)
|
||||
{
|
||||
/* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not
|
||||
continuous */
|
||||
|
|
@ -347,15 +345,26 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
|
|||
}
|
||||
#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.NbPagesToErase = pEraseInit->NbPages;
|
||||
pFlash.Page = pEraseInit->PageAddress;
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
|
||||
pFlash.NbPagesToErase = pEraseInit->NbPages;
|
||||
pFlash.Page = pEraseInit->PageAddress;
|
||||
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
/*Erase 1st page and wait for IT*/
|
||||
FLASH_PageErase(pEraseInit->PageAddress);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
|
@ -605,7 +614,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO
|
|||
*/
|
||||
void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
|
||||
{
|
||||
pAdvOBInit->OptionType = 0;
|
||||
pAdvOBInit->OptionType = 0U;
|
||||
|
||||
#if defined(FLASH_OBR_SPRMOD)
|
||||
|
||||
|
|
@ -630,7 +639,7 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
|
|||
pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG;
|
||||
|
||||
/* Get Boot config OB */
|
||||
pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16;
|
||||
pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16U;
|
||||
|
||||
#endif /* FLASH_OBR_nRST_BFB2 */
|
||||
}
|
||||
|
|
@ -649,10 +658,10 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
|
|||
HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t tmp1 = 0;
|
||||
uint32_t tmp2 = 0;
|
||||
uint8_t optiontmp = 0;
|
||||
uint16_t optiontmp2 = 0;
|
||||
uint16_t tmp1 = 0U;
|
||||
uint32_t tmp2 = 0U;
|
||||
uint8_t optiontmp = 0U;
|
||||
uint16_t optiontmp2 = 0U;
|
||||
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
|
|
@ -664,7 +673,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
|
|||
|
||||
/* calculate the option byte to write */
|
||||
tmp1 = (uint16_t)(~(optiontmp2 ));
|
||||
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
|
||||
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
|
|
@ -692,10 +701,10 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
|
|||
HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint16_t tmp1 = 0;
|
||||
uint32_t tmp2 = 0;
|
||||
uint8_t optiontmp = 0;
|
||||
uint16_t optiontmp2 = 0;
|
||||
uint16_t tmp1 = 0U;
|
||||
uint32_t tmp2 = 0U;
|
||||
uint8_t optiontmp = 0U;
|
||||
uint16_t optiontmp2 = 0U;
|
||||
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
|
|
@ -707,7 +716,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
|
|||
|
||||
/* calculate the option byte to write */
|
||||
tmp1 = (uint16_t)(~(optiontmp2 ));
|
||||
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
|
||||
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
|
|
@ -813,7 +822,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr
|
|||
if(TypeErase == FLASH_TYPEERASEDATA_WORD)
|
||||
{
|
||||
/* Write 00000000h to valid address in the data memory */
|
||||
*(__IO uint32_t *) Address = 0x00000000;
|
||||
*(__IO uint32_t *) Address = 0x00000000U;
|
||||
}
|
||||
|
||||
if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD)
|
||||
|
|
@ -846,8 +855,8 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Addr
|
|||
* this function to configure the Fixed Time Programming.
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASHEx_Type_Program_Data
|
||||
* @param Address specifies the address to be programmed.
|
||||
* @param Data specifies the data to be programmed
|
||||
* @param Address specifie the address to be programmed.
|
||||
* @param Data specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
|
|
@ -870,43 +879,43 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_
|
|||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE)
|
||||
{
|
||||
/*Program word (8-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);
|
||||
}
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)
|
||||
{
|
||||
/* Program word (32-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
|
||||
}
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD)
|
||||
{
|
||||
/* Program word (32-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data);
|
||||
}
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
|
||||
{
|
||||
/* Program byte (8-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE)
|
||||
{
|
||||
/*Program word (8-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)
|
||||
{
|
||||
/* Program halfword (16-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
|
||||
}
|
||||
else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)
|
||||
{
|
||||
/* Program word (32-bit) at a specified address.*/
|
||||
status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
|
|
@ -965,7 +974,7 @@ void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
|
|||
static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
|
||||
uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_RDP(OB_RDP));
|
||||
|
|
@ -991,7 +1000,7 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
|
|||
|
||||
/* calculate the option byte to write */
|
||||
tmp1 = (~((uint32_t)(OB_RDP | tmp3)));
|
||||
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | tmp3)));
|
||||
tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3)));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
|
@ -1029,16 +1038,16 @@ static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
|
|||
static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmp = 0, tmp1 = 0;
|
||||
uint32_t tmp = 0U, tmp1 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_BOR_LEVEL(OB_BOR));
|
||||
|
||||
/* Get the User Option byte register */
|
||||
tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16);
|
||||
tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16U);
|
||||
|
||||
/* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/
|
||||
tmp = (uint32_t)~((OB_BOR | tmp1)) << 16;
|
||||
/* Calculate the option byte to write - [0xFFU | nUSER | 0x00U | USER]*/
|
||||
tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U;
|
||||
tmp |= (OB_BOR | tmp1);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
|
|
@ -1067,7 +1076,7 @@ static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
|
|||
static uint8_t FLASH_OB_GetUser(void)
|
||||
{
|
||||
/* Return the User Option Byte */
|
||||
return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> 16);
|
||||
return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1090,7 +1099,7 @@ static uint8_t FLASH_OB_GetRDP(void)
|
|||
static uint8_t FLASH_OB_GetBOR(void)
|
||||
{
|
||||
/* Return the BOR level */
|
||||
return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16);
|
||||
return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1114,7 +1123,7 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit,
|
|||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/* WRP for sector between 0 to 31 */
|
||||
if (pOBInit->WRPSector0To31 != 0)
|
||||
if (pOBInit->WRPSector0To31 != 0U)
|
||||
{
|
||||
FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState);
|
||||
}
|
||||
|
|
@ -1126,7 +1135,7 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit,
|
|||
|
||||
/* Pages for Cat3, Cat4 & Cat5 devices*/
|
||||
/* WRP for sector between 32 to 63 */
|
||||
if (pOBInit->WRPSector32To63 != 0)
|
||||
if (pOBInit->WRPSector32To63 != 0U)
|
||||
{
|
||||
FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState);
|
||||
}
|
||||
|
|
@ -1139,7 +1148,7 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit,
|
|||
|
||||
/* Pages for devices with FLASH >= 256KB*/
|
||||
/* WRP for sector between 64 to 95 */
|
||||
if (pOBInit->WRPSector64To95 != 0)
|
||||
if (pOBInit->WRPSector64To95 != 0U)
|
||||
{
|
||||
FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState);
|
||||
}
|
||||
|
|
@ -1151,7 +1160,7 @@ static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit,
|
|||
|
||||
/* Pages for Cat5 devices*/
|
||||
/* WRP for sector between 96 to 127 */
|
||||
if (pOBInit->WRPSector96To127 != 0)
|
||||
if (pOBInit->WRPSector96To127 != 0U)
|
||||
{
|
||||
FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState);
|
||||
}
|
||||
|
|
@ -1199,7 +1208,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd
|
|||
|
||||
/* Pages for Cat2 devices*/
|
||||
/* PCROP for sector between 0 to 31 */
|
||||
if (pAdvOBInit->PCROPSector0To31 != 0)
|
||||
if (pAdvOBInit->PCROPSector0To31 != 0U)
|
||||
{
|
||||
FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate);
|
||||
}
|
||||
|
|
@ -1208,7 +1217,7 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd
|
|||
|
||||
/* Pages for Cat3 devices*/
|
||||
/* WRP for sector between 32 to 63 */
|
||||
if (pAdvOBInit->PCROPSector32To63 != 0)
|
||||
if (pAdvOBInit->PCROPSector32To63 != 0U)
|
||||
{
|
||||
FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate);
|
||||
}
|
||||
|
|
@ -1234,9 +1243,9 @@ static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAd
|
|||
*/
|
||||
static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState)
|
||||
{
|
||||
uint32_t wrp01data = 0, wrp23data = 0;
|
||||
uint32_t wrp01data = 0U, wrp23data = 0U;
|
||||
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
uint32_t tmp1 = 0U, tmp2 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WRP1OrPCROP1));
|
||||
|
|
@ -1245,22 +1254,22 @@ static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalStat
|
|||
if (NewState != DISABLE)
|
||||
{
|
||||
wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01));
|
||||
wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 | OB->WRP23)));
|
||||
tmp1 = (uint32_t)(~(wrp01data) << 16)|(wrp01data);
|
||||
wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U | OB->WRP23)));
|
||||
tmp1 = (uint32_t)(~(wrp01data) << 16U)|(wrp01data);
|
||||
OB->WRP01 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)(~(wrp23data) << 16)|(wrp23data);
|
||||
tmp2 = (uint32_t)(~(wrp23data) << 16U)|(wrp23data);
|
||||
OB->WRP23 = tmp2;
|
||||
}
|
||||
else
|
||||
{
|
||||
wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01));
|
||||
wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 & OB->WRP23)));
|
||||
wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U & OB->WRP23)));
|
||||
|
||||
tmp1 = (uint32_t)((~wrp01data) << 16)|(wrp01data);
|
||||
tmp1 = (uint32_t)((~wrp01data) << 16U)|(wrp01data);
|
||||
OB->WRP01 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)((~wrp23data) << 16)|(wrp23data);
|
||||
tmp2 = (uint32_t)((~wrp23data) << 16U)|(wrp23data);
|
||||
OB->WRP23 = tmp2;
|
||||
}
|
||||
}
|
||||
|
|
@ -1280,9 +1289,9 @@ static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalStat
|
|||
*/
|
||||
static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState)
|
||||
{
|
||||
uint32_t wrp45data = 0, wrp67data = 0;
|
||||
uint32_t wrp45data = 0U, wrp67data = 0U;
|
||||
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
uint32_t tmp1 = 0U, tmp2 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WRP2OrPCROP2));
|
||||
|
|
@ -1291,22 +1300,22 @@ static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalStat
|
|||
if (NewState != DISABLE)
|
||||
{
|
||||
wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45));
|
||||
wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 | OB->WRP67)));
|
||||
tmp1 = (uint32_t)(~(wrp45data) << 16)|(wrp45data);
|
||||
wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U | OB->WRP67)));
|
||||
tmp1 = (uint32_t)(~(wrp45data) << 16U)|(wrp45data);
|
||||
OB->WRP45 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)(~(wrp67data) << 16)|(wrp67data);
|
||||
tmp2 = (uint32_t)(~(wrp67data) << 16U)|(wrp67data);
|
||||
OB->WRP67 = tmp2;
|
||||
}
|
||||
else
|
||||
{
|
||||
wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45));
|
||||
wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 & OB->WRP67)));
|
||||
wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U & OB->WRP67)));
|
||||
|
||||
tmp1 = (uint32_t)((~wrp45data) << 16)|(wrp45data);
|
||||
tmp1 = (uint32_t)((~wrp45data) << 16U)|(wrp45data);
|
||||
OB->WRP45 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)((~wrp67data) << 16)|(wrp67data);
|
||||
tmp2 = (uint32_t)((~wrp67data) << 16U)|(wrp67data);
|
||||
OB->WRP67 = tmp2;
|
||||
}
|
||||
}
|
||||
|
|
@ -1326,9 +1335,9 @@ static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalStat
|
|||
*/
|
||||
static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
|
||||
{
|
||||
uint32_t wrp89data = 0, wrp1011data = 0;
|
||||
uint32_t wrp89data = 0U, wrp1011data = 0U;
|
||||
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
uint32_t tmp1 = 0U, tmp2 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WRP3));
|
||||
|
|
@ -1337,22 +1346,22 @@ static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
|
|||
if (NewState != DISABLE)
|
||||
{
|
||||
wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89));
|
||||
wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16 | OB->WRP1011)));
|
||||
tmp1 = (uint32_t)(~(wrp89data) << 16)|(wrp89data);
|
||||
wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16U | OB->WRP1011)));
|
||||
tmp1 = (uint32_t)(~(wrp89data) << 16U)|(wrp89data);
|
||||
OB->WRP89 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)(~(wrp1011data) << 16)|(wrp1011data);
|
||||
tmp2 = (uint32_t)(~(wrp1011data) << 16U)|(wrp1011data);
|
||||
OB->WRP1011 = tmp2;
|
||||
}
|
||||
else
|
||||
{
|
||||
wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89));
|
||||
wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16 & OB->WRP1011)));
|
||||
wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16U & OB->WRP1011)));
|
||||
|
||||
tmp1 = (uint32_t)((~wrp89data) << 16)|(wrp89data);
|
||||
tmp1 = (uint32_t)((~wrp89data) << 16U)|(wrp89data);
|
||||
OB->WRP89 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)((~wrp1011data) << 16)|(wrp1011data);
|
||||
tmp2 = (uint32_t)((~wrp1011data) << 16U)|(wrp1011data);
|
||||
OB->WRP1011 = tmp2;
|
||||
}
|
||||
}
|
||||
|
|
@ -1371,9 +1380,9 @@ static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
|
|||
*/
|
||||
static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
|
||||
{
|
||||
uint32_t wrp1213data = 0, wrp1415data = 0;
|
||||
uint32_t wrp1213data = 0U, wrp1415data = 0U;
|
||||
|
||||
uint32_t tmp1 = 0, tmp2 = 0;
|
||||
uint32_t tmp1 = 0U, tmp2 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_WRP(WRP4));
|
||||
|
|
@ -1382,22 +1391,22 @@ static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
|
|||
if (NewState != DISABLE)
|
||||
{
|
||||
wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213));
|
||||
wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16 | OB->WRP1415)));
|
||||
tmp1 = (uint32_t)(~(wrp1213data) << 16)|(wrp1213data);
|
||||
wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16U | OB->WRP1415)));
|
||||
tmp1 = (uint32_t)(~(wrp1213data) << 16U)|(wrp1213data);
|
||||
OB->WRP1213 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)(~(wrp1415data) << 16)|(wrp1415data);
|
||||
tmp2 = (uint32_t)(~(wrp1415data) << 16U)|(wrp1415data);
|
||||
OB->WRP1415 = tmp2;
|
||||
}
|
||||
else
|
||||
{
|
||||
wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213));
|
||||
wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16 & OB->WRP1415)));
|
||||
wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16U & OB->WRP1415)));
|
||||
|
||||
tmp1 = (uint32_t)((~wrp1213data) << 16)|(wrp1213data);
|
||||
tmp1 = (uint32_t)((~wrp1213data) << 16U)|(wrp1213data);
|
||||
OB->WRP1213 = tmp1;
|
||||
|
||||
tmp2 = (uint32_t)((~wrp1415data) << 16)|(wrp1415data);
|
||||
tmp2 = (uint32_t)((~wrp1415data) << 16U)|(wrp1415data);
|
||||
OB->WRP1415 = tmp2;
|
||||
}
|
||||
}
|
||||
|
|
@ -1422,7 +1431,7 @@ static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
|
|||
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmp = 0, tmp1 = 0;
|
||||
uint32_t tmp = 0U, tmp1 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
|
||||
|
|
@ -1430,10 +1439,10 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u
|
|||
assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
|
||||
|
||||
/* Get the User Option byte register */
|
||||
tmp1 = OB->USER & ((~FLASH_OBR_USER) >> 16);
|
||||
tmp1 = OB->USER & ((~FLASH_OBR_USER) >> 16U);
|
||||
|
||||
/* Calculate the user option byte to write */
|
||||
tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16);
|
||||
tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U);
|
||||
tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
|
|
@ -1475,16 +1484,16 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u
|
|||
static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmp = 0, tmp1 = 0;
|
||||
uint32_t tmp = 0U, tmp1 = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_OB_BOOT_BANK(OB_BOOT));
|
||||
|
||||
/* Get the User Option byte register and BOR Level*/
|
||||
tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16);
|
||||
tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16U);
|
||||
|
||||
/* Calculate the option byte to write */
|
||||
tmp = (uint32_t)~(OB_BOOT | tmp1) << 16;
|
||||
tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U;
|
||||
tmp |= (OB_BOOT | tmp1);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
|
|
@ -1525,7 +1534,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
uint32_t tmp = 0, tmpaddr = 0;
|
||||
uint32_t tmp = 0U, tmpaddr = 0U;
|
||||
#endif /* STM32L100xB || STM32L151xB || STM32L152xB */
|
||||
|
||||
/* Check the parameters */
|
||||
|
|
@ -1541,7 +1550,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint
|
|||
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
/* Possible only on Cat1 devices */
|
||||
if(Data != (uint8_t)0x00)
|
||||
if(Data != (uint8_t)0x00U)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to write the new Data */
|
||||
*(__IO uint8_t *)Address = Data;
|
||||
|
|
@ -1551,14 +1560,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint
|
|||
}
|
||||
else
|
||||
{
|
||||
tmpaddr = Address & 0xFFFFFFFC;
|
||||
tmpaddr = Address & 0xFFFFFFFCU;
|
||||
tmp = * (__IO uint32_t *) tmpaddr;
|
||||
tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
|
||||
tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
|
||||
tmp &= ~tmpaddr;
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
}
|
||||
|
|
@ -1585,7 +1594,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address,
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
uint32_t tmp = 0, tmpaddr = 0;
|
||||
uint32_t tmp = 0U, tmpaddr = 0U;
|
||||
#endif /* STM32L100xB || STM32L151xB || STM32L152xB */
|
||||
|
||||
/* Check the parameters */
|
||||
|
|
@ -1601,7 +1610,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address,
|
|||
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
/* Possible only on Cat1 devices */
|
||||
if(Data != (uint16_t)0x0000)
|
||||
if(Data != (uint16_t)0x0000U)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to write the new data */
|
||||
*(__IO uint16_t *)Address = Data;
|
||||
|
|
@ -1613,19 +1622,19 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address,
|
|||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
if((Address & 0x3) != 0x3)
|
||||
if((Address & 0x3U) != 0x3U)
|
||||
{
|
||||
tmpaddr = Address & 0xFFFFFFFC;
|
||||
tmpaddr = Address & 0xFFFFFFFCU;
|
||||
tmp = * (__IO uint32_t *) tmpaddr;
|
||||
tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
|
||||
tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
|
||||
tmp &= ~tmpaddr;
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00);
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00);
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);
|
||||
}
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
|
@ -1684,7 +1693,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
uint32_t tmp = 0, tmpaddr = 0;
|
||||
uint32_t tmp = 0U, tmpaddr = 0U;
|
||||
#endif /* STM32L100xB || STM32L151xB || STM32L152xB */
|
||||
|
||||
/* Check the parameters */
|
||||
|
|
@ -1696,7 +1705,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t
|
|||
if(status == HAL_OK)
|
||||
{
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
if(Data != (uint8_t) 0x00)
|
||||
if(Data != (uint8_t) 0x00U)
|
||||
{
|
||||
*(__IO uint8_t *)Address = Data;
|
||||
|
||||
|
|
@ -1706,14 +1715,14 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t
|
|||
}
|
||||
else
|
||||
{
|
||||
tmpaddr = Address & 0xFFFFFFFC;
|
||||
tmpaddr = Address & 0xFFFFFFFCU;
|
||||
tmp = * (__IO uint32_t *) tmpaddr;
|
||||
tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
|
||||
tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
|
||||
tmp &= ~tmpaddr;
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
}
|
||||
|
|
@ -1738,7 +1747,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
uint32_t tmp = 0, tmpaddr = 0;
|
||||
uint32_t tmp = 0U, tmpaddr = 0U;
|
||||
#endif /* STM32L100xB || STM32L151xB || STM32L152xB */
|
||||
|
||||
/* Check the parameters */
|
||||
|
|
@ -1750,7 +1759,7 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint
|
|||
if(status == HAL_OK)
|
||||
{
|
||||
#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
|
||||
if(Data != (uint16_t)0x0000)
|
||||
if(Data != (uint16_t)0x0000U)
|
||||
{
|
||||
*(__IO uint16_t *)Address = Data;
|
||||
|
||||
|
|
@ -1761,19 +1770,19 @@ static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint
|
|||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
if((Address & 0x3) != 0x3)
|
||||
if((Address & 0x3U) != 0x3U)
|
||||
{
|
||||
tmpaddr = Address & 0xFFFFFFFC;
|
||||
tmpaddr = Address & 0xFFFFFFFCU;
|
||||
tmp = * (__IO uint32_t *) tmpaddr;
|
||||
tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
|
||||
tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
|
||||
tmp &= ~tmpaddr;
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
|
||||
status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00);
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00);
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);
|
||||
HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);
|
||||
}
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
|
|
|||
|
|
@ -1,14 +1,12 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash.h
|
||||
* @file stm32l1xx_hal_flash_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of Flash HAL module.
|
||||
* @brief Header file of Flash HAL Extended module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -86,29 +84,29 @@
|
|||
|| defined(STM32L151xBA) || defined(STM32L152xBA)
|
||||
|
||||
/******* Devices with FLASH 128K *******/
|
||||
#define FLASH_NBPAGES_MAX 512 /* 512 pages from page 0 to page 511 */
|
||||
#define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */
|
||||
|
||||
#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
|
||||
|| defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
|
||||
|
||||
/******* Devices with FLASH 256K *******/
|
||||
#define FLASH_NBPAGES_MAX 1025 /* 1025 pages from page 0 to page 1024 */
|
||||
#define FLASH_NBPAGES_MAX 1025U /* 1025 pages from page 0 to page 1024U */
|
||||
|
||||
#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
|
||||
|| defined(STM32L162xD) || defined(STM32L162xDX)
|
||||
|
||||
/******* Devices with FLASH 384K *******/
|
||||
#define FLASH_NBPAGES_MAX 1536 /* 1536 pages from page 0 to page 1535 */
|
||||
#define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */
|
||||
|
||||
#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
|
||||
|
||||
/******* Devices with FLASH 512K *******/
|
||||
#define FLASH_NBPAGES_MAX 2048 /* 2048 pages from page 0 to page 2047 */
|
||||
#define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */
|
||||
|
||||
#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
|
||||
|
||||
#define WRP_MASK_LOW ((uint32_t)0x0000FFFFU)
|
||||
#define WRP_MASK_HIGH ((uint32_t)0xFFFF0000U)
|
||||
#define WRP_MASK_LOW (0x0000FFFFU)
|
||||
#define WRP_MASK_HIGH (0xFFFF0000U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -175,7 +173,6 @@
|
|||
#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
|
||||
((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
|
||||
((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
|
||||
|
||||
#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
|
||||
((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
|
||||
((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
|
||||
|
|
@ -183,6 +180,7 @@
|
|||
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
|
||||
((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
|
||||
|
||||
|
||||
/** @defgroup FLASHEx_Address FLASHEx Address
|
||||
* @{
|
||||
*/
|
||||
|
|
@ -204,7 +202,7 @@
|
|||
|
||||
#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
|
||||
|
||||
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
|
||||
#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -325,8 +323,8 @@ typedef struct
|
|||
/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASE_PAGES ((uint32_t)0x00U) /*!<Page erase only*/
|
||||
|
||||
#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Page erase only*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -334,10 +332,10 @@ typedef struct
|
|||
/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
|
||||
* @{
|
||||
*/
|
||||
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!<BOR option byte configuration*/
|
||||
#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
|
||||
#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
|
||||
#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
|
||||
#define OPTIONBYTE_BOR (0x08U) /*!<BOR option byte configuration*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -346,8 +344,8 @@ typedef struct
|
|||
/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!<Disable the write protection of the desired sectors*/
|
||||
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!<Enable the write protection of the desired sectors*/
|
||||
#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired sectors*/
|
||||
#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired sectors*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -358,38 +356,38 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
|
||||
#define OB_WRP1_PAGES0TO15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
|
||||
#define OB_WRP1_PAGES16TO31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
|
||||
#define OB_WRP1_PAGES32TO47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
|
||||
#define OB_WRP1_PAGES48TO63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
|
||||
#define OB_WRP1_PAGES64TO79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
|
||||
#define OB_WRP1_PAGES80TO95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
|
||||
#define OB_WRP1_PAGES96TO111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
|
||||
#define OB_WRP1_PAGES112TO127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
|
||||
#define OB_WRP1_PAGES128TO143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
|
||||
#define OB_WRP1_PAGES144TO159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
|
||||
#define OB_WRP1_PAGES160TO175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
|
||||
#define OB_WRP1_PAGES176TO191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
|
||||
#define OB_WRP1_PAGES192TO207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
|
||||
#define OB_WRP1_PAGES208TO223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
|
||||
#define OB_WRP1_PAGES224TO239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
|
||||
#define OB_WRP1_PAGES240TO255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
|
||||
#define OB_WRP1_PAGES256TO271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
|
||||
#define OB_WRP1_PAGES272TO287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
|
||||
#define OB_WRP1_PAGES288TO303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
|
||||
#define OB_WRP1_PAGES304TO319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
|
||||
#define OB_WRP1_PAGES320TO335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
|
||||
#define OB_WRP1_PAGES336TO351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
|
||||
#define OB_WRP1_PAGES352TO367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
|
||||
#define OB_WRP1_PAGES368TO383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
|
||||
#define OB_WRP1_PAGES384TO399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
|
||||
#define OB_WRP1_PAGES400TO415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
|
||||
#define OB_WRP1_PAGES416TO431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
|
||||
#define OB_WRP1_PAGES432TO447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
|
||||
#define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
|
||||
#define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
|
||||
#define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
|
||||
#define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000U) /* Write protection of Sector31 */
|
||||
#define OB_WRP1_PAGES0TO15 (0x00000001U) /* Write protection of Sector0 */
|
||||
#define OB_WRP1_PAGES16TO31 (0x00000002U) /* Write protection of Sector1 */
|
||||
#define OB_WRP1_PAGES32TO47 (0x00000004U) /* Write protection of Sector2 */
|
||||
#define OB_WRP1_PAGES48TO63 (0x00000008U) /* Write protection of Sector3 */
|
||||
#define OB_WRP1_PAGES64TO79 (0x00000010U) /* Write protection of Sector4 */
|
||||
#define OB_WRP1_PAGES80TO95 (0x00000020U) /* Write protection of Sector5 */
|
||||
#define OB_WRP1_PAGES96TO111 (0x00000040U) /* Write protection of Sector6 */
|
||||
#define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */
|
||||
#define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */
|
||||
#define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */
|
||||
#define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */
|
||||
#define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */
|
||||
#define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */
|
||||
#define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */
|
||||
#define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */
|
||||
#define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */
|
||||
#define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */
|
||||
#define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */
|
||||
#define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */
|
||||
#define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */
|
||||
#define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */
|
||||
#define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */
|
||||
#define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */
|
||||
#define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */
|
||||
#define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */
|
||||
#define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */
|
||||
#define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */
|
||||
#define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */
|
||||
#define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */
|
||||
#define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */
|
||||
#define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */
|
||||
#define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */
|
||||
|
||||
#define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
|
||||
|
||||
|
|
@ -407,44 +405,44 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Pages for Cat3, Cat4 & Cat5 devices*/
|
||||
#define OB_WRP2_PAGES512TO527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
|
||||
#define OB_WRP2_PAGES528TO543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
|
||||
#define OB_WRP2_PAGES544TO559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
|
||||
#define OB_WRP2_PAGES560TO575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
|
||||
#define OB_WRP2_PAGES576TO591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
|
||||
#define OB_WRP2_PAGES592TO607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
|
||||
#define OB_WRP2_PAGES608TO623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
|
||||
#define OB_WRP2_PAGES624TO639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
|
||||
#define OB_WRP2_PAGES640TO655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
|
||||
#define OB_WRP2_PAGES656TO671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
|
||||
#define OB_WRP2_PAGES672TO687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
|
||||
#define OB_WRP2_PAGES688TO703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
|
||||
#define OB_WRP2_PAGES704TO719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
|
||||
#define OB_WRP2_PAGES720TO735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
|
||||
#define OB_WRP2_PAGES736TO751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
|
||||
#define OB_WRP2_PAGES752TO767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
|
||||
#define OB_WRP2_PAGES512TO527 (0x00000001U) /* Write protection of Sector32 */
|
||||
#define OB_WRP2_PAGES528TO543 (0x00000002U) /* Write protection of Sector33 */
|
||||
#define OB_WRP2_PAGES544TO559 (0x00000004U) /* Write protection of Sector34 */
|
||||
#define OB_WRP2_PAGES560TO575 (0x00000008U) /* Write protection of Sector35 */
|
||||
#define OB_WRP2_PAGES576TO591 (0x00000010U) /* Write protection of Sector36 */
|
||||
#define OB_WRP2_PAGES592TO607 (0x00000020U) /* Write protection of Sector37 */
|
||||
#define OB_WRP2_PAGES608TO623 (0x00000040U) /* Write protection of Sector38 */
|
||||
#define OB_WRP2_PAGES624TO639 (0x00000080U) /* Write protection of Sector39 */
|
||||
#define OB_WRP2_PAGES640TO655 (0x00000100U) /* Write protection of Sector40 */
|
||||
#define OB_WRP2_PAGES656TO671 (0x00000200U) /* Write protection of Sector41 */
|
||||
#define OB_WRP2_PAGES672TO687 (0x00000400U) /* Write protection of Sector42 */
|
||||
#define OB_WRP2_PAGES688TO703 (0x00000800U) /* Write protection of Sector43 */
|
||||
#define OB_WRP2_PAGES704TO719 (0x00001000U) /* Write protection of Sector44 */
|
||||
#define OB_WRP2_PAGES720TO735 (0x00002000U) /* Write protection of Sector45 */
|
||||
#define OB_WRP2_PAGES736TO751 (0x00004000U) /* Write protection of Sector46 */
|
||||
#define OB_WRP2_PAGES752TO767 (0x00008000U) /* Write protection of Sector47 */
|
||||
|
||||
#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
|
||||
|| defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
|
||||
|| defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \
|
||||
|| defined(STM32L162xE)
|
||||
|
||||
#define OB_WRP2_PAGES768TO783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
|
||||
#define OB_WRP2_PAGES784TO799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
|
||||
#define OB_WRP2_PAGES800TO815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
|
||||
#define OB_WRP2_PAGES816TO831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
|
||||
#define OB_WRP2_PAGES832TO847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
|
||||
#define OB_WRP2_PAGES848TO863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
|
||||
#define OB_WRP2_PAGES864TO879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
|
||||
#define OB_WRP2_PAGES880TO895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
|
||||
#define OB_WRP2_PAGES896TO911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
|
||||
#define OB_WRP2_PAGES912TO927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
|
||||
#define OB_WRP2_PAGES928TO943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
|
||||
#define OB_WRP2_PAGES944TO959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
|
||||
#define OB_WRP2_PAGES960TO975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
|
||||
#define OB_WRP2_PAGES976TO991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
|
||||
#define OB_WRP2_PAGES992TO1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
|
||||
#define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* Write protection of Sector63 */
|
||||
#define OB_WRP2_PAGES768TO783 (0x00010000U) /* Write protection of Sector48 */
|
||||
#define OB_WRP2_PAGES784TO799 (0x00020000U) /* Write protection of Sector49 */
|
||||
#define OB_WRP2_PAGES800TO815 (0x00040000U) /* Write protection of Sector50 */
|
||||
#define OB_WRP2_PAGES816TO831 (0x00080000U) /* Write protection of Sector51 */
|
||||
#define OB_WRP2_PAGES832TO847 (0x00100000U) /* Write protection of Sector52 */
|
||||
#define OB_WRP2_PAGES848TO863 (0x00200000U) /* Write protection of Sector53 */
|
||||
#define OB_WRP2_PAGES864TO879 (0x00400000U) /* Write protection of Sector54 */
|
||||
#define OB_WRP2_PAGES880TO895 (0x00800000U) /* Write protection of Sector55 */
|
||||
#define OB_WRP2_PAGES896TO911 (0x01000000U) /* Write protection of Sector56 */
|
||||
#define OB_WRP2_PAGES912TO927 (0x02000000U) /* Write protection of Sector57 */
|
||||
#define OB_WRP2_PAGES928TO943 (0x04000000U) /* Write protection of Sector58 */
|
||||
#define OB_WRP2_PAGES944TO959 (0x08000000U) /* Write protection of Sector59 */
|
||||
#define OB_WRP2_PAGES960TO975 (0x10000000U) /* Write protection of Sector60 */
|
||||
#define OB_WRP2_PAGES976TO991 (0x20000000U) /* Write protection of Sector61 */
|
||||
#define OB_WRP2_PAGES992TO1007 (0x40000000U) /* Write protection of Sector62 */
|
||||
#define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */
|
||||
|
||||
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
|
||||
|
||||
|
|
@ -465,38 +463,38 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Pages for devices with FLASH >= 256KB*/
|
||||
#define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
|
||||
#define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
|
||||
#define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
|
||||
#define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
|
||||
#define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
|
||||
#define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
|
||||
#define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
|
||||
#define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
|
||||
#define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
|
||||
#define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
|
||||
#define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
|
||||
#define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
|
||||
#define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
|
||||
#define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
|
||||
#define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
|
||||
#define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
|
||||
#define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
|
||||
#define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
|
||||
#define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
|
||||
#define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
|
||||
#define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
|
||||
#define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
|
||||
#define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
|
||||
#define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
|
||||
#define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
|
||||
#define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
|
||||
#define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
|
||||
#define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
|
||||
#define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
|
||||
#define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
|
||||
#define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
|
||||
#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000U) /* Write protection of Sector95 */
|
||||
#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */
|
||||
#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */
|
||||
#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */
|
||||
#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */
|
||||
#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */
|
||||
#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */
|
||||
#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */
|
||||
#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */
|
||||
#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */
|
||||
#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */
|
||||
#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */
|
||||
#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */
|
||||
#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */
|
||||
#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */
|
||||
#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */
|
||||
#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */
|
||||
#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */
|
||||
#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */
|
||||
#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */
|
||||
#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */
|
||||
#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */
|
||||
#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */
|
||||
#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */
|
||||
#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */
|
||||
#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */
|
||||
#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */
|
||||
#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */
|
||||
#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */
|
||||
#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */
|
||||
#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */
|
||||
#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */
|
||||
#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */
|
||||
|
||||
#define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
|
||||
|
||||
|
|
@ -514,41 +512,41 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Pages for Cat5 devices*/
|
||||
#define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/
|
||||
#define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/
|
||||
#define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/
|
||||
#define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/
|
||||
#define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/
|
||||
#define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/
|
||||
#define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/
|
||||
#define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/
|
||||
#define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/
|
||||
#define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/
|
||||
#define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/
|
||||
#define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/
|
||||
#define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/
|
||||
#define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/
|
||||
#define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/
|
||||
#define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/
|
||||
#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/
|
||||
#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/
|
||||
#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/
|
||||
#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/
|
||||
#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/
|
||||
#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/
|
||||
#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/
|
||||
#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/
|
||||
#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/
|
||||
#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/
|
||||
#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/
|
||||
#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/
|
||||
#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/
|
||||
#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/
|
||||
#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/
|
||||
#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/
|
||||
|
||||
#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
|
||||
|
||||
#define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/
|
||||
#define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/
|
||||
#define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/
|
||||
#define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/
|
||||
#define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/
|
||||
#define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/
|
||||
#define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/
|
||||
#define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/
|
||||
#define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/
|
||||
#define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/
|
||||
#define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/
|
||||
#define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/
|
||||
#define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/
|
||||
#define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/
|
||||
#define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/
|
||||
#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000U) /* Write protection of Sector127*/
|
||||
#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/
|
||||
#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/
|
||||
#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/
|
||||
#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/
|
||||
#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/
|
||||
#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/
|
||||
#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/
|
||||
#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/
|
||||
#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/
|
||||
#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/
|
||||
#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/
|
||||
#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/
|
||||
#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/
|
||||
#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/
|
||||
#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/
|
||||
#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/
|
||||
|
||||
#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
|
||||
|
||||
|
|
@ -626,7 +624,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define OPTIONBYTE_PCROP ((uint32_t)0x01U) /*!<PCROP option byte configuration*/
|
||||
#define OPTIONBYTE_PCROP (0x01U) /*!<PCROP option byte configuration*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -640,7 +638,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define OPTIONBYTE_BOOTCONFIG ((uint32_t)0x02U) /*!<BOOTConfig option byte configuration*/
|
||||
#define OPTIONBYTE_BOOTCONFIG (0x02U) /*!<BOOTConfig option byte configuration*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -653,8 +651,8 @@ typedef struct
|
|||
/** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
|
||||
* @{
|
||||
*/
|
||||
#define OB_PCROP_STATE_DISABLE ((uint32_t)0x00U) /*!<Disable PCROP for selected sectors */
|
||||
#define OB_PCROP_STATE_ENABLE ((uint32_t)0x01U) /*!<Enable PCROP for selected sectors */
|
||||
#define OB_PCROP_STATE_DISABLE (0x00U) /*!<Disable PCROP for selected sectors */
|
||||
#define OB_PCROP_STATE_ENABLE (0x01U) /*!<Enable PCROP for selected sectors */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -678,40 +676,40 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
|
||||
#define OB_PCROP1_PAGES0TO15 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector0 */
|
||||
#define OB_PCROP1_PAGES16TO31 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector1 */
|
||||
#define OB_PCROP1_PAGES32TO47 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector2 */
|
||||
#define OB_PCROP1_PAGES48TO63 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector3 */
|
||||
#define OB_PCROP1_PAGES64TO79 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector4 */
|
||||
#define OB_PCROP1_PAGES80TO95 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector5 */
|
||||
#define OB_PCROP1_PAGES96TO111 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector6 */
|
||||
#define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector7 */
|
||||
#define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector8 */
|
||||
#define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector9 */
|
||||
#define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector10 */
|
||||
#define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector11 */
|
||||
#define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector12 */
|
||||
#define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector13 */
|
||||
#define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector14 */
|
||||
#define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector15 */
|
||||
#define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector16 */
|
||||
#define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector17 */
|
||||
#define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector18 */
|
||||
#define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector19 */
|
||||
#define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector20 */
|
||||
#define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector21 */
|
||||
#define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector22 */
|
||||
#define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector23 */
|
||||
#define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector24 */
|
||||
#define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector25 */
|
||||
#define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector26 */
|
||||
#define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector27 */
|
||||
#define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector28 */
|
||||
#define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector29 */
|
||||
#define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector30 */
|
||||
#define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector31 */
|
||||
#define OB_PCROP1_PAGES0TO15 (0x00000001U) /* PC Read/Write protection of Sector0 */
|
||||
#define OB_PCROP1_PAGES16TO31 (0x00000002U) /* PC Read/Write protection of Sector1 */
|
||||
#define OB_PCROP1_PAGES32TO47 (0x00000004U) /* PC Read/Write protection of Sector2 */
|
||||
#define OB_PCROP1_PAGES48TO63 (0x00000008U) /* PC Read/Write protection of Sector3 */
|
||||
#define OB_PCROP1_PAGES64TO79 (0x00000010U) /* PC Read/Write protection of Sector4 */
|
||||
#define OB_PCROP1_PAGES80TO95 (0x00000020U) /* PC Read/Write protection of Sector5 */
|
||||
#define OB_PCROP1_PAGES96TO111 (0x00000040U) /* PC Read/Write protection of Sector6 */
|
||||
#define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write protection of Sector7 */
|
||||
#define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write protection of Sector8 */
|
||||
#define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write protection of Sector9 */
|
||||
#define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write protection of Sector10 */
|
||||
#define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write protection of Sector11 */
|
||||
#define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write protection of Sector12 */
|
||||
#define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write protection of Sector13 */
|
||||
#define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write protection of Sector14 */
|
||||
#define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write protection of Sector15 */
|
||||
#define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write protection of Sector16 */
|
||||
#define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write protection of Sector17 */
|
||||
#define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write protection of Sector18 */
|
||||
#define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write protection of Sector19 */
|
||||
#define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write protection of Sector20 */
|
||||
#define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write protection of Sector21 */
|
||||
#define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write protection of Sector22 */
|
||||
#define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write protection of Sector23 */
|
||||
#define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write protection of Sector24 */
|
||||
#define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write protection of Sector25 */
|
||||
#define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write protection of Sector26 */
|
||||
#define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write protection of Sector27 */
|
||||
#define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write protection of Sector28 */
|
||||
#define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write protection of Sector29 */
|
||||
#define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write protection of Sector30 */
|
||||
#define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write protection of Sector31 */
|
||||
|
||||
#define OB_PCROP1_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
|
||||
#define OB_PCROP1_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -725,40 +723,40 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* Pages for Cat3, Cat4 & Cat5 devices*/
|
||||
#define OB_PCROP2_PAGES512TO527 ((uint32_t)0x00000001U) /* PC Read/Write protection of Sector32 */
|
||||
#define OB_PCROP2_PAGES528TO543 ((uint32_t)0x00000002U) /* PC Read/Write protection of Sector33 */
|
||||
#define OB_PCROP2_PAGES544TO559 ((uint32_t)0x00000004U) /* PC Read/Write protection of Sector34 */
|
||||
#define OB_PCROP2_PAGES560TO575 ((uint32_t)0x00000008U) /* PC Read/Write protection of Sector35 */
|
||||
#define OB_PCROP2_PAGES576TO591 ((uint32_t)0x00000010U) /* PC Read/Write protection of Sector36 */
|
||||
#define OB_PCROP2_PAGES592TO607 ((uint32_t)0x00000020U) /* PC Read/Write protection of Sector37 */
|
||||
#define OB_PCROP2_PAGES608TO623 ((uint32_t)0x00000040U) /* PC Read/Write protection of Sector38 */
|
||||
#define OB_PCROP2_PAGES624TO639 ((uint32_t)0x00000080U) /* PC Read/Write protection of Sector39 */
|
||||
#define OB_PCROP2_PAGES640TO655 ((uint32_t)0x00000100U) /* PC Read/Write protection of Sector40 */
|
||||
#define OB_PCROP2_PAGES656TO671 ((uint32_t)0x00000200U) /* PC Read/Write protection of Sector41 */
|
||||
#define OB_PCROP2_PAGES672TO687 ((uint32_t)0x00000400U) /* PC Read/Write protection of Sector42 */
|
||||
#define OB_PCROP2_PAGES688TO703 ((uint32_t)0x00000800U) /* PC Read/Write protection of Sector43 */
|
||||
#define OB_PCROP2_PAGES704TO719 ((uint32_t)0x00001000U) /* PC Read/Write protection of Sector44 */
|
||||
#define OB_PCROP2_PAGES720TO735 ((uint32_t)0x00002000U) /* PC Read/Write protection of Sector45 */
|
||||
#define OB_PCROP2_PAGES736TO751 ((uint32_t)0x00004000U) /* PC Read/Write protection of Sector46 */
|
||||
#define OB_PCROP2_PAGES752TO767 ((uint32_t)0x00008000U) /* PC Read/Write protection of Sector47 */
|
||||
#define OB_PCROP2_PAGES768TO783 ((uint32_t)0x00010000U) /* PC Read/Write protection of Sector48 */
|
||||
#define OB_PCROP2_PAGES784TO799 ((uint32_t)0x00020000U) /* PC Read/Write protection of Sector49 */
|
||||
#define OB_PCROP2_PAGES800TO815 ((uint32_t)0x00040000U) /* PC Read/Write protection of Sector50 */
|
||||
#define OB_PCROP2_PAGES816TO831 ((uint32_t)0x00080000U) /* PC Read/Write protection of Sector51 */
|
||||
#define OB_PCROP2_PAGES832TO847 ((uint32_t)0x00100000U) /* PC Read/Write protection of Sector52 */
|
||||
#define OB_PCROP2_PAGES848TO863 ((uint32_t)0x00200000U) /* PC Read/Write protection of Sector53 */
|
||||
#define OB_PCROP2_PAGES864TO879 ((uint32_t)0x00400000U) /* PC Read/Write protection of Sector54 */
|
||||
#define OB_PCROP2_PAGES880TO895 ((uint32_t)0x00800000U) /* PC Read/Write protection of Sector55 */
|
||||
#define OB_PCROP2_PAGES896TO911 ((uint32_t)0x01000000U) /* PC Read/Write protection of Sector56 */
|
||||
#define OB_PCROP2_PAGES912TO927 ((uint32_t)0x02000000U) /* PC Read/Write protection of Sector57 */
|
||||
#define OB_PCROP2_PAGES928TO943 ((uint32_t)0x04000000U) /* PC Read/Write protection of Sector58 */
|
||||
#define OB_PCROP2_PAGES944TO959 ((uint32_t)0x08000000U) /* PC Read/Write protection of Sector59 */
|
||||
#define OB_PCROP2_PAGES960TO975 ((uint32_t)0x10000000U) /* PC Read/Write protection of Sector60 */
|
||||
#define OB_PCROP2_PAGES976TO991 ((uint32_t)0x20000000U) /* PC Read/Write protection of Sector61 */
|
||||
#define OB_PCROP2_PAGES992TO1007 ((uint32_t)0x40000000U) /* PC Read/Write protection of Sector62 */
|
||||
#define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* PC Read/Write protection of Sector63 */
|
||||
#define OB_PCROP2_PAGES512TO527 (0x00000001U) /* PC Read/Write protection of Sector32 */
|
||||
#define OB_PCROP2_PAGES528TO543 (0x00000002U) /* PC Read/Write protection of Sector33 */
|
||||
#define OB_PCROP2_PAGES544TO559 (0x00000004U) /* PC Read/Write protection of Sector34 */
|
||||
#define OB_PCROP2_PAGES560TO575 (0x00000008U) /* PC Read/Write protection of Sector35 */
|
||||
#define OB_PCROP2_PAGES576TO591 (0x00000010U) /* PC Read/Write protection of Sector36 */
|
||||
#define OB_PCROP2_PAGES592TO607 (0x00000020U) /* PC Read/Write protection of Sector37 */
|
||||
#define OB_PCROP2_PAGES608TO623 (0x00000040U) /* PC Read/Write protection of Sector38 */
|
||||
#define OB_PCROP2_PAGES624TO639 (0x00000080U) /* PC Read/Write protection of Sector39 */
|
||||
#define OB_PCROP2_PAGES640TO655 (0x00000100U) /* PC Read/Write protection of Sector40 */
|
||||
#define OB_PCROP2_PAGES656TO671 (0x00000200U) /* PC Read/Write protection of Sector41 */
|
||||
#define OB_PCROP2_PAGES672TO687 (0x00000400U) /* PC Read/Write protection of Sector42 */
|
||||
#define OB_PCROP2_PAGES688TO703 (0x00000800U) /* PC Read/Write protection of Sector43 */
|
||||
#define OB_PCROP2_PAGES704TO719 (0x00001000U) /* PC Read/Write protection of Sector44 */
|
||||
#define OB_PCROP2_PAGES720TO735 (0x00002000U) /* PC Read/Write protection of Sector45 */
|
||||
#define OB_PCROP2_PAGES736TO751 (0x00004000U) /* PC Read/Write protection of Sector46 */
|
||||
#define OB_PCROP2_PAGES752TO767 (0x00008000U) /* PC Read/Write protection of Sector47 */
|
||||
#define OB_PCROP2_PAGES768TO783 (0x00010000U) /* PC Read/Write protection of Sector48 */
|
||||
#define OB_PCROP2_PAGES784TO799 (0x00020000U) /* PC Read/Write protection of Sector49 */
|
||||
#define OB_PCROP2_PAGES800TO815 (0x00040000U) /* PC Read/Write protection of Sector50 */
|
||||
#define OB_PCROP2_PAGES816TO831 (0x00080000U) /* PC Read/Write protection of Sector51 */
|
||||
#define OB_PCROP2_PAGES832TO847 (0x00100000U) /* PC Read/Write protection of Sector52 */
|
||||
#define OB_PCROP2_PAGES848TO863 (0x00200000U) /* PC Read/Write protection of Sector53 */
|
||||
#define OB_PCROP2_PAGES864TO879 (0x00400000U) /* PC Read/Write protection of Sector54 */
|
||||
#define OB_PCROP2_PAGES880TO895 (0x00800000U) /* PC Read/Write protection of Sector55 */
|
||||
#define OB_PCROP2_PAGES896TO911 (0x01000000U) /* PC Read/Write protection of Sector56 */
|
||||
#define OB_PCROP2_PAGES912TO927 (0x02000000U) /* PC Read/Write protection of Sector57 */
|
||||
#define OB_PCROP2_PAGES928TO943 (0x04000000U) /* PC Read/Write protection of Sector58 */
|
||||
#define OB_PCROP2_PAGES944TO959 (0x08000000U) /* PC Read/Write protection of Sector59 */
|
||||
#define OB_PCROP2_PAGES960TO975 (0x10000000U) /* PC Read/Write protection of Sector60 */
|
||||
#define OB_PCROP2_PAGES976TO991 (0x20000000U) /* PC Read/Write protection of Sector61 */
|
||||
#define OB_PCROP2_PAGES992TO1007 (0x40000000U) /* PC Read/Write protection of Sector62 */
|
||||
#define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write protection of Sector63 */
|
||||
|
||||
#define OB_PCROP2_ALLPAGES ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
|
||||
#define OB_PCROP2_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -768,9 +766,9 @@ typedef struct
|
|||
/** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEERASEDATA_BYTE ((uint32_t)0x00U) /*!<Erase byte (8-bit) at a specified address.*/
|
||||
#define FLASH_TYPEERASEDATA_HALFWORD ((uint32_t)0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEERASEDATA_WORD ((uint32_t)0x02U) /*!<Erase a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEERASEDATA_BYTE (0x00U) /*!<Erase byte (8-bit) at a specified address.*/
|
||||
#define FLASH_TYPEERASEDATA_HALFWORD (0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEERASEDATA_WORD (0x02U) /*!<Erase a word (32-bit) at a specified address.*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -779,12 +777,12 @@ typedef struct
|
|||
/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00U) /*!<Program byte (8-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02U) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_FASTBYTE ((uint32_t)0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD ((uint32_t)0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_FASTWORD ((uint32_t)0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_BYTE (0x00U) /*!<Program byte (8-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_FASTBYTE (0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD (0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
|
||||
#define FLASH_TYPEPROGRAMDATA_FASTWORD (0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -799,7 +797,7 @@ typedef struct
|
|||
#define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank 2
|
||||
or Bank 1, depending on the activation of the bank */
|
||||
#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
#define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank1(Default) */
|
||||
|
||||
/**
|
||||
|
|
@ -828,7 +826,7 @@ typedef struct
|
|||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \
|
||||
if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
|
||||
MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Get the FLASH Latency.
|
||||
|
|
@ -863,7 +861,7 @@ typedef struct
|
|||
*/
|
||||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \
|
||||
SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable the FLASH prefetch buffer.
|
||||
|
|
@ -891,7 +889,7 @@ typedef struct
|
|||
#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
|
||||
FLASH->PDKEYR = FLASH_PDKEY2; \
|
||||
SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
|
||||
} while (0)
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
* @brief Disable the Flash Run power down mode.
|
||||
|
|
@ -901,7 +899,7 @@ typedef struct
|
|||
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
|
||||
FLASH->PDKEYR = FLASH_PDKEY2; \
|
||||
CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
|
||||
} while (0)
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash_ramfunc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief FLASH RAMFUNC driver.
|
||||
* This file provides a Flash firmware functions which should be
|
||||
* executed from internal SRAM
|
||||
|
|
@ -32,7 +30,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -195,9 +193,9 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
|
|||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Write 00000000h to the first word of the first program page to erase */
|
||||
*(__IO uint32_t *)Page_Address1 = 0x00000000;
|
||||
*(__IO uint32_t *)Page_Address1 = 0x00000000U;
|
||||
/* Write 00000000h to the first word of the second program page to erase */
|
||||
*(__IO uint32_t *)Page_Address2 = 0x00000000;
|
||||
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
|
@ -243,10 +241,10 @@ __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_A
|
|||
*/
|
||||
__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
|
||||
|
|
@ -269,7 +267,7 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
|
|||
__disable_irq();
|
||||
|
||||
/* Write the first half page directly with 32 different words */
|
||||
while(count < 32)
|
||||
while(count < 32U)
|
||||
{
|
||||
*(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
|
||||
pBuffer1++;
|
||||
|
|
@ -277,8 +275,8 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
|
|||
}
|
||||
|
||||
/* Write the second half page directly with 32 different words */
|
||||
count = 0;
|
||||
while(count < 32)
|
||||
count = 0U;
|
||||
while(count < 32U)
|
||||
{
|
||||
*(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
|
||||
pBuffer2++;
|
||||
|
|
@ -331,10 +329,10 @@ __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuf
|
|||
*/
|
||||
__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
|
||||
|
|
@ -352,18 +350,18 @@ __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
|
|||
__disable_irq();
|
||||
|
||||
/* Write one half page directly with 32 different words */
|
||||
while(count < 32)
|
||||
while(count < 32U)
|
||||
{
|
||||
*(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
|
||||
pBuffer++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Enable IRQs */
|
||||
__enable_irq();
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* Enable IRQs */
|
||||
__enable_irq();
|
||||
|
||||
/* If the write operation is completed, disable the PROG and FPRG bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
|
@ -462,7 +460,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
|
||||
|
|
@ -480,9 +478,9 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
|
|||
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
|
||||
|
||||
/* Write 00000000h to the 2 words to erase */
|
||||
*(__IO uint32_t *)Address = 0x00000000;
|
||||
Address += 4;
|
||||
*(__IO uint32_t *)Address = 0x00000000;
|
||||
*(__IO uint32_t *)Address = 0x00000000U;
|
||||
Address += 4U;
|
||||
*(__IO uint32_t *)Address = 0x00000000U;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
|
@ -520,7 +518,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
|
|||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
|
||||
|
|
@ -536,7 +534,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
|
|||
|
||||
/* Write the 2 words */
|
||||
*(__IO uint32_t *)Address = (uint32_t) Data;
|
||||
Address += 4;
|
||||
Address += 4U;
|
||||
*(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
|
|
@ -571,7 +569,7 @@ __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t D
|
|||
*/
|
||||
static __RAM_FUNC FLASHRAM_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0;
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
|
|
@ -621,12 +619,12 @@ static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
|
|||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00))
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
|
||||
{
|
||||
Timeout--;
|
||||
}
|
||||
|
||||
if(Timeout == 0x00 )
|
||||
if(Timeout == 0x00U)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash_ramfunc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of FLASH RAMFUNC driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
|
|
@ -105,7 +103,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -151,15 +149,15 @@
|
|||
/** @addtogroup GPIO_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE ((uint32_t)0x00000003)
|
||||
#define EXTI_MODE ((uint32_t)0x10000000)
|
||||
#define GPIO_MODE_IT ((uint32_t)0x00010000)
|
||||
#define GPIO_MODE_EVT ((uint32_t)0x00020000)
|
||||
#define RISING_EDGE ((uint32_t)0x00100000)
|
||||
#define FALLING_EDGE ((uint32_t)0x00200000)
|
||||
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
|
||||
#define GPIO_MODE (0x00000003U)
|
||||
#define EXTI_MODE (0x10000000U)
|
||||
#define GPIO_MODE_IT (0x00010000U)
|
||||
#define GPIO_MODE_EVT (0x00020000U)
|
||||
#define RISING_EDGE (0x00100000U)
|
||||
#define FALLING_EDGE (0x00200000U)
|
||||
#define GPIO_OUTPUT_TYPE (0x00000010U)
|
||||
|
||||
#define GPIO_NUMBER ((uint32_t)16)
|
||||
#define GPIO_NUMBER (16U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -209,7 +207,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
while (((GPIO_Init->Pin) >> position) != 0)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & ((uint32_t)1 << position);
|
||||
iocurrent = (GPIO_Init->Pin) & (1U << position);
|
||||
|
||||
if(iocurrent)
|
||||
{
|
||||
|
|
@ -224,8 +222,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
/* Configure Alternate function mapped with the current IO */
|
||||
/* Identify AFRL or AFRH register based on IO position*/
|
||||
temp = GPIOx->AFR[position >> 3];
|
||||
CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
|
||||
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
|
||||
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
|
||||
GPIOx->AFR[position >> 3] = temp;
|
||||
}
|
||||
|
||||
|
|
@ -268,7 +266,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2];
|
||||
CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
|
||||
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
|
||||
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
|
||||
SYSCFG->EXTICR[position >> 2] = temp;
|
||||
|
||||
|
|
@ -333,7 +331,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
while ((GPIO_Pin >> position) != 0)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
|
||||
iocurrent = (GPIO_Pin) & (1U << position);
|
||||
|
||||
if (iocurrent)
|
||||
{
|
||||
|
|
@ -342,7 +340,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
|
||||
CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
|
|
@ -357,10 +355,10 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
|||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2];
|
||||
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
|
||||
tmp &= ((0x0FU) << (4 * (position & 0x03)));
|
||||
if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
|
||||
{
|
||||
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
|
||||
tmp = (0x0FU) << (4 * (position & 0x03));
|
||||
CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of GPIO HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -103,25 +101,25 @@ typedef enum
|
|||
/** @defgroup GPIO_pins GPIO pins
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
|
||||
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
|
||||
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
|
||||
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
|
||||
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
|
||||
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
|
||||
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
|
||||
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
|
||||
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
|
||||
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
|
||||
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
|
||||
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
|
||||
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
|
||||
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
|
||||
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
|
||||
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
|
||||
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
|
||||
|
||||
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
|
||||
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -136,21 +134,21 @@ typedef enum
|
|||
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
|
||||
#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */
|
||||
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */
|
||||
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */
|
||||
#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */
|
||||
#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */
|
||||
|
||||
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
|
||||
#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */
|
||||
|
||||
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
|
||||
#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
|
||||
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -160,10 +158,10 @@ typedef enum
|
|||
* @brief GPIO Output Maximum frequency
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< max: 400 KHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */
|
||||
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -173,9 +171,9 @@ typedef enum
|
|||
* @brief GPIO Pull-Up or Pull-Down Activation
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
|
||||
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
|
||||
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
|
||||
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -201,8 +199,8 @@ typedef enum
|
|||
|
||||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
|
||||
|
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
|
||||
(((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
|
||||
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
|
||||
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
|
||||
|
||||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
|
||||
((PULL) == GPIO_PULLDOWN))
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_gpio_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of GPIO HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_i2c.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief I2C HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
|
||||
|
|
@ -211,7 +209,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -257,12 +255,12 @@
|
|||
/** @defgroup I2C_Private_Define I2C Private Define
|
||||
* @{
|
||||
*/
|
||||
#define I2C_TIMEOUT_FLAG ((uint32_t)35U) /*!< Timeout 35 ms */
|
||||
#define I2C_TIMEOUT_ADDR_SLAVE ((uint32_t)10000U) /*!< Timeout 10 s */
|
||||
#define I2C_TIMEOUT_BUSY_FLAG ((uint32_t)25U) /*!< Timeout 25 ms */
|
||||
#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
|
||||
#define I2C_TIMEOUT_FLAG (35U) /*!< Timeout 35 ms */
|
||||
#define I2C_TIMEOUT_ADDR_SLAVE (10000U) /*!< Timeout 10 s */
|
||||
#define I2C_TIMEOUT_BUSY_FLAG (25U) /*!< Timeout 25 ms */
|
||||
#define I2C_NO_OPTION_FRAME (0xFFFF0000U) /*!< XferOptions default value */
|
||||
|
||||
#define I2C_MIN_PCLK_FREQ ((uint32_t)2000000U) /*!< 2 MHz */
|
||||
#define I2C_MIN_PCLK_FREQ (2000000U) /*!< 2 MHz */
|
||||
|
||||
/* Private define for @ref PreviousState usage */
|
||||
#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits */
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of I2C HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -179,13 +177,13 @@ typedef enum
|
|||
* @brief I2C Error Code definition
|
||||
* @{
|
||||
*/
|
||||
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< AF error */
|
||||
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout Error */
|
||||
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
|
||||
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
|
||||
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
|
||||
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< AF error */
|
||||
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
|
||||
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
|
||||
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout Error */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -248,7 +246,7 @@ typedef struct
|
|||
/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUTYCYCLE_2 ((uint32_t)0x00000000U)
|
||||
#define I2C_DUTYCYCLE_2 (0x00000000U)
|
||||
#define I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -257,8 +255,8 @@ typedef struct
|
|||
/** @defgroup I2C_addressing_mode I2C addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00004000U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
|
||||
#define I2C_ADDRESSINGMODE_7BIT (0x00004000U)
|
||||
#define I2C_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | (0x00004000U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -266,7 +264,7 @@ typedef struct
|
|||
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
|
||||
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -275,7 +273,7 @@ typedef struct
|
|||
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_GENERALCALL_DISABLE (0x00000000U)
|
||||
#define I2C_GENERALCALL_ENABLE I2C_CR1_ENGC
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -284,7 +282,7 @@ typedef struct
|
|||
/** @defgroup I2C_nostretch_mode I2C nostretch mode
|
||||
* @{
|
||||
*/
|
||||
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
|
||||
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
|
||||
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -293,8 +291,8 @@ typedef struct
|
|||
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
|
||||
* @{
|
||||
*/
|
||||
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000010U)
|
||||
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
|
||||
#define I2C_MEMADD_SIZE_16BIT (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -302,8 +300,8 @@ typedef struct
|
|||
/** @defgroup I2C_XferDirection_definition I2C XferDirection definition Master Point of View
|
||||
* @{
|
||||
*/
|
||||
#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000000U)
|
||||
#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000001U)
|
||||
#define I2C_DIRECTION_RECEIVE (0x00000000U)
|
||||
#define I2C_DIRECTION_TRANSMIT (0x00000001U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -311,10 +309,10 @@ typedef struct
|
|||
/** @defgroup I2C_XferOptions_definition I2C XferOptions definition
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FIRST_FRAME ((uint32_t)0x00000001U)
|
||||
#define I2C_NEXT_FRAME ((uint32_t)0x00000002U)
|
||||
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)0x00000004U)
|
||||
#define I2C_LAST_FRAME ((uint32_t)0x00000008U)
|
||||
#define I2C_FIRST_FRAME (0x00000001U)
|
||||
#define I2C_NEXT_FRAME (0x00000002U)
|
||||
#define I2C_FIRST_AND_LAST_FRAME (0x00000004U)
|
||||
#define I2C_LAST_FRAME (0x00000008U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -581,7 +579,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
|||
/** @defgroup I2C_Private_Constants I2C Private Constants
|
||||
* @{
|
||||
*/
|
||||
#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU)
|
||||
#define I2C_FLAG_MASK (0x0000FFFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_i2s.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief I2S HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
|
||||
|
|
@ -108,7 +106,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -279,7 +277,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
|
|||
tmp = tmp / 10;
|
||||
|
||||
/* Check the parity of the divider */
|
||||
i2sodd = (uint32_t)(tmp & (uint32_t)1);
|
||||
i2sodd = (uint32_t)(tmp & 1U);
|
||||
|
||||
/* Compute the i2sdiv prescaler */
|
||||
i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_i2s.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of I2S HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -153,11 +151,11 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */
|
||||
#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */
|
||||
#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */
|
||||
#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */
|
||||
#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */
|
||||
#define HAL_I2S_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_I2S_ERROR_UDR (0x01U) /*!< I2S Underrun error */
|
||||
#define HAL_I2S_ERROR_OVR (0x02U) /*!< I2S Overrun error */
|
||||
#define HAL_I2S_ERROR_FRE (0x04U) /*!< I2S Frame format error */
|
||||
#define HAL_I2S_ERROR_DMA (0x08U) /*!< DMA transfer error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -166,10 +164,10 @@ typedef struct
|
|||
/** @defgroup I2S_Mode I2S Mode
|
||||
* @{
|
||||
*/
|
||||
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
|
||||
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
|
||||
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
|
||||
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
|
||||
#define I2S_MODE_SLAVE_TX (0x00000000U)
|
||||
#define I2S_MODE_SLAVE_RX (0x00000100U)
|
||||
#define I2S_MODE_MASTER_TX (0x00000200U)
|
||||
#define I2S_MODE_MASTER_RX (0x00000300U)
|
||||
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
|
||||
((MODE) == I2S_MODE_SLAVE_RX) || \
|
||||
|
|
@ -182,7 +180,7 @@ typedef struct
|
|||
/** @defgroup I2S_Standard I2S Standard
|
||||
* @{
|
||||
*/
|
||||
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
|
||||
#define I2S_STANDARD_PHILIPS (0x00000000U)
|
||||
#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
|
||||
#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
|
||||
#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
|
||||
|
|
@ -204,7 +202,7 @@ typedef struct
|
|||
/** @defgroup I2S_Data_Format I2S Data Format
|
||||
* @{
|
||||
*/
|
||||
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
|
||||
#define I2S_DATAFORMAT_16B (0x00000000U)
|
||||
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN)
|
||||
#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
|
||||
#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
|
||||
|
|
@ -221,7 +219,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
|
||||
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
|
||||
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
|
||||
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
|
||||
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
|
||||
|
|
@ -232,16 +230,16 @@ typedef struct
|
|||
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
|
||||
* @{
|
||||
*/
|
||||
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
|
||||
#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
|
||||
#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
|
||||
#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
|
||||
#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
|
||||
#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
|
||||
#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
|
||||
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
|
||||
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
|
||||
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
|
||||
#define I2S_AUDIOFREQ_192K (192000U)
|
||||
#define I2S_AUDIOFREQ_96K (96000U)
|
||||
#define I2S_AUDIOFREQ_48K (48000U)
|
||||
#define I2S_AUDIOFREQ_44K (44100U)
|
||||
#define I2S_AUDIOFREQ_32K (32000U)
|
||||
#define I2S_AUDIOFREQ_22K (22050U)
|
||||
#define I2S_AUDIOFREQ_16K (16000U)
|
||||
#define I2S_AUDIOFREQ_11K (11025U)
|
||||
#define I2S_AUDIOFREQ_8K (8000U)
|
||||
#define I2S_AUDIOFREQ_DEFAULT (2U)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
|
||||
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
|
||||
|
|
@ -253,7 +251,7 @@ typedef struct
|
|||
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
|
||||
* @{
|
||||
*/
|
||||
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
|
||||
#define I2S_CPOL_LOW (0x00000000U)
|
||||
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
|
||||
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_irda.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief IRDA HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the IrDA SIR ENDEC block (IrDA):
|
||||
|
|
@ -103,7 +101,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_irda.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief This file contains all the functions prototypes for the IRDA
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -154,12 +152,12 @@ typedef struct
|
|||
/** @defgroup IRDA_Error_Codes IRDA Error Codes
|
||||
* @{
|
||||
*/
|
||||
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
|
||||
#define HAL_IRDA_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_IRDA_ERROR_PE (0x01U) /*!< Parity error */
|
||||
#define HAL_IRDA_ERROR_NE (0x02U) /*!< Noise error */
|
||||
#define HAL_IRDA_ERROR_FE (0x04U) /*!< frame error */
|
||||
#define HAL_IRDA_ERROR_ORE (0x08U) /*!< Overrun error */
|
||||
#define HAL_IRDA_ERROR_DMA (0x10U) /*!< DMA transfer error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -169,7 +167,7 @@ typedef struct
|
|||
/** @defgroup IRDA_Word_Length IRDA Word Length
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
|
||||
#define IRDA_WORDLENGTH_8B (0x00000000U)
|
||||
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -178,7 +176,7 @@ typedef struct
|
|||
/** @defgroup IRDA_Parity IRDA Parity
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_PARITY_NONE ((uint32_t)0x00000000)
|
||||
#define IRDA_PARITY_NONE (0x00000000U)
|
||||
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
|
||||
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
|
||||
/**
|
||||
|
|
@ -199,7 +197,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
|
||||
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000)
|
||||
#define IRDA_POWERMODE_NORMAL (0x00000000U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -207,7 +205,7 @@ typedef struct
|
|||
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
|
||||
* @{
|
||||
*/
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
|
||||
#define IRDA_ONE_BIT_SAMPLE_DISABLE (0x00000000U)
|
||||
#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -485,7 +483,7 @@ do{ \
|
|||
((PARITY) == IRDA_PARITY_ODD))
|
||||
|
||||
#define IS_IRDA_MODE(MODE) ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \
|
||||
((MODE) != (uint32_t)0x00000000))
|
||||
((MODE) != 0x00000000U))
|
||||
|
||||
#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
|
||||
((MODE) == IRDA_POWERMODE_NORMAL))
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief IWDG HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent Watchdog (IWDG) peripheral:
|
||||
|
|
@ -75,7 +73,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of IWDG HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_lcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief LCD Controller HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the LCD Controller (LCD) peripheral:
|
||||
|
|
@ -63,7 +61,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_lcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of LCD Controller HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -139,12 +137,12 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */
|
||||
#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */
|
||||
#define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */
|
||||
#define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */
|
||||
#define HAL_LCD_ERROR_NONE (0x00U) /*!< No error */
|
||||
#define HAL_LCD_ERROR_FCRSF (0x01U) /*!< Synchro flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDR (0x02U) /*!< Update display request flag timeout error */
|
||||
#define HAL_LCD_ERROR_UDD (0x04U) /*!< Update display done flag timeout error */
|
||||
#define HAL_LCD_ERROR_ENS (0x08U) /*!< LCD enabled status flag timeout error */
|
||||
#define HAL_LCD_ERROR_RDY (0x10U) /*!< LCD Booster ready timeout error */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -154,21 +152,21 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_PRESCALER_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */
|
||||
#define LCD_PRESCALER_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */
|
||||
#define LCD_PRESCALER_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */
|
||||
#define LCD_PRESCALER_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */
|
||||
#define LCD_PRESCALER_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */
|
||||
#define LCD_PRESCALER_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */
|
||||
#define LCD_PRESCALER_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */
|
||||
#define LCD_PRESCALER_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */
|
||||
#define LCD_PRESCALER_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */
|
||||
#define LCD_PRESCALER_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */
|
||||
#define LCD_PRESCALER_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */
|
||||
#define LCD_PRESCALER_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */
|
||||
#define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */
|
||||
#define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */
|
||||
#define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */
|
||||
#define LCD_PRESCALER_1 (0x00000000U) /*!< CLKPS = LCDCLK */
|
||||
#define LCD_PRESCALER_2 (0x00400000U) /*!< CLKPS = LCDCLK/2 */
|
||||
#define LCD_PRESCALER_4 (0x00800000U) /*!< CLKPS = LCDCLK/4 */
|
||||
#define LCD_PRESCALER_8 (0x00C00000U) /*!< CLKPS = LCDCLK/8 */
|
||||
#define LCD_PRESCALER_16 (0x01000000U) /*!< CLKPS = LCDCLK/16 */
|
||||
#define LCD_PRESCALER_32 (0x01400000U) /*!< CLKPS = LCDCLK/32 */
|
||||
#define LCD_PRESCALER_64 (0x01800000U) /*!< CLKPS = LCDCLK/64 */
|
||||
#define LCD_PRESCALER_128 (0x01C00000U) /*!< CLKPS = LCDCLK/128 */
|
||||
#define LCD_PRESCALER_256 (0x02000000U) /*!< CLKPS = LCDCLK/256 */
|
||||
#define LCD_PRESCALER_512 (0x02400000U) /*!< CLKPS = LCDCLK/512 */
|
||||
#define LCD_PRESCALER_1024 (0x02800000U) /*!< CLKPS = LCDCLK/1024 */
|
||||
#define LCD_PRESCALER_2048 (0x02C00000U) /*!< CLKPS = LCDCLK/2048 */
|
||||
#define LCD_PRESCALER_4096 (0x03000000U) /*!< CLKPS = LCDCLK/4096 */
|
||||
#define LCD_PRESCALER_8192 (0x03400000U) /*!< CLKPS = LCDCLK/8192 */
|
||||
#define LCD_PRESCALER_16384 (0x03800000U) /*!< CLKPS = LCDCLK/16384 */
|
||||
#define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */
|
||||
|
||||
#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \
|
||||
|
|
@ -196,21 +194,21 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_DIVIDER_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */
|
||||
#define LCD_DIVIDER_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */
|
||||
#define LCD_DIVIDER_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */
|
||||
#define LCD_DIVIDER_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */
|
||||
#define LCD_DIVIDER_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */
|
||||
#define LCD_DIVIDER_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */
|
||||
#define LCD_DIVIDER_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */
|
||||
#define LCD_DIVIDER_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */
|
||||
#define LCD_DIVIDER_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */
|
||||
#define LCD_DIVIDER_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */
|
||||
#define LCD_DIVIDER_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */
|
||||
#define LCD_DIVIDER_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */
|
||||
#define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */
|
||||
#define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */
|
||||
#define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */
|
||||
#define LCD_DIVIDER_16 (0x00000000U) /*!< LCD frequency = CLKPS/16 */
|
||||
#define LCD_DIVIDER_17 (0x00040000U) /*!< LCD frequency = CLKPS/17 */
|
||||
#define LCD_DIVIDER_18 (0x00080000U) /*!< LCD frequency = CLKPS/18 */
|
||||
#define LCD_DIVIDER_19 (0x000C0000U) /*!< LCD frequency = CLKPS/19 */
|
||||
#define LCD_DIVIDER_20 (0x00100000U) /*!< LCD frequency = CLKPS/20 */
|
||||
#define LCD_DIVIDER_21 (0x00140000U) /*!< LCD frequency = CLKPS/21 */
|
||||
#define LCD_DIVIDER_22 (0x00180000U) /*!< LCD frequency = CLKPS/22 */
|
||||
#define LCD_DIVIDER_23 (0x001C0000U) /*!< LCD frequency = CLKPS/23 */
|
||||
#define LCD_DIVIDER_24 (0x00200000U) /*!< LCD frequency = CLKPS/24 */
|
||||
#define LCD_DIVIDER_25 (0x00240000U) /*!< LCD frequency = CLKPS/25 */
|
||||
#define LCD_DIVIDER_26 (0x00280000U) /*!< LCD frequency = CLKPS/26 */
|
||||
#define LCD_DIVIDER_27 (0x002C0000U) /*!< LCD frequency = CLKPS/27 */
|
||||
#define LCD_DIVIDER_28 (0x00300000U) /*!< LCD frequency = CLKPS/28 */
|
||||
#define LCD_DIVIDER_29 (0x00340000U) /*!< LCD frequency = CLKPS/29 */
|
||||
#define LCD_DIVIDER_30 (0x00380000U) /*!< LCD frequency = CLKPS/30 */
|
||||
#define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
|
||||
|
||||
#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
|
||||
|
|
@ -239,7 +237,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */
|
||||
#define LCD_DUTY_STATIC (0x00000000U) /*!< Static duty */
|
||||
#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */
|
||||
#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */
|
||||
#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */
|
||||
|
|
@ -260,7 +258,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_BIAS_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */
|
||||
#define LCD_BIAS_1_4 (0x00000000U) /*!< 1/4 Bias */
|
||||
#define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
|
||||
#define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
|
||||
|
||||
|
|
@ -275,7 +273,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_VOLTAGESOURCE_INTERNAL ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */
|
||||
#define LCD_VOLTAGESOURCE_INTERNAL (0x00000000U) /*!< Internal voltage source for the LCD */
|
||||
#define LCD_VOLTAGESOURCE_EXTERNAL LCD_CR_VSEL /*!< External voltage source for the LCD */
|
||||
|
||||
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
|
||||
|
|
@ -299,7 +297,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */
|
||||
#define LCD_PULSEONDURATION_0 (0x00000000U) /*!< Pulse ON duration = 0 pulse */
|
||||
#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */
|
||||
#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */
|
||||
#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */
|
||||
|
|
@ -324,7 +322,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000) /*!< Low resistance Drive */
|
||||
#define LCD_HIGHDRIVE_0 (0x00000000U) /*!< Low resistance Drive */
|
||||
#define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */
|
||||
|
||||
#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
|
||||
|
|
@ -337,7 +335,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */
|
||||
#define LCD_DEADTIME_0 (0x00000000U) /*!< No dead Time */
|
||||
#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */
|
||||
#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
|
||||
|
|
@ -362,7 +360,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */
|
||||
#define LCD_BLINKMODE_OFF (0x00000000U) /*!< Blink disabled */
|
||||
#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
|
||||
#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to
|
||||
8 pixels according to the programmed duty) */
|
||||
|
|
@ -380,7 +378,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */
|
||||
#define LCD_BLINKFREQUENCY_DIV8 (0x00000000U) /*!< The Blink frequency = fLCD/8 */
|
||||
#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */
|
||||
#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */
|
||||
#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */
|
||||
|
|
@ -405,7 +403,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */
|
||||
#define LCD_CONTRASTLEVEL_0 (0x00000000U) /*!< Maximum Voltage = 2.60V */
|
||||
#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */
|
||||
#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */
|
||||
#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */
|
||||
|
|
@ -430,7 +428,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_MUXSEGMENT_DISABLE ((uint32_t)0x00000000) /*!< SEG pin multiplexing disabled */
|
||||
#define LCD_MUXSEGMENT_DISABLE (0x00000000U) /*!< SEG pin multiplexing disabled */
|
||||
#define LCD_MUXSEGMENT_ENABLE (LCD_CR_MUX_SEG) /*!< SEG[31:28] are multiplexed with SEG[43:40] */
|
||||
|
||||
#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
|
||||
|
|
@ -458,22 +456,22 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_RAM_REGISTER0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */
|
||||
#define LCD_RAM_REGISTER1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */
|
||||
#define LCD_RAM_REGISTER2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */
|
||||
#define LCD_RAM_REGISTER3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */
|
||||
#define LCD_RAM_REGISTER4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */
|
||||
#define LCD_RAM_REGISTER5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */
|
||||
#define LCD_RAM_REGISTER6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */
|
||||
#define LCD_RAM_REGISTER7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */
|
||||
#define LCD_RAM_REGISTER8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */
|
||||
#define LCD_RAM_REGISTER9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */
|
||||
#define LCD_RAM_REGISTER10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
|
||||
#define LCD_RAM_REGISTER11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
|
||||
#define LCD_RAM_REGISTER12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
|
||||
#define LCD_RAM_REGISTER13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
|
||||
#define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
|
||||
#define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
|
||||
#define LCD_RAM_REGISTER0 (0x00000000U) /*!< LCD RAM Register 0 */
|
||||
#define LCD_RAM_REGISTER1 (0x00000001U) /*!< LCD RAM Register 1 */
|
||||
#define LCD_RAM_REGISTER2 (0x00000002U) /*!< LCD RAM Register 2 */
|
||||
#define LCD_RAM_REGISTER3 (0x00000003U) /*!< LCD RAM Register 3 */
|
||||
#define LCD_RAM_REGISTER4 (0x00000004U) /*!< LCD RAM Register 4 */
|
||||
#define LCD_RAM_REGISTER5 (0x00000005U) /*!< LCD RAM Register 5 */
|
||||
#define LCD_RAM_REGISTER6 (0x00000006U) /*!< LCD RAM Register 6 */
|
||||
#define LCD_RAM_REGISTER7 (0x00000007U) /*!< LCD RAM Register 7 */
|
||||
#define LCD_RAM_REGISTER8 (0x00000008U) /*!< LCD RAM Register 8 */
|
||||
#define LCD_RAM_REGISTER9 (0x00000009U) /*!< LCD RAM Register 9 */
|
||||
#define LCD_RAM_REGISTER10 (0x0000000AU) /*!< LCD RAM Register 10 */
|
||||
#define LCD_RAM_REGISTER11 (0x0000000BU) /*!< LCD RAM Register 11 */
|
||||
#define LCD_RAM_REGISTER12 (0x0000000CU) /*!< LCD RAM Register 12 */
|
||||
#define LCD_RAM_REGISTER13 (0x0000000DU) /*!< LCD RAM Register 13 */
|
||||
#define LCD_RAM_REGISTER14 (0x0000000EU) /*!< LCD RAM Register 14 */
|
||||
#define LCD_RAM_REGISTER15 (0x0000000FU) /*!< LCD RAM Register 15 */
|
||||
|
||||
#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \
|
||||
((__REGISTER__) == LCD_RAM_REGISTER1) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_nor.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief NOR HAL module driver.
|
||||
* This file provides a generic firmware to drive NOR memories mounted
|
||||
* as external device.
|
||||
|
|
@ -55,7 +53,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_nor.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of NOR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_opamp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief OPAMP HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc)
|
||||
|
|
@ -138,7 +136,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of OPAMP HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -174,15 +172,15 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
/**
|
||||
* CSR register Mask
|
||||
*/
|
||||
#define OPAMP_CSR_INSTANCE_OFFSET ((uint32_t) 8) /* Offset of each OPAMP instance into register CSR */
|
||||
#define OPAMP_OTR_INSTANCE_OFFSET ((uint32_t) 10) /* Offset of each OPAMP instance into register OTR */
|
||||
#define OPAMP_CSR_INSTANCE_OFFSET ( 8U) /* Offset of each OPAMP instance into register CSR */
|
||||
#define OPAMP_OTR_INSTANCE_OFFSET (10U) /* Offset of each OPAMP instance into register OTR */
|
||||
|
||||
|
||||
/** @defgroup OPAMP_Mode OPAMP Mode
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< OPAMP standalone mode */
|
||||
#define OPAMP_FOLLOWER_MODE ((uint32_t)0x00000001) /*!< OPAMP follower mode */
|
||||
#define OPAMP_STANDALONE_MODE (0x00000000U) /*!< OPAMP standalone mode */
|
||||
#define OPAMP_FOLLOWER_MODE (0x00000001U) /*!< OPAMP follower mode */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -191,9 +189,9 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
/** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */
|
||||
#define OPAMP_NONINVERTINGINPUT_DAC_CH1 ((uint32_t)0x00000001) /*!< Comparator non-inverting input connected internally to DAC channel 1. Available only on OPAMP1 and OPAMP2. */
|
||||
#define OPAMP_NONINVERTINGINPUT_DAC_CH2 ((uint32_t)0x00000002) /*!< Comparator non-inverting input connected internally to DAC channel 2. Available only on OPAMP2 and OPAMP3 (OPAMP3 availability depends on STM32L1 devices). */
|
||||
#define OPAMP_NONINVERTINGINPUT_IO0 (0x00000000U) /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */
|
||||
#define OPAMP_NONINVERTINGINPUT_DAC_CH1 (0x00000001U) /*!< Comparator non-inverting input connected internally to DAC channel 1. Available only on OPAMP1 and OPAMP2. */
|
||||
#define OPAMP_NONINVERTINGINPUT_DAC_CH2 (0x00000002U) /*!< Comparator non-inverting input connected internally to DAC channel 2. Available only on OPAMP2 and OPAMP3 (OPAMP3 availability depends on STM32L1 devices). */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -203,8 +201,8 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
* @{
|
||||
*/
|
||||
/* Note: Literal "OPAMP_SEC_INVERTINGINPUT_IO1" is a legacy naming of "OPAMP_INVERTINGINPUT_IO1". It is equivalent and must be replaced by "OPAMP_INVERTINGINPUT_IO1". */
|
||||
#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< Comparator inverting input connected to dedicated IO pin low-leakage */
|
||||
#define OPAMP_INVERTINGINPUT_IO1 ((uint32_t)0x00000001) /*!< Comparator inverting input connected to alternative IO pin available on some device packages */
|
||||
#define OPAMP_INVERTINGINPUT_IO0 (0x00000000U) /*!< Comparator inverting input connected to dedicated IO pin low-leakage */
|
||||
#define OPAMP_INVERTINGINPUT_IO1 (0x00000001U) /*!< Comparator inverting input connected to alternative IO pin available on some device packages */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -213,8 +211,8 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
/** @defgroup OPAMP_PowerMode OPAMP PowerMode
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
|
||||
#define OPAMP_POWERMODE_LOWPOWER ((uint32_t)0x00000001)
|
||||
#define OPAMP_POWERMODE_NORMAL (0x00000000U)
|
||||
#define OPAMP_POWERMODE_LOWPOWER (0x00000001U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -223,7 +221,7 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_POWERSUPPLY_LOW ((uint32_t)0x00000000) /*!< Power supply range low (VDDA lower than 2.4V) */
|
||||
#define OPAMP_POWERSUPPLY_LOW (0x00000000U) /*!< Power supply range low (VDDA lower than 2.4V) */
|
||||
#define OPAMP_POWERSUPPLY_HIGH OPAMP_CSR_AOP_RANGE /*!< Power supply range high (VDDA higher than 2.4V) */
|
||||
|
||||
/**
|
||||
|
|
@ -233,8 +231,8 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
|
||||
#define OPAMP_TRIMMING_USER OPAMP_OTR_OT_USER /*!< User trimming */
|
||||
#define OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< Factory trimming */
|
||||
#define OPAMP_TRIMMING_USER OPAMP_OTR_OT_USER /*!< User trimming */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -243,9 +241,9 @@ typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
|
|||
/** @defgroup OPAMP_FactoryTrimming OPAMP FactoryTrimming
|
||||
* @{
|
||||
*/
|
||||
#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */
|
||||
#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFU) /*!< Dummy value if trimming value could not be retrieved */
|
||||
|
||||
#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000000) /*!< Offset trimming P */
|
||||
#define OPAMP_FACTORYTRIMMING_P (0x00000000U) /*!< Offset trimming P */
|
||||
#define OPAMP_FACTORYTRIMMING_N POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_opamp_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended OPAMP HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
@ -15,7 +13,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_opamp_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of OPAMP HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief PCD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
|
|
@ -44,7 +42,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -195,19 +193,19 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
|
|||
/*Clear pending interrupts*/
|
||||
hpcd->Instance->ISTR = 0;
|
||||
|
||||
/*Set Btable Adress*/
|
||||
/*Set Btable Adress*/
|
||||
hpcd->Instance->BTABLE = BTABLE_ADDRESS;
|
||||
|
||||
/*set wInterrupt_Mask global variable*/
|
||||
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
|
||||
| USB_CNTR_ESOFM | USB_CNTR_RESETM;
|
||||
|
||||
/*Set interrupt mask*/
|
||||
hpcd->Instance->CNTR = wInterrupt_Mask;
|
||||
|
||||
hpcd->USB_Address = 0;
|
||||
hpcd->State= HAL_PCD_STATE_READY;
|
||||
|
||||
|
||||
/*set wInterrupt_Mask global variable*/
|
||||
wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
|
||||
| USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
|
||||
|
||||
/*Set interrupt mask*/
|
||||
hpcd->Instance->CNTR = wInterrupt_Mask;
|
||||
|
||||
hpcd->USB_Address = 0;
|
||||
hpcd->State= HAL_PCD_STATE_READY;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -413,8 +411,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
/* Process Control Data OUT Packet*/
|
||||
HAL_PCD_DataOutStageCallback(hpcd, 0);
|
||||
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -442,7 +440,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
else
|
||||
{
|
||||
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
|
||||
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
|
||||
{
|
||||
/*read from endpoint BUF0Addr buffer*/
|
||||
count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
||||
|
|
@ -460,7 +458,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
|
||||
}
|
||||
}
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)
|
||||
}
|
||||
/*multi-packet on the NON control OUT endpoint*/
|
||||
ep->xfer_count+=count;
|
||||
|
|
@ -496,7 +494,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
}
|
||||
else
|
||||
{
|
||||
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
|
||||
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
|
||||
{
|
||||
/*read from endpoint BUF0Addr buffer*/
|
||||
ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
|
||||
|
|
@ -514,7 +512,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
|
||||
}
|
||||
}
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)
|
||||
}
|
||||
/*multi-packet on the NON control IN endpoint*/
|
||||
ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
|
||||
|
|
@ -546,15 +544,17 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
|
|||
*/
|
||||
static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1; /* n = (wNBytes + 1) / 2 */
|
||||
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
|
||||
|
||||
uint32_t i, temp1, temp2;
|
||||
uint16_t *pdwVal;
|
||||
pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
|
||||
pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
|
||||
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
temp1 = (uint16_t) * pbUsrBuf;
|
||||
pbUsrBuf++;
|
||||
temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
|
||||
temp2 = temp1 | ((uint16_t)((uint16_t) * pbUsrBuf << 8U)) ;
|
||||
*pdwVal++ = temp2;
|
||||
pdwVal++;
|
||||
pbUsrBuf++;
|
||||
|
|
@ -571,13 +571,19 @@ static void PCD_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABuf
|
|||
*/
|
||||
static void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
|
||||
{
|
||||
uint32_t n = (wNBytes + 1) >> 1;/* /2*/
|
||||
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
|
||||
uint32_t i;
|
||||
uint32_t *pdwVal;
|
||||
pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
|
||||
|
||||
pdwVal = (uint32_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
|
||||
uint32_t tmp = *pdwVal++;
|
||||
*pbUsrBuf++ = (uint16_t)((tmp >> 0) & 0xFF);
|
||||
*pbUsrBuf++ = (uint16_t)((tmp >> 8) & 0xFF);
|
||||
|
||||
|
||||
for (i = n; i != 0; i--)
|
||||
{
|
||||
*(uint16_t*)pbUsrBuf++ = *pdwVal++;
|
||||
*(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
|
||||
pbUsrBuf++;
|
||||
}
|
||||
}
|
||||
|
|
@ -971,19 +977,19 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
|
|||
{
|
||||
/*Set the endpoint Transmit buffer address */
|
||||
PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
/* Configure NAK status for the Endpoint*/
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK)
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Set the endpoint Receive buffer address */
|
||||
PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
|
||||
/*Set the endpoint Receive buffer counter*/
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
/* Configure VALID status for the Endpoint*/
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
|
||||
}
|
||||
}
|
||||
/*Double Buffer*/
|
||||
|
|
@ -992,29 +998,29 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
|
|||
/*Set the endpoint as double buffered*/
|
||||
PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
|
||||
/*Set buffer address for double buffered mode*/
|
||||
PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
|
||||
PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
|
||||
|
||||
if (ep->is_in==0)
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
|
||||
/* Reset value of the data toggle bits for the endpoint out*/
|
||||
PCD_TX_DTOG(hpcd->Instance, ep->num);
|
||||
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_RX_DTOG(hpcd->Instance, ep->num);
|
||||
/* Configure DISABLE status for the Endpoint*/
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1051,15 +1057,15 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
{
|
||||
if (ep->is_in)
|
||||
{
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
/* Configure DISABLE status for the Endpoint*/
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
|
||||
}
|
||||
else
|
||||
{
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
/* Configure DISABLE status for the Endpoint*/
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
|
||||
}
|
||||
}
|
||||
/*Double Buffer*/
|
||||
|
|
@ -1068,24 +1074,24 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
if (ep->is_in==0)
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
|
||||
/* Reset value of the data toggle bits for the endpoint out*/
|
||||
PCD_TX_DTOG(hpcd->Instance, ep->num);
|
||||
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the data toggle bits for the endpoint IN/OUT*/
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_RX_DTOG(hpcd->Instance, ep->num);
|
||||
/* Configure DISABLE status for the Endpoint*/
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1116,8 +1122,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
|
|||
ep->is_in = 0;
|
||||
ep->num = ep_addr & 0x7F;
|
||||
|
||||
__HAL_LOCK(hpcd);
|
||||
|
||||
/* Multi packet transfer*/
|
||||
if (ep->xfer_len > ep->maxpacket)
|
||||
{
|
||||
|
|
@ -1134,18 +1138,16 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
|
|||
if (ep->doublebuffer == 0)
|
||||
{
|
||||
/*Set RX buffer count*/
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
|
||||
PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Set the Double buffer counter*/
|
||||
PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
||||
PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len)
|
||||
}
|
||||
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1180,9 +1182,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|||
ep->xfer_count = 0;
|
||||
ep->is_in = 1;
|
||||
ep->num = ep_addr & 0x7F;
|
||||
|
||||
__HAL_LOCK(hpcd);
|
||||
|
||||
|
||||
/*Multi packet transfer*/
|
||||
if (ep->xfer_len > ep->maxpacket)
|
||||
{
|
||||
|
|
@ -1203,27 +1203,26 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
|
|||
}
|
||||
else
|
||||
{
|
||||
/*Set the Double buffer counter */
|
||||
PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
|
||||
|
||||
/*Write the data to the USB endpoint*/
|
||||
if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
|
||||
if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
|
||||
{
|
||||
/*Set the Double buffer counter for pmabuffer1*/
|
||||
PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
|
||||
pmabuffer = ep->pmaaddr1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/*Set the Double buffer counter for pmabuffer0*/
|
||||
PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len)
|
||||
pmabuffer = ep->pmaaddr0;
|
||||
}
|
||||
|
||||
PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
|
||||
PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
|
||||
}
|
||||
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
|
||||
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1255,17 +1254,17 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
if (ep->num == 0)
|
||||
{
|
||||
/* This macro sets STALL status for RX & TX*/
|
||||
PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL);
|
||||
PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL)
|
||||
}
|
||||
else
|
||||
{
|
||||
if (ep->is_in)
|
||||
{
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
|
||||
}
|
||||
else
|
||||
{
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
|
||||
}
|
||||
}
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
|
@ -1300,13 +1299,13 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
|
|||
|
||||
if (ep->is_in)
|
||||
{
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
|
||||
PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
|
||||
}
|
||||
else
|
||||
{
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
|
||||
PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
|
||||
PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
|
||||
}
|
||||
__HAL_UNLOCK(hpcd);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -198,7 +196,7 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
||||
#define USB_WAKEUP_EXTI_LINE (0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -328,10 +326,11 @@ typedef struct
|
|||
*/
|
||||
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
|
||||
/* SetENDPOINT */
|
||||
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
|
||||
|
||||
/* GetENDPOINT */
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(&(USBx)->EP0R + (bEpNum) * 2))
|
||||
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
|
||||
|
||||
|
||||
|
||||
|
|
@ -343,7 +342,7 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
|
||||
((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
|
||||
|
||||
/**
|
||||
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
|
||||
|
|
@ -351,7 +350,7 @@ typedef struct
|
|||
* @param bEpNum: Endpoint Number.
|
||||
* @retval Endpoint Type
|
||||
*/
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
|
||||
#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
|
||||
|
||||
|
||||
/**
|
||||
|
|
@ -400,18 +399,18 @@ typedef struct
|
|||
*/
|
||||
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
|
||||
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPTX_DTOG1 & (wState))!= 0) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG1; \
|
||||
_wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPTX_DTOG2 & (wState))!= 0) \
|
||||
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPTX_DTOG2; \
|
||||
_wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
|
||||
} /* PCD_SET_EP_TX_STATUS */
|
||||
|
||||
/**
|
||||
|
|
@ -424,18 +423,18 @@ typedef struct
|
|||
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
|
||||
register uint16_t _wRegVal; \
|
||||
\
|
||||
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
|
||||
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
|
||||
/* toggle first bit ? */ \
|
||||
if((USB_EPRX_DTOG1 & (wState))!= 0) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG1; \
|
||||
_wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
|
||||
} \
|
||||
/* toggle second bit ? */ \
|
||||
if((USB_EPRX_DTOG2 & (wState))!= 0) \
|
||||
if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
|
||||
{ \
|
||||
_wRegVal ^= USB_EPRX_DTOG2; \
|
||||
_wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
|
||||
} \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
|
||||
} /* PCD_SET_EP_RX_STATUS */
|
||||
|
||||
/**
|
||||
|
|
@ -480,9 +479,8 @@ typedef struct
|
|||
* @param bEpNum: Endpoint Number.
|
||||
* @retval status
|
||||
*/
|
||||
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
|
||||
|
||||
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
|
||||
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
|
||||
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
|
||||
|
||||
/**
|
||||
* @brief sets directly the VALID tx/rx-status into the endpoint register
|
||||
|
|
@ -512,9 +510,9 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
|
||||
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
|
||||
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
|
||||
|
||||
/**
|
||||
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
|
||||
|
|
@ -541,9 +539,9 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
|
||||
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
|
||||
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
|
||||
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
|
||||
|
||||
/**
|
||||
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
|
|
@ -552,9 +550,9 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
|
||||
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
|
||||
|
||||
/**
|
||||
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
|
||||
|
|
@ -562,13 +560,13 @@ typedef struct
|
|||
* @param bEpNum: Endpoint Number.
|
||||
* @retval None
|
||||
*/
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
|
||||
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
|
||||
{ \
|
||||
PCD_RX_DTOG((USBx), (bEpNum)); \
|
||||
PCD_RX_DTOG((USBx),(bEpNum));\
|
||||
}
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
|
||||
{ \
|
||||
PCD_TX_DTOG((USBx), (bEpNum)); \
|
||||
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
|
||||
{\
|
||||
PCD_TX_DTOG((USBx),(bEpNum));\
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -579,18 +577,18 @@ typedef struct
|
|||
* @retval None
|
||||
*/
|
||||
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
|
||||
USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
|
||||
|
||||
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
|
||||
|
||||
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400)))
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400)))
|
||||
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400)))
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400)))
|
||||
#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+ ((uint32_t)(USBx) + 0x400U)))))
|
||||
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+ ((uint32_t)(USBx) + 0x400U)))))
|
||||
#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
|
||||
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+ ((uint32_t)(USBx) + 0x400U)))))
|
||||
|
||||
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
|
||||
uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
|
||||
uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
|
||||
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -625,7 +623,7 @@ typedef struct
|
|||
{ \
|
||||
(wNBlocks)--;\
|
||||
} \
|
||||
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
|
||||
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
|
||||
}/* PCD_CALC_BLK32 */
|
||||
|
||||
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
|
||||
|
|
@ -641,17 +639,17 @@ typedef struct
|
|||
uint16_t wNBlocks;\
|
||||
if((wCount) > 62) \
|
||||
{ \
|
||||
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks); \
|
||||
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks); \
|
||||
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
|
||||
} \
|
||||
}/* PCD_SET_EP_CNT_RX_REG */
|
||||
|
||||
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
|
||||
uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
|
||||
uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
|
||||
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
|
||||
}
|
||||
/**
|
||||
* @brief sets counter for the tx/rx buffer.
|
||||
|
|
@ -679,8 +677,8 @@ typedef struct
|
|||
* @param wBuf0Addr: buffer 0 address.
|
||||
* @retval Counter value
|
||||
*/
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
|
||||
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
|
||||
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
|
||||
|
||||
/**
|
||||
* @brief Sets addresses in a double buffer endpoint.
|
||||
|
|
@ -716,7 +714,7 @@ typedef struct
|
|||
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) { \
|
||||
if((bDir) == PCD_EP_DBUF_OUT)\
|
||||
/* OUT endpoint */ \
|
||||
{PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
|
||||
{PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
|
||||
else if((bDir) == PCD_EP_DBUF_IN)\
|
||||
/* IN endpoint */ \
|
||||
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
|
||||
|
|
@ -725,17 +723,17 @@ typedef struct
|
|||
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) { \
|
||||
if((bDir) == PCD_EP_DBUF_OUT)\
|
||||
{/* OUT endpoint */ \
|
||||
PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)); \
|
||||
PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount)) \
|
||||
} \
|
||||
else if((bDir) == PCD_EP_DBUF_IN)\
|
||||
{/* IN endpoint */ \
|
||||
*PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
|
||||
*PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
|
||||
} \
|
||||
} /* SetEPDblBuf1Count */
|
||||
|
||||
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
|
||||
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
|
||||
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
|
||||
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
|
||||
} /* PCD_SET_EP_DBUF_CNT */
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pcd_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended PCD HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the USB Peripheral Controller:
|
||||
|
|
@ -12,7 +10,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pcd_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PCD HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief PWR HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
|
|
@ -14,7 +12,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -57,10 +55,10 @@
|
|||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define PVD_MODE_IT ((uint32_t)0x00010000)
|
||||
#define PVD_MODE_EVT ((uint32_t)0x00020000)
|
||||
#define PVD_RISING_EDGE ((uint32_t)0x00000001)
|
||||
#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
|
||||
#define PVD_MODE_IT (0x00010000U)
|
||||
#define PVD_MODE_EVT (0x00020000U)
|
||||
#define PVD_RISING_EDGE (0x00000001U)
|
||||
#define PVD_FALLING_EDGE (0x00000002U)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PWR HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -81,7 +79,7 @@ typedef struct
|
|||
/** @addtogroup PWR_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
#define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -170,13 +168,13 @@ typedef struct
|
|||
/** @defgroup PWR_PVD_Mode PWR PVD Mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */
|
||||
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
|
||||
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -185,7 +183,7 @@ typedef struct
|
|||
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
|
||||
* @{
|
||||
*/
|
||||
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
|
||||
#define PWR_MAINREGULATOR_ON (0x00000000U)
|
||||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
|
|
@ -13,7 +11,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pwr_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of PWR HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rcc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Reset and Clock Control (RCC) peripheral:
|
||||
|
|
@ -51,7 +49,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -272,10 +270,10 @@ void HAL_RCC_DeInit(void)
|
|||
CLEAR_REG(RCC->CFGR);
|
||||
|
||||
/* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */
|
||||
MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));
|
||||
MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), ((0U << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));
|
||||
|
||||
/* Set HSITRIM bits to the reset value */
|
||||
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM)));
|
||||
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (0x10U << POSITION_VAL(RCC_ICSCR_HSITRIM)));
|
||||
|
||||
/* Disable all interrupts */
|
||||
CLEAR_REG(RCC->CIR);
|
||||
|
|
@ -903,7 +901,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
|
|||
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
||||
{
|
||||
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
||||
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
||||
}
|
||||
|
||||
/* Update the SystemCoreClock global variable */
|
||||
|
|
@ -961,7 +959,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
|
|||
*/
|
||||
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
||||
{
|
||||
GPIO_InitTypeDef gpio = {0};
|
||||
GPIO_InitTypeDef gpio;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_MCO(RCC_MCOx));
|
||||
|
|
@ -1039,8 +1037,8 @@ void HAL_RCC_DisableCSS(void)
|
|||
*/
|
||||
uint32_t HAL_RCC_GetSysClockFreq(void)
|
||||
{
|
||||
uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0;
|
||||
uint32_t sysclockfreq = 0;
|
||||
uint32_t tmpreg = 0U, pllm = 0U, plld = 0U, pllvco = 0U, msiclkrange = 0U;
|
||||
uint32_t sysclockfreq = 0U;
|
||||
|
||||
tmpreg = RCC->CFGR;
|
||||
|
||||
|
|
@ -1060,7 +1058,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
|
|||
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
||||
{
|
||||
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
|
||||
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1;
|
||||
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1U;
|
||||
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
|
|
@ -1078,7 +1076,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
|
|||
default: /* MSI used as system clock */
|
||||
{
|
||||
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_BITNUMBER;
|
||||
sysclockfreq = (32768 * (1 << (msiclkrange + 1)));
|
||||
sysclockfreq = (32768U * (1U << (msiclkrange + 1U)));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1245,7 +1243,7 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF
|
|||
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
||||
|
||||
/* Get the APB2 configuration ----------------------------------------------*/
|
||||
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
|
||||
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
|
||||
|
||||
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
||||
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
||||
|
|
@ -1300,7 +1298,7 @@ __weak void HAL_RCC_CSSCallback(void)
|
|||
*/
|
||||
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
|
||||
{
|
||||
uint32_t vos = 0;
|
||||
uint32_t vos = 0U;
|
||||
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
||||
|
||||
/* HCLK can reach 4 MHz only if AHB prescaler = 1 */
|
||||
|
|
@ -1308,12 +1306,12 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
|
|||
{
|
||||
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
||||
{
|
||||
vos = HAL_PWREx_GetVoltageRange();
|
||||
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
vos = HAL_PWREx_GetVoltageRange();
|
||||
vos = READ_BIT(PWR->CR, PWR_CR_VOS);
|
||||
__HAL_RCC_PWR_CLK_DISABLE();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RCC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -68,10 +66,10 @@
|
|||
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
|
||||
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
|
||||
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
|
||||
#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */
|
||||
#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
|
||||
#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
|
||||
#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
|
||||
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -100,63 +98,63 @@
|
|||
/* --- CR Register ---*/
|
||||
/* Alias word address of HSION bit */
|
||||
#define RCC_HSION_BIT_NUMBER POSITION_VAL(RCC_CR_HSION)
|
||||
#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
|
||||
#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of MSION bit */
|
||||
#define RCC_MSION_BIT_NUMBER POSITION_VAL(RCC_CR_MSION)
|
||||
#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_MSION_BIT_NUMBER * 4)))
|
||||
#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of HSEON bit */
|
||||
#define RCC_HSEON_BIT_NUMBER POSITION_VAL(RCC_CR_HSEON)
|
||||
#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
|
||||
#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of CSSON bit */
|
||||
#define RCC_CSSON_BIT_NUMBER POSITION_VAL(RCC_CR_CSSON)
|
||||
#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
|
||||
#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
|
||||
/* Alias word address of PLLON bit */
|
||||
#define RCC_PLLON_BIT_NUMBER POSITION_VAL(RCC_CR_PLLON)
|
||||
#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
|
||||
#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
/* Alias word address of LSION bit */
|
||||
#define RCC_LSION_BIT_NUMBER POSITION_VAL(RCC_CSR_LSION)
|
||||
#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
|
||||
#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of RMVF bit */
|
||||
#define RCC_RMVF_BIT_NUMBER POSITION_VAL(RCC_CSR_RMVF)
|
||||
#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
|
||||
#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of LSEON bit */
|
||||
#define RCC_LSEON_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEON)
|
||||
#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
|
||||
#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of LSEON bit */
|
||||
#define RCC_LSEBYP_BIT_NUMBER POSITION_VAL(RCC_CSR_LSEBYP)
|
||||
#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
|
||||
#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of RTCEN bit */
|
||||
#define RCC_RTCEN_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCEN)
|
||||
#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
|
||||
#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
|
||||
|
||||
/* Alias word address of RTCRST bit */
|
||||
#define RCC_RTCRST_BIT_NUMBER POSITION_VAL(RCC_CSR_RTCRST)
|
||||
#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCRST_BIT_NUMBER * 4)))
|
||||
#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* CR register byte 2 (Bits[23:16]) base address */
|
||||
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
|
||||
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
|
||||
|
||||
/* CIR register byte 1 (Bits[15:8]) base address */
|
||||
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
|
||||
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
|
||||
|
||||
/* CIR register byte 2 (Bits[23:16]) base address */
|
||||
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
|
||||
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
|
||||
|
||||
/* Defines used for Flags */
|
||||
#define CR_REG_INDEX ((uint8_t)1)
|
||||
#define CSR_REG_INDEX ((uint8_t)2)
|
||||
#define CR_REG_INDEX ((uint8_t)1U)
|
||||
#define CSR_REG_INDEX ((uint8_t)2U)
|
||||
|
||||
#define RCC_FLAG_MASK ((uint8_t)0x1F)
|
||||
#define RCC_FLAG_MASK ((uint8_t)0x1FU)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -178,8 +176,8 @@
|
|||
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
|
||||
((__LSE__) == RCC_LSE_BYPASS))
|
||||
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
|
||||
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
|
||||
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
|
||||
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
|
||||
#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
|
||||
#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \
|
||||
((__RANGE__) == RCC_MSIRANGE_1) || \
|
||||
((__RANGE__) == RCC_MSIRANGE_2) || \
|
||||
|
|
@ -282,7 +280,7 @@ typedef struct
|
|||
This parameter can be a value of @ref RCC_HSI_Config */
|
||||
|
||||
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
|
||||
|
||||
uint32_t LSIState; /*!< The new state of the LSI.
|
||||
This parameter can be a value of @ref RCC_LSI_Config */
|
||||
|
|
@ -291,7 +289,7 @@ typedef struct
|
|||
This parameter can be a value of @ref RCC_MSI_Config */
|
||||
|
||||
uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
|
||||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
|
||||
|
||||
uint32_t MSIClockRange; /*!< The MSI frequency range.
|
||||
This parameter can be a value of @ref RCC_MSI_Clock_Range */
|
||||
|
|
@ -344,12 +342,12 @@ typedef struct
|
|||
/** @defgroup RCC_Oscillator_Type Oscillator Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
|
||||
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
|
||||
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
|
||||
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
|
||||
#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
|
||||
#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
|
||||
#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
|
||||
#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
|
||||
#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
|
||||
#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
|
||||
#define RCC_OSCILLATORTYPE_MSI (0x00000010U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -357,9 +355,9 @@ typedef struct
|
|||
/** @defgroup RCC_HSE_Config HSE Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF ((uint32_t)0x00000000) /*!< HSE clock deactivation */
|
||||
#define RCC_HSE_ON ((uint32_t)0x00000001) /*!< HSE clock activation */
|
||||
#define RCC_HSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for HSE clock */
|
||||
#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */
|
||||
#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */
|
||||
#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -367,9 +365,9 @@ typedef struct
|
|||
/** @defgroup RCC_LSE_Config LSE Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF ((uint32_t)0x00000000) /*!< LSE clock deactivation */
|
||||
#define RCC_LSE_ON ((uint32_t)0x00000001) /*!< LSE clock activation */
|
||||
#define RCC_LSE_BYPASS ((uint32_t)0x00000005) /*!< External clock source for LSE clock */
|
||||
#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */
|
||||
#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */
|
||||
#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -378,10 +376,10 @@ typedef struct
|
|||
/** @defgroup RCC_HSI_Config HSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSI_OFF ((uint32_t)0x00000000) /*!< HSI clock deactivation */
|
||||
#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */
|
||||
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
|
||||
|
||||
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
|
||||
#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -406,7 +404,7 @@ typedef struct
|
|||
/** @defgroup RCC_LSI_Config LSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSI_OFF ((uint32_t)0x00000000) /*!< LSI clock deactivation */
|
||||
#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */
|
||||
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
|
||||
|
||||
/**
|
||||
|
|
@ -416,10 +414,10 @@ typedef struct
|
|||
/** @defgroup RCC_MSI_Config MSI Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MSI_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_MSI_ON ((uint32_t)0x00000001)
|
||||
#define RCC_MSI_OFF (0x00000000U)
|
||||
#define RCC_MSI_ON (0x00000001U)
|
||||
|
||||
#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00000000U) /* Default MSI calibration trimming value */
|
||||
#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -428,9 +426,9 @@ typedef struct
|
|||
/** @defgroup RCC_PLL_Config PLL Config
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLL_NONE ((uint32_t)0x00000000) /*!< PLL is not configured */
|
||||
#define RCC_PLL_OFF ((uint32_t)0x00000001) /*!< PLL deactivation */
|
||||
#define RCC_PLL_ON ((uint32_t)0x00000002) /*!< PLL activation */
|
||||
#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */
|
||||
#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */
|
||||
#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -439,10 +437,10 @@ typedef struct
|
|||
/** @defgroup RCC_System_Clock_Type System Clock Type
|
||||
* @{
|
||||
*/
|
||||
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /*!< SYSCLK to configure */
|
||||
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /*!< HCLK to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /*!< PCLK1 to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /*!< PCLK2 to configure */
|
||||
#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */
|
||||
#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */
|
||||
#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -505,7 +503,7 @@ typedef struct
|
|||
/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock */
|
||||
#define RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */
|
||||
#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */
|
||||
#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */
|
||||
#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */
|
||||
|
|
@ -516,7 +514,7 @@ typedef struct
|
|||
/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) /*!< No clock */
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */
|
||||
#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
|
||||
#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */
|
||||
|
|
@ -561,7 +559,7 @@ typedef struct
|
|||
/** @defgroup RCC_MCO_Index MCO Index
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1 (0x00000000U)
|
||||
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
|
||||
|
||||
/**
|
||||
|
|
@ -620,22 +618,22 @@ typedef struct
|
|||
* @{
|
||||
*/
|
||||
/* Flags in the CR register */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
|
||||
#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
|
||||
#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
|
||||
|
||||
/* Flags in the CSR register */
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */
|
||||
#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
|
||||
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
|
||||
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< Internal Low Speed oscillator Ready */
|
||||
#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSECSSD))) /*!< CSS on LSE failure Detection */
|
||||
#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Options bytes loading reset flag */
|
||||
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */
|
||||
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF))) /*!< POR/PDR reset flag */
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -664,56 +662,56 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
|
||||
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
|
||||
|
|
@ -742,105 +740,105 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_USB_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_DAC_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_COMP_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
|
||||
#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
|
||||
|
|
@ -876,49 +874,49 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */\
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
|
||||
#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
|
||||
|
|
@ -1422,7 +1420,7 @@ typedef struct
|
|||
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
|
||||
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
|
||||
} \
|
||||
}while(0)
|
||||
}while(0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1470,7 +1468,7 @@ typedef struct
|
|||
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
|
||||
CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
|
||||
} \
|
||||
}while(0)
|
||||
}while(0U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1701,12 +1699,12 @@ typedef struct
|
|||
{ \
|
||||
MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
|
||||
} \
|
||||
} while (0)
|
||||
} while (0U)
|
||||
|
||||
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
|
||||
__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
|
||||
RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
|
||||
} while (0)
|
||||
} while (0U)
|
||||
|
||||
/** @brief Macro to get the RTC clock source.
|
||||
* @retval The clock source can be one of the following values:
|
||||
|
|
@ -1840,7 +1838,7 @@ typedef struct
|
|||
* @note (*) This bit is available in high and medium+ density devices only.
|
||||
* @retval The new state of __FLAG__ (TRUE or FALSE).
|
||||
*/
|
||||
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
|
||||
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1878,6 +1876,10 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
|
|||
/* Peripheral Control functions ************************************************/
|
||||
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
|
||||
void HAL_RCC_EnableCSS(void);
|
||||
/* CSS NMI IRQ handler */
|
||||
void HAL_RCC_NMI_IRQHandler(void);
|
||||
/* User Callbacks in non blocking mode (IT mode) */
|
||||
void HAL_RCC_CSSCallback(void);
|
||||
void HAL_RCC_DisableCSS(void);
|
||||
uint32_t HAL_RCC_GetSysClockFreq(void);
|
||||
uint32_t HAL_RCC_GetHCLKFreq(void);
|
||||
|
|
@ -1886,12 +1888,6 @@ uint32_t HAL_RCC_GetPCLK2Freq(void);
|
|||
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
|
||||
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
|
||||
|
||||
/* CSS NMI IRQ handler */
|
||||
void HAL_RCC_NMI_IRQHandler(void);
|
||||
|
||||
/* User Callbacks in non blocking mode (IT mode) */
|
||||
void HAL_RCC_CSSCallback(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
|
|
@ -12,7 +10,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -235,7 +233,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
|
|||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t srcclk = 0;
|
||||
uint32_t srcclk = 0U;
|
||||
|
||||
/* Set all possible values for the extended clock type parameter------------*/
|
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rcc_ex.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RCC HAL Extension module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -58,7 +56,7 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#define LSI_VALUE ((uint32_t)37000) /* ~37kHz */
|
||||
#define LSI_VALUE (37000U) /* ~37kHz */
|
||||
|
||||
#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
|
||||
|| defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
|
||||
|
|
@ -69,7 +67,7 @@
|
|||
|
||||
/* Alias word address of LSECSSON bit */
|
||||
#define LSECSSON_BITNUMBER POSITION_VAL(RCC_CSR_LSECSSON)
|
||||
#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4)))
|
||||
#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))
|
||||
|
||||
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
|
||||
|
||||
|
|
@ -132,11 +130,11 @@ typedef struct
|
|||
/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
|
||||
#define RCC_PERIPHCLK_RTC (0x00000001U)
|
||||
|
||||
#if defined(LCD)
|
||||
|
||||
#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000002)
|
||||
#define RCC_PERIPHCLK_LCD (0x00000002U)
|
||||
|
||||
#endif /* LCD */
|
||||
|
||||
|
|
@ -183,7 +181,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
|
||||
|
||||
#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
|
|
@ -198,14 +196,14 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
|
||||
#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
|
||||
|
|
@ -224,7 +222,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
|
||||
|
||||
|
|
@ -239,7 +237,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
|
||||
|
||||
#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
|
||||
|
|
@ -252,7 +250,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
|
||||
|
||||
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
|
||||
|
|
@ -269,7 +267,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
|
||||
|
||||
#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
|
|
@ -290,7 +288,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
|
||||
|
||||
#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
|
|
@ -307,7 +305,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
|
||||
|
||||
#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
|
|
@ -321,14 +319,14 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
|
||||
__IO uint32_t tmpreg; \
|
||||
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
|
||||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
|
||||
#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
|
||||
|
|
@ -359,7 +357,7 @@ typedef struct
|
|||
/* Delay after an RCC peripheral clock enabling */ \
|
||||
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
|
||||
UNUSED(tmpreg); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
|
||||
|
||||
#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
|
||||
|
|
@ -927,7 +925,7 @@ typedef struct
|
|||
do { \
|
||||
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
|
||||
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
|
||||
|
|
@ -937,7 +935,7 @@ typedef struct
|
|||
do { \
|
||||
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
} while(0U)
|
||||
|
||||
/**
|
||||
* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
|
||||
|
|
@ -1035,7 +1033,7 @@ void HAL_RCCEx_LSECSS_Callback(void);
|
|||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rtc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief RTC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Real Time Clock (RTC) peripheral:
|
||||
|
|
@ -102,7 +100,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -421,7 +419,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
|
|||
hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
|
||||
|
||||
/* Clear the bits to be configured */
|
||||
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
|
||||
hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
|
||||
|
||||
/* Configure the RTC_CR register */
|
||||
hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
|
||||
|
|
|
|||
|
|
@ -2,13 +2,11 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Header file of RTC HAL module.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -187,7 +185,7 @@ typedef struct
|
|||
/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -195,10 +193,10 @@ typedef struct
|
|||
/** @defgroup RTC_Time_Definitions Time Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -254,7 +252,7 @@ typedef struct
|
|||
/** @defgroup RTC_Year_Date_Definitions Year Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -277,8 +275,8 @@ typedef struct
|
|||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
|
||||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
|
||||
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -308,7 +306,7 @@ typedef struct
|
|||
/** @defgroup RTC_Alarm_Definitions Alarm Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
|
||||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
|
||||
|
|
|
|||
|
|
@ -2,8 +2,6 @@
|
|||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rtc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.2.0
|
||||
* @date 01-July-2016
|
||||
* @brief Extended RTC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Real Time Clock (RTC) Extension peripheral:
|
||||
|
|
@ -63,7 +61,7 @@
|
|||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
|
|
@ -153,10 +151,10 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
|
|||
else
|
||||
{
|
||||
/* Reset TR, DR and CR registers */
|
||||
hrtc->Instance->TR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->DR = (uint32_t)0x00002101;
|
||||
hrtc->Instance->TR = 0x00000000U;
|
||||
hrtc->Instance->DR = 0x00002101U;
|
||||
/* Reset All CR bits except CR[2:0] */
|
||||
hrtc->Instance->CR &= (uint32_t)0x00000007;
|
||||
hrtc->Instance->CR &= 0x00000007U;
|
||||
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
|
|
@ -176,23 +174,23 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
|
|||
}
|
||||
|
||||
/* Reset all RTC CR register bits */
|
||||
hrtc->Instance->CR &= (uint32_t)0x00000000;
|
||||
hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
|
||||
hrtc->Instance->PRER = (uint32_t)0x007F00FF;
|
||||
hrtc->Instance->CALIBR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->CR &= 0x00000000U;
|
||||
hrtc->Instance->WUTR = 0x0000FFFFU;
|
||||
hrtc->Instance->PRER = 0x007F00FFU;
|
||||
hrtc->Instance->CALIBR = 0x00000000U;
|
||||
hrtc->Instance->ALRMAR = 0x00000000U;
|
||||
hrtc->Instance->ALRMBR = 0x00000000U;
|
||||
#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
|
||||
hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->CALR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->SHIFTR = 0x00000000U;
|
||||
hrtc->Instance->CALR = 0x00000000U;
|
||||
hrtc->Instance->ALRMASSR = 0x00000000U;
|
||||
hrtc->Instance->ALRMBSSR = 0x00000000U;
|
||||
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
|
||||
/* Reset ISR register and exit initialization mode */
|
||||
hrtc->Instance->ISR = (uint32_t)0x00000000;
|
||||
hrtc->Instance->ISR = 0x00000000U;
|
||||
|
||||
/* Reset Tamper and alternate functions configuration register */
|
||||
hrtc->Instance->TAFCR = 0x00000000;
|
||||
hrtc->Instance->TAFCR = 0x00000000U;
|
||||
|
||||
/* Wait for synchro */
|
||||
if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
|
||||
|
|
|
|||
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Reference in New Issue