ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #6245 from mbedNoobNinja/Sync_PR 

Update for VK_RZ_A1H
pull/6401/merge
Cruz Monrreal 2018-03-20 15:21:01 -05:00 committed by GitHub
parent f3e2a3dd4b cf8fd20f9b
commit 2c7f909eea
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
71 changed files with 19583 additions and 19445 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h
View File

@ -1,3 +1,19 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RESERVED_PINS_H
#define RESERVED_PINS_H

15
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h
View File

@ -26,23 +26,12 @@
#endif
/* <-Take measures about optimization problems of web compiler */
#define TRANSACTION_QUEUE_SIZE_SPI 16
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#include "dma_api.h"
#endif

2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c
View File

@ -47,7 +47,9 @@ Macro definitions
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM))
#define CS2_SDRAM
#endif
/******************************************************************************
Imported global variables and functions (from other files)

64
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct
View File

@ -1,42 +1,62 @@
#! armcc -E -I"../"
;**************************************************
; Copyright (c) 2017 ARM Ltd. All rights reserved.
;**************************************************
; Scatter-file for RTX Example on Versatile Express
LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
#include "mbed_config.h"
#include "mem_VK_RZ_A1H.h"
LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
{
TTB +0 EMPTY 0x4000
{ } ; Level-1 Translation Table for MMU
}
SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region
SFLASH __ROM_BASE __ROM_SIZE ; load region size_region
{
}
VECTORS __VECTOR_BASE FIXED
{
* (RESET, +FIRST) ; Vector table and other startup code
* (InRoot$$Sections) ; All (library) code that must be in a root region
* (+RO-CODE) ; Application RO code (.text)
}
SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024)
{
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; S-Flash ROM : Executable cached region
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
RO_DATA +0
{ * (+RO-DATA) } ; Application RO data (.constdata)
VECTORS 0x18020000 FIXED
{
* (RESET, +FIRST) ; Vector table and other (assembler) startup code
* (InRoot$$Sections) ; All (library) code that must be in a root region
* (+RO-CODE) ; Application RO code (.text)
}
RW_DATA __DATA_BASE
{ * (+RW) } ; Application RW data (.data)
RO_DATA +0
{ * (+RO-DATA) } ; Application RO data (.constdata)
RW_IRAM1 +0 ALIGN 0x10
{ * (+ZI) } ; Application ZI data (.bss)
RW_DATA 0x20020000
{ * (+RW) } ; Application RW data (.data)
ARM_LIB_HEAP +0
{ * (HEAP) } ; Application heap area (HEAP)
ZI_DATA +0 ALIGN 0x400
{ * (+ZI) } ; Application ZI data (.bss)
ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
{ }
RW_DATA_NC 0x60900000 0x00100000
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; RAM-NC : Internal non-cached RAM region
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
{ * (NC_DATA) } ; Application RW data Non cached area
ZI_DATA_NC +0
{ * (NC_BSS) } ; Application ZI data Non cached area
}
#ifndef RUN_FROM_SDRAM
SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region
{
}
#else
SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!)
{
}
#endif

95
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h Normal file
View File

@ -0,0 +1,95 @@
/**************************************************************************//**
* @file mem_VK_RZ_A1H.h
* @brief Memory base and size definitions (used in scatter file)
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __MEM_VK_RZ_A1H_H
#define __MEM_VK_RZ_A1H_H
/*----------------------------------------------------------------------------
User Stack & Heap size definition
*----------------------------------------------------------------------------*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- ROM Configuration ------------------------------------
//
// <h> ROM Configuration
// <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
// <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*----------------------------------------------------------------------------*/
#ifdef RUN_FROM_SDRAM
#define __ROM_BASE 0x08000000
#define __ROM_SIZE 0x02000000
#define __VECTOR_BASE 0x08000000
#define __DATA_BASE +0 ALIGN 0x100000
#elif defined (RUN_FROM_SRAM)
#define __ROM_BASE 0x200A0000
#define __ROM_SIZE 0x00960000
#define __VECTOR_BASE 0x200A0000
#define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS
#else
#define __ROM_BASE 0x18020000
#define __ROM_SIZE 0x01FE0000
#define __VECTOR_BASE 0x18020000
#define __DATA_BASE 0x20020000
#endif
/*--------------------- RAM Configuration -----------------------------------
*----------------------------------------------------------------------------*/
#ifdef RUN_FROM_SDRAM
#define __RAM_BASE 0x08000000
#define __RAM_SIZE 0x02000000
#define __NC_RAM_SIZE 0x00200000
#else
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00A00000
#define __NC_RAM_SIZE 0x00100000
#endif
#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
#define __UND_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00008000
#define __ABT_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x0000F000
#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
/*----------------------------------------------------------------------------*/
/*--------------------- TTB Configuration ------------------------------------
//
// <h> TTB Configuration
// <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
// <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*----------------------------------------------------------------------------*/
#define __TTB_BASE 0x20000000
#define __TTB_SIZE 0x00004000
#endif /* __MEM_VK_RZ_A1H_H */

454
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S
View File

@ -1,454 +0,0 @@
;/*****************************************************************************
; * @file: startup_VKRZA1H.s
; * @purpose: CMSIS Cortex-A9 Core Device Startup File
; * for the Renesas RZA1H Device Series
; * @version: V1.02, modified for mbed
; * @date: 27. July 2009, modified 3rd Aug 2009
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
; *
; * Copyright (C) 2009 ARM Limited. All rights reserved.
; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; *****************************************************************************/
GICI_BASE EQU 0xe8202000
ICCIAR_OFFSET EQU 0x0000000C
ICCEOIR_OFFSET EQU 0x00000010
ICCHPIR_OFFSET EQU 0x00000018
GICD_BASE EQU 0xe8201000
ICDISER0_OFFSET EQU 0x00000100
ICDICER0_OFFSET EQU 0x00000180
ICDISPR0_OFFSET EQU 0x00000200
ICDABR0_OFFSET EQU 0x00000300
ICDIPR0_OFFSET EQU 0x00000400
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state
GIC_ERRATA_CHECK_1 EQU 0x000003FE
GIC_ERRATA_CHECK_2 EQU 0x000003FF
Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable
Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable
Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0
Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable
Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored)
RAM_BASE EQU 0x80000000
VRAM_BASE EQU 0x18000000
SRAM_BASE EQU 0x2e000000
ETHERNET EQU 0x1a000000
CS3_PERIPHERAL_BASE EQU 0x1c000000
; <h> Stack Configuration
; <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8>
; </h>
UND_Stack_Size EQU 0x00000100
SVC_Stack_Size EQU 0x00008000
ABT_Stack_Size EQU 0x00000100
FIQ_Stack_Size EQU 0x00000100
IRQ_Stack_Size EQU 0x00008000
USR_Stack_Size EQU 0x00004000
ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE USR_Stack_Size
__initial_sp SPACE ISR_Stack_Size
Stack_Top
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00080000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
ARM
; Vector Table Mapped to Address 0 at Reset
AREA RESET, CODE, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors LDR PC, Reset_Addr ; Address of Reset Handler
LDR PC, Undef_Addr ; Address of Undef Handler
LDR PC, SVC_Addr ; Address of SVC Handler
LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler
LDR PC, DAbt_Addr ; Address of Data Abort Handler
NOP ; Reserved Vector
LDR PC, IRQ_Addr ; Address of IRQ Handler
LDR PC, FIQ_Addr ; Address of FIQ Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SVC_Addr DCD SVC_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT InitMemorySubsystem
IMPORT __main
IMPORT RZ_A1_SetSramWriteEnable
; Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
ANDS R0, R0, #3
goToSleep
WFINE
BNE goToSleep
; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
; Enables Full Access i.e. in both privileged and non privileged modes
MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR)
ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11
MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR)
ISB
; Switch on the VFP and NEON hardware
MOV r0, #0x40000000
VMSR FPEXC, r0 ; Write FPEXC register, EN bit set
MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
ISB
; Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =__Vectors
MCR p15, 0, R0, c12, c0, 0
; Setup Stack for each exceptional mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
; Enter System Mode to complete initialization and enter kernel
MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit
MOV SP, R0
ISB
LDR R0, =RZ_A1_SetSramWriteEnable
BLX R0
IMPORT create_translation_table
BL create_translation_table
; USR/SYS stack pointer will be set during kernel init
LDR R0, =SystemInit
BLX R0
LDR R0, =InitMemorySubsystem
BLX R0
LDR R0, =__main
BLX R0
ENDP
Undef_Handler\
PROC
EXPORT Undef_Handler [WEAK]
IMPORT CUndefHandler
SRSFD SP!, #Mode_UND
PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack
MRS R0, SPSR
TST R0, #T_Bit ; Check mode
MOVEQ R1, #4 ; R1 = 4 ARM mode
MOVNE R1, #2 ; R1 = 2 Thumb mode
SUB R0, LR, R1
LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction
BEQ undef_cont
;Thumb instruction
;Determine if it is a 32-bit Thumb instruction
LDRH R0, [R0]
MOV R2, #0x1c
CMP R2, R0, LSR #11
BHS undef_cont ;16-bit Thumb instruction
;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction.
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
undef_cont
MOV R2, LR ; Set LR to third argument
; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R12, R3, #4
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
;R0 Offending instruction
;R1 =2 (Thumb) or =4 (ARM)
BL CUndefHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry
SUB LR, LR, R0
LDR R0, [SP, #28] ; Restore stacked SPSR
MSR SPSR_CXSF, R0
POP {R0-R4, R12} ; Restore stacked APCS registers
ADD SP, SP, #8 ; Adjust SP for already-restored banked registers
MOVS PC, LR
ENDP
PAbt_Handler\
PROC
EXPORT PAbt_Handler [WEAK]
IMPORT CPAbtHandler
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
MRC p15, 0, R0, c5, c0, 1 ; IFSR
MRC p15, 0, R1, c6, c0, 2 ; IFAR
MOV R2, LR ; Set LR to third argument
; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R12, R3, #4
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CPAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
POP {R0-R4, R12} ; Restore stack APCS registers
RFEFD SP! ; Return from exception
ENDP
DAbt_Handler\
PROC
EXPORT DAbt_Handler [WEAK]
IMPORT CDAbtHandler
SUB LR, LR, #8 ; Pre-adjust LR
SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack
PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack
CLREX ; State of exclusive monitors unknown after taken data abort
MRC p15, 0, R0, c5, c0, 0 ; DFSR
MRC p15, 0, R1, c6, c0, 0 ; DFAR
MOV R2, LR ; Set LR to third argument
; AND R12, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R12, R3, #4
SUB SP, SP, R12 ; Adjust stack
PUSH {R12, LR} ; Store stack adjustment and dummy LR
BL CDAbtHandler
POP {R12, LR} ; Get stack adjustment & discard dummy LR
ADD SP, SP, R12 ; Unadjust stack
POP {R0-R4, R12} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
ENDP
FIQ_Handler\
PROC
EXPORT FIQ_Handler [WEAK]
;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
;; so if a real FIQ Handler is implemented, this will be needed before returning:
;; LDR R1, =GICI_BASE
;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
IRQ_Handler\
PROC
EXPORT IRQ_Handler [WEAK]
IMPORT IRQCount
IMPORT IRQTable
IMPORT IRQNestLevel
;prologue
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack
CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL
PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack
; AND R1, SP, #4 ; Ensure stack is 8-byte aligned
MOV R3, SP ; Ensure stack is 8-byte aligned
AND R1, R3, #4
SUB SP, SP, R1 ; Adjust stack
PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack
LDR R0, =IRQNestLevel ; Get address of nesting counter
LDR R1, [R0]
ADD R1, R1, #1 ; Increment nesting counter
STR R1, [R0]
;identify and acknowledge interrupt
LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register)
DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts
; Workaround GIC 390 errata 733075
; If the ID is not 0, then service the interrupt as normal.
; If the ID is 0 and active, then service interrupt ID 0 as normal.
; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
;
LDR R2, =GICD_BASE
LDR R3, =GIC_ERRATA_CHECK_1
CMP R0, R3
BEQ unlock_cpu
LDR R3, =GIC_ERRATA_CHECK_2
CMP R0, R3
BEQ unlock_cpu
CMP R0, #0
BNE int_active ; If the ID is not 0, then service the interrupt
LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state
TST R3, #1
BNE int_active ; If active, then service the interrupt
unlock_cpu
LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface
STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write
DSB ; Ensure the write completes before continuing
B ret_irq ; Do not service the spurious interrupt
; End workaround
int_active
LDR R2, =IRQCount ; Read number of IRQs
LDR R2, [R2]
CMP R0, R2 ; Clean up and return if no handler
BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling
LDR R2, =IRQTable ; Get address of handler
LDR R2, [R2, R0, LSL #2]
CMP R2, #0 ; Clean up and return if handler address is 0
BEQ ret_irq
PUSH {R0,R1}
CPSIE i ; Now safe to re-enable interrupts
BLX R2 ; Call handler. R0 will be IRQ number
CPSID i ; Disable interrupts again
;write EOIR (GIC CPU Interface register)
POP {R0,R1}
DSB ; Ensure that interrupt source is cleared before we write the EOIR
ret_irq
;epilogue
STR R0, [R1, #ICCEOIR_OFFSET]
LDR R0, =IRQNestLevel ; Get address of nesting counter
LDR R1, [R0]
SUB R1, R1, #1 ; Decrement nesting counter
STR R1, [R0]
POP {R1, LR} ; Get stack adjustment and restore LR_SVC
ADD SP, SP, R1 ; Unadjust stack
POP {R0-R3,R12} ; Restore stacked APCS registers
RFEFD SP! ; Return from exception
ENDP
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END

162
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c Normal file
View File

@ -0,0 +1,162 @@
/******************************************************************************
* @file startup_RZ_A1H_H.c
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "VKRZA1H.h"
#include "mem_VK_RZ_A1H.h"
/*----------------------------------------------------------------------------
Definitions
*----------------------------------------------------------------------------*/
#define USR_MODE 0x10 // User mode
#define FIQ_MODE 0x11 // Fast Interrupt Request mode
#define IRQ_MODE 0x12 // Interrupt Request mode
#define SVC_MODE 0x13 // Supervisor mode
#define ABT_MODE 0x17 // Abort mode
#define UND_MODE 0x1B // Undefined Instruction mode
#define SYS_MODE 0x1F // System mode
/*----------------------------------------------------------------------------
Internal References
*----------------------------------------------------------------------------*/
void Vectors (void) __attribute__ ((section("RESET")));
void Reset_Handler(void);
/*----------------------------------------------------------------------------
Exception / Interrupt Handler
*----------------------------------------------------------------------------*/
void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
/*----------------------------------------------------------------------------
Exception / Interrupt Vector Table
*----------------------------------------------------------------------------*/
__ASM void Vectors(void) {
IMPORT Undef_Handler
IMPORT SVC_Handler
IMPORT PAbt_Handler
IMPORT DAbt_Handler
IMPORT IRQ_Handler
IMPORT FIQ_Handler
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
}
/*----------------------------------------------------------------------------
Reset Handler called on controller reset
*----------------------------------------------------------------------------*/
__ASM void Reset_Handler(void) {
// Mask interrupts
CPSID if
// Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5 // Read MPIDR
ANDS R0, R0, #3
goToSleep
WFINE
BNE goToSleep
// Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register
ISB
// Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register
// Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
// Setup Stack for each exceptional mode
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
//Enter Undefined Instruction Mode and set its Stack Pointer
CPS #UND_MODE
MOV SP, R0
SUB R0, R0, #__UND_STACK_SIZE
// Enter Abort Mode and set its Stack Pointer
CPS #ABT_MODE
MOV SP, R0
SUB R0, R0, #__ABT_STACK_SIZE
// Enter FIQ Mode and set its Stack Pointer
CPS #FIQ_MODE
MOV SP, R0
SUB R0, R0, #__FIQ_STACK_SIZE
// Enter IRQ Mode and set its Stack Pointer
CPS #IRQ_MODE
MOV SP, R0
SUB R0, R0, #__IRQ_STACK_SIZE
// Enter Supervisor Mode and set its Stack Pointer
CPS #SVC_MODE
MOV SP, R0
SUB R0, R0, #__SVC_STACK_SIZE
// Enter System Mode to complete initialization and enter kernel
CPS #SYS_MODE
MOV SP, R0
// Call SystemInit
IMPORT SystemInit
BL SystemInit
// Unmask interrupts
CPSIE if
// Call __main
IMPORT __main
BL __main
}
/*----------------------------------------------------------------------------
Default Handler for Exceptions / Interrupts
*----------------------------------------------------------------------------*/
void Default_Handler(void) {
while(1);
}

61
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp Normal file
View File

@ -0,0 +1,61 @@
/* mbed Microcontroller Library - stackheap
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*******************************************************************************
* Copyright (c) 2017 ARM Limited.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include <arm_compat.h>
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_STACK$$Base[];
extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base;
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

78
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld
View File

@ -1,15 +1,40 @@
/* Linker script for mbed VK_RZ_A1H */
/* Linker script to configure memory regions. */
/*
#ifdef RUN_FROM_SDRAM
MEMORY
{
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x01E00000
RAM_NC (rwx) : ORIGIN = 0x49E00000, LENGTH = 0x00200000
SRAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00960000
}
REGION_ALIAS("SFLASH", RAM);
TTBOFFSET = 1M;
#elif defined (RUN_FROM_SRAM)
MEMORY
{
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00860000
RAM_NC (rwx) : ORIGIN = 0x60900000, LENGTH = 0x00100000
SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000
}
REGION_ALIAS("SFLASH", RAM);
TTBOFFSET = 1M;
#else
*/
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000
SFLASH_DUAL (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000
SFLASH (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000
RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000
}
/*#endif*/
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@ -45,8 +70,7 @@ SECTIONS
{
Image$$VECTORS$$Base = .;
*(.isr_vector)
Image$$VECTORS$$Limit = .;
KEEP(*(.isr_vector))
*(SVC_TABLE)
*(.text*)
@ -66,24 +90,25 @@ SECTIONS
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
Image$$VECTORS$$Limit = .;
Image$$RO_DATA$$Base = .;
*(.rodata*)
Image$$RO_DATA$$Limit = .;
KEEP(*(.eh_frame*))
} > SFLASH_DUAL
} > SFLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SFLASH_DUAL
} > SFLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SFLASH_DUAL
} > SFLASH
__exidx_end = .;
@ -98,7 +123,7 @@ SECTIONS
LONG (__nc_data_start)
LONG (__nc_data_end - __nc_data_start)
__copy_table_end__ = .;
} > SFLASH_DUAL
} > SFLASH
.zero.table :
{
@ -109,7 +134,7 @@ SECTIONS
LONG (__nc_bss_start)
LONG (__nc_bss_end - __nc_bss_start)
__zero_table_end__ = .;
} > SFLASH_DUAL
} > SFLASH
__etext = .;
@ -155,34 +180,42 @@ SECTIONS
} > RAM
.bss ALIGN(0x400):
.bss ALIGN(0x10):
{
Image$$ZI_DATA$$Base = .;
Image$$RW_IRAM1$$Base = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$ZI_DATA$$Limit = .;
Image$$RW_IRAM1$$Limit = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
.stack_dummy (COPY):
{
*(.stack)
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
__HeapLimit = __StackLimit;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
__etext2 = __etext + SIZEOF(.data);
.nc_data : AT (__etext2)
{
@ -205,15 +238,4 @@ SECTIONS
__nc_bss_end = .;
Image$$ZI_DATA_NC$$Limit = .;
} > RAM_NC
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

326
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S
View File

@ -19,26 +19,6 @@
.extern _start
@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.equ USR_MODE , 0x10
.equ FIQ_MODE , 0x11
.equ IRQ_MODE , 0x12
.equ SVC_MODE , 0x13
.equ ABT_MODE , 0x17
.equ UND_MODE , 0x1b
.equ SYS_MODE , 0x1f
.equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
.equ GICI_BASE , 0xe8202000
.equ ICCIAR_OFFSET , 0x0000000C
.equ ICCEOIR_OFFSET , 0x00000010
.equ ICCHPIR_OFFSET , 0x00000018
.equ GICD_BASE , 0xe8201000
.equ ICDISER0_OFFSET , 0x00000100
.equ ICDICER0_OFFSET , 0x00000180
.equ ICDISPR0_OFFSET , 0x00000200
.equ ICDABR0_OFFSET , 0x00000300
.equ ICDIPR0_OFFSET , 0x00000400
.equ Mode_USR , 0x10
.equ Mode_FIQ , 0x11
.equ Mode_IRQ , 0x12
@ -51,33 +31,13 @@
.equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
.equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
.equ GIC_ERRATA_CHECK_1, 0x000003FE
.equ GIC_ERRATA_CHECK_2, 0x000003FF
.equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
.equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
.equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
.equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
.equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
.equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
.equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
.equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
.equ RAM_BASE , 0x80000000
.equ VRAM_BASE , 0x18000000
.equ SRAM_BASE , 0x2e000000
.equ ETHERNET , 0x1a000000
.equ CS3_PERIPHERAL_BASE, 0x1c000000
@ Stack Configuration
.EQU UND_Stack_Size , 0x00000100
.EQU SVC_Stack_Size , 0x00008000
.EQU ABT_Stack_Size , 0x00000100
.EQU FIQ_Stack_Size , 0x00000100
.EQU IRQ_Stack_Size , 0x00008000
.EQU USR_Stack_Size , 0x00004000
.EQU IRQ_Stack_Size , 0x0000F000
.EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
@ -88,7 +48,6 @@
__StackLimit:
.space ISR_Stack_Size
__initial_sp:
.space USR_Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
@ -139,25 +98,17 @@ __isr_vector:
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
@ Mask interrupts
CPSID if
@ Put any cores other than 0 to sleep
mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
ands r0, r0, #3
goToSleep:
wfine
bne goToSleep
@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
@ Enables Full Access i.e. in both privileged and non privileged modes
mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
isb
@ Switch on the VFP and NEON hardware
mov r0, #0x40000000
vmsr fpexc, r0 @ Write FPEXC register, EN bit set
@ Reset SCTLR Settings
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
@ -167,13 +118,17 @@ goToSleep:
mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
isb
@ Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register
@ Set Vector Base Address Register (VBAR) to point to this application's vector table
ldr r0, =__isr_vector
mcr p15, 0, r0, c12, c0, 0
@ Setup Stack for each exceptional mode
/* ldr r0, =__StackTop */
ldr r0, =(__StackTop - USR_Stack_Size)
ldr r0, =__StackTop
@ Enter Undefined Instruction Mode and set its Stack Pointer
msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
@ -203,23 +158,12 @@ goToSleep:
msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
mov sp, r0
isb
ldr r0, =RZ_A1_SetSramWriteEnable
blx r0
.extern create_translation_table
bl create_translation_table
@ USR/SYS stack pointer will be set during kernel init
ldr r0, =SystemInit
blx r0
ldr r0, =InitMemorySubsystem
blx r0
@ fp_init
mov r0, #0x3000000
vmsr fpscr, r0
@ Unmask interrupts
CPSIE if
@ data sections copy
ldr r4, =__copy_table_start__
@ -269,227 +213,12 @@ goToSleep:
ldr r0, =_start
bx r0
ldr r0, sf_boot @ dummy to keep boot loader area
loop_here:
b loop_here
sf_boot:
.word 0x18020000
.pool
.size Reset_Handler, . - Reset_Handler
.text
Undef_Handler:
.global Undef_Handler
.func Undef_Handler
.extern CUndefHandler
SRSDB SP!, #Mode_UND
PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
MRS R0, SPSR
TST R0, #T_Bit /* Check mode */
MOVEQ R1, #4 /* R1 = 4 ARM mode */
MOVNE R1, #2 /* R1 = 2 Thumb mode */
SUB R0, LR, R1
LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
BEQ undef_cont
/* Thumb instruction */
/* Determine if it is a 32-bit Thumb instruction */
LDRH R0, [R0]
MOV R2, #0x1c
CMP R2, R0, LSR #11
BHS undef_cont /* 16-bit Thumb instruction */
/* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
undef_cont:
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
/* R0 Offending instruction */
/* R1 =2 (Thumb) or =4 (ARM) */
BL CUndefHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
SUB LR, LR, R0
LDR R0, [SP, #28] /* Restore stacked SPSR */
MSR SPSR_cxsf, R0
POP {R0-R4, R12} /* Restore stacked APCS registers */
ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
MOVS PC, LR
.endfunc
PAbt_Handler:
.global PAbt_Handler
.func PAbt_Handler
.extern CPAbtHandler
SUB LR, LR, #4 /* Pre-adjust LR */
SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
MRC p15, 0, R0, c5, c0, 1 /* IFSR */
MRC p15, 0, R1, c6, c0, 2 /* IFAR */
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
BL CPAbtHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
POP {R0-R4, R12} /* Restore stack APCS registers */
RFEFD SP! /* Return from exception */
.endfunc
DAbt_Handler:
.global DAbt_Handler
.func DAbt_Handler
.extern CDAbtHandler
SUB LR, LR, #8 /* Pre-adjust LR */
SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
CLREX /* State of exclusive monitors unknown after taken data abort */
MRC p15, 0, R0, c5, c0, 0 /* DFSR */
MRC p15, 0, R1, c6, c0, 0 /* DFAR */
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
BL CDAbtHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
POP {R0-R4, R12} /* Restore stacked APCS registers */
RFEFD SP! /* Return from exception */
.endfunc
FIQ_Handler:
.global FIQ_Handler
.func FIQ_Handler
/* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
* so if a real FIQ Handler is implemented, this will be needed before returning:
*/
/* LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
*/
B .
.endfunc
.extern SVC_Handler /* refer RTX function */
IRQ_Handler:
.global IRQ_Handler
.func IRQ_Handler
.extern IRQCount
.extern IRQTable
.extern IRQNestLevel
/* prologue */
SUB LR, LR, #4 /* Pre-adjust LR */
SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R1, R3, #4
SUB SP, SP, R1 /* Adjust stack */
PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
LDR R0, =IRQNestLevel /* Get address of nesting counter */
LDR R1, [R0]
ADD R1, R1, #1 /* Increment nesting counter */
STR R1, [R0]
/* identify and acknowledge interrupt */
LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
/* Workaround GIC 390 errata 733075
* If the ID is not 0, then service the interrupt as normal.
* If the ID is 0 and active, then service interrupt ID 0 as normal.
* If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
* with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
*/
LDR R2, =GICD_BASE
LDR R3, =GIC_ERRATA_CHECK_1
CMP R0, R3
BEQ unlock_cpu
LDR R3, =GIC_ERRATA_CHECK_2
CMP R0, R3
BEQ unlock_cpu
CMP R0, #0
BNE int_active /* If the ID is not 0, then service the interrupt */
LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
TST R3, #1
BNE int_active /* If active, then service the interrupt */
unlock_cpu:
LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
DSB /* Ensure the write completes before continuing */
B ret_irq /* Do not service the spurious interrupt */
/* End workaround */
int_active:
LDR R2, =IRQCount /* Read number of IRQs */
LDR R2, [R2]
CMP R0, R2 /* Clean up and return if no handler */
BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
LDR R2, =IRQTable /* Get address of handler */
LDR R2, [R2, R0, LSL #2]
CMP R2, #0 /* Clean up and return if handler address is 0 */
BEQ ret_irq
PUSH {R0,R1}
CPSIE i /* Now safe to re-enable interrupts */
BLX R2 /* Call handler. R0 will be IRQ number */
CPSID i /* Disable interrupts again */
/* write EOIR (GIC CPU Interface register) */
POP {R0,R1}
DSB /* Ensure that interrupt source is cleared before we write the EOIR */
ret_irq:
/* epilogue */
STR R0, [R1, #ICCEOIR_OFFSET]
LDR R0, =IRQNestLevel /* Get address of nesting counter */
LDR R1, [R0]
SUB R1, R1, #1 /* Decrement nesting counter */
STR R1, [R0]
POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
ADD SP, SP, R1 /* Unadjust stack */
POP {R0-R3,R12} /* Restore stacked APCS registers */
RFEFD SP! /* Return from exception */
.endfunc
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
@ -503,30 +232,11 @@ ret_irq:
.size \handler_name, . - \handler_name
.endm
def_default_handler Undef_Handler
def_default_handler SVC_Handler
/* User Initial Stack & Heap */
.ifdef __MICROLIB
.global __initial_sp
.global __heap_base
.global __heap_limit
.else
.extern __use_two_region_memory
.global __user_initial_stackheap
__user_initial_stackheap:
LDR R0, = __HeapBase
LDR R1, =(__StackTop)
LDR R2, = (__HeapBase + Heap_Size)
LDR R3, = (__StackTop - USR_Stack_Size)
BX LR
.endif
def_default_handler PAbt_Handler
def_default_handler DAbt_Handler
def_default_handler IRQ_Handler
def_default_handler FIQ_Handler
.END

5
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf
View File

@ -41,6 +41,7 @@ define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__
define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
define block ROM_FIXED_ORDER with fixed order { ro code, ro data };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
@ -51,11 +52,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section MMU_TT };
do not initialize { section .retram };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in ROM_region { readonly, block ROM_FIXED_ORDER };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };

339
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S
View File

@ -29,30 +29,21 @@
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector_core_a9
PUBWEAK __iar_program_start
PUBLIC Undefined_Handler
EXTERN SWI_Handler
PUBLIC Prefetch_Handler
PUBLIC Abort_Handler
PUBLIC IRQ_Handler
PUBLIC __vector_table
PUBLIC __RST_Handler
EXTERN Undef_Handler
EXTERN SVC_Handler
EXTERN PAbt_Handler
EXTERN DAbt_Handler
EXTERN IRQ_Handler
PUBLIC FIQ_Handler
EXTERN VbarInit
EXTERN SetLowVectors
EXTERN init_TTB
EXTERN enable_mmu
EXTERN Peripheral_BasicInit
EXTERN initsct
EXTERN PowerON_Reset
PUBLIC FPUEnable
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
__vector_core_a9: ; Make this a DATA label, so that stack usage
__vector_table: ; Make this a DATA label, so that stack usage
; analysis doesn't consider it an uncalled fun
ARM
@ -71,11 +62,11 @@ __vector_core_a9: ; Make this a DATA label, so that stack usage
DATA
Reset_Addr: DCD __iar_program_start
Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
Reset_Addr: DCD __RST_Handler
Undefined_Addr: DCD Undef_Handler
SWI_Addr: DCD SVC_Handler
Prefetch_Addr: DCD PAbt_Handler
Abort_Addr: DCD DAbt_Handler
IRQ_Addr: DCD IRQ_Handler
FIQ_Addr: DCD FIQ_Handler
@ -90,21 +81,20 @@ FIQ_Addr: DCD FIQ_Handler
SECTION .text:CODE:NOROOT(2)
EXTERN RZ_A1_SetSramWriteEnable
EXTERN create_translation_table
EXTERN SystemInit
EXTERN InitMemorySubsystem
EXTERN __cmain
REQUIRE __vector_core_a9
EXTERN __iar_program_start
REQUIRE __vector_table
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
ARM
__iar_program_start:
__RST_Handler:
?cstartup:
;;; @ Mask interrupts
CPSID if
;;; @ Put any cores other than 0 to sleep
mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR
@ -114,19 +104,7 @@ goToSleep:
wfine
bne goToSleep
//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
//@ Enables Full Access i.e. in both privileged and non privileged modes
mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR)
orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11
mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR)
isb
;; Switch on the VFP and NEON hardware
mov r0, #0x40000000
vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set
;;; @ Reset SCTLR Settings
mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register
bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache
@ -136,9 +114,13 @@ goToSleep:
mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register
isb
;;; @ Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register
;; Set Vector Base Address Register (VBAR) to point to this application's vector table
ldr r0, =__vector_core_a9
ldr r0, =__vector_table
mcr p15, 0, r0, c12, c0, 0
@ -169,20 +151,6 @@ goToSleep:
#define UND_MODE 0x1B ; Undefined Instruction mode
#define SYS_MODE 0x1F ; System mode
#define Mode_SVC 0x13
#define Mode_ABT 0x17
#define Mode_UND 0x1B
#define GICI_BASE 0xe8202000
#define ICCIAR_OFFSET 0x0000000C
#define ICCEOIR_OFFSET 0x00000010
#define ICCHPIR_OFFSET 0x00000018
#define GICD_BASE 0xe8201000
#define GIC_ERRATA_CHECK_1 0x000003FE
#define GIC_ERRATA_CHECK_2 0x000003FF
#define ICDABR0_OFFSET 0x00000300
#define ICDIPR0_OFFSET 0x00000400
#define T_Bit 0x20 ; when T bit is set, core is in Thumb state
MRS r0, cpsr ; Original PSR value
;; Set up the SVC stack pointer.
@ -235,271 +203,16 @@ goToSleep:
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;;;
isb
ldr r0, =RZ_A1_SetSramWriteEnable
blx r0
bl create_translation_table
; USR/SYS stack pointer will be set during kernel init
ldr r0, =SystemInit
blx r0
ldr r0, =InitMemorySubsystem
blx r0
; fp_init
mov r0, #0x3000000
vmsr fpscr, r0
;;; Continue to __cmain for C-level initialization.
FUNCALL __iar_program_start, __cmain
B __cmain
ldr r0, sf_boot ;@ dummy to keep boot loader area
loop_here:
b loop_here
sf_boot:
DC32 0x00000001
Undefined_Handler:
EXTERN CUndefHandler
SRSDB SP!, #Mode_UND
PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
MRS R0, SPSR
TST R0, #T_Bit /* Check mode */
MOVEQ R1, #4 /* R1 = 4 ARM mode */
MOVNE R1, #2 /* R1 = 2 Thumb mode */
SUB R0, LR, R1
LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
BEQ undef_cont
/* Thumb instruction */
/* Determine if it is a 32-bit Thumb instruction */
LDRH R0, [R0]
MOV R2, #0x1c
CMP R2, R0, LSR #11
BHS undef_cont /* 16-bit Thumb instruction */
/* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
LDRH R2, [LR]
ORR R0, R2, R0, LSL #16
undef_cont:
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
/* R0 Offending instruction */
/* R1 =2 (Thumb) or =4 (ARM) */
BL CUndefHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
SUB LR, LR, R0
LDR R0, [SP, #28] /* Restore stacked SPSR */
MSR SPSR_cxsf, R0
POP {R0-R4, R12} /* Restore stacked APCS registers */
ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
MOVS PC, LR
Prefetch_Handler:
EXTERN CPAbtHandler
SUB LR, LR, #4 /* Pre-adjust LR */
SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
MRC p15, 0, R0, c5, c0, 1 /* IFSR */
MRC p15, 0, R1, c6, c0, 2 /* IFAR */
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
BL CPAbtHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
POP {R0-R4, R12} /* Restore stack APCS registers */
RFEFD SP! /* Return from exception */
Abort_Handler:
EXTERN CDAbtHandler
SUB LR, LR, #8 /* Pre-adjust LR */
SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
CLREX /* State of exclusive monitors unknown after taken data abort */
MRC p15, 0, R0, c5, c0, 0 /* DFSR */
MRC p15, 0, R1, c6, c0, 0 /* DFAR */
MOV R2, LR /* Set LR to third argument */
/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R12, R3, #4
SUB SP, SP, R12 /* Adjust stack */
PUSH {R12, LR} /* Store stack adjustment and dummy LR */
BL CDAbtHandler
POP {R12, LR} /* Get stack adjustment & discard dummy LR */
ADD SP, SP, R12 /* Unadjust stack */
POP {R0-R4, R12} /* Restore stacked APCS registers */
RFEFD SP! /* Return from exception */
FUNCALL __RST_Handler, __iar_program_start
B __iar_program_start
FIQ_Handler:
/* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
* so if a real FIQ Handler is implemented, this will be needed before returning:
*/
/* LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
*/
B .
EXTERN SVC_Handler /* refer RTX function */
IRQ_Handler:
EXTERN IRQCount
EXTERN IRQTable
EXTERN IRQNestLevel
/* prologue */
SUB LR, LR, #4 /* Pre-adjust LR */
SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
MOV R3, SP /* Ensure stack is 8-byte aligned */
AND R1, R3, #4
SUB SP, SP, R1 /* Adjust stack */
PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
LDR R0, =IRQNestLevel /* Get address of nesting counter */
LDR R1, [R0]
ADD R1, R1, #1 /* Increment nesting counter */
STR R1, [R0]
/* identify and acknowledge interrupt */
LDR R1, =GICI_BASE
LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
/* Workaround GIC 390 errata 733075
* If the ID is not 0, then service the interrupt as normal.
* If the ID is 0 and active, then service interrupt ID 0 as normal.
* If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
* with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
*/
LDR R2, =GICD_BASE
LDR R3, =GIC_ERRATA_CHECK_1
CMP R0, R3
BEQ unlock_cpu
LDR R3, =GIC_ERRATA_CHECK_2
CMP R0, R3
BEQ unlock_cpu
CMP R0, #0
BNE int_active /* If the ID is not 0, then service the interrupt */
LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
TST R3, #1
BNE int_active /* If active, then service the interrupt */
unlock_cpu:
LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
DSB /* Ensure the write completes before continuing */
B ret_irq /* Do not service the spurious interrupt */
/* End workaround */
int_active:
LDR R2, =IRQCount /* Read number of IRQs */
LDR R2, [R2]
CMP R0, R2 /* Clean up and return if no handler */
BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
LDR R2, =IRQTable /* Get address of handler */
LDR R2, [R2, R0, LSL #2]
CMP R2, #0 /* Clean up and return if handler address is 0 */
BEQ ret_irq
PUSH {R0,R1}
CPSIE i /* Now safe to re-enable interrupts */
BLX R2 /* Call handler. R0 will be IRQ number */
CPSID i /* Disable interrupts again */
/* write EOIR (GIC CPU Interface register) */
POP {R0,R1}
DSB /* Ensure that interrupt source is cleared before we write the EOIR */
ret_irq:
/* epilogue */
STR R0, [R1, #ICCEOIR_OFFSET]
LDR R0, =IRQNestLevel /* Get address of nesting counter */
LDR R1, [R0]
SUB R1, R1, #1 /* Decrement nesting counter */
STR R1, [R0]
POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
ADD SP, SP, R1 /* Unadjust stack */
POP {R0-R3,R12} /* Restore stacked APCS registers */
RFEFD SP! /* Return from exception */
;;;
;;; Add more initialization here
;;;
FPUEnable:
ARM
//Permit access to VFP registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
//Enable VFP
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
//Initialise VFP registers to 0
MOV R2,#0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
VMOV D3, R2,R2
VMOV D4, R2,R2
VMOV D5, R2,R2
VMOV D6, R2,R2
VMOV D7, R2,R2
VMOV D8, R2,R2
VMOV D9, R2,R2
VMOV D10,R2,R2
VMOV D11,R2,R2
VMOV D12,R2,R2
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
//Initialise FPSCR to a known state
VMRS R2,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AND R2,R2,R3
VMSR FPSCR,R2
BX LR
END

1076
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h
View File

File diff suppressed because it is too large Load Diff

1
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h
View File

@ -8,5 +8,6 @@
#define MBED_CMSIS_H
#include "VKRZA1H.h"
#include "cmsis_nvic.h"
#endif

11
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c
View File

@ -29,14 +29,15 @@
*******************************************************************************
*/
#include "VKRZA1H.h"
#include "irq_ctrl.h"
extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
InterruptHandlerRegister(IRQn, (IRQHandler)vector);
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t vectors = (uint32_t)IRQTable[IRQn];
uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn);
return vectors;
}

305
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c
View File

@ -1,305 +0,0 @@
/**************************************************************************//**
* @file gic.c
* @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 19 Sept 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "VKRZA1H.h"
#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */
/* Globals for use of post-scatterloading code that must access GIC */
const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
void GIC_EnableDistributor(void)
{
GICDistributor->ICDDCR |= 1; //enable distributor
}
void GIC_DisableDistributor(void)
{
GICDistributor->ICDDCR &=~1; //disable distributor
}
uint32_t GIC_DistributorInfo(void)
{
return (uint32_t)(GICDistributor->ICDICTR);
}
uint32_t GIC_DistributorImplementer(void)
{
return (uint32_t)(GICDistributor->ICDIIDR);
}
void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
field += IRQn % 4;
*field = (uint8_t)cpu_target & 0xf;
}
void GIC_SetICDICFR (const uint32_t *ICDICFRn)
{
uint32_t i, num_irq;
//Get the maximum number of interrupts that the GIC supports
num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
for (i = 0; i < (num_irq/16); i++)
{
GICDistributor->ICDISPR[i] = *ICDICFRn++;
}
}
uint32_t GIC_GetTarget(IRQn_Type IRQn)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
field += IRQn % 4;
return ((uint32_t)*field & 0xf);
}
void GIC_EnableInterface(void)
{
GICInterface->ICCICR |= 1; //enable interface
}
void GIC_DisableInterface(void)
{
GICInterface->ICCICR &=~1; //disable distributor
}
IRQn_Type GIC_AcknowledgePending(void)
{
return (IRQn_Type)(GICInterface->ICCIAR);
}
void GIC_EndInterrupt(IRQn_Type IRQn)
{
GICInterface->ICCEOIR = IRQn;
}
void GIC_EnableIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_DisableIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_SetPendingIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_ClearPendingIRQ(IRQn_Type IRQn)
{
GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
}
void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
int bit_shift = (IRQn % 16)<<1;
uint8_t save_byte;
field += (bit_shift / 8);
bit_shift %= 8;
save_byte = *field;
save_byte &= ((uint8_t)~(3u << bit_shift));
*field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
}
void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
field += (IRQn % 4);
*field = (uint8_t)priority;
}
uint32_t GIC_GetPriority(IRQn_Type IRQn)
{
volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
field += (IRQn % 4);
return (uint32_t)*field;
}
void GIC_InterfacePriorityMask(uint32_t priority)
{
GICInterface->ICCPMR = priority & 0xff; //set priority mask
}
void GIC_SetBinaryPoint(uint32_t binary_point)
{
GICInterface->ICCBPR = binary_point & 0x07; //set binary point
}
uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
{
return (uint32_t)GICInterface->ICCBPR;
}
uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
{
uint32_t pending, active;
active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
return ((active<<1) | pending);
}
void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
{
GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
}
void GIC_DistInit(void)
{
//IRQn_Type i;
uint32_t i;
uint32_t num_irq = 0;
uint32_t priority_field;
//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
//configuring all of the interrupts as Secure.
//Disable interrupt forwarding
GIC_DisableDistributor();
//Get the maximum number of interrupts that the GIC supports
num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
/* Priority level is implementation defined.
To determine the number of priority bits implemented write 0xFF to an ICDIPR
priority field and read back the value stored.*/
GIC_SetPriority((IRQn_Type)0, 0xff);
priority_field = GIC_GetPriority((IRQn_Type)0);
for (i = 32; i < num_irq; i++)
{
//Disable all SPI the interrupts
GIC_DisableIRQ((IRQn_Type)i);
//Set level-sensitive and N-N model
//GIC_SetLevelModel(i, 0, 0);
//Set priority
GIC_SetPriority((IRQn_Type)i, priority_field/2);
//Set target list to "all cpus"
GIC_SetTarget((IRQn_Type)i, 0xff);
}
/* Set level-edge and 1-N model */
/* GICDistributor->ICDICFR[ 0] is read only */
GICDistributor->ICDICFR[ 1] = 0x00000055;
GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
GICDistributor->ICDICFR[ 4] = 0x55555555;
GICDistributor->ICDICFR[ 5] = 0x55555555;
GICDistributor->ICDICFR[ 6] = 0x55555555;
GICDistributor->ICDICFR[ 7] = 0x55555555;
GICDistributor->ICDICFR[ 8] = 0x5555F555;
GICDistributor->ICDICFR[ 9] = 0x55555555;
GICDistributor->ICDICFR[10] = 0x55555555;
GICDistributor->ICDICFR[11] = 0xF5555555;
GICDistributor->ICDICFR[12] = 0xF555F555;
GICDistributor->ICDICFR[13] = 0x5555F555;
GICDistributor->ICDICFR[14] = 0x55555555;
GICDistributor->ICDICFR[15] = 0x55555555;
GICDistributor->ICDICFR[16] = 0x55555555;
GICDistributor->ICDICFR[17] = 0xFD555555;
GICDistributor->ICDICFR[18] = 0x55555557;
GICDistributor->ICDICFR[19] = 0x55555555;
GICDistributor->ICDICFR[20] = 0xFFD55555;
GICDistributor->ICDICFR[21] = 0x5F55557F;
GICDistributor->ICDICFR[22] = 0xFD55555F;
GICDistributor->ICDICFR[23] = 0x55555557;
GICDistributor->ICDICFR[24] = 0x55555555;
GICDistributor->ICDICFR[25] = 0x55555555;
GICDistributor->ICDICFR[26] = 0x55555555;
GICDistributor->ICDICFR[27] = 0x55555555;
GICDistributor->ICDICFR[28] = 0x55555555;
GICDistributor->ICDICFR[29] = 0x55555555;
GICDistributor->ICDICFR[30] = 0x55555555;
GICDistributor->ICDICFR[31] = 0x55555555;
GICDistributor->ICDICFR[32] = 0x55555555;
GICDistributor->ICDICFR[33] = 0x55555555;
//Enable distributor
GIC_EnableDistributor();
}
void GIC_CPUInterfaceInit(void)
{
IRQn_Type i;
uint32_t priority_field;
//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
//configuring all of the interrupts as Secure.
//Disable interrupt forwarding
GIC_DisableInterface();
/* Priority level is implementation defined.
To determine the number of priority bits implemented write 0xFF to an ICDIPR
priority field and read back the value stored.*/
GIC_SetPriority((IRQn_Type)0, 0xff);
priority_field = GIC_GetPriority((IRQn_Type)0);
//SGI and PPI
for (i = (IRQn_Type)0; i < 32; i++)
{
//Set level-sensitive and N-N model for PPI
//if(i > 15)
//GIC_SetLevelModel(i, 0, 0);
//Disable SGI and PPI interrupts
GIC_DisableIRQ(i);
//Set priority
GIC_SetPriority(i, priority_field/2);
}
//Enable interface
GIC_EnableInterface();
//Set binary point to 0
GIC_SetBinaryPoint(0);
//Set priority mask
GIC_InterfacePriorityMask(0xff);
}
void GIC_Enable(void)
{
GIC_DistInit();
GIC_CPUInterfaceInit(); //per CPU
}

316
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h
View File

@ -1,316 +0,0 @@
/**************************************************************************//**
* @file gic.h
* @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version
* @date 29 August 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef GIC_H_
#define GIC_H_
/* IO definitions (access restrictions to peripheral registers) */
/**
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
*/
typedef struct
{
__IO uint32_t ICDDCR;
__I uint32_t ICDICTR;
__I uint32_t ICDIIDR;
uint32_t RESERVED0[29];
__IO uint32_t ICDISR[32];
__IO uint32_t ICDISER[32];
__IO uint32_t ICDICER[32];
__IO uint32_t ICDISPR[32];
__IO uint32_t ICDICPR[32];
__I uint32_t ICDABR[32];
uint32_t RESERVED1[32];
__IO uint32_t ICDIPR[256];
__IO uint32_t ICDIPTR[256];
__IO uint32_t ICDICFR[64];
uint32_t RESERVED2[128];
__IO uint32_t ICDSGIR;
} GICDistributor_Type;
/** \brief Structure type to access the Controller Interface (GICC)
*/
typedef struct
{
__IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
__IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
__IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
__I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
__IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
__I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
__I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
__IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
uint32_t RESERVED[55];
__I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
} GICInterface_Type;
/*@} end of GICD */
/* ########################## GIC functions #################################### */
/** \brief Functions that manage interrupts via the GIC.
@{
*/
/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
Enables the forwarding of pending interrupts to the CPU interfaces.
*/
void GIC_EnableDistributor(void);
/** \brief Disable Distributor
Disables the forwarding of pending interrupts to the CPU interfaces.
*/
void GIC_DisableDistributor(void);
/** \brief Provides information about the configuration of the GIC.
Provides information about the configuration of the GIC.
- whether the GIC implements the Security Extensions
- the maximum number of interrupt IDs that the GIC supports
- the number of CPU interfaces implemented
- if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
\return Distributor Information.
*/
uint32_t GIC_DistributorInfo(void);
/** \brief Distributor Implementer Identification Register.
Distributor Implementer Identification Register
\return Implementer Information.
*/
uint32_t GIC_DistributorImplementer(void);
/** \brief Set list of processors that the interrupt is sent to if it is asserted.
The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
This field stores the list of processors that the interrupt is sent to if it is asserted.
\param [in] IRQn Interrupt number.
\param [in] target CPU target
*/
void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
/** \brief Get list of processors that the interrupt is sent to if it is asserted.
The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
This field stores the list of processors that the interrupt is sent to if it is asserted.
\param [in] IRQn Interrupt number.
\param [in] target CPU target
*/
uint32_t GIC_GetTarget(IRQn_Type IRQn);
/** \brief Enable Interface
Enables the signalling of interrupts to the target processors.
*/
void GIC_EnableInterface(void);
/** \brief Disable Interface
Disables the signalling of interrupts to the target processors.
*/
void GIC_DisableInterface(void);
/** \brief Acknowledge Interrupt
The function acknowledges the highest priority pending interrupt and returns its IRQ number.
\return Interrupt number
*/
IRQn_Type GIC_AcknowledgePending(void);
/** \brief End Interrupt
The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
\param [in] IRQn Interrupt number.
*/
void GIC_EndInterrupt(IRQn_Type IRQn);
/** \brief Enable Interrupt
Set-enable bit for each interrupt supported by the GIC.
\param [in] IRQn External interrupt number.
*/
void GIC_EnableIRQ(IRQn_Type IRQn);
/** \brief Disable Interrupt
Clear-enable bit for each interrupt supported by the GIC.
\param [in] IRQn Number of the external interrupt to disable
*/
void GIC_DisableIRQ(IRQn_Type IRQn);
/** \brief Set Pending Interrupt
Set-pending bit for each interrupt supported by the GIC.
\param [in] IRQn Interrupt number.
*/
void GIC_SetPendingIRQ(IRQn_Type IRQn);
/** \brief Clear Pending Interrupt
Clear-pending bit for each interrupt supported by the GIC
\param [in] IRQn Number of the interrupt for clear pending
*/
void GIC_ClearPendingIRQ(IRQn_Type IRQn);
/** \brief Int_config field for each interrupt supported by the GIC.
This field identifies whether the corresponding interrupt is:
(1) edge-triggered or (0) level-sensitive
(1) 1-N model or (0) N-N model
\param [in] IRQn Interrupt number.
\param [in] edge_level (1) edge-triggered or (0) level-sensitive
\param [in] model (1) 1-N model or (0) N-N model
*/
void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
*/
uint32_t GIC_GetPriority(IRQn_Type IRQn);
/** \brief CPU Interface Priority Mask Register
The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
value indicated by this field, the interface signals the interrupt to the processor.
\param [in] Mask.
*/
void GIC_InterfacePriorityMask(uint32_t priority);
/** \brief Set the binary point.
Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
\param [in] Mask.
*/
void GIC_SetBinaryPoint(uint32_t binary_point);
/** \brief Get the binary point.
Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
\return Binary point.
*/
uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
/** \brief Get Interrupt state.
Get the interrupt state, whether pending and/or active
\return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
*/
uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
/** \brief Send Software Generated interrupt
Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
GIC_InterfacePriorityMask
\param [in] IRQn The Interrupt ID of the SGI.
\param [in] target_list CPUTargetList
\param [in] filter_list TargetListFilter
*/
void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
/** \brief API call to initialise the interrupt distributor
API call to initialise the interrupt distributor
*/
void GIC_DistInit(void);
/** \brief API call to initialise the CPU interface
API call to initialise the CPU interface
*/
void GIC_CPUInterfaceInit(void);
/** \brief API call to set the Interrupt Configuration Registers
API call to initialise the Interrupt Configuration Registers
*/
void GIC_SetICDICFR (const uint32_t *ICDICFRn);
/** \brief API call to Enable the GIC
API call to Enable the GIC
*/
void GIC_Enable(void);
#endif /* GIC_H_ */

922
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h Normal file
View File

@ -0,0 +1,922 @@
/******************************************************************************
* @file VK_RZ_A1H.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version V1.00
* @data 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VK_RZ_A1H_H__
#define __VK_RZ_A1H_H__
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/****** SGI Interrupts Numbers ****************************************/
SGI0_IRQn = 0,
SGI1_IRQn = 1,
SGI2_IRQn = 2,
SGI3_IRQn = 3,
SGI4_IRQn = 4,
SGI5_IRQn = 5,
SGI6_IRQn = 6,
SGI7_IRQn = 7,
SGI8_IRQn = 8,
SGI9_IRQn = 9,
SGI10_IRQn = 10,
SGI11_IRQn = 11,
SGI12_IRQn = 12,
SGI13_IRQn = 13,
SGI14_IRQn = 14,
SGI15_IRQn = 15,
/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
/* 16 - 578 */
PMUIRQ0_IRQn = 16,
COMMRX0_IRQn = 17,
COMMTX0_IRQn = 18,
CTIIRQ0_IRQn = 19,
IRQ0_IRQn = 32,
IRQ1_IRQn = 33,
IRQ2_IRQn = 34,
IRQ3_IRQn = 35,
IRQ4_IRQn = 36,
IRQ5_IRQn = 37,
IRQ6_IRQn = 38,
IRQ7_IRQn = 39,
PL310ERR_IRQn = 40,
DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
DMAERR_IRQn = 57, /*!< DMAC Interrupt */
/* 58-72 Reserved */
USBI0_IRQn = 73,
USBI1_IRQn = 74,
S0_VI_VSYNC0_IRQn = 75,
S0_LO_VSYNC0_IRQn = 76,
S0_VSYNCERR0_IRQn = 77,
GR3_VLINE0_IRQn = 78,
S0_VFIELD0_IRQn = 79,
IV1_VBUFERR0_IRQn = 80,
IV3_VBUFERR0_IRQn = 81,
IV5_VBUFERR0_IRQn = 82,
IV6_VBUFERR0_IRQn = 83,
S0_WLINE0_IRQn = 84,
S1_VI_VSYNC0_IRQn = 85,
S1_LO_VSYNC0_IRQn = 86,
S1_VSYNCERR0_IRQn = 87,
S1_VFIELD0_IRQn = 88,
IV2_VBUFERR0_IRQn = 89,
IV4_VBUFERR0_IRQn = 90,
S1_WLINE0_IRQn = 91,
OIR_VI_VSYNC0_IRQn = 92,
OIR_LO_VSYNC0_IRQn = 93,
OIR_VSYNCERR0_IRQn = 94,
OIR_VFIELD0_IRQn = 95,
IV7_VBUFERR0_IRQn = 96,
IV8_VBUFERR0_IRQn = 97,
/* 98 Reserved */
S0_VI_VSYNC1_IRQn = 99,
S0_LO_VSYNC1_IRQn = 100,
S0_VSYNCERR1_IRQn = 101,
GR3_VLINE1_IRQn = 102,
S0_VFIELD1_IRQn = 103,
IV1_VBUFERR1_IRQn = 104,
IV3_VBUFERR1_IRQn = 105,
IV5_VBUFERR1_IRQn = 106,
IV6_VBUFERR1_IRQn = 107,
S0_WLINE1_IRQn = 108,
S1_VI_VSYNC1_IRQn = 109,
S1_LO_VSYNC1_IRQn = 110,
S1_VSYNCERR1_IRQn = 111,
S1_VFIELD1_IRQn = 112,
IV2_VBUFERR1_IRQn = 113,
IV4_VBUFERR1_IRQn = 114,
S1_WLINE1_IRQn = 115,
OIR_VI_VSYNC1_IRQn = 116,
OIR_LO_VSYNC1_IRQn = 117,
OIR_VSYNCERR1_IRQn = 118,
OIR_VFIELD1_IRQn = 119,
IV7_VBUFERR1_IRQn = 120,
IV8_VBUFERR1_IRQn = 121,
/* Reserved = 122 */
IMRDI_IRQn = 123,
IMR2I0_IRQn = 124,
IMR2I1_IRQn = 125,
JEDI_IRQn = 126,
JDTI_IRQn = 127,
CMP0_IRQn = 128,
CMP1_IRQn = 129,
INT0_IRQn = 130,
INT1_IRQn = 131,
INT2_IRQn = 132,
INT3_IRQn = 133,
OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
CMI_IRQn = 136,
WTOUT_IRQn = 137,
ITI_IRQn = 138,
TGI0A_IRQn = 139,
TGI0B_IRQn = 140,
TGI0C_IRQn = 141,
TGI0D_IRQn = 142,
TGI0V_IRQn = 143,
TGI0E_IRQn = 144,
TGI0F_IRQn = 145,
TGI1A_IRQn = 146,
TGI1B_IRQn = 147,
TGI1V_IRQn = 148,
TGI1U_IRQn = 149,
TGI2A_IRQn = 150,
TGI2B_IRQn = 151,
TGI2V_IRQn = 152,
TGI2U_IRQn = 153,
TGI3A_IRQn = 154,
TGI3B_IRQn = 155,
TGI3C_IRQn = 156,
TGI3D_IRQn = 157,
TGI3V_IRQn = 158,
TGI4A_IRQn = 159,
TGI4B_IRQn = 160,
TGI4C_IRQn = 161,
TGI4D_IRQn = 162,
TGI4V_IRQn = 163,
CMI1_IRQn = 164,
CMI2_IRQn = 165,
SGDEI0_IRQn = 166,
SGDEI1_IRQn = 167,
SGDEI2_IRQn = 168,
SGDEI3_IRQn = 169,
ADI_IRQn = 170,
LMTI_IRQn = 171,
SSII0_IRQn = 172, /*!< SSIF Interrupt */
SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
SSII1_IRQn = 175, /*!< SSIF Interrupt */
SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
SSII2_IRQn = 178, /*!< SSIF Interrupt */
SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
SSII3_IRQn = 180, /*!< SSIF Interrupt */
SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
SSII4_IRQn = 183, /*!< SSIF Interrupt */
SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
SSII5_IRQn = 185, /*!< SSIF Interrupt */
SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
SPDIFI_IRQn = 188,
INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
INTRCANGERR_IRQn = 253,
INTRCANGRECC_IRQn = 254,
INTRCAN0REC_IRQn = 255,
INTRCAN0ERR_IRQn = 256,
INTRCAN0TRX_IRQn = 257,
INTRCAN1REC_IRQn = 258,
INTRCAN1ERR_IRQn = 259,
INTRCAN1TRX_IRQn = 260,
INTRCAN2REC_IRQn = 261,
INTRCAN2ERR_IRQn = 262,
INTRCAN2TRX_IRQn = 263,
INTRCAN3REC_IRQn = 264,
INTRCAN3ERR_IRQn = 265,
INTRCAN3TRX_IRQn = 266,
INTRCAN4REC_IRQn = 267,
INTRCAN4ERR_IRQn = 268,
INTRCAN4TRX_IRQn = 269,
RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
IEBBTD_IRQn = 285,
IEBBTERR_IRQn = 286,
IEBBTSTA_IRQn = 287,
IEBBTV_IRQn = 288,
ISY_IRQn = 289,
IERR_IRQn = 290,
ITARG_IRQn = 291,
ISEC_IRQn = 292,
IBUF_IRQn = 293,
IREADY_IRQn = 294,
STERB_IRQn = 295,
FLTENDI_IRQn = 296,
FLTREQ0I_IRQn = 297,
FLTREQ1I_IRQn = 298,
MMC0_IRQn = 299,
MMC1_IRQn = 300,
MMC2_IRQn = 301,
SCHI0_3_IRQn = 302,
SDHI0_0_IRQn = 303,
SDHI0_1_IRQn = 304,
SCHI1_3_IRQn = 305,
SDHI1_0_IRQn = 306,
SDHI1_1_IRQn = 307,
ARM_IRQn = 308,
PRD_IRQn = 309,
CUP_IRQn = 310,
SCUAI0_IRQn = 311,
SCUAI1_IRQn = 312,
SCUFDI0_IRQn = 313,
SCUFDI1_IRQn = 314,
SCUFDI2_IRQn = 315,
SCUFDI3_IRQn = 316,
SCUFUI0_IRQn = 317,
SCUFUI1_IRQn = 318,
SCUFUI2_IRQn = 319,
SCUFUI3_IRQn = 320,
SCUDVI0_IRQn = 321,
SCUDVI1_IRQn = 322,
SCUDVI2_IRQn = 323,
SCUDVI3_IRQn = 324,
MLB_CINT_IRQn = 325,
MLB_SINT_IRQn = 326,
DRC10_IRQn = 327,
DRC11_IRQn = 328,
/* 329-330 Reserved */
LINI0_INT_T_IRQn = 331,
LINI0_INT_R_IRQn = 332,
LINI0_INT_S_IRQn = 333,
LINI0_INT_M_IRQn = 334,
LINI1_INT_T_IRQn = 335,
LINI1_INT_R_IRQn = 336,
LINI1_INT_S_IRQn = 337,
LINI1_INT_M_IRQn = 338,
/* 339-346 Reserved */
SCIERI0_IRQn = 347,
SCIRXI0_IRQn = 348,
SCITXI0_IRQn = 349,
SCITEI0_IRQn = 350,
SCIERI1_IRQn = 351,
SCIRXI1_IRQn = 352,
SCITXI1_IRQn = 353,
SCITEI1_IRQn = 354,
AVBI_DATA = 355,
AVBI_ERROR = 356,
AVBI_MANAGE = 357,
AVBI_MAC = 358,
ETHERI_IRQn = 359,
/* 360-363 Reserved */
CEUI_IRQn = 364,
/* 365-380 Reserved */
H2XMLB_ERRINT_IRQn = 381,
H2XIC1_ERRINT_IRQn = 382,
X2HPERI1_ERRINT_IRQn = 383,
X2HPERR2_ERRINT_IRQn = 384,
X2HPERR34_ERRINT_IRQn= 385,
X2HPERR5_ERRINT_IRQn = 386,
X2HPERR67_ERRINT_IRQn= 387,
X2HDBGR_ERRINT_IRQn = 388,
X2HBSC_ERRINT_IRQn = 389,
X2HSPI1_ERRINT_IRQn = 390,
X2HSPI2_ERRINT_IRQn = 391,
PRRI_IRQn = 392,
IFEI0_IRQn = 393,
OFFI0_IRQn = 394,
PFVEI0_IRQn = 395,
IFEI1_IRQn = 396,
OFFI1_IRQn = 397,
PFVEI1_IRQn = 398,
/* 399-415 Reserved */
TINT0_IRQn = 416,
TINT1_IRQn = 417,
TINT2_IRQn = 418,
TINT3_IRQn = 419,
TINT4_IRQn = 420,
TINT5_IRQn = 421,
TINT6_IRQn = 422,
TINT7_IRQn = 423,
TINT8_IRQn = 424,
TINT9_IRQn = 425,
TINT10_IRQn = 426,
TINT11_IRQn = 427,
TINT12_IRQn = 428,
TINT13_IRQn = 429,
TINT14_IRQn = 430,
TINT15_IRQn = 431,
TINT16_IRQn = 432,
TINT17_IRQn = 433,
TINT18_IRQn = 434,
TINT19_IRQn = 435,
TINT20_IRQn = 436,
TINT21_IRQn = 437,
TINT22_IRQn = 438,
TINT23_IRQn = 439,
TINT24_IRQn = 440,
TINT25_IRQn = 441,
TINT26_IRQn = 442,
TINT27_IRQn = 443,
TINT28_IRQn = 444,
TINT29_IRQn = 445,
TINT30_IRQn = 446,
TINT31_IRQn = 447,
TINT32_IRQn = 448,
TINT33_IRQn = 449,
TINT34_IRQn = 450,
TINT35_IRQn = 451,
TINT36_IRQn = 452,
TINT37_IRQn = 453,
TINT38_IRQn = 454,
TINT39_IRQn = 455,
TINT40_IRQn = 456,
TINT41_IRQn = 457,
TINT42_IRQn = 458,
TINT43_IRQn = 459,
TINT44_IRQn = 460,
TINT45_IRQn = 461,
TINT46_IRQn = 462,
TINT47_IRQn = 463,
TINT48_IRQn = 464,
TINT49_IRQn = 465,
TINT50_IRQn = 466,
TINT51_IRQn = 467,
TINT52_IRQn = 468,
TINT53_IRQn = 469,
TINT54_IRQn = 470,
TINT55_IRQn = 471,
TINT56_IRQn = 472,
TINT57_IRQn = 473,
TINT58_IRQn = 474,
TINT59_IRQn = 475,
TINT60_IRQn = 476,
TINT61_IRQn = 477,
TINT62_IRQn = 478,
TINT63_IRQn = 479,
TINT64_IRQn = 480,
TINT65_IRQn = 481,
TINT66_IRQn = 482,
TINT67_IRQn = 483,
TINT68_IRQn = 484,
TINT69_IRQn = 485,
TINT70_IRQn = 486,
TINT71_IRQn = 487,
TINT72_IRQn = 488,
TINT73_IRQn = 489,
TINT74_IRQn = 490,
TINT75_IRQn = 491,
TINT76_IRQn = 492,
TINT77_IRQn = 493,
TINT78_IRQn = 494,
TINT79_IRQn = 495,
TINT80_IRQn = 496,
TINT81_IRQn = 497,
TINT82_IRQn = 498,
TINT83_IRQn = 499,
TINT84_IRQn = 500,
TINT85_IRQn = 501,
TINT86_IRQn = 502,
TINT87_IRQn = 503,
TINT88_IRQn = 504,
TINT89_IRQn = 505,
TINT90_IRQn = 506,
TINT91_IRQn = 507,
TINT92_IRQn = 508,
TINT93_IRQn = 509,
TINT94_IRQn = 510,
TINT95_IRQn = 511,
TINT96_IRQn = 512,
TINT97_IRQn = 513,
TINT98_IRQn = 514,
TINT99_IRQn = 515,
TINT100_IRQn = 516,
TINT101_IRQn = 517,
TINT102_IRQn = 518,
TINT103_IRQn = 519,
TINT104_IRQn = 520,
TINT105_IRQn = 521,
TINT106_IRQn = 522,
TINT107_IRQn = 523,
TINT108_IRQn = 524,
TINT109_IRQn = 525,
TINT110_IRQn = 526,
TINT111_IRQn = 527,
TINT112_IRQn = 528,
TINT113_IRQn = 529,
TINT114_IRQn = 530,
TINT115_IRQn = 531,
TINT116_IRQn = 532,
TINT117_IRQn = 533,
TINT118_IRQn = 534,
TINT119_IRQn = 535,
TINT120_IRQn = 536,
TINT121_IRQn = 537,
TINT122_IRQn = 538,
TINT123_IRQn = 539,
TINT124_IRQn = 540,
TINT125_IRQn = 541,
TINT126_IRQn = 542,
TINT127_IRQn = 543,
TINT128_IRQn = 544,
TINT129_IRQn = 545,
TINT130_IRQn = 546,
TINT131_IRQn = 547,
TINT132_IRQn = 548,
TINT133_IRQn = 549,
TINT134_IRQn = 550,
TINT135_IRQn = 551,
TINT136_IRQn = 552,
TINT137_IRQn = 553,
TINT138_IRQn = 554,
TINT139_IRQn = 555,
TINT140_IRQn = 556,
TINT141_IRQn = 557,
TINT142_IRQn = 558,
TINT143_IRQn = 559,
TINT144_IRQn = 560,
TINT145_IRQn = 561,
TINT146_IRQn = 562,
TINT147_IRQn = 563,
TINT148_IRQn = 564,
TINT149_IRQn = 565,
TINT150_IRQn = 566,
TINT151_IRQn = 567,
TINT152_IRQn = 568,
TINT153_IRQn = 569,
TINT154_IRQn = 570,
TINT155_IRQn = 571,
TINT156_IRQn = 572,
TINT157_IRQn = 573,
TINT158_IRQn = 574,
TINT159_IRQn = 575,
TINT160_IRQn = 576,
TINT161_IRQn = 577,
TINT162_IRQn = 578,
TINT163_IRQn = 579,
TINT164_IRQn = 580,
TINT165_IRQn = 581,
TINT166_IRQn = 582,
TINT167_IRQn = 583,
TINT168_IRQn = 584,
TINT169_IRQn = 585,
TINT170_IRQn = 586
} IRQn_Type;
#define RZ_A1_IRQ_MAX TINT170_IRQn
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */
#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE
#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE
#define L2C_310_BASE RZ_A1_PL310_BASE
#define TIMER_BASE RZ_A1_PRIVATE_TIMER
/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
#define __CORTEX_A 9U /*!< Cortex-A9 Core */
#if (__FPU_PRESENT != 1)
#undef __FPU_PRESENT
#define __FPU_PRESENT 1U /* FPU present */
#endif
#define __GIC_PRESENT 1U /* GIC present */
#define __TIM_PRESENT 0U /* TIM present */
#define __L2C_PRESENT 1U /* L2C present */
#include "core_ca.h"
#include "nvic_wrapper.h"
#include <system_VK_RZ_A1H.h>
#include "iodefine.h"
/******************************************************************************/
/* Clock Settings */
/******************************************************************************/
/*
* Clock Mode 0 settings
* SW1-4(MD_CLK):ON
* SW1-5(MD_CLKS):ON
* FRQCR=0x1035
* CLKEN2 = 0b - unstable
* CLKEN[1:0]=01b - Output, Low, Low
* IFC[1:0] =00b - CPU clock is 1/1 PLL clock
* FRQCR2=0x0001
* GFC[1:0] =01b - Graphic clock is 2/3 bus clock
*/
#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
#define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
#define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
#define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
/*
* Clock Mode 1 settings
* SW1-4(MD_CLK):OFF
* SW1-5(MD_CLKS):ON
* FRQCR=0x1335
* CLKEN2 = 0b - unstable
* CLKEN[1:0]=01b - Output, Low, Low
* IFC[1:0] =11b - CPU clock is 1/3 PLL clock
* FRQCR2=0x0003
* GFC[1:0] =11b - graphic clock is 1/3 bus clock
*/
#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
#define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
#define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
#define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
/******************************************************************************/
/* CPG Settings */
/******************************************************************************/
#define CPG_FRQCR_SHIFT_CKOEN2 (14)
#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
#define CPG_FRQCR_SHIFT_CKOEN0 (12)
#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
#define CPG_FRQCR_SHIFT_IFC (8)
#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
#define CPG_FRQCR2_SHIFT_GFC (0)
#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
#define CPG_STBCR1_BIT_STBY (0x80u)
#define CPG_STBCR1_BIT_DEEP (0x40u)
#define CPG_STBCR2_BIT_HIZ (0x80u)
#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */
#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */
#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */
#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */
#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */
#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */
#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */
#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */
#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */
#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */
#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */
#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */
#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */
#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */
#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */
#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */
#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */
#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */
#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */
#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */
#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */
#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */
#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */
#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */
#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */
#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */
#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */
#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */
#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */
#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */
#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */
#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */
#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */
#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */
#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */
#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */
#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */
#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */
#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */
#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */
#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */
#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */
#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */
#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */
#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */
#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */
#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */
#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */
#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */
#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */
#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */
#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */
#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */
#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */
/******************************************************************************/
/* GPIO Settings */
/******************************************************************************/
#define GPIO_BIT_N0 (1u << 0)
#define GPIO_BIT_N1 (1u << 1)
#define GPIO_BIT_N2 (1u << 2)
#define GPIO_BIT_N3 (1u << 3)
#define GPIO_BIT_N4 (1u << 4)
#define GPIO_BIT_N5 (1u << 5)
#define GPIO_BIT_N6 (1u << 6)
#define GPIO_BIT_N7 (1u << 7)
#define GPIO_BIT_N8 (1u << 8)
#define GPIO_BIT_N9 (1u << 9)
#define GPIO_BIT_N10 (1u << 10)
#define GPIO_BIT_N11 (1u << 11)
#define GPIO_BIT_N12 (1u << 12)
#define GPIO_BIT_N13 (1u << 13)
#define GPIO_BIT_N14 (1u << 14)
#define GPIO_BIT_N15 (1u << 15)
#define MD_BOOT10_MASK (0x3)
#define MD_BOOT10_BM0 (0x0)
#define MD_BOOT10_BM1 (0x2)
#define MD_BOOT10_BM3 (0x1)
#define MD_BOOT10_BM4_5 (0x3)
#define MD_CLK (1u << 2)
#define MD_CLKS (1u << 3)
#ifdef __cplusplus
}
#endif
#endif // __VK_RZ_A1H_H__

151
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h
View File

@ -18,119 +18,56 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef R7S72100_IODEFINE_H
#define R7S72100_IODEFINE_H
#define IODEFINE_H_VERSION 100
#ifndef R7S721000_IODEFINE_H
#define R7S721000_IODEFINE_H
enum iodefine_byte_select_t
{
L = 0, H = 1,
LL= 0, LH = 1, HL = 2, HH = 3
};
#include "iodefines/iodefine_typedef.h" /* (V2.00h) */
/***********************************************************************
<<< [iodefine_reg32_t] >>>
- Padding : sizeof(iodefine_reg32_t) == 4
- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
- Endian : Independent (Same as CPU endian as register endian)
- Bit-Order : Independent
************************************************************************/
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union iodefine_reg32_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
volatile uint8_t UINT8[4]; /* 8-bit Access */
};
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/***********************************************************************
<<< [iodefine_reg32_16_t] >>>
- Padding : sizeof(iodefine_reg32_16_t) == 4
- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
- Endian : Independent (Same as CPU endian as register endian)
- Bit-Order : Independent
************************************************************************/
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union iodefine_reg32_16_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
};
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/***********************************************************************
<<< [iodefine_reg16_8_t] >>>
- Padding : sizeof(iodefine_reg16_8_t) == 2
- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
- Endian : Independent (Same as CPU endian as register endian)
- Bit-Order : Independent
************************************************************************/
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union iodefine_reg16_8_t
{
volatile uint16_t UINT16; /* 16-bit Access */
volatile uint8_t UINT8[2]; /* 8-bit Access */
};
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
#include "adc_iodefine.h" /* (V1.00a) */
#include "bsc_iodefine.h" /* (V1.00a) */
#include "ceu_iodefine.h" /* (V1.00a) */
#include "cpg_iodefine.h" /* (V1.00a) */
#include "disc_iodefine.h" /* (V1.00a) */
#include "dmac_iodefine.h" /* (V1.00a) */
#include "dvdec_iodefine.h" /* (V1.00a) */
#include "ether_iodefine.h" /* (V1.00a) */
#include "flctl_iodefine.h" /* (V1.00a) */
#include "gpio_iodefine.h" /* (V1.00a) */
#include "ieb_iodefine.h" /* (V1.00a) */
#include "inb_iodefine.h" /* (V1.00a) */
#include "intc_iodefine.h" /* (V1.00a) */
#include "irda_iodefine.h" /* (V1.00a) */
#include "jcu_iodefine.h" /* (V1.00a) */
#include "l2c_iodefine.h" /* (V1.00a) */
#include "lin_iodefine.h" /* (V1.00a) */
#include "lvds_iodefine.h" /* (V1.00a) */
#include "mlb_iodefine.h" /* (V1.00a) */
#include "mmc_iodefine.h" /* (V1.00a) */
#include "mtu2_iodefine.h" /* (V1.00a) */
#include "ostm_iodefine.h" /* (V1.00a) */
#include "pfv_iodefine.h" /* (V1.00a) */
#include "pwm_iodefine.h" /* (V1.00a) */
#include "riic_iodefine.h" /* (V1.00a) */
#include "romdec_iodefine.h" /* (V1.00a) */
#include "rscan0_iodefine.h" /* (V1.00a) */
#include "rspi_iodefine.h" /* (V1.00a) */
#include "rtc_iodefine.h" /* (V1.00a) */
#include "scif_iodefine.h" /* (V1.00a) */
#include "scim_iodefine.h" /* (V1.00a) */
#include "scux_iodefine.h" /* (V1.00a) */
#include "sdg_iodefine.h" /* (V1.00a) */
#include "spdif_iodefine.h" /* (V1.00a) */
#include "spibsc_iodefine.h" /* (V1.00a) */
#include "ssif_iodefine.h" /* (V1.00a) */
#include "usb20_iodefine.h" /* (V1.00a) */
#include "vdc5_iodefine.h" /* (V1.00a) */
#include "wdt_iodefine.h" /* (V1.00a) */
#include "iodefines/adc_iodefine.h" /* (V2.00h) */
#include "iodefines/bsc_iodefine.h" /* (V2.00h) */
#include "iodefines/ceu_iodefine.h" /* (V2.00h) */
#include "iodefines/cpg_iodefine.h" /* (V2.00h) */
#include "iodefines/disc_iodefine.h" /* (V2.00h) */
#include "iodefines/dmac_iodefine.h" /* (V2.00h) */
#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */
#include "iodefines/ether_iodefine.h" /* (V2.00h) */
#include "iodefines/flctl_iodefine.h" /* (V2.00h) */
#include "iodefines/gpio_iodefine.h" /* (V2.00h) */
#include "iodefines/ieb_iodefine.h" /* (V2.00h) */
#include "iodefines/inb_iodefine.h" /* (V2.00h) */
#include "iodefines/intc_iodefine.h" /* (V2.00h) */
#include "iodefines/irda_iodefine.h" /* (V2.00h) */
#include "iodefines/jcu_iodefine.h" /* (V2.00h) */
#include "iodefines/l2c_iodefine.h" /* (V2.00h) */
#include "iodefines/lin_iodefine.h" /* (V2.00h) */
#include "iodefines/lvds_iodefine.h" /* (V2.00h) */
#include "iodefines/mlb_iodefine.h" /* (V2.00h) */
#include "iodefines/mmc_iodefine.h" /* (V2.00h) */
#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */
#include "iodefines/ostm_iodefine.h" /* (V2.00h) */
#include "iodefines/pfv_iodefine.h" /* (V2.00h) */
#include "iodefines/pwm_iodefine.h" /* (V2.00h) */
#include "iodefines/riic_iodefine.h" /* (V2.00h) */
#include "iodefines/romdec_iodefine.h" /* (V2.00h) */
#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */
#include "iodefines/rspi_iodefine.h" /* (V2.00h) */
#include "iodefines/rtc_iodefine.h" /* (V2.00h) */
#include "iodefines/scif_iodefine.h" /* (V2.00h) */
#include "iodefines/scim_iodefine.h" /* (V2.00h) */
#include "iodefines/scux_iodefine.h" /* (V2.00h) */
#include "iodefines/sdg_iodefine.h" /* (V2.00h) */
#include "iodefines/spdif_iodefine.h" /* (V2.00h) */
#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */
#include "iodefines/ssif_iodefine.h" /* (V2.00h) */
#include "iodefines/usb20_iodefine.h" /* (V2.00h) */
#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */
#include "iodefines/wdt_iodefine.h" /* (V2.00h) */
#endif

79
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h
View File

@ -18,20 +18,56 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : adc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef ADC_IODEFINE_H
#define ADC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_adc
{ /* ADC */
#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
#define ADCADDRA (ADC.ADDRA)
#define ADCADDRB (ADC.ADDRB)
#define ADCADDRC (ADC.ADDRC)
#define ADCADDRD (ADC.ADDRD)
#define ADCADDRE (ADC.ADDRE)
#define ADCADDRF (ADC.ADDRF)
#define ADCADDRG (ADC.ADDRG)
#define ADCADDRH (ADC.ADDRH)
#define ADCADCMPHA (ADC.ADCMPHA)
#define ADCADCMPLA (ADC.ADCMPLA)
#define ADCADCMPHB (ADC.ADCMPHB)
#define ADCADCMPLB (ADC.ADCMPLB)
#define ADCADCMPHC (ADC.ADCMPHC)
#define ADCADCMPLC (ADC.ADCMPLC)
#define ADCADCMPHD (ADC.ADCMPHD)
#define ADCADCMPLD (ADC.ADCMPLD)
#define ADCADCMPHE (ADC.ADCMPHE)
#define ADCADCMPLE (ADC.ADCMPLE)
#define ADCADCMPHF (ADC.ADCMPHF)
#define ADCADCMPLF (ADC.ADCMPLF)
#define ADCADCMPHG (ADC.ADCMPHG)
#define ADCADCMPLG (ADC.ADCMPLG)
#define ADCADCMPHH (ADC.ADCMPHH)
#define ADCADCMPLH (ADC.ADCMPLH)
#define ADCADCSR (ADC.ADCSR)
#define ADCADCMPER (ADC.ADCMPER)
#define ADCADCMPSR (ADC.ADCMPSR)
typedef struct st_adc
{
/* ADC */
volatile uint16_t ADDRA; /* ADDRA */
volatile uint16_t ADDRB; /* ADDRB */
volatile uint16_t ADDRC; /* ADDRC */
@ -61,38 +97,11 @@ struct st_adc
volatile uint16_t ADCSR; /* ADCSR */
volatile uint16_t ADCMPER; /* ADCMPER */
volatile uint16_t ADCMPSR; /* ADCMPSR */
};
} r_io_adc_t;
#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
#define ADCADDRA ADC.ADDRA
#define ADCADDRB ADC.ADDRB
#define ADCADDRC ADC.ADDRC
#define ADCADDRD ADC.ADDRD
#define ADCADDRE ADC.ADDRE
#define ADCADDRF ADC.ADDRF
#define ADCADDRG ADC.ADDRG
#define ADCADDRH ADC.ADDRH
#define ADCADCMPHA ADC.ADCMPHA
#define ADCADCMPLA ADC.ADCMPLA
#define ADCADCMPHB ADC.ADCMPHB
#define ADCADCMPLB ADC.ADCMPLB
#define ADCADCMPHC ADC.ADCMPHC
#define ADCADCMPLC ADC.ADCMPLC
#define ADCADCMPHD ADC.ADCMPHD
#define ADCADCMPLD ADC.ADCMPLD
#define ADCADCMPHE ADC.ADCMPHE
#define ADCADCMPLE ADC.ADCMPLE
#define ADCADCMPHF ADC.ADCMPHF
#define ADCADCMPLF ADC.ADCMPLF
#define ADCADCMPHG ADC.ADCMPHG
#define ADCADCMPLG ADC.ADCMPLG
#define ADCADCMPHH ADC.ADCMPHH
#define ADCADCMPLH ADC.ADCMPLH
#define ADCADCSR ADC.ADCSR
#define ADCADCMPER ADC.ADCMPER
#define ADCADCMPSR ADC.ADCMPSR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

88
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h
View File

@ -18,22 +18,61 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef BSC_IODEFINE_H
#define BSC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_bsc
{ /* BSC */
#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
#define BSCCMNCR (BSC.CMNCR)
#define BSCCS0BCR (BSC.CS0BCR)
#define BSCCS1BCR (BSC.CS1BCR)
#define BSCCS2BCR (BSC.CS2BCR)
#define BSCCS3BCR (BSC.CS3BCR)
#define BSCCS4BCR (BSC.CS4BCR)
#define BSCCS5BCR (BSC.CS5BCR)
#define BSCCS0WCR (BSC.CS0WCR)
#define BSCCS1WCR (BSC.CS1WCR)
#define BSCCS2WCR (BSC.CS2WCR)
#define BSCCS3WCR (BSC.CS3WCR)
#define BSCCS4WCR (BSC.CS4WCR)
#define BSCCS5WCR (BSC.CS5WCR)
#define BSCSDCR (BSC.SDCR)
#define BSCRTCSR (BSC.RTCSR)
#define BSCRTCNT (BSC.RTCNT)
#define BSCRTCOR (BSC.RTCOR)
#define BSCTOSCOR0 (BSC.TOSCOR0)
#define BSCTOSCOR1 (BSC.TOSCOR1)
#define BSCTOSCOR2 (BSC.TOSCOR2)
#define BSCTOSCOR3 (BSC.TOSCOR3)
#define BSCTOSCOR4 (BSC.TOSCOR4)
#define BSCTOSCOR5 (BSC.TOSCOR5)
#define BSCTOSTR (BSC.TOSTR)
#define BSCTOENR (BSC.TOENR)
#define BSC_CSnBCR_COUNT (6)
#define BSC_CSnWCR_COUNT (6)
#define BSC_TOSCORn_COUNT (6)
typedef struct st_bsc
{
/* BSC */
volatile uint32_t CMNCR; /* CMNCR */
#define BSC_CSnBCR_COUNT 6
/* #define BSC_CSnBCR_COUNT (6) */
volatile uint32_t CS0BCR; /* CS0BCR */
volatile uint32_t CS1BCR; /* CS1BCR */
volatile uint32_t CS2BCR; /* CS2BCR */
@ -41,7 +80,8 @@ struct st_bsc
volatile uint32_t CS4BCR; /* CS4BCR */
volatile uint32_t CS5BCR; /* CS5BCR */
volatile uint8_t dummy4[12]; /* */
#define BSC_CSnWCR_COUNT 6
/* #define BSC_CSnWCR_COUNT (6) */
volatile uint32_t CS0WCR; /* CS0WCR */
volatile uint32_t CS1WCR; /* CS1WCR */
volatile uint32_t CS2WCR; /* CS2WCR */
@ -54,7 +94,8 @@ struct st_bsc
volatile uint32_t RTCNT; /* RTCNT */
volatile uint32_t RTCOR; /* RTCOR */
volatile uint8_t dummy6[4]; /* */
#define BSC_TOSCORn_COUNT 6
/* #define BSC_TOSCORn_COUNT (6) */
volatile uint32_t TOSCOR0; /* TOSCOR0 */
volatile uint32_t TOSCOR1; /* TOSCOR1 */
volatile uint32_t TOSCOR2; /* TOSCOR2 */
@ -64,36 +105,11 @@ struct st_bsc
volatile uint8_t dummy7[8]; /* */
volatile uint32_t TOSTR; /* TOSTR */
volatile uint32_t TOENR; /* TOENR */
};
} r_io_bsc_t;
#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
#define BSCCMNCR BSC.CMNCR
#define BSCCS0BCR BSC.CS0BCR
#define BSCCS1BCR BSC.CS1BCR
#define BSCCS2BCR BSC.CS2BCR
#define BSCCS3BCR BSC.CS3BCR
#define BSCCS4BCR BSC.CS4BCR
#define BSCCS5BCR BSC.CS5BCR
#define BSCCS0WCR BSC.CS0WCR
#define BSCCS1WCR BSC.CS1WCR
#define BSCCS2WCR BSC.CS2WCR
#define BSCCS3WCR BSC.CS3WCR
#define BSCCS4WCR BSC.CS4WCR
#define BSCCS5WCR BSC.CS5WCR
#define BSCSDCR BSC.SDCR
#define BSCRTCSR BSC.RTCSR
#define BSCRTCNT BSC.RTCNT
#define BSCRTCOR BSC.RTCOR
#define BSCTOSCOR0 BSC.TOSCOR0
#define BSCTOSCOR1 BSC.TOSCOR1
#define BSCTOSCOR2 BSC.TOSCOR2
#define BSCTOSCOR3 BSC.TOSCOR3
#define BSCTOSCOR4 BSC.TOSCOR4
#define BSCTOSCOR5 BSC.TOSCOR5
#define BSCTOSTR BSC.TOSTR
#define BSCTOENR BSC.TOENR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

198
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h
View File

@ -18,20 +18,108 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ceu_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef CEU_IODEFINE_H
#define CEU_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_ceu
{ /* CEU */
#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
/* Start of channel array defines of CEU */
/* Channel array defines of CEUn */
/*(Sample) value = CEUn[ channel ]->CAMOR; */
#define CEUn_COUNT (3)
#define CEUn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
(volatile struct st_ceu_n*)&CEU_A, \
(volatile struct st_ceu_n*)&CEU_B, \
(volatile struct st_ceu_n*)&CEU_M \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
/* End of channel array defines of CEU */
#define CEUCAPSR (CEU.CAPSR)
#define CEUCAPCR (CEU.CAPCR)
#define CEUCAMCR (CEU.CAMCR)
#define CEUCMCYR (CEU.CMCYR)
#define CEUCAMOR_A (CEU.CAMOR_A)
#define CEUCAPWR_A (CEU.CAPWR_A)
#define CEUCAIFR (CEU.CAIFR)
#define CEUCRCNTR (CEU.CRCNTR)
#define CEUCRCMPR (CEU.CRCMPR)
#define CEUCFLCR_A (CEU.CFLCR_A)
#define CEUCFSZR_A (CEU.CFSZR_A)
#define CEUCDWDR_A (CEU.CDWDR_A)
#define CEUCDAYR_A (CEU.CDAYR_A)
#define CEUCDACR_A (CEU.CDACR_A)
#define CEUCDBYR_A (CEU.CDBYR_A)
#define CEUCDBCR_A (CEU.CDBCR_A)
#define CEUCBDSR_A (CEU.CBDSR_A)
#define CEUCFWCR (CEU.CFWCR)
#define CEUCLFCR_A (CEU.CLFCR_A)
#define CEUCDOCR_A (CEU.CDOCR_A)
#define CEUCEIER (CEU.CEIER)
#define CEUCETCR (CEU.CETCR)
#define CEUCSTSR (CEU.CSTSR)
#define CEUCDSSR (CEU.CDSSR)
#define CEUCDAYR2_A (CEU.CDAYR2_A)
#define CEUCDACR2_A (CEU.CDACR2_A)
#define CEUCDBYR2_A (CEU.CDBYR2_A)
#define CEUCDBCR2_A (CEU.CDBCR2_A)
#define CEUCAMOR_B (CEU.CAMOR_B)
#define CEUCAPWR_B (CEU.CAPWR_B)
#define CEUCFLCR_B (CEU.CFLCR_B)
#define CEUCFSZR_B (CEU.CFSZR_B)
#define CEUCDWDR_B (CEU.CDWDR_B)
#define CEUCDAYR_B (CEU.CDAYR_B)
#define CEUCDACR_B (CEU.CDACR_B)
#define CEUCDBYR_B (CEU.CDBYR_B)
#define CEUCDBCR_B (CEU.CDBCR_B)
#define CEUCBDSR_B (CEU.CBDSR_B)
#define CEUCLFCR_B (CEU.CLFCR_B)
#define CEUCDOCR_B (CEU.CDOCR_B)
#define CEUCDAYR2_B (CEU.CDAYR2_B)
#define CEUCDACR2_B (CEU.CDACR2_B)
#define CEUCDBYR2_B (CEU.CDBYR2_B)
#define CEUCDBCR2_B (CEU.CDBCR2_B)
#define CEUCAMOR_M (CEU.CAMOR_M)
#define CEUCAPWR_M (CEU.CAPWR_M)
#define CEUCFLCR_M (CEU.CFLCR_M)
#define CEUCFSZR_M (CEU.CFSZR_M)
#define CEUCDWDR_M (CEU.CDWDR_M)
#define CEUCDAYR_M (CEU.CDAYR_M)
#define CEUCDACR_M (CEU.CDACR_M)
#define CEUCDBYR_M (CEU.CDBYR_M)
#define CEUCDBCR_M (CEU.CDBCR_M)
#define CEUCBDSR_M (CEU.CBDSR_M)
#define CEUCLFCR_M (CEU.CLFCR_M)
#define CEUCDOCR_M (CEU.CDOCR_M)
#define CEUCDAYR2_M (CEU.CDAYR2_M)
#define CEUCDACR2_M (CEU.CDACR2_M)
#define CEUCDBYR2_M (CEU.CDBYR2_M)
#define CEUCDBCR2_M (CEU.CDBCR2_M)
typedef struct st_ceu
{
/* CEU */
/* start of struct st_ceu_n */
volatile uint32_t CAPSR; /* CAPSR */
volatile uint32_t CAPCR; /* CAPCR */
@ -67,8 +155,10 @@ struct st_ceu
volatile uint32_t CDACR2_A; /* CDACR2_A */
volatile uint32_t CDBYR2_A; /* CDBYR2_A */
volatile uint32_t CDBCR2_A; /* CDBCR2_A */
/* end of struct st_ceu_n */
volatile uint8_t dummy3110[3936]; /* */
/* start of struct st_ceu_n */
volatile uint8_t dummy3111[4]; /* */
volatile uint8_t dummy3112[4]; /* */
@ -104,8 +194,10 @@ struct st_ceu
volatile uint32_t CDACR2_B; /* CDACR2_B */
volatile uint32_t CDBYR2_B; /* CDBYR2_B */
volatile uint32_t CDBCR2_B; /* CDBCR2_B */
/* end of struct st_ceu_n */
volatile uint8_t dummy3150[3936]; /* */
/* start of struct st_ceu_n */
volatile uint8_t dummy3151[4]; /* */
volatile uint8_t dummy3152[4]; /* */
@ -141,12 +233,14 @@ struct st_ceu
volatile uint32_t CDACR2_M; /* CDACR2_M */
volatile uint32_t CDBYR2_M; /* CDBYR2_M */
volatile uint32_t CDBCR2_M; /* CDBCR2_M */
/* end of struct st_ceu_n */
};
} r_io_ceu_t;
struct st_ceu_n
typedef struct st_ceu_n
{
volatile uint32_t not_common1; /* */
volatile uint32_t not_common2; /* */
volatile uint32_t not_common3; /* */
@ -181,89 +275,21 @@ struct st_ceu_n
volatile uint32_t CDACR2; /* CDACR2 */
volatile uint32_t CDBYR2; /* CDBYR2 */
volatile uint32_t CDBCR2; /* CDBCR2 */
};
} r_io_ceu_n_t;
#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
/* Channel array defines of CEUn (2)*/
#ifdef DECLARE_CEUn_CHANNELS
volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CEUn_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CEUn_CHANNELS */
/* End of channel array defines of CEUn (2)*/
/* Start of channnel array defines of CEU */
/* Channnel array defines of CEUn */
/*(Sample) value = CEUn[ channel ]->CAMOR; */
#define CEUn_COUNT 3
#define CEUn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
(volatile struct st_ceu_n*)&CEU_A, \
(volatile struct st_ceu_n*)&CEU_B, \
(volatile struct st_ceu_n*)&CEU_M \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
/* End of channnel array defines of CEU */
#define CEUCAPSR CEU.CAPSR
#define CEUCAPCR CEU.CAPCR
#define CEUCAMCR CEU.CAMCR
#define CEUCMCYR CEU.CMCYR
#define CEUCAMOR_A CEU.CAMOR_A
#define CEUCAPWR_A CEU.CAPWR_A
#define CEUCAIFR CEU.CAIFR
#define CEUCRCNTR CEU.CRCNTR
#define CEUCRCMPR CEU.CRCMPR
#define CEUCFLCR_A CEU.CFLCR_A
#define CEUCFSZR_A CEU.CFSZR_A
#define CEUCDWDR_A CEU.CDWDR_A
#define CEUCDAYR_A CEU.CDAYR_A
#define CEUCDACR_A CEU.CDACR_A
#define CEUCDBYR_A CEU.CDBYR_A
#define CEUCDBCR_A CEU.CDBCR_A
#define CEUCBDSR_A CEU.CBDSR_A
#define CEUCFWCR CEU.CFWCR
#define CEUCLFCR_A CEU.CLFCR_A
#define CEUCDOCR_A CEU.CDOCR_A
#define CEUCEIER CEU.CEIER
#define CEUCETCR CEU.CETCR
#define CEUCSTSR CEU.CSTSR
#define CEUCDSSR CEU.CDSSR
#define CEUCDAYR2_A CEU.CDAYR2_A
#define CEUCDACR2_A CEU.CDACR2_A
#define CEUCDBYR2_A CEU.CDBYR2_A
#define CEUCDBCR2_A CEU.CDBCR2_A
#define CEUCAMOR_B CEU.CAMOR_B
#define CEUCAPWR_B CEU.CAPWR_B
#define CEUCFLCR_B CEU.CFLCR_B
#define CEUCFSZR_B CEU.CFSZR_B
#define CEUCDWDR_B CEU.CDWDR_B
#define CEUCDAYR_B CEU.CDAYR_B
#define CEUCDACR_B CEU.CDACR_B
#define CEUCDBYR_B CEU.CDBYR_B
#define CEUCDBCR_B CEU.CDBCR_B
#define CEUCBDSR_B CEU.CBDSR_B
#define CEUCLFCR_B CEU.CLFCR_B
#define CEUCDOCR_B CEU.CDOCR_B
#define CEUCDAYR2_B CEU.CDAYR2_B
#define CEUCDACR2_B CEU.CDACR2_B
#define CEUCDBYR2_B CEU.CDBYR2_B
#define CEUCDBCR2_B CEU.CDBCR2_B
#define CEUCAMOR_M CEU.CAMOR_M
#define CEUCAPWR_M CEU.CAPWR_M
#define CEUCFLCR_M CEU.CFLCR_M
#define CEUCFSZR_M CEU.CFSZR_M
#define CEUCDWDR_M CEU.CDWDR_M
#define CEUCDAYR_M CEU.CDAYR_M
#define CEUCDACR_M CEU.CDACR_M
#define CEUCDBYR_M CEU.CDBYR_M
#define CEUCDBCR_M CEU.CDBCR_M
#define CEUCBDSR_M CEU.CBDSR_M
#define CEUCLFCR_M CEU.CLFCR_M
#define CEUCDOCR_M CEU.CDOCR_M
#define CEUCDAYR2_M CEU.CDAYR2_M
#define CEUCDACR2_M CEU.CDACR2_M
#define CEUCDBYR2_M CEU.CDBYR2_M
#define CEUCDBCR2_M CEU.CDBCR2_M
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

252
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h
View File

@ -18,20 +18,109 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : cpg_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef CPG_IODEFINE_H
#define CPG_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_cpg
{ /* CPG */
#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
/* Start of channel array defines of CPG */
/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3)
#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
#define CPG_FROM_STBCR3_ARRAY_COUNT (10)
#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
&CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
#define CPG_FROM_SYSCR1_ARRAY_COUNT (3)
#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
/* End of channel array defines of CPG */
#define CPGFRQCR (CPG.FRQCR)
#define CPGFRQCR2 (CPG.FRQCR2)
#define CPGCPUSTS (CPG.CPUSTS)
#define CPGSTBCR1 (CPG.STBCR1)
#define CPGSTBCR2 (CPG.STBCR2)
#define CPGSTBREQ1 (CPG.STBREQ1)
#define CPGSTBREQ2 (CPG.STBREQ2)
#define CPGSTBACK1 (CPG.STBACK1)
#define CPGSTBACK2 (CPG.STBACK2)
#define CPGSYSCR1 (CPG.SYSCR1)
#define CPGSYSCR2 (CPG.SYSCR2)
#define CPGSYSCR3 (CPG.SYSCR3)
#define CPGSTBCR3 (CPG.STBCR3)
#define CPGSTBCR4 (CPG.STBCR4)
#define CPGSTBCR5 (CPG.STBCR5)
#define CPGSTBCR6 (CPG.STBCR6)
#define CPGSTBCR7 (CPG.STBCR7)
#define CPGSTBCR8 (CPG.STBCR8)
#define CPGSTBCR9 (CPG.STBCR9)
#define CPGSTBCR10 (CPG.STBCR10)
#define CPGSTBCR11 (CPG.STBCR11)
#define CPGSTBCR12 (CPG.STBCR12)
#define CPGSWRSTCR1 (CPG.SWRSTCR1)
#define CPGSWRSTCR2 (CPG.SWRSTCR2)
#define CPGSWRSTCR3 (CPG.SWRSTCR3)
#define CPGSTBCR13 (CPG.STBCR13)
#define CPGRRAMKP (CPG.RRAMKP)
#define CPGDSCTR (CPG.DSCTR)
#define CPGDSSSR (CPG.DSSSR)
#define CPGDSESR (CPG.DSESR)
#define CPGDSFR (CPG.DSFR)
#define CPGXTALCTR (CPG.XTALCTR)
typedef struct st_cpg
{
/* CPG */
volatile uint16_t FRQCR; /* FRQCR */
volatile uint8_t dummy319[2]; /* */
volatile uint16_t FRQCR2; /* FRQCR2 */
@ -50,71 +139,103 @@ struct st_cpg
volatile uint8_t dummy326[3]; /* */
volatile uint8_t STBACK2; /* STBACK2 */
volatile uint8_t dummy327[955]; /* */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR1; /* SYSCR1 */
volatile uint8_t dummy328[3]; /* */
/* end of struct st_cpg_from_syscr1 */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR2; /* SYSCR2 */
volatile uint8_t dummy329[3]; /* */
/* end of struct st_cpg_from_syscr1 */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR3; /* SYSCR3 */
volatile uint8_t dummy3300[3]; /* */
/* end of struct st_cpg_from_syscr1 */
volatile uint8_t dummy3301[20]; /* */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR3; /* STBCR3 */
volatile uint8_t dummy331[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR4; /* STBCR4 */
volatile uint8_t dummy332[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR5; /* STBCR5 */
volatile uint8_t dummy333[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR6; /* STBCR6 */
volatile uint8_t dummy334[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR7; /* STBCR7 */
volatile uint8_t dummy335[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR8; /* STBCR8 */
volatile uint8_t dummy336[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR9; /* STBCR9 */
volatile uint8_t dummy337[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR10; /* STBCR10 */
volatile uint8_t dummy338[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR11; /* STBCR11 */
volatile uint8_t dummy339[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR12; /* STBCR12 */
volatile uint8_t dummy3400[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
volatile uint8_t dummy3401[24]; /* */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
volatile uint8_t dummy341[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR2; /* SWRSTCR2 */
volatile uint8_t dummy342[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR3; /* SWRSTCR3 */
volatile uint8_t dummy3430[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
volatile uint8_t dummy3431[4]; /* */
volatile uint8_t STBCR13; /* STBCR13 */
@ -128,112 +249,59 @@ struct st_cpg
volatile uint16_t DSFR; /* DSFR */
volatile uint8_t dummy347[6]; /* */
volatile uint8_t XTALCTR; /* XTALCTR */
};
} r_io_cpg_t;
struct st_cpg_from_syscr1
typedef struct st_cpg_from_syscr1
{
volatile uint8_t SYSCR1; /* SYSCR1 */
volatile uint8_t dummy1[3]; /* */
};
} r_io_cpg_from_syscr1_t;
struct st_cpg_from_stbcr3
typedef struct st_cpg_from_stbcr3
{
volatile uint8_t STBCR3; /* STBCR3 */
volatile uint8_t dummy1[3]; /* */
};
} r_io_cpg_from_stbcr3_t;
struct st_cpg_from_swrstcr1
typedef struct st_cpg_from_swrstcr1
{
volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
volatile uint8_t dummy1[3]; /* */
};
} r_io_cpg_from_swrstcr1_t;
#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
/* Channel array defines of CPG (2)*/
#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
/* End of channel array defines of CPG (2)*/
/* Start of channnel array defines of CPG */
/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3
#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
#define CPG_FROM_STBCR3_ARRAY_COUNT 10
#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
&CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
#define CPG_FROM_SYSCR1_ARRAY_COUNT 3
#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
/* End of channnel array defines of CPG */
#define CPGFRQCR CPG.FRQCR
#define CPGFRQCR2 CPG.FRQCR2
#define CPGCPUSTS CPG.CPUSTS
#define CPGSTBCR1 CPG.STBCR1
#define CPGSTBCR2 CPG.STBCR2
#define CPGSTBREQ1 CPG.STBREQ1
#define CPGSTBREQ2 CPG.STBREQ2
#define CPGSTBACK1 CPG.STBACK1
#define CPGSTBACK2 CPG.STBACK2
#define CPGSYSCR1 CPG.SYSCR1
#define CPGSYSCR2 CPG.SYSCR2
#define CPGSYSCR3 CPG.SYSCR3
#define CPGSTBCR3 CPG.STBCR3
#define CPGSTBCR4 CPG.STBCR4
#define CPGSTBCR5 CPG.STBCR5
#define CPGSTBCR6 CPG.STBCR6
#define CPGSTBCR7 CPG.STBCR7
#define CPGSTBCR8 CPG.STBCR8
#define CPGSTBCR9 CPG.STBCR9
#define CPGSTBCR10 CPG.STBCR10
#define CPGSTBCR11 CPG.STBCR11
#define CPGSTBCR12 CPG.STBCR12
#define CPGSWRSTCR1 CPG.SWRSTCR1
#define CPGSWRSTCR2 CPG.SWRSTCR2
#define CPGSWRSTCR3 CPG.SWRSTCR3
#define CPGSTBCR13 CPG.STBCR13
#define CPGRRAMKP CPG.RRAMKP
#define CPGDSCTR CPG.DSCTR
#define CPGDSSSR CPG.DSSSR
#define CPGDSESR CPG.DSESR
#define CPGDSFR CPG.DSFR
#define CPGXTALCTR CPG.XTALCTR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

107
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h
View File

@ -18,20 +18,67 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : disc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef DISC_IODEFINE_H
#define DISC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_disc
{ /* DISC */
#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
/* Start of channel array defines of DISC */
/* Channel array defines of DISC */
/*(Sample) value = DISC[ channel ]->DOCMCR; */
#define DISC_COUNT (2)
#define DISC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DISC0, &DISC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of DISC */
#define DISC0DOCMCR (DISC0.DOCMCR)
#define DISC0DOCMSTR (DISC0.DOCMSTR)
#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
#define DISC0DOCMIENR (DISC0.DOCMIENR)
#define DISC0DOCMPMR (DISC0.DOCMPMR)
#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
#define DISC1DOCMCR (DISC1.DOCMCR)
#define DISC1DOCMSTR (DISC1.DOCMSTR)
#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
#define DISC1DOCMIENR (DISC1.DOCMIENR)
#define DISC1DOCMPMR (DISC1.DOCMPMR)
#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
typedef struct st_disc
{
/* DISC */
volatile uint32_t DOCMCR; /* DOCMCR */
volatile uint32_t DOCMSTR; /* DOCMSTR */
volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */
@ -45,49 +92,21 @@ struct st_disc
volatile uint32_t DOCMSZXR; /* DOCMSZXR */
volatile uint32_t DOCMSZYR; /* DOCMSZYR */
volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */
};
} r_io_disc_t;
#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
/* Channel array defines of DISC (2)*/
#ifdef DECLARE_DISC_CHANNELS
volatile struct st_disc* DISC[ DISC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DISC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DISC_CHANNELS */
/* End of channel array defines of DISC (2)*/
/* Start of channnel array defines of DISC */
/* Channnel array defines of DISC */
/*(Sample) value = DISC[ channel ]->DOCMCR; */
#define DISC_COUNT 2
#define DISC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DISC0, &DISC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of DISC */
#define DISC0DOCMCR DISC0.DOCMCR
#define DISC0DOCMSTR DISC0.DOCMSTR
#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
#define DISC0DOCMIENR DISC0.DOCMIENR
#define DISC0DOCMPMR DISC0.DOCMPMR
#define DISC0DOCMECRCR DISC0.DOCMECRCR
#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
#define DISC0DOCMSPXR DISC0.DOCMSPXR
#define DISC0DOCMSPYR DISC0.DOCMSPYR
#define DISC0DOCMSZXR DISC0.DOCMSZXR
#define DISC0DOCMSZYR DISC0.DOCMSZYR
#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
#define DISC1DOCMCR DISC1.DOCMCR
#define DISC1DOCMSTR DISC1.DOCMSTR
#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
#define DISC1DOCMIENR DISC1.DOCMIENR
#define DISC1DOCMPMR DISC1.DOCMPMR
#define DISC1DOCMECRCR DISC1.DOCMECRCR
#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
#define DISC1DOCMSPXR DISC1.DOCMSPXR
#define DISC1DOCMSPYR DISC1.DOCMSPYR
#define DISC1DOCMSZXR DISC1.DOCMSZXR
#define DISC1DOCMSZYR DISC1.DOCMSZYR
#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

1384
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h
View File

File diff suppressed because it is too large Load Diff

532
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h
View File

@ -18,40 +18,289 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : dvdec_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef DVDEC_IODEFINE_H
#define DVDEC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_dvdec
{ /* DVDEC */
#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */
#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */
/* Start of channel array defines of DVDEC */
/* Channel array defines of DVDEC */
/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
#define DVDEC_COUNT (2)
#define DVDEC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DVDEC0, &DVDEC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of DVDEC */
#define ADCCR1_1 (DVDEC1.ADCCR1)
#define TGCR1_1 (DVDEC1.TGCR1)
#define TGCR2_1 (DVDEC1.TGCR2)
#define TGCR3_1 (DVDEC1.TGCR3)
#define SYNSCR1_1 (DVDEC1.SYNSCR1)
#define SYNSCR2_1 (DVDEC1.SYNSCR2)
#define SYNSCR3_1 (DVDEC1.SYNSCR3)
#define SYNSCR4_1 (DVDEC1.SYNSCR4)
#define SYNSCR5_1 (DVDEC1.SYNSCR5)
#define HAFCCR1_1 (DVDEC1.HAFCCR1)
#define HAFCCR2_1 (DVDEC1.HAFCCR2)
#define HAFCCR3_1 (DVDEC1.HAFCCR3)
#define VCDWCR1_1 (DVDEC1.VCDWCR1)
#define DCPCR1_1 (DVDEC1.DCPCR1)
#define DCPCR2_1 (DVDEC1.DCPCR2)
#define DCPCR3_1 (DVDEC1.DCPCR3)
#define DCPCR4_1 (DVDEC1.DCPCR4)
#define DCPCR5_1 (DVDEC1.DCPCR5)
#define DCPCR6_1 (DVDEC1.DCPCR6)
#define DCPCR7_1 (DVDEC1.DCPCR7)
#define DCPCR8_1 (DVDEC1.DCPCR8)
#define NSDCR_1 (DVDEC1.NSDCR)
#define BTLCR_1 (DVDEC1.BTLCR)
#define BTGPCR_1 (DVDEC1.BTGPCR)
#define ACCCR1_1 (DVDEC1.ACCCR1)
#define ACCCR2_1 (DVDEC1.ACCCR2)
#define ACCCR3_1 (DVDEC1.ACCCR3)
#define TINTCR_1 (DVDEC1.TINTCR)
#define YCDCR_1 (DVDEC1.YCDCR)
#define AGCCR1_1 (DVDEC1.AGCCR1)
#define AGCCR2_1 (DVDEC1.AGCCR2)
#define PKLIMITCR_1 (DVDEC1.PKLIMITCR)
#define RGORCR1_1 (DVDEC1.RGORCR1)
#define RGORCR2_1 (DVDEC1.RGORCR2)
#define RGORCR3_1 (DVDEC1.RGORCR3)
#define RGORCR4_1 (DVDEC1.RGORCR4)
#define RGORCR5_1 (DVDEC1.RGORCR5)
#define RGORCR6_1 (DVDEC1.RGORCR6)
#define RGORCR7_1 (DVDEC1.RGORCR7)
#define AFCPFCR_1 (DVDEC1.AFCPFCR)
#define RUPDCR_1 (DVDEC1.RUPDCR)
#define VSYNCSR_1 (DVDEC1.VSYNCSR)
#define HSYNCSR_1 (DVDEC1.HSYNCSR)
#define DCPSR1_1 (DVDEC1.DCPSR1)
#define DCPSR2_1 (DVDEC1.DCPSR2)
#define NSDSR_1 (DVDEC1.NSDSR)
#define CROMASR1_1 (DVDEC1.CROMASR1)
#define CROMASR2_1 (DVDEC1.CROMASR2)
#define SYNCSSR_1 (DVDEC1.SYNCSSR)
#define AGCCSR1_1 (DVDEC1.AGCCSR1)
#define AGCCSR2_1 (DVDEC1.AGCCSR2)
#define YCSCR3_1 (DVDEC1.YCSCR3)
#define YCSCR4_1 (DVDEC1.YCSCR4)
#define YCSCR5_1 (DVDEC1.YCSCR5)
#define YCSCR6_1 (DVDEC1.YCSCR6)
#define YCSCR7_1 (DVDEC1.YCSCR7)
#define YCSCR8_1 (DVDEC1.YCSCR8)
#define YCSCR9_1 (DVDEC1.YCSCR9)
#define YCSCR11_1 (DVDEC1.YCSCR11)
#define YCSCR12_1 (DVDEC1.YCSCR12)
#define DCPCR9_1 (DVDEC1.DCPCR9)
#define YCTWA_F0_1 (DVDEC1.YCTWA_F0)
#define YCTWA_F1_1 (DVDEC1.YCTWA_F1)
#define YCTWA_F2_1 (DVDEC1.YCTWA_F2)
#define YCTWA_F3_1 (DVDEC1.YCTWA_F3)
#define YCTWA_F4_1 (DVDEC1.YCTWA_F4)
#define YCTWA_F5_1 (DVDEC1.YCTWA_F5)
#define YCTWA_F6_1 (DVDEC1.YCTWA_F6)
#define YCTWA_F7_1 (DVDEC1.YCTWA_F7)
#define YCTWA_F8_1 (DVDEC1.YCTWA_F8)
#define YCTWB_F0_1 (DVDEC1.YCTWB_F0)
#define YCTWB_F1_1 (DVDEC1.YCTWB_F1)
#define YCTWB_F2_1 (DVDEC1.YCTWB_F2)
#define YCTWB_F3_1 (DVDEC1.YCTWB_F3)
#define YCTWB_F4_1 (DVDEC1.YCTWB_F4)
#define YCTWB_F5_1 (DVDEC1.YCTWB_F5)
#define YCTWB_F6_1 (DVDEC1.YCTWB_F6)
#define YCTWB_F7_1 (DVDEC1.YCTWB_F7)
#define YCTWB_F8_1 (DVDEC1.YCTWB_F8)
#define YCTNA_F0_1 (DVDEC1.YCTNA_F0)
#define YCTNA_F1_1 (DVDEC1.YCTNA_F1)
#define YCTNA_F2_1 (DVDEC1.YCTNA_F2)
#define YCTNA_F3_1 (DVDEC1.YCTNA_F3)
#define YCTNA_F4_1 (DVDEC1.YCTNA_F4)
#define YCTNA_F5_1 (DVDEC1.YCTNA_F5)
#define YCTNA_F6_1 (DVDEC1.YCTNA_F6)
#define YCTNA_F7_1 (DVDEC1.YCTNA_F7)
#define YCTNA_F8_1 (DVDEC1.YCTNA_F8)
#define YCTNB_F0_1 (DVDEC1.YCTNB_F0)
#define YCTNB_F1_1 (DVDEC1.YCTNB_F1)
#define YCTNB_F2_1 (DVDEC1.YCTNB_F2)
#define YCTNB_F3_1 (DVDEC1.YCTNB_F3)
#define YCTNB_F4_1 (DVDEC1.YCTNB_F4)
#define YCTNB_F5_1 (DVDEC1.YCTNB_F5)
#define YCTNB_F6_1 (DVDEC1.YCTNB_F6)
#define YCTNB_F7_1 (DVDEC1.YCTNB_F7)
#define YCTNB_F8_1 (DVDEC1.YCTNB_F8)
#define YGAINCR_1 (DVDEC1.YGAINCR)
#define CBGAINCR_1 (DVDEC1.CBGAINCR)
#define CRGAINCR_1 (DVDEC1.CRGAINCR)
#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE)
#define PGACR_1 (DVDEC1.PGACR)
#define ADCCR2_1 (DVDEC1.ADCCR2)
#define ADCCR1_0 (DVDEC0.ADCCR1)
#define TGCR1_0 (DVDEC0.TGCR1)
#define TGCR2_0 (DVDEC0.TGCR2)
#define TGCR3_0 (DVDEC0.TGCR3)
#define SYNSCR1_0 (DVDEC0.SYNSCR1)
#define SYNSCR2_0 (DVDEC0.SYNSCR2)
#define SYNSCR3_0 (DVDEC0.SYNSCR3)
#define SYNSCR4_0 (DVDEC0.SYNSCR4)
#define SYNSCR5_0 (DVDEC0.SYNSCR5)
#define HAFCCR1_0 (DVDEC0.HAFCCR1)
#define HAFCCR2_0 (DVDEC0.HAFCCR2)
#define HAFCCR3_0 (DVDEC0.HAFCCR3)
#define VCDWCR1_0 (DVDEC0.VCDWCR1)
#define DCPCR1_0 (DVDEC0.DCPCR1)
#define DCPCR2_0 (DVDEC0.DCPCR2)
#define DCPCR3_0 (DVDEC0.DCPCR3)
#define DCPCR4_0 (DVDEC0.DCPCR4)
#define DCPCR5_0 (DVDEC0.DCPCR5)
#define DCPCR6_0 (DVDEC0.DCPCR6)
#define DCPCR7_0 (DVDEC0.DCPCR7)
#define DCPCR8_0 (DVDEC0.DCPCR8)
#define NSDCR_0 (DVDEC0.NSDCR)
#define BTLCR_0 (DVDEC0.BTLCR)
#define BTGPCR_0 (DVDEC0.BTGPCR)
#define ACCCR1_0 (DVDEC0.ACCCR1)
#define ACCCR2_0 (DVDEC0.ACCCR2)
#define ACCCR3_0 (DVDEC0.ACCCR3)
#define TINTCR_0 (DVDEC0.TINTCR)
#define YCDCR_0 (DVDEC0.YCDCR)
#define AGCCR1_0 (DVDEC0.AGCCR1)
#define AGCCR2_0 (DVDEC0.AGCCR2)
#define PKLIMITCR_0 (DVDEC0.PKLIMITCR)
#define RGORCR1_0 (DVDEC0.RGORCR1)
#define RGORCR2_0 (DVDEC0.RGORCR2)
#define RGORCR3_0 (DVDEC0.RGORCR3)
#define RGORCR4_0 (DVDEC0.RGORCR4)
#define RGORCR5_0 (DVDEC0.RGORCR5)
#define RGORCR6_0 (DVDEC0.RGORCR6)
#define RGORCR7_0 (DVDEC0.RGORCR7)
#define AFCPFCR_0 (DVDEC0.AFCPFCR)
#define RUPDCR_0 (DVDEC0.RUPDCR)
#define VSYNCSR_0 (DVDEC0.VSYNCSR)
#define HSYNCSR_0 (DVDEC0.HSYNCSR)
#define DCPSR1_0 (DVDEC0.DCPSR1)
#define DCPSR2_0 (DVDEC0.DCPSR2)
#define NSDSR_0 (DVDEC0.NSDSR)
#define CROMASR1_0 (DVDEC0.CROMASR1)
#define CROMASR2_0 (DVDEC0.CROMASR2)
#define SYNCSSR_0 (DVDEC0.SYNCSSR)
#define AGCCSR1_0 (DVDEC0.AGCCSR1)
#define AGCCSR2_0 (DVDEC0.AGCCSR2)
#define YCSCR3_0 (DVDEC0.YCSCR3)
#define YCSCR4_0 (DVDEC0.YCSCR4)
#define YCSCR5_0 (DVDEC0.YCSCR5)
#define YCSCR6_0 (DVDEC0.YCSCR6)
#define YCSCR7_0 (DVDEC0.YCSCR7)
#define YCSCR8_0 (DVDEC0.YCSCR8)
#define YCSCR9_0 (DVDEC0.YCSCR9)
#define YCSCR11_0 (DVDEC0.YCSCR11)
#define YCSCR12_0 (DVDEC0.YCSCR12)
#define DCPCR9_0 (DVDEC0.DCPCR9)
#define YCTWA_F0_0 (DVDEC0.YCTWA_F0)
#define YCTWA_F1_0 (DVDEC0.YCTWA_F1)
#define YCTWA_F2_0 (DVDEC0.YCTWA_F2)
#define YCTWA_F3_0 (DVDEC0.YCTWA_F3)
#define YCTWA_F4_0 (DVDEC0.YCTWA_F4)
#define YCTWA_F5_0 (DVDEC0.YCTWA_F5)
#define YCTWA_F6_0 (DVDEC0.YCTWA_F6)
#define YCTWA_F7_0 (DVDEC0.YCTWA_F7)
#define YCTWA_F8_0 (DVDEC0.YCTWA_F8)
#define YCTWB_F0_0 (DVDEC0.YCTWB_F0)
#define YCTWB_F1_0 (DVDEC0.YCTWB_F1)
#define YCTWB_F2_0 (DVDEC0.YCTWB_F2)
#define YCTWB_F3_0 (DVDEC0.YCTWB_F3)
#define YCTWB_F4_0 (DVDEC0.YCTWB_F4)
#define YCTWB_F5_0 (DVDEC0.YCTWB_F5)
#define YCTWB_F6_0 (DVDEC0.YCTWB_F6)
#define YCTWB_F7_0 (DVDEC0.YCTWB_F7)
#define YCTWB_F8_0 (DVDEC0.YCTWB_F8)
#define YCTNA_F0_0 (DVDEC0.YCTNA_F0)
#define YCTNA_F1_0 (DVDEC0.YCTNA_F1)
#define YCTNA_F2_0 (DVDEC0.YCTNA_F2)
#define YCTNA_F3_0 (DVDEC0.YCTNA_F3)
#define YCTNA_F4_0 (DVDEC0.YCTNA_F4)
#define YCTNA_F5_0 (DVDEC0.YCTNA_F5)
#define YCTNA_F6_0 (DVDEC0.YCTNA_F6)
#define YCTNA_F7_0 (DVDEC0.YCTNA_F7)
#define YCTNA_F8_0 (DVDEC0.YCTNA_F8)
#define YCTNB_F0_0 (DVDEC0.YCTNB_F0)
#define YCTNB_F1_0 (DVDEC0.YCTNB_F1)
#define YCTNB_F2_0 (DVDEC0.YCTNB_F2)
#define YCTNB_F3_0 (DVDEC0.YCTNB_F3)
#define YCTNB_F4_0 (DVDEC0.YCTNB_F4)
#define YCTNB_F5_0 (DVDEC0.YCTNB_F5)
#define YCTNB_F6_0 (DVDEC0.YCTNB_F6)
#define YCTNB_F7_0 (DVDEC0.YCTNB_F7)
#define YCTNB_F8_0 (DVDEC0.YCTNB_F8)
#define YGAINCR_0 (DVDEC0.YGAINCR)
#define CBGAINCR_0 (DVDEC0.CBGAINCR)
#define CRGAINCR_0 (DVDEC0.CRGAINCR)
#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE)
#define PGACR_0 (DVDEC0.PGACR)
#define ADCCR2_0 (DVDEC0.ADCCR2)
#define DVDEC_TGCRn_COUNT (3)
#define DVDEC_SYNSCRn_COUNT (5)
#define DVDEC_HAFCCRn_COUNT (3)
#define DVDEC_DCPCRn_COUNT (8)
#define DVDEC_ACCCRn_COUNT (3)
#define DVDEC_AGCCRn_COUNT (2)
#define DVDEC_RGORCRn_COUNT (7)
#define DVDEC_DCPSRn_COUNT (2)
#define DVDEC_CROMASRn_COUNT (2)
#define DVDEC_AGCCSRn_COUNT (2)
#define DVDEC_YCSCRn_COUNT (7)
#define DVDEC_YCTWA_Fn_COUNT (9)
#define DVDEC_YCTWB_Fn_COUNT (9)
#define DVDEC_YCTNA_Fn_COUNT (9)
#define DVDEC_YCTNB_Fn_COUNT (9)
typedef struct st_dvdec
{
/* DVDEC */
volatile uint16_t ADCCR1; /* ADCCR1 */
volatile uint8_t dummy1[4]; /* */
#define DVDEC_TGCRn_COUNT 3
/* #define DVDEC_TGCRn_COUNT (3) */
volatile uint16_t TGCR1; /* TGCR1 */
volatile uint16_t TGCR2; /* TGCR2 */
volatile uint16_t TGCR3; /* TGCR3 */
volatile uint8_t dummy2[6]; /* */
#define DVDEC_SYNSCRn_COUNT 5
/* #define DVDEC_SYNSCRn_COUNT (5) */
volatile uint16_t SYNSCR1; /* SYNSCR1 */
volatile uint16_t SYNSCR2; /* SYNSCR2 */
volatile uint16_t SYNSCR3; /* SYNSCR3 */
volatile uint16_t SYNSCR4; /* SYNSCR4 */
volatile uint16_t SYNSCR5; /* SYNSCR5 */
#define DVDEC_HAFCCRn_COUNT 3
/* #define DVDEC_HAFCCRn_COUNT (3) */
volatile uint16_t HAFCCR1; /* HAFCCR1 */
volatile uint16_t HAFCCR2; /* HAFCCR2 */
volatile uint16_t HAFCCR3; /* HAFCCR3 */
volatile uint16_t VCDWCR1; /* VCDWCR1 */
volatile uint8_t dummy3[4]; /* */
#define DVDEC_DCPCRn_COUNT 8
/* #define DVDEC_DCPCRn_COUNT (8) */
volatile uint16_t DCPCR1; /* DCPCR1 */
volatile uint16_t DCPCR2; /* DCPCR2 */
volatile uint16_t DCPCR3; /* DCPCR3 */
@ -63,17 +312,20 @@ struct st_dvdec
volatile uint16_t NSDCR; /* NSDCR */
volatile uint16_t BTLCR; /* BTLCR */
volatile uint16_t BTGPCR; /* BTGPCR */
#define DVDEC_ACCCRn_COUNT 3
/* #define DVDEC_ACCCRn_COUNT (3) */
volatile uint16_t ACCCR1; /* ACCCR1 */
volatile uint16_t ACCCR2; /* ACCCR2 */
volatile uint16_t ACCCR3; /* ACCCR3 */
volatile uint16_t TINTCR; /* TINTCR */
volatile uint16_t YCDCR; /* YCDCR */
#define DVDEC_AGCCRn_COUNT 2
/* #define DVDEC_AGCCRn_COUNT (2) */
volatile uint16_t AGCCR1; /* AGCCR1 */
volatile uint16_t AGCCR2; /* AGCCR2 */
volatile uint16_t PKLIMITCR; /* PKLIMITCR */
#define DVDEC_RGORCRn_COUNT 7
/* #define DVDEC_RGORCRn_COUNT (7) */
volatile uint16_t RGORCR1; /* RGORCR1 */
volatile uint16_t RGORCR2; /* RGORCR2 */
volatile uint16_t RGORCR3; /* RGORCR3 */
@ -86,20 +338,24 @@ struct st_dvdec
volatile uint16_t RUPDCR; /* RUPDCR */
volatile uint16_t VSYNCSR; /* VSYNCSR */
volatile uint16_t HSYNCSR; /* HSYNCSR */
#define DVDEC_DCPSRn_COUNT 2
/* #define DVDEC_DCPSRn_COUNT (2) */
volatile uint16_t DCPSR1; /* DCPSR1 */
volatile uint16_t DCPSR2; /* DCPSR2 */
volatile uint8_t dummy5[4]; /* */
volatile uint16_t NSDSR; /* NSDSR */
#define DVDEC_CROMASRn_COUNT 2
/* #define DVDEC_CROMASRn_COUNT (2) */
volatile uint16_t CROMASR1; /* CROMASR1 */
volatile uint16_t CROMASR2; /* CROMASR2 */
volatile uint16_t SYNCSSR; /* SYNCSSR */
#define DVDEC_AGCCSRn_COUNT 2
/* #define DVDEC_AGCCSRn_COUNT (2) */
volatile uint16_t AGCCSR1; /* AGCCSR1 */
volatile uint16_t AGCCSR2; /* AGCCSR2 */
volatile uint8_t dummy6[108]; /* */
#define DVDEC_YCSCRn_COUNT 7
/* #define DVDEC_YCSCRn_COUNT (7) */
volatile uint16_t YCSCR3; /* YCSCR3 */
volatile uint16_t YCSCR4; /* YCSCR4 */
volatile uint16_t YCSCR5; /* YCSCR5 */
@ -113,7 +369,8 @@ struct st_dvdec
volatile uint8_t dummy8[104]; /* */
volatile uint16_t DCPCR9; /* DCPCR9 */
volatile uint8_t dummy9[16]; /* */
#define DVDEC_YCTWA_Fn_COUNT 9
/* #define DVDEC_YCTWA_Fn_COUNT (9) */
volatile uint16_t YCTWA_F0; /* YCTWA_F0 */
volatile uint16_t YCTWA_F1; /* YCTWA_F1 */
volatile uint16_t YCTWA_F2; /* YCTWA_F2 */
@ -123,7 +380,8 @@ struct st_dvdec
volatile uint16_t YCTWA_F6; /* YCTWA_F6 */
volatile uint16_t YCTWA_F7; /* YCTWA_F7 */
volatile uint16_t YCTWA_F8; /* YCTWA_F8 */
#define DVDEC_YCTWB_Fn_COUNT 9
/* #define DVDEC_YCTWB_Fn_COUNT (9) */
volatile uint16_t YCTWB_F0; /* YCTWB_F0 */
volatile uint16_t YCTWB_F1; /* YCTWB_F1 */
volatile uint16_t YCTWB_F2; /* YCTWB_F2 */
@ -133,7 +391,8 @@ struct st_dvdec
volatile uint16_t YCTWB_F6; /* YCTWB_F6 */
volatile uint16_t YCTWB_F7; /* YCTWB_F7 */
volatile uint16_t YCTWB_F8; /* YCTWB_F8 */
#define DVDEC_YCTNA_Fn_COUNT 9
/* #define DVDEC_YCTNA_Fn_COUNT (9) */
volatile uint16_t YCTNA_F0; /* YCTNA_F0 */
volatile uint16_t YCTNA_F1; /* YCTNA_F1 */
volatile uint16_t YCTNA_F2; /* YCTNA_F2 */
@ -143,7 +402,8 @@ struct st_dvdec
volatile uint16_t YCTNA_F6; /* YCTNA_F6 */
volatile uint16_t YCTNA_F7; /* YCTNA_F7 */
volatile uint16_t YCTNA_F8; /* YCTNA_F8 */
#define DVDEC_YCTNB_Fn_COUNT 9
/* #define DVDEC_YCTNB_Fn_COUNT (9) */
volatile uint16_t YCTNB_F0; /* YCTNB_F0 */
volatile uint16_t YCTNB_F1; /* YCTNB_F1 */
volatile uint16_t YCTNB_F2; /* YCTNB_F2 */
@ -161,231 +421,21 @@ struct st_dvdec
volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */
volatile uint16_t PGACR; /* PGACR */
volatile uint16_t ADCCR2; /* ADCCR2 */
};
} r_io_dvdec_t;
#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */
#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */
/* Channel array defines of DVDEC (2)*/
#ifdef DECLARE_DVDEC_CHANNELS
volatile struct st_dvdec* DVDEC[ DVDEC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DVDEC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DVDEC_CHANNELS */
/* End of channel array defines of DVDEC (2)*/
/* Start of channnel array defines of DVDEC */
/* Channnel array defines of DVDEC */
/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
#define DVDEC_COUNT 2
#define DVDEC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DVDEC0, &DVDEC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of DVDEC */
#define ADCCR1_1 DVDEC1.ADCCR1
#define TGCR1_1 DVDEC1.TGCR1
#define TGCR2_1 DVDEC1.TGCR2
#define TGCR3_1 DVDEC1.TGCR3
#define SYNSCR1_1 DVDEC1.SYNSCR1
#define SYNSCR2_1 DVDEC1.SYNSCR2
#define SYNSCR3_1 DVDEC1.SYNSCR3
#define SYNSCR4_1 DVDEC1.SYNSCR4
#define SYNSCR5_1 DVDEC1.SYNSCR5
#define HAFCCR1_1 DVDEC1.HAFCCR1
#define HAFCCR2_1 DVDEC1.HAFCCR2
#define HAFCCR3_1 DVDEC1.HAFCCR3
#define VCDWCR1_1 DVDEC1.VCDWCR1
#define DCPCR1_1 DVDEC1.DCPCR1
#define DCPCR2_1 DVDEC1.DCPCR2
#define DCPCR3_1 DVDEC1.DCPCR3
#define DCPCR4_1 DVDEC1.DCPCR4
#define DCPCR5_1 DVDEC1.DCPCR5
#define DCPCR6_1 DVDEC1.DCPCR6
#define DCPCR7_1 DVDEC1.DCPCR7
#define DCPCR8_1 DVDEC1.DCPCR8
#define NSDCR_1 DVDEC1.NSDCR
#define BTLCR_1 DVDEC1.BTLCR
#define BTGPCR_1 DVDEC1.BTGPCR
#define ACCCR1_1 DVDEC1.ACCCR1
#define ACCCR2_1 DVDEC1.ACCCR2
#define ACCCR3_1 DVDEC1.ACCCR3
#define TINTCR_1 DVDEC1.TINTCR
#define YCDCR_1 DVDEC1.YCDCR
#define AGCCR1_1 DVDEC1.AGCCR1
#define AGCCR2_1 DVDEC1.AGCCR2
#define PKLIMITCR_1 DVDEC1.PKLIMITCR
#define RGORCR1_1 DVDEC1.RGORCR1
#define RGORCR2_1 DVDEC1.RGORCR2
#define RGORCR3_1 DVDEC1.RGORCR3
#define RGORCR4_1 DVDEC1.RGORCR4
#define RGORCR5_1 DVDEC1.RGORCR5
#define RGORCR6_1 DVDEC1.RGORCR6
#define RGORCR7_1 DVDEC1.RGORCR7
#define AFCPFCR_1 DVDEC1.AFCPFCR
#define RUPDCR_1 DVDEC1.RUPDCR
#define VSYNCSR_1 DVDEC1.VSYNCSR
#define HSYNCSR_1 DVDEC1.HSYNCSR
#define DCPSR1_1 DVDEC1.DCPSR1
#define DCPSR2_1 DVDEC1.DCPSR2
#define NSDSR_1 DVDEC1.NSDSR
#define CROMASR1_1 DVDEC1.CROMASR1
#define CROMASR2_1 DVDEC1.CROMASR2
#define SYNCSSR_1 DVDEC1.SYNCSSR
#define AGCCSR1_1 DVDEC1.AGCCSR1
#define AGCCSR2_1 DVDEC1.AGCCSR2
#define YCSCR3_1 DVDEC1.YCSCR3
#define YCSCR4_1 DVDEC1.YCSCR4
#define YCSCR5_1 DVDEC1.YCSCR5
#define YCSCR6_1 DVDEC1.YCSCR6
#define YCSCR7_1 DVDEC1.YCSCR7
#define YCSCR8_1 DVDEC1.YCSCR8
#define YCSCR9_1 DVDEC1.YCSCR9
#define YCSCR11_1 DVDEC1.YCSCR11
#define YCSCR12_1 DVDEC1.YCSCR12
#define DCPCR9_1 DVDEC1.DCPCR9
#define YCTWA_F0_1 DVDEC1.YCTWA_F0
#define YCTWA_F1_1 DVDEC1.YCTWA_F1
#define YCTWA_F2_1 DVDEC1.YCTWA_F2
#define YCTWA_F3_1 DVDEC1.YCTWA_F3
#define YCTWA_F4_1 DVDEC1.YCTWA_F4
#define YCTWA_F5_1 DVDEC1.YCTWA_F5
#define YCTWA_F6_1 DVDEC1.YCTWA_F6
#define YCTWA_F7_1 DVDEC1.YCTWA_F7
#define YCTWA_F8_1 DVDEC1.YCTWA_F8
#define YCTWB_F0_1 DVDEC1.YCTWB_F0
#define YCTWB_F1_1 DVDEC1.YCTWB_F1
#define YCTWB_F2_1 DVDEC1.YCTWB_F2
#define YCTWB_F3_1 DVDEC1.YCTWB_F3
#define YCTWB_F4_1 DVDEC1.YCTWB_F4
#define YCTWB_F5_1 DVDEC1.YCTWB_F5
#define YCTWB_F6_1 DVDEC1.YCTWB_F6
#define YCTWB_F7_1 DVDEC1.YCTWB_F7
#define YCTWB_F8_1 DVDEC1.YCTWB_F8
#define YCTNA_F0_1 DVDEC1.YCTNA_F0
#define YCTNA_F1_1 DVDEC1.YCTNA_F1
#define YCTNA_F2_1 DVDEC1.YCTNA_F2
#define YCTNA_F3_1 DVDEC1.YCTNA_F3
#define YCTNA_F4_1 DVDEC1.YCTNA_F4
#define YCTNA_F5_1 DVDEC1.YCTNA_F5
#define YCTNA_F6_1 DVDEC1.YCTNA_F6
#define YCTNA_F7_1 DVDEC1.YCTNA_F7
#define YCTNA_F8_1 DVDEC1.YCTNA_F8
#define YCTNB_F0_1 DVDEC1.YCTNB_F0
#define YCTNB_F1_1 DVDEC1.YCTNB_F1
#define YCTNB_F2_1 DVDEC1.YCTNB_F2
#define YCTNB_F3_1 DVDEC1.YCTNB_F3
#define YCTNB_F4_1 DVDEC1.YCTNB_F4
#define YCTNB_F5_1 DVDEC1.YCTNB_F5
#define YCTNB_F6_1 DVDEC1.YCTNB_F6
#define YCTNB_F7_1 DVDEC1.YCTNB_F7
#define YCTNB_F8_1 DVDEC1.YCTNB_F8
#define YGAINCR_1 DVDEC1.YGAINCR
#define CBGAINCR_1 DVDEC1.CBGAINCR
#define CRGAINCR_1 DVDEC1.CRGAINCR
#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
#define PGACR_1 DVDEC1.PGACR
#define ADCCR2_1 DVDEC1.ADCCR2
#define ADCCR1_0 DVDEC0.ADCCR1
#define TGCR1_0 DVDEC0.TGCR1
#define TGCR2_0 DVDEC0.TGCR2
#define TGCR3_0 DVDEC0.TGCR3
#define SYNSCR1_0 DVDEC0.SYNSCR1
#define SYNSCR2_0 DVDEC0.SYNSCR2
#define SYNSCR3_0 DVDEC0.SYNSCR3
#define SYNSCR4_0 DVDEC0.SYNSCR4
#define SYNSCR5_0 DVDEC0.SYNSCR5
#define HAFCCR1_0 DVDEC0.HAFCCR1
#define HAFCCR2_0 DVDEC0.HAFCCR2
#define HAFCCR3_0 DVDEC0.HAFCCR3
#define VCDWCR1_0 DVDEC0.VCDWCR1
#define DCPCR1_0 DVDEC0.DCPCR1
#define DCPCR2_0 DVDEC0.DCPCR2
#define DCPCR3_0 DVDEC0.DCPCR3
#define DCPCR4_0 DVDEC0.DCPCR4
#define DCPCR5_0 DVDEC0.DCPCR5
#define DCPCR6_0 DVDEC0.DCPCR6
#define DCPCR7_0 DVDEC0.DCPCR7
#define DCPCR8_0 DVDEC0.DCPCR8
#define NSDCR_0 DVDEC0.NSDCR
#define BTLCR_0 DVDEC0.BTLCR
#define BTGPCR_0 DVDEC0.BTGPCR
#define ACCCR1_0 DVDEC0.ACCCR1
#define ACCCR2_0 DVDEC0.ACCCR2
#define ACCCR3_0 DVDEC0.ACCCR3
#define TINTCR_0 DVDEC0.TINTCR
#define YCDCR_0 DVDEC0.YCDCR
#define AGCCR1_0 DVDEC0.AGCCR1
#define AGCCR2_0 DVDEC0.AGCCR2
#define PKLIMITCR_0 DVDEC0.PKLIMITCR
#define RGORCR1_0 DVDEC0.RGORCR1
#define RGORCR2_0 DVDEC0.RGORCR2
#define RGORCR3_0 DVDEC0.RGORCR3
#define RGORCR4_0 DVDEC0.RGORCR4
#define RGORCR5_0 DVDEC0.RGORCR5
#define RGORCR6_0 DVDEC0.RGORCR6
#define RGORCR7_0 DVDEC0.RGORCR7
#define AFCPFCR_0 DVDEC0.AFCPFCR
#define RUPDCR_0 DVDEC0.RUPDCR
#define VSYNCSR_0 DVDEC0.VSYNCSR
#define HSYNCSR_0 DVDEC0.HSYNCSR
#define DCPSR1_0 DVDEC0.DCPSR1
#define DCPSR2_0 DVDEC0.DCPSR2
#define NSDSR_0 DVDEC0.NSDSR
#define CROMASR1_0 DVDEC0.CROMASR1
#define CROMASR2_0 DVDEC0.CROMASR2
#define SYNCSSR_0 DVDEC0.SYNCSSR
#define AGCCSR1_0 DVDEC0.AGCCSR1
#define AGCCSR2_0 DVDEC0.AGCCSR2
#define YCSCR3_0 DVDEC0.YCSCR3
#define YCSCR4_0 DVDEC0.YCSCR4
#define YCSCR5_0 DVDEC0.YCSCR5
#define YCSCR6_0 DVDEC0.YCSCR6
#define YCSCR7_0 DVDEC0.YCSCR7
#define YCSCR8_0 DVDEC0.YCSCR8
#define YCSCR9_0 DVDEC0.YCSCR9
#define YCSCR11_0 DVDEC0.YCSCR11
#define YCSCR12_0 DVDEC0.YCSCR12
#define DCPCR9_0 DVDEC0.DCPCR9
#define YCTWA_F0_0 DVDEC0.YCTWA_F0
#define YCTWA_F1_0 DVDEC0.YCTWA_F1
#define YCTWA_F2_0 DVDEC0.YCTWA_F2
#define YCTWA_F3_0 DVDEC0.YCTWA_F3
#define YCTWA_F4_0 DVDEC0.YCTWA_F4
#define YCTWA_F5_0 DVDEC0.YCTWA_F5
#define YCTWA_F6_0 DVDEC0.YCTWA_F6
#define YCTWA_F7_0 DVDEC0.YCTWA_F7
#define YCTWA_F8_0 DVDEC0.YCTWA_F8
#define YCTWB_F0_0 DVDEC0.YCTWB_F0
#define YCTWB_F1_0 DVDEC0.YCTWB_F1
#define YCTWB_F2_0 DVDEC0.YCTWB_F2
#define YCTWB_F3_0 DVDEC0.YCTWB_F3
#define YCTWB_F4_0 DVDEC0.YCTWB_F4
#define YCTWB_F5_0 DVDEC0.YCTWB_F5
#define YCTWB_F6_0 DVDEC0.YCTWB_F6
#define YCTWB_F7_0 DVDEC0.YCTWB_F7
#define YCTWB_F8_0 DVDEC0.YCTWB_F8
#define YCTNA_F0_0 DVDEC0.YCTNA_F0
#define YCTNA_F1_0 DVDEC0.YCTNA_F1
#define YCTNA_F2_0 DVDEC0.YCTNA_F2
#define YCTNA_F3_0 DVDEC0.YCTNA_F3
#define YCTNA_F4_0 DVDEC0.YCTNA_F4
#define YCTNA_F5_0 DVDEC0.YCTNA_F5
#define YCTNA_F6_0 DVDEC0.YCTNA_F6
#define YCTNA_F7_0 DVDEC0.YCTNA_F7
#define YCTNA_F8_0 DVDEC0.YCTNA_F8
#define YCTNB_F0_0 DVDEC0.YCTNB_F0
#define YCTNB_F1_0 DVDEC0.YCTNB_F1
#define YCTNB_F2_0 DVDEC0.YCTNB_F2
#define YCTNB_F3_0 DVDEC0.YCTNB_F3
#define YCTNB_F4_0 DVDEC0.YCTNB_F4
#define YCTNB_F5_0 DVDEC0.YCTNB_F5
#define YCTNB_F6_0 DVDEC0.YCTNB_F6
#define YCTNB_F7_0 DVDEC0.YCTNB_F7
#define YCTNB_F8_0 DVDEC0.YCTNB_F8
#define YGAINCR_0 DVDEC0.YGAINCR
#define CBGAINCR_0 DVDEC0.CBGAINCR
#define CRGAINCR_0 DVDEC0.CRGAINCR
#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
#define PGACR_0 DVDEC0.PGACR
#define ADCCR2_0 DVDEC0.ADCCR2
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

424
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h
View File

@ -18,21 +18,192 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ether_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef ETHER_IODEFINE_H
#define ETHER_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_ether
{ /* ETHER */
#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */
/* Start of channel array defines of ETHER */
/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32)
#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
&ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
&ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
&ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
/* End of channel array defines of ETHER */
#define ETHEREDSR0 (ETHER.EDSR0)
#define ETHERTDLAR0 (ETHER.TDLAR0)
#define ETHERTDFAR0 (ETHER.TDFAR0)
#define ETHERTDFXR0 (ETHER.TDFXR0)
#define ETHERTDFFR0 (ETHER.TDFFR0)
#define ETHERRDLAR0 (ETHER.RDLAR0)
#define ETHERRDFAR0 (ETHER.RDFAR0)
#define ETHERRDFXR0 (ETHER.RDFXR0)
#define ETHERRDFFR0 (ETHER.RDFFR0)
#define ETHEREDMR0 (ETHER.EDMR0)
#define ETHEREDTRR0 (ETHER.EDTRR0)
#define ETHEREDRRR0 (ETHER.EDRRR0)
#define ETHEREESR0 (ETHER.EESR0)
#define ETHEREESIPR0 (ETHER.EESIPR0)
#define ETHERTRSCER0 (ETHER.TRSCER0)
#define ETHERRMFCR0 (ETHER.RMFCR0)
#define ETHERTFTR0 (ETHER.TFTR0)
#define ETHERFDR0 (ETHER.FDR0)
#define ETHERRMCR0 (ETHER.RMCR0)
#define ETHERRPADIR0 (ETHER.RPADIR0)
#define ETHERFCFTR0 (ETHER.FCFTR0)
#define ETHERCSMR (ETHER.CSMR)
#define ETHERCSSBM (ETHER.CSSBM)
#define ETHERCSSMR (ETHER.CSSMR)
#define ETHERECMR0 (ETHER.ECMR0)
#define ETHERRFLR0 (ETHER.RFLR0)
#define ETHERECSR0 (ETHER.ECSR0)
#define ETHERECSIPR0 (ETHER.ECSIPR0)
#define ETHERPIR0 (ETHER.PIR0)
#define ETHERAPR0 (ETHER.APR0)
#define ETHERMPR0 (ETHER.MPR0)
#define ETHERPFTCR0 (ETHER.PFTCR0)
#define ETHERPFRCR0 (ETHER.PFRCR0)
#define ETHERTPAUSER0 (ETHER.TPAUSER0)
#define ETHERMAHR0 (ETHER.MAHR0)
#define ETHERMALR0 (ETHER.MALR0)
#define ETHERCEFCR0 (ETHER.CEFCR0)
#define ETHERFRECR0 (ETHER.FRECR0)
#define ETHERTSFRCR0 (ETHER.TSFRCR0)
#define ETHERTLFRCR0 (ETHER.TLFRCR0)
#define ETHERRFCR0 (ETHER.RFCR0)
#define ETHERMAFCR0 (ETHER.MAFCR0)
#define ETHERARSTR (ETHER.ARSTR)
#define ETHERTSU_CTRST (ETHER.TSU_CTRST)
#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0)
#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY)
#define ETHERTSU_TEN (ETHER.TSU_TEN)
#define ETHERTXNLCR0 (ETHER.TXNLCR0)
#define ETHERTXALCR0 (ETHER.TXALCR0)
#define ETHERRXNLCR0 (ETHER.RXNLCR0)
#define ETHERRXALCR0 (ETHER.RXALCR0)
#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0)
#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0)
#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1)
#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1)
#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2)
#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2)
#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3)
#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3)
#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4)
#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4)
#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5)
#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5)
#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6)
#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6)
#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7)
#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7)
#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8)
#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8)
#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9)
#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9)
#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10)
#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10)
#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11)
#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11)
#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12)
#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12)
#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13)
#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13)
#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14)
#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14)
#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15)
#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15)
#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16)
#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16)
#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17)
#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17)
#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18)
#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18)
#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19)
#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19)
#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20)
#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20)
#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21)
#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21)
#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22)
#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22)
#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23)
#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23)
#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24)
#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24)
#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25)
#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25)
#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26)
#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26)
#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27)
#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27)
#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28)
#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28)
#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29)
#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29)
#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30)
#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30)
#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31)
#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31)
typedef struct st_ether
{
/* ETHER */
volatile uint32_t EDSR0; /* EDSR0 */
volatile uint8_t dummy207[12]; /* */
volatile uint32_t TDLAR0; /* TDLAR0 */
@ -118,310 +289,221 @@ struct st_ether
volatile uint32_t RXNLCR0; /* RXNLCR0 */
volatile uint32_t RXALCR0; /* RXALCR0 */
volatile uint8_t dummy240[112]; /* */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */
volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */
volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */
volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */
volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */
volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */
volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */
volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */
volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */
volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */
volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */
volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */
volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */
volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */
volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */
volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */
volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */
volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */
volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */
volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */
volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */
volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */
volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */
volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */
volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */
volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */
volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */
volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */
volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */
volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */
volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */
volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */
/* end of struct st_ether_from_tsu_adrh0 */
};
} r_io_ether_t;
struct st_ether_from_tsu_adrh0
typedef struct st_ether_from_tsu_adrh0
{
volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
};
} r_io_ether_from_tsu_adrh0_t;
#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */
/* Channel array defines of ETHER (2)*/
#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS
volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */
/* End of channel array defines of ETHER (2)*/
/* Start of channnel array defines of ETHER */
/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32
#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
&ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
&ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
&ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
/* End of channnel array defines of ETHER */
#define ETHEREDSR0 ETHER.EDSR0
#define ETHERTDLAR0 ETHER.TDLAR0
#define ETHERTDFAR0 ETHER.TDFAR0
#define ETHERTDFXR0 ETHER.TDFXR0
#define ETHERTDFFR0 ETHER.TDFFR0
#define ETHERRDLAR0 ETHER.RDLAR0
#define ETHERRDFAR0 ETHER.RDFAR0
#define ETHERRDFXR0 ETHER.RDFXR0
#define ETHERRDFFR0 ETHER.RDFFR0
#define ETHEREDMR0 ETHER.EDMR0
#define ETHEREDTRR0 ETHER.EDTRR0
#define ETHEREDRRR0 ETHER.EDRRR0
#define ETHEREESR0 ETHER.EESR0
#define ETHEREESIPR0 ETHER.EESIPR0
#define ETHERTRSCER0 ETHER.TRSCER0
#define ETHERRMFCR0 ETHER.RMFCR0
#define ETHERTFTR0 ETHER.TFTR0
#define ETHERFDR0 ETHER.FDR0
#define ETHERRMCR0 ETHER.RMCR0
#define ETHERRPADIR0 ETHER.RPADIR0
#define ETHERFCFTR0 ETHER.FCFTR0
#define ETHERCSMR ETHER.CSMR
#define ETHERCSSBM ETHER.CSSBM
#define ETHERCSSMR ETHER.CSSMR
#define ETHERECMR0 ETHER.ECMR0
#define ETHERRFLR0 ETHER.RFLR0
#define ETHERECSR0 ETHER.ECSR0
#define ETHERECSIPR0 ETHER.ECSIPR0
#define ETHERPIR0 ETHER.PIR0
#define ETHERAPR0 ETHER.APR0
#define ETHERMPR0 ETHER.MPR0
#define ETHERPFTCR0 ETHER.PFTCR0
#define ETHERPFRCR0 ETHER.PFRCR0
#define ETHERTPAUSER0 ETHER.TPAUSER0
#define ETHERMAHR0 ETHER.MAHR0
#define ETHERMALR0 ETHER.MALR0
#define ETHERCEFCR0 ETHER.CEFCR0
#define ETHERFRECR0 ETHER.FRECR0
#define ETHERTSFRCR0 ETHER.TSFRCR0
#define ETHERTLFRCR0 ETHER.TLFRCR0
#define ETHERRFCR0 ETHER.RFCR0
#define ETHERMAFCR0 ETHER.MAFCR0
#define ETHERARSTR ETHER.ARSTR
#define ETHERTSU_CTRST ETHER.TSU_CTRST
#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
#define ETHERTSU_TEN ETHER.TSU_TEN
#define ETHERTXNLCR0 ETHER.TXNLCR0
#define ETHERTXALCR0 ETHER.TXALCR0
#define ETHERRXNLCR0 ETHER.RXNLCR0
#define ETHERRXALCR0 ETHER.RXALCR0
#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

52
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h
View File

@ -18,20 +18,41 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : flctl_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef FLCTL_IODEFINE_H
#define FLCTL_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_flctl
{ /* FLCTL */
#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
#define FLCTLFLADR (FLCTL.FLADR)
#define FLCTLFLDATAR (FLCTL.FLDATAR)
#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
#define FLCTLFLTRCR (FLCTL.FLTRCR)
#define FLCTLFLADR2 (FLCTL.FLADR2)
#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
typedef struct st_flctl
{
/* FLCTL */
volatile uint32_t FLCMNCR; /* FLCMNCR */
volatile uint32_t FLCMDCR; /* FLCMDCR */
volatile uint32_t FLCMCDR; /* FLCMCDR */
@ -47,26 +68,11 @@ struct st_flctl
volatile uint32_t FLADR2; /* FLADR2 */
volatile uint8_t dummy557[16]; /* */
volatile uint32_t FLDTFIFO; /* FLDTFIFO */
volatile uint8_t dummy558[12]; /* */
volatile uint32_t FLECFIFO; /* FLECFIFO */
};
} r_io_flctl_t;
#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
#define FLCTLFLCMNCR FLCTL.FLCMNCR
#define FLCTLFLCMDCR FLCTL.FLCMDCR
#define FLCTLFLCMCDR FLCTL.FLCMCDR
#define FLCTLFLADR FLCTL.FLADR
#define FLCTLFLDATAR FLCTL.FLDATAR
#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
#define FLCTLFLTRCR FLCTL.FLTRCR
#define FLCTLFLADR2 FLCTL.FLADR2
#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
#define FLCTLFLECFIFO FLCTL.FLECFIFO
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

2011
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h
View File

File diff suppressed because it is too large Load Diff

77
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h
View File

@ -18,20 +18,55 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ieb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef IEB_IODEFINE_H
#define IEB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_ieb
{ /* IEB */
#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
#define IEBB0BCR (IEB.B0BCR)
#define IEBB0PSR (IEB.B0PSR)
#define IEBB0UAR (IEB.B0UAR)
#define IEBB0SAR (IEB.B0SAR)
#define IEBB0PAR (IEB.B0PAR)
#define IEBB0RSA (IEB.B0RSA)
#define IEBB0CDR (IEB.B0CDR)
#define IEBB0TCD (IEB.B0TCD)
#define IEBB0RCD (IEB.B0RCD)
#define IEBB0DLR (IEB.B0DLR)
#define IEBB0TDL (IEB.B0TDL)
#define IEBB0RDL (IEB.B0RDL)
#define IEBB0CKS (IEB.B0CKS)
#define IEBB0TMS (IEB.B0TMS)
#define IEBB0PCR (IEB.B0PCR)
#define IEBB0BSR (IEB.B0BSR)
#define IEBB0SSR (IEB.B0SSR)
#define IEBB0USR (IEB.B0USR)
#define IEBB0ISR (IEB.B0ISR)
#define IEBB0ESR (IEB.B0ESR)
#define IEBB0FSR (IEB.B0FSR)
#define IEBB0SCR (IEB.B0SCR)
#define IEBB0CCR (IEB.B0CCR)
#define IEBB0STC0 (IEB.B0STC0)
#define IEBB0STC1 (IEB.B0STC1)
#define IEBB0DR (IEB.B0DR)
typedef struct st_ieb
{
/* IEB */
volatile uint8_t B0BCR; /* B0BCR */
volatile uint8_t dummy495[3]; /* */
volatile uint8_t B0PSR; /* B0PSR */
@ -83,37 +118,11 @@ struct st_ieb
volatile uint8_t B0STC1; /* B0STC1 */
volatile uint8_t dummy519[3]; /* */
volatile uint8_t B0DR; /* B0DR */
};
} r_io_ieb_t;
#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
#define IEBB0BCR IEB.B0BCR
#define IEBB0PSR IEB.B0PSR
#define IEBB0UAR IEB.B0UAR
#define IEBB0SAR IEB.B0SAR
#define IEBB0PAR IEB.B0PAR
#define IEBB0RSA IEB.B0RSA
#define IEBB0CDR IEB.B0CDR
#define IEBB0TCD IEB.B0TCD
#define IEBB0RCD IEB.B0RCD
#define IEBB0DLR IEB.B0DLR
#define IEBB0TDL IEB.B0TDL
#define IEBB0RDL IEB.B0RDL
#define IEBB0CKS IEB.B0CKS
#define IEBB0TMS IEB.B0TMS
#define IEBB0PCR IEB.B0PCR
#define IEBB0BSR IEB.B0BSR
#define IEBB0SSR IEB.B0SSR
#define IEBB0USR IEB.B0USR
#define IEBB0ISR IEB.B0ISR
#define IEBB0ESR IEB.B0ESR
#define IEBB0FSR IEB.B0FSR
#define IEBB0SCR IEB.B0SCR
#define IEBB0CCR IEB.B0CCR
#define IEBB0STC0 IEB.B0STC0
#define IEBB0STC1 IEB.B0STC1
#define IEBB0DR IEB.B0DR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

92
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h
View File

@ -18,21 +18,61 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : inb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef INB_IODEFINE_H
#define INB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_inb
{ /* INB */
#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
#define INBRMPR (INB.RMPR)
#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
#define INBAXIRERRST0 (INB.AXIRERRST0)
#define INBAXIRERRST1 (INB.AXIRERRST1)
#define INBAXIRERRST2 (INB.AXIRERRST2)
#define INBAXIRERRST3 (INB.AXIRERRST3)
#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
#define INB_AXIBUSCTLn_COUNT (11)
#define INB_AXIRERRCTLn_COUNT (4)
#define INB_AXIRERRSTn_COUNT (4)
#define INB_AXIRERRCLRn_COUNT (4)
typedef struct st_inb
{
/* INB */
volatile uint32_t RMPR; /* RMPR */
#define INB_AXIBUSCTLn_COUNT 11
/* #define INB_AXIBUSCTLn_COUNT (11) */
volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
@ -44,49 +84,29 @@ struct st_inb
volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
#define INB_AXIRERRCTLn_COUNT 4
/* #define INB_AXIRERRCTLn_COUNT (4) */
volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
#define INB_AXIRERRSTn_COUNT 4
/* #define INB_AXIRERRSTn_COUNT (4) */
volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
#define INB_AXIRERRCLRn_COUNT 4
/* #define INB_AXIRERRCLRn_COUNT (4) */
volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
};
} r_io_inb_t;
#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
#define INBRMPR INB.RMPR
#define INBAXIBUSCTL0 INB.AXIBUSCTL0
#define INBAXIBUSCTL1 INB.AXIBUSCTL1
#define INBAXIBUSCTL2 INB.AXIBUSCTL2
#define INBAXIBUSCTL3 INB.AXIBUSCTL3
#define INBAXIBUSCTL4 INB.AXIBUSCTL4
#define INBAXIBUSCTL5 INB.AXIBUSCTL5
#define INBAXIBUSCTL6 INB.AXIBUSCTL6
#define INBAXIBUSCTL7 INB.AXIBUSCTL7
#define INBAXIBUSCTL8 INB.AXIBUSCTL8
#define INBAXIBUSCTL9 INB.AXIBUSCTL9
#define INBAXIBUSCTL10 INB.AXIBUSCTL10
#define INBAXIRERRCTL0 INB.AXIRERRCTL0
#define INBAXIRERRCTL1 INB.AXIRERRCTL1
#define INBAXIRERRCTL2 INB.AXIRERRCTL2
#define INBAXIRERRCTL3 INB.AXIRERRCTL3
#define INBAXIRERRST0 INB.AXIRERRST0
#define INBAXIRERRST1 INB.AXIRERRST1
#define INBAXIRERRST2 INB.AXIRERRST2
#define INBAXIRERRST3 INB.AXIRERRST3
#define INBAXIRERRCLR0 INB.AXIRERRCLR0
#define INBAXIRERRCLR1 INB.AXIRERRCLR1
#define INBAXIRERRCLR2 INB.AXIRERRCLR2
#define INBAXIRERRCLR3 INB.AXIRERRCLR3
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

1022
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h
View File

File diff suppressed because it is too large Load Diff

118
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h Normal file
View File

@ -0,0 +1,118 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : iodefine_typedef.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef IODEFINE_TYPEDEF_H
#define IODEFINE_TYPEDEF_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
/* Shared types and macros for iodefine.h */
/***********************************************************************
* Macro: IODEFINE_H_VERSION
************************************************************************/
#define IODEFINE_H_VERSION (200)
/***********************************************************************
* Enum: iodefine_byte_select_t
*
* R_IO_L - Low 16bit or Low 8 bit
* R_IO_H - High 16bit or Low 8 bit
* R_IO_LL - Low 8 bit
* R_IO_LH - Middle Low 8 bit
* R_IO_HL - Middle High 8 bit
* R_IO_HH - High 8 bit
************************************************************************/
typedef enum iodefine_byte_select_t
{
R_IO_L = 0, R_IO_H = 1,
R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3,
L = 0, H = 1,
LL= 0, LH = 1, HL = 2, HH = 3
} iodefine_byte_select_t;
/***********************************************************************
* Type: iodefine_reg32_t
* 32/16/8 bit access register
*
* - Padding : sizeof(iodefine_reg32_t) == 4
* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
* - Endian : Independent (Same as CPU endian as register endian)
* - Bit-Order : Independent
************************************************************************/
typedef union iodefine_reg32_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
volatile uint8_t UINT8[4]; /* 8-bit Access */
} iodefine_reg32_t;
/***********************************************************************
* Type: iodefine_reg32_16_t
* 32/16 bit access register
*
* - Padding : sizeof(iodefine_reg32_16_t) == 4
* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
* - Endian : Independent (Same as CPU endian as register endian)
* - Bit-Order : Independent
************************************************************************/
typedef union iodefine_reg32_16_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
} iodefine_reg32_16_t;
/***********************************************************************
* Type: iodefine_reg16_8_t
* 16/8 bit access register
*
* - Padding : sizeof(iodefine_reg16_8_t) == 2
* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
* - Endian : Independent (Same as CPU endian as register endian)
* - Bit-Order : Independent
************************************************************************/
typedef union iodefine_reg16_8_t
{
volatile uint16_t UINT16; /* 16-bit Access */
volatile uint8_t UINT8[2]; /* 8-bit Access */
} iodefine_reg16_8_t;
/* End of shared types and macros for iodefine.h */
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

29
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h
View File

@ -18,25 +18,36 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : irda_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef IRDA_IODEFINE_H
#define IRDA_IODEFINE_H
struct st_irda
{ /* IRDA */
volatile uint8_t IRCR; /* IRCR */
};
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */
#define IRDAIRCR IRDA.IRCR
#define IRDAIRCR (IRDA.IRCR)
typedef struct st_irda
{
/* IRDA */
volatile uint8_t IRCR; /* IRCR */
} r_io_irda_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

162
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h
View File

@ -18,20 +18,88 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : jcu_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef JCU_IODEFINE_H
#define JCU_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_jcu
{ /* JCU */
#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
/* Start of channel array defines of JCU */
/* Channel array defines of JCU_JCQTBL0 */
/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
#define JCU_JCQTBL0_COUNT (4)
#define JCU_JCQTBL0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
/* End of channel array defines of JCU */
#define JCUJCMOD (JCU.JCMOD)
#define JCUJCCMD (JCU.JCCMD)
#define JCUJCQTN (JCU.JCQTN)
#define JCUJCHTN (JCU.JCHTN)
#define JCUJCDRIU (JCU.JCDRIU)
#define JCUJCDRID (JCU.JCDRID)
#define JCUJCVSZU (JCU.JCVSZU)
#define JCUJCVSZD (JCU.JCVSZD)
#define JCUJCHSZU (JCU.JCHSZU)
#define JCUJCHSZD (JCU.JCHSZD)
#define JCUJCDTCU (JCU.JCDTCU)
#define JCUJCDTCM (JCU.JCDTCM)
#define JCUJCDTCD (JCU.JCDTCD)
#define JCUJINTE0 (JCU.JINTE0)
#define JCUJINTS0 (JCU.JINTS0)
#define JCUJCDERR (JCU.JCDERR)
#define JCUJCRST (JCU.JCRST)
#define JCUJIFECNT (JCU.JIFECNT)
#define JCUJIFESA (JCU.JIFESA)
#define JCUJIFESOFST (JCU.JIFESOFST)
#define JCUJIFEDA (JCU.JIFEDA)
#define JCUJIFESLC (JCU.JIFESLC)
#define JCUJIFEDDC (JCU.JIFEDDC)
#define JCUJIFDCNT (JCU.JIFDCNT)
#define JCUJIFDSA (JCU.JIFDSA)
#define JCUJIFDDOFST (JCU.JIFDDOFST)
#define JCUJIFDDA (JCU.JIFDDA)
#define JCUJIFDSDC (JCU.JIFDSDC)
#define JCUJIFDDLC (JCU.JIFDDLC)
#define JCUJIFDADT (JCU.JIFDADT)
#define JCUJINTE1 (JCU.JINTE1)
#define JCUJINTS1 (JCU.JINTS1)
#define JCUJIFESVSZ (JCU.JIFESVSZ)
#define JCUJIFESHSZ (JCU.JIFESHSZ)
#define JCUJCQTBL0 (JCU.JCQTBL0)
#define JCUJCQTBL1 (JCU.JCQTBL1)
#define JCUJCQTBL2 (JCU.JCQTBL2)
#define JCUJCQTBL3 (JCU.JCQTBL3)
#define JCUJCHTBD0 (JCU.JCHTBD0)
#define JCUJCHTBA0 (JCU.JCHTBA0)
#define JCUJCHTBD1 (JCU.JCHTBD1)
#define JCUJCHTBA1 (JCU.JCHTBA1)
typedef struct st_jcu
{
/* JCU */
volatile uint8_t JCMOD; /* JCMOD */
volatile uint8_t JCCMD; /* JCCMD */
volatile uint8_t dummy145[1]; /* */
@ -70,21 +138,29 @@ struct st_jcu
volatile uint32_t JIFESVSZ; /* JIFESVSZ */
volatile uint32_t JIFESHSZ; /* JIFESHSZ */
volatile uint8_t dummy148[100]; /* */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL0; /* JCQTBL0 */
volatile uint8_t dummy149[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL1; /* JCQTBL1 */
volatile uint8_t dummy150[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL2; /* JCQTBL2 */
volatile uint8_t dummy151[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL3; /* JCQTBL3 */
volatile uint8_t dummy152[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCHTBD0; /* JCHTBD0 */
volatile uint8_t dummy153[31]; /* */
@ -93,77 +169,29 @@ struct st_jcu
volatile uint8_t JCHTBD1; /* JCHTBD1 */
volatile uint8_t dummy155[31]; /* */
volatile uint8_t JCHTBA1; /* JCHTBA1 */
};
} r_io_jcu_t;
struct st_jcu_from_jcqtbl0
typedef struct st_jcu_from_jcqtbl0
{
volatile uint8_t JCQTBL0; /* JCQTBL0 */
volatile uint8_t dummy1[63]; /* */
};
} r_io_jcu_from_jcqtbl0_t;
#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
/* Channel array defines of JCU (2)*/
#ifdef DECLARE_JCU_JCQTBL0_CHANNELS
volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
JCU_JCQTBL0_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */
/* End of channel array defines of JCU (2)*/
/* Start of channnel array defines of JCU */
/* Channnel array defines of JCU_JCQTBL0 */
/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
#define JCU_JCQTBL0_COUNT 4
#define JCU_JCQTBL0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
/* End of channnel array defines of JCU */
#define JCUJCMOD JCU.JCMOD
#define JCUJCCMD JCU.JCCMD
#define JCUJCQTN JCU.JCQTN
#define JCUJCHTN JCU.JCHTN
#define JCUJCDRIU JCU.JCDRIU
#define JCUJCDRID JCU.JCDRID
#define JCUJCVSZU JCU.JCVSZU
#define JCUJCVSZD JCU.JCVSZD
#define JCUJCHSZU JCU.JCHSZU
#define JCUJCHSZD JCU.JCHSZD
#define JCUJCDTCU JCU.JCDTCU
#define JCUJCDTCM JCU.JCDTCM
#define JCUJCDTCD JCU.JCDTCD
#define JCUJINTE0 JCU.JINTE0
#define JCUJINTS0 JCU.JINTS0
#define JCUJCDERR JCU.JCDERR
#define JCUJCRST JCU.JCRST
#define JCUJIFECNT JCU.JIFECNT
#define JCUJIFESA JCU.JIFESA
#define JCUJIFESOFST JCU.JIFESOFST
#define JCUJIFEDA JCU.JIFEDA
#define JCUJIFESLC JCU.JIFESLC
#define JCUJIFEDDC JCU.JIFEDDC
#define JCUJIFDCNT JCU.JIFDCNT
#define JCUJIFDSA JCU.JIFDSA
#define JCUJIFDDOFST JCU.JIFDDOFST
#define JCUJIFDDA JCU.JIFDDA
#define JCUJIFDSDC JCU.JIFDSDC
#define JCUJIFDDLC JCU.JIFDDLC
#define JCUJIFDADT JCU.JIFDADT
#define JCUJINTE1 JCU.JINTE1
#define JCUJINTS1 JCU.JINTS1
#define JCUJIFESVSZ JCU.JIFESVSZ
#define JCUJIFESHSZ JCU.JIFESHSZ
#define JCUJCQTBL0 JCU.JCQTBL0
#define JCUJCQTBL1 JCU.JCQTBL1
#define JCUJCQTBL2 JCU.JCQTBL2
#define JCUJCQTBL3 JCU.JCQTBL3
#define JCUJCHTBD0 JCU.JCHTBD0
#define JCUJCHTBA0 JCU.JCHTBA0
#define JCUJCHTBD1 JCU.JCHTBD1
#define JCUJCHTBA1 JCU.JCHTBA1
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

188
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h
View File

@ -18,20 +18,97 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : l2c_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef L2C_IODEFINE_H
#define L2C_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_l2c
{ /* L2C */
#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
/* Start of channel array defines of L2C */
/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8)
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
/* End of channel array defines of L2C */
#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
typedef struct st_l2c
{
/* L2C */
volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
volatile uint8_t dummy8[248]; /* */
@ -66,37 +143,53 @@ struct st_l2c
volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
volatile uint8_t dummy17[256]; /* */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint8_t dummy18[16]; /* */
volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
@ -110,86 +203,29 @@ struct st_l2c
volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
volatile uint8_t dummy22[28]; /* */
volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
};
} r_io_l2c_t;
struct st_l2c_from_reg9_d_lockdown0
typedef struct st_l2c_from_reg9_d_lockdown0
{
volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
};
} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
/* Channel array defines of L2C (2)*/
#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
/* End of channel array defines of L2C (2)*/
/* Start of channnel array defines of L2C */
/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
/* End of channnel array defines of L2C */
#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
#define L2CREG1_CONTROL L2C.REG1_CONTROL
#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
#define L2CREG7_INV_PA L2C.REG7_INV_PA
#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

205
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h
View File

@ -18,25 +18,101 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : lin_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef LIN_IODEFINE_H
#define LIN_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_lin
{ /* LIN */
#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */
#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */
/* Start of channel array defines of LIN */
/* Channel array defines of LIN */
/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
#define LIN_COUNT (2)
#define LIN_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&LIN0, &LIN1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of LIN */
#define LIN0RLN30LWBR (LIN0.RLN3nLWBR)
#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0)
#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1)
#define LIN0RLN30LSTC (LIN0.RLN3nLSTC)
#define LIN0RLN30LMD (LIN0.RLN3nLMD)
#define LIN0RLN30LBFC (LIN0.RLN3nLBFC)
#define LIN0RLN30LSC (LIN0.RLN3nLSC)
#define LIN0RLN30LWUP (LIN0.RLN3nLWUP)
#define LIN0RLN30LIE (LIN0.RLN3nLIE)
#define LIN0RLN30LEDE (LIN0.RLN3nLEDE)
#define LIN0RLN30LCUC (LIN0.RLN3nLCUC)
#define LIN0RLN30LTRC (LIN0.RLN3nLTRC)
#define LIN0RLN30LMST (LIN0.RLN3nLMST)
#define LIN0RLN30LST (LIN0.RLN3nLST)
#define LIN0RLN30LEST (LIN0.RLN3nLEST)
#define LIN0RLN30LDFC (LIN0.RLN3nLDFC)
#define LIN0RLN30LIDB (LIN0.RLN3nLIDB)
#define LIN0RLN30LCBR (LIN0.RLN3nLCBR)
#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1)
#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2)
#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3)
#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4)
#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5)
#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6)
#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7)
#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8)
#define LIN1RLN31LWBR (LIN1.RLN3nLWBR)
#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0)
#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1)
#define LIN1RLN31LSTC (LIN1.RLN3nLSTC)
#define LIN1RLN31LMD (LIN1.RLN3nLMD)
#define LIN1RLN31LBFC (LIN1.RLN3nLBFC)
#define LIN1RLN31LSC (LIN1.RLN3nLSC)
#define LIN1RLN31LWUP (LIN1.RLN3nLWUP)
#define LIN1RLN31LIE (LIN1.RLN3nLIE)
#define LIN1RLN31LEDE (LIN1.RLN3nLEDE)
#define LIN1RLN31LCUC (LIN1.RLN3nLCUC)
#define LIN1RLN31LTRC (LIN1.RLN3nLTRC)
#define LIN1RLN31LMST (LIN1.RLN3nLMST)
#define LIN1RLN31LST (LIN1.RLN3nLST)
#define LIN1RLN31LEST (LIN1.RLN3nLEST)
#define LIN1RLN31LDFC (LIN1.RLN3nLDFC)
#define LIN1RLN31LIDB (LIN1.RLN3nLIDB)
#define LIN1RLN31LCBR (LIN1.RLN3nLCBR)
#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1)
#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2)
#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3)
#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4)
#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5)
#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6)
#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7)
#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8)
#define LIN_LDBn_COUNT (8)
typedef struct st_lin
{
/* LIN */
volatile uint8_t dummy1[1]; /* */
volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */
union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */
volatile uint8_t RLN3nLBRP0; /* RLN3nLBRP0 */
volatile uint8_t RLN3nLBRP1; /* RLN3nLBRP1 */
volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */
volatile uint8_t dummy2[3]; /* */
volatile uint8_t RLN3nLMD; /* RLN3nLMD */
@ -54,8 +130,9 @@ struct st_lin
volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */
volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */
volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */
volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */
#define LIN_LDBn_COUNT 8
volatile uint8_t dummy4[1]; /* */
/* #define LIN_LDBn_COUNT (8) */
volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */
volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */
volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */
@ -64,111 +141,21 @@ struct st_lin
volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */
volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */
volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */
volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */
volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */
volatile uint8_t dummy4[2]; /* */
union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */
union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */
union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */
};
} r_io_lin_t;
#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */
#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */
/* Channel array defines of LIN (2)*/
#ifdef DECLARE_LIN_CHANNELS
volatile struct st_lin* LIN[ LIN_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
LIN_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_LIN_CHANNELS */
/* End of channel array defines of LIN (2)*/
/* Start of channnel array defines of LIN */
/* Channnel array defines of LIN */
/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
#define LIN_COUNT 2
#define LIN_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&LIN0, &LIN1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of LIN */
#define LIN0RLN30LWBR LIN0.RLN3nLWBR
#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
#define LIN0RLN30LSTC LIN0.RLN3nLSTC
#define LIN0RLN30LMD LIN0.RLN3nLMD
#define LIN0RLN30LBFC LIN0.RLN3nLBFC
#define LIN0RLN30LSC LIN0.RLN3nLSC
#define LIN0RLN30LWUP LIN0.RLN3nLWUP
#define LIN0RLN30LIE LIN0.RLN3nLIE
#define LIN0RLN30LEDE LIN0.RLN3nLEDE
#define LIN0RLN30LCUC LIN0.RLN3nLCUC
#define LIN0RLN30LTRC LIN0.RLN3nLTRC
#define LIN0RLN30LMST LIN0.RLN3nLMST
#define LIN0RLN30LST LIN0.RLN3nLST
#define LIN0RLN30LEST LIN0.RLN3nLEST
#define LIN0RLN30LDFC LIN0.RLN3nLDFC
#define LIN0RLN30LIDB LIN0.RLN3nLIDB
#define LIN0RLN30LCBR LIN0.RLN3nLCBR
#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
#define LIN0RLN30LUOER LIN0.RLN3nLUOER
#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
#define LIN1RLN31LWBR LIN1.RLN3nLWBR
#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
#define LIN1RLN31LSTC LIN1.RLN3nLSTC
#define LIN1RLN31LMD LIN1.RLN3nLMD
#define LIN1RLN31LBFC LIN1.RLN3nLBFC
#define LIN1RLN31LSC LIN1.RLN3nLSC
#define LIN1RLN31LWUP LIN1.RLN3nLWUP
#define LIN1RLN31LIE LIN1.RLN3nLIE
#define LIN1RLN31LEDE LIN1.RLN3nLEDE
#define LIN1RLN31LCUC LIN1.RLN3nLCUC
#define LIN1RLN31LTRC LIN1.RLN3nLTRC
#define LIN1RLN31LMST LIN1.RLN3nLMST
#define LIN1RLN31LST LIN1.RLN3nLST
#define LIN1RLN31LEST LIN1.RLN3nLEST
#define LIN1RLN31LDFC LIN1.RLN3nLDFC
#define LIN1RLN31LIDB LIN1.RLN3nLIDB
#define LIN1RLN31LCBR LIN1.RLN3nLCBR
#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
#define LIN1RLN31LUOER LIN1.RLN3nLUOER
#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

35
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h
View File

@ -18,20 +18,34 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : lvds_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.01a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef LVDS_IODEFINE_H
#define LVDS_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_lvds
{ /* LVDS */
#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */
#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE)
#define LVDSLVDSFCL (LVDS.LVDSFCL)
#define LVDSLCLKSELR (LVDS.LCLKSELR)
#define LVDSLPLLSETR (LVDS.LPLLSETR)
#define LVDSLPHYACC (LVDS.LPHYACC)
typedef struct st_lvds
{
/* LVDS */
volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */
volatile uint32_t LVDSFCL; /* LVDSFCL */
volatile uint8_t dummy608[24]; /* */
@ -39,16 +53,11 @@ struct st_lvds
volatile uint32_t LPLLSETR; /* LPLLSETR */
volatile uint8_t dummy609[4]; /* */
volatile uint32_t LPHYACC; /* LPHYACC */
};
} r_io_lvds_t;
#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */
#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
#define LVDSLVDSFCL LVDS.LVDSFCL
#define LVDSLCLKSELR LVDS.LCLKSELR
#define LVDSLPLLSETR LVDS.LPLLSETR
#define LVDSLPHYACC LVDS.LPHYACC
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

913
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h
View File

@ -18,273 +18,29 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mlb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef MLB_IODEFINE_H
#define MLB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_mlb
{ /* MLB */
volatile uint32_t DCCR; /* DCCR */
volatile uint32_t SSCR; /* SSCR */
volatile uint32_t SDCR; /* SDCR */
volatile uint32_t SMCR; /* SMCR */
volatile uint8_t dummy156[12]; /* */
volatile uint32_t VCCR; /* VCCR */
volatile uint32_t SBCR; /* SBCR */
volatile uint32_t ABCR; /* ABCR */
volatile uint32_t CBCR; /* CBCR */
volatile uint32_t IBCR; /* IBCR */
volatile uint32_t CICR; /* CICR */
volatile uint8_t dummy157[12]; /* */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR1; /* CECR1 */
volatile uint32_t CSCR1; /* CSCR1 */
volatile uint32_t CCBCR1; /* CCBCR1 */
volatile uint32_t CNBCR1; /* CNBCR1 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR2; /* CECR2 */
volatile uint32_t CSCR2; /* CSCR2 */
volatile uint32_t CCBCR2; /* CCBCR2 */
volatile uint32_t CNBCR2; /* CNBCR2 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR3; /* CECR3 */
volatile uint32_t CSCR3; /* CSCR3 */
volatile uint32_t CCBCR3; /* CCBCR3 */
volatile uint32_t CNBCR3; /* CNBCR3 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR4; /* CECR4 */
volatile uint32_t CSCR4; /* CSCR4 */
volatile uint32_t CCBCR4; /* CCBCR4 */
volatile uint32_t CNBCR4; /* CNBCR4 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR5; /* CECR5 */
volatile uint32_t CSCR5; /* CSCR5 */
volatile uint32_t CCBCR5; /* CCBCR5 */
volatile uint32_t CNBCR5; /* CNBCR5 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR6; /* CECR6 */
volatile uint32_t CSCR6; /* CSCR6 */
volatile uint32_t CCBCR6; /* CCBCR6 */
volatile uint32_t CNBCR6; /* CNBCR6 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR7; /* CECR7 */
volatile uint32_t CSCR7; /* CSCR7 */
volatile uint32_t CCBCR7; /* CCBCR7 */
volatile uint32_t CNBCR7; /* CNBCR7 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR8; /* CECR8 */
volatile uint32_t CSCR8; /* CSCR8 */
volatile uint32_t CCBCR8; /* CCBCR8 */
volatile uint32_t CNBCR8; /* CNBCR8 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR9; /* CECR9 */
volatile uint32_t CSCR9; /* CSCR9 */
volatile uint32_t CCBCR9; /* CCBCR9 */
volatile uint32_t CNBCR9; /* CNBCR9 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR10; /* CECR10 */
volatile uint32_t CSCR10; /* CSCR10 */
volatile uint32_t CCBCR10; /* CCBCR10 */
volatile uint32_t CNBCR10; /* CNBCR10 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR11; /* CECR11 */
volatile uint32_t CSCR11; /* CSCR11 */
volatile uint32_t CCBCR11; /* CCBCR11 */
volatile uint32_t CNBCR11; /* CNBCR11 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR12; /* CECR12 */
volatile uint32_t CSCR12; /* CSCR12 */
volatile uint32_t CCBCR12; /* CCBCR12 */
volatile uint32_t CNBCR12; /* CNBCR12 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR13; /* CECR13 */
volatile uint32_t CSCR13; /* CSCR13 */
volatile uint32_t CCBCR13; /* CCBCR13 */
volatile uint32_t CNBCR13; /* CNBCR13 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR14; /* CECR14 */
volatile uint32_t CSCR14; /* CSCR14 */
volatile uint32_t CCBCR14; /* CCBCR14 */
volatile uint32_t CNBCR14; /* CNBCR14 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR15; /* CECR15 */
volatile uint32_t CSCR15; /* CSCR15 */
volatile uint32_t CCBCR15; /* CCBCR15 */
volatile uint32_t CNBCR15; /* CNBCR15 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR16; /* CECR16 */
volatile uint32_t CSCR16; /* CSCR16 */
volatile uint32_t CCBCR16; /* CCBCR16 */
volatile uint32_t CNBCR16; /* CNBCR16 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR17; /* CECR17 */
volatile uint32_t CSCR17; /* CSCR17 */
volatile uint32_t CCBCR17; /* CCBCR17 */
volatile uint32_t CNBCR17; /* CNBCR17 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR18; /* CECR18 */
volatile uint32_t CSCR18; /* CSCR18 */
volatile uint32_t CCBCR18; /* CCBCR18 */
volatile uint32_t CNBCR18; /* CNBCR18 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR19; /* CECR19 */
volatile uint32_t CSCR19; /* CSCR19 */
volatile uint32_t CCBCR19; /* CCBCR19 */
volatile uint32_t CNBCR19; /* CNBCR19 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR20; /* CECR20 */
volatile uint32_t CSCR20; /* CSCR20 */
volatile uint32_t CCBCR20; /* CCBCR20 */
volatile uint32_t CNBCR20; /* CNBCR20 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR21; /* CECR21 */
volatile uint32_t CSCR21; /* CSCR21 */
volatile uint32_t CCBCR21; /* CCBCR21 */
volatile uint32_t CNBCR21; /* CNBCR21 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR22; /* CECR22 */
volatile uint32_t CSCR22; /* CSCR22 */
volatile uint32_t CCBCR22; /* CCBCR22 */
volatile uint32_t CNBCR22; /* CNBCR22 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR23; /* CECR23 */
volatile uint32_t CSCR23; /* CSCR23 */
volatile uint32_t CCBCR23; /* CCBCR23 */
volatile uint32_t CNBCR23; /* CNBCR23 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR24; /* CECR24 */
volatile uint32_t CSCR24; /* CSCR24 */
volatile uint32_t CCBCR24; /* CCBCR24 */
volatile uint32_t CNBCR24; /* CNBCR24 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR25; /* CECR25 */
volatile uint32_t CSCR25; /* CSCR25 */
volatile uint32_t CCBCR25; /* CCBCR25 */
volatile uint32_t CNBCR25; /* CNBCR25 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR26; /* CECR26 */
volatile uint32_t CSCR26; /* CSCR26 */
volatile uint32_t CCBCR26; /* CCBCR26 */
volatile uint32_t CNBCR26; /* CNBCR26 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR27; /* CECR27 */
volatile uint32_t CSCR27; /* CSCR27 */
volatile uint32_t CCBCR27; /* CCBCR27 */
volatile uint32_t CNBCR27; /* CNBCR27 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR28; /* CECR28 */
volatile uint32_t CSCR28; /* CSCR28 */
volatile uint32_t CCBCR28; /* CCBCR28 */
volatile uint32_t CNBCR28; /* CNBCR28 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR29; /* CECR29 */
volatile uint32_t CSCR29; /* CSCR29 */
volatile uint32_t CCBCR29; /* CCBCR29 */
volatile uint32_t CNBCR29; /* CNBCR29 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR30; /* CECR30 */
volatile uint32_t CSCR30; /* CSCR30 */
volatile uint32_t CCBCR30; /* CCBCR30 */
volatile uint32_t CNBCR30; /* CNBCR30 */
/* end of struct st_mlb_from_cecr0 */
volatile uint8_t dummy158[80]; /* */
#define MLB_LCBCR0_COUNT 31
volatile uint32_t LCBCR0; /* LCBCR0 */
volatile uint32_t LCBCR1; /* LCBCR1 */
volatile uint32_t LCBCR2; /* LCBCR2 */
volatile uint32_t LCBCR3; /* LCBCR3 */
volatile uint32_t LCBCR4; /* LCBCR4 */
volatile uint32_t LCBCR5; /* LCBCR5 */
volatile uint32_t LCBCR6; /* LCBCR6 */
volatile uint32_t LCBCR7; /* LCBCR7 */
volatile uint32_t LCBCR8; /* LCBCR8 */
volatile uint32_t LCBCR9; /* LCBCR9 */
volatile uint32_t LCBCR10; /* LCBCR10 */
volatile uint32_t LCBCR11; /* LCBCR11 */
volatile uint32_t LCBCR12; /* LCBCR12 */
volatile uint32_t LCBCR13; /* LCBCR13 */
volatile uint32_t LCBCR14; /* LCBCR14 */
volatile uint32_t LCBCR15; /* LCBCR15 */
volatile uint32_t LCBCR16; /* LCBCR16 */
volatile uint32_t LCBCR17; /* LCBCR17 */
volatile uint32_t LCBCR18; /* LCBCR18 */
volatile uint32_t LCBCR19; /* LCBCR19 */
volatile uint32_t LCBCR20; /* LCBCR20 */
volatile uint32_t LCBCR21; /* LCBCR21 */
volatile uint32_t LCBCR22; /* LCBCR22 */
volatile uint32_t LCBCR23; /* LCBCR23 */
volatile uint32_t LCBCR24; /* LCBCR24 */
volatile uint32_t LCBCR25; /* LCBCR25 */
volatile uint32_t LCBCR26; /* LCBCR26 */
volatile uint32_t LCBCR27; /* LCBCR27 */
volatile uint32_t LCBCR28; /* LCBCR28 */
volatile uint32_t LCBCR29; /* LCBCR29 */
volatile uint32_t LCBCR30; /* LCBCR30 */
};
struct st_mlb_from_cecr0
{
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
};
#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */
/* Start of channnel array defines of MLB */
/* Start of channel array defines of MLB */
/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
/* Channel array defines of MLB_FROM_CECR0_ARRAY */
/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
#define MLB_FROM_CECR0_ARRAY_COUNT 31
#define MLB_FROM_CECR0_ARRAY_COUNT (31)
#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
@ -324,175 +80,500 @@ struct st_mlb_from_cecr0
#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
/* End of channnel array defines of MLB */
/* End of channel array defines of MLB */
#define MLBDCCR (MLB.DCCR)
#define MLBSSCR (MLB.SSCR)
#define MLBSDCR (MLB.SDCR)
#define MLBSMCR (MLB.SMCR)
#define MLBVCCR (MLB.VCCR)
#define MLBSBCR (MLB.SBCR)
#define MLBABCR (MLB.ABCR)
#define MLBCBCR (MLB.CBCR)
#define MLBIBCR (MLB.IBCR)
#define MLBCICR (MLB.CICR)
#define MLBCECR0 (MLB.CECR0)
#define MLBCSCR0 (MLB.CSCR0)
#define MLBCCBCR0 (MLB.CCBCR0)
#define MLBCNBCR0 (MLB.CNBCR0)
#define MLBCECR1 (MLB.CECR1)
#define MLBCSCR1 (MLB.CSCR1)
#define MLBCCBCR1 (MLB.CCBCR1)
#define MLBCNBCR1 (MLB.CNBCR1)
#define MLBCECR2 (MLB.CECR2)
#define MLBCSCR2 (MLB.CSCR2)
#define MLBCCBCR2 (MLB.CCBCR2)
#define MLBCNBCR2 (MLB.CNBCR2)
#define MLBCECR3 (MLB.CECR3)
#define MLBCSCR3 (MLB.CSCR3)
#define MLBCCBCR3 (MLB.CCBCR3)
#define MLBCNBCR3 (MLB.CNBCR3)
#define MLBCECR4 (MLB.CECR4)
#define MLBCSCR4 (MLB.CSCR4)
#define MLBCCBCR4 (MLB.CCBCR4)
#define MLBCNBCR4 (MLB.CNBCR4)
#define MLBCECR5 (MLB.CECR5)
#define MLBCSCR5 (MLB.CSCR5)
#define MLBCCBCR5 (MLB.CCBCR5)
#define MLBCNBCR5 (MLB.CNBCR5)
#define MLBCECR6 (MLB.CECR6)
#define MLBCSCR6 (MLB.CSCR6)
#define MLBCCBCR6 (MLB.CCBCR6)
#define MLBCNBCR6 (MLB.CNBCR6)
#define MLBCECR7 (MLB.CECR7)
#define MLBCSCR7 (MLB.CSCR7)
#define MLBCCBCR7 (MLB.CCBCR7)
#define MLBCNBCR7 (MLB.CNBCR7)
#define MLBCECR8 (MLB.CECR8)
#define MLBCSCR8 (MLB.CSCR8)
#define MLBCCBCR8 (MLB.CCBCR8)
#define MLBCNBCR8 (MLB.CNBCR8)
#define MLBCECR9 (MLB.CECR9)
#define MLBCSCR9 (MLB.CSCR9)
#define MLBCCBCR9 (MLB.CCBCR9)
#define MLBCNBCR9 (MLB.CNBCR9)
#define MLBCECR10 (MLB.CECR10)
#define MLBCSCR10 (MLB.CSCR10)
#define MLBCCBCR10 (MLB.CCBCR10)
#define MLBCNBCR10 (MLB.CNBCR10)
#define MLBCECR11 (MLB.CECR11)
#define MLBCSCR11 (MLB.CSCR11)
#define MLBCCBCR11 (MLB.CCBCR11)
#define MLBCNBCR11 (MLB.CNBCR11)
#define MLBCECR12 (MLB.CECR12)
#define MLBCSCR12 (MLB.CSCR12)
#define MLBCCBCR12 (MLB.CCBCR12)
#define MLBCNBCR12 (MLB.CNBCR12)
#define MLBCECR13 (MLB.CECR13)
#define MLBCSCR13 (MLB.CSCR13)
#define MLBCCBCR13 (MLB.CCBCR13)
#define MLBCNBCR13 (MLB.CNBCR13)
#define MLBCECR14 (MLB.CECR14)
#define MLBCSCR14 (MLB.CSCR14)
#define MLBCCBCR14 (MLB.CCBCR14)
#define MLBCNBCR14 (MLB.CNBCR14)
#define MLBCECR15 (MLB.CECR15)
#define MLBCSCR15 (MLB.CSCR15)
#define MLBCCBCR15 (MLB.CCBCR15)
#define MLBCNBCR15 (MLB.CNBCR15)
#define MLBCECR16 (MLB.CECR16)
#define MLBCSCR16 (MLB.CSCR16)
#define MLBCCBCR16 (MLB.CCBCR16)
#define MLBCNBCR16 (MLB.CNBCR16)
#define MLBCECR17 (MLB.CECR17)
#define MLBCSCR17 (MLB.CSCR17)
#define MLBCCBCR17 (MLB.CCBCR17)
#define MLBCNBCR17 (MLB.CNBCR17)
#define MLBCECR18 (MLB.CECR18)
#define MLBCSCR18 (MLB.CSCR18)
#define MLBCCBCR18 (MLB.CCBCR18)
#define MLBCNBCR18 (MLB.CNBCR18)
#define MLBCECR19 (MLB.CECR19)
#define MLBCSCR19 (MLB.CSCR19)
#define MLBCCBCR19 (MLB.CCBCR19)
#define MLBCNBCR19 (MLB.CNBCR19)
#define MLBCECR20 (MLB.CECR20)
#define MLBCSCR20 (MLB.CSCR20)
#define MLBCCBCR20 (MLB.CCBCR20)
#define MLBCNBCR20 (MLB.CNBCR20)
#define MLBCECR21 (MLB.CECR21)
#define MLBCSCR21 (MLB.CSCR21)
#define MLBCCBCR21 (MLB.CCBCR21)
#define MLBCNBCR21 (MLB.CNBCR21)
#define MLBCECR22 (MLB.CECR22)
#define MLBCSCR22 (MLB.CSCR22)
#define MLBCCBCR22 (MLB.CCBCR22)
#define MLBCNBCR22 (MLB.CNBCR22)
#define MLBCECR23 (MLB.CECR23)
#define MLBCSCR23 (MLB.CSCR23)
#define MLBCCBCR23 (MLB.CCBCR23)
#define MLBCNBCR23 (MLB.CNBCR23)
#define MLBCECR24 (MLB.CECR24)
#define MLBCSCR24 (MLB.CSCR24)
#define MLBCCBCR24 (MLB.CCBCR24)
#define MLBCNBCR24 (MLB.CNBCR24)
#define MLBCECR25 (MLB.CECR25)
#define MLBCSCR25 (MLB.CSCR25)
#define MLBCCBCR25 (MLB.CCBCR25)
#define MLBCNBCR25 (MLB.CNBCR25)
#define MLBCECR26 (MLB.CECR26)
#define MLBCSCR26 (MLB.CSCR26)
#define MLBCCBCR26 (MLB.CCBCR26)
#define MLBCNBCR26 (MLB.CNBCR26)
#define MLBCECR27 (MLB.CECR27)
#define MLBCSCR27 (MLB.CSCR27)
#define MLBCCBCR27 (MLB.CCBCR27)
#define MLBCNBCR27 (MLB.CNBCR27)
#define MLBCECR28 (MLB.CECR28)
#define MLBCSCR28 (MLB.CSCR28)
#define MLBCCBCR28 (MLB.CCBCR28)
#define MLBCNBCR28 (MLB.CNBCR28)
#define MLBCECR29 (MLB.CECR29)
#define MLBCSCR29 (MLB.CSCR29)
#define MLBCCBCR29 (MLB.CCBCR29)
#define MLBCNBCR29 (MLB.CNBCR29)
#define MLBCECR30 (MLB.CECR30)
#define MLBCSCR30 (MLB.CSCR30)
#define MLBCCBCR30 (MLB.CCBCR30)
#define MLBCNBCR30 (MLB.CNBCR30)
#define MLBLCBCR0 (MLB.LCBCR0)
#define MLBLCBCR1 (MLB.LCBCR1)
#define MLBLCBCR2 (MLB.LCBCR2)
#define MLBLCBCR3 (MLB.LCBCR3)
#define MLBLCBCR4 (MLB.LCBCR4)
#define MLBLCBCR5 (MLB.LCBCR5)
#define MLBLCBCR6 (MLB.LCBCR6)
#define MLBLCBCR7 (MLB.LCBCR7)
#define MLBLCBCR8 (MLB.LCBCR8)
#define MLBLCBCR9 (MLB.LCBCR9)
#define MLBLCBCR10 (MLB.LCBCR10)
#define MLBLCBCR11 (MLB.LCBCR11)
#define MLBLCBCR12 (MLB.LCBCR12)
#define MLBLCBCR13 (MLB.LCBCR13)
#define MLBLCBCR14 (MLB.LCBCR14)
#define MLBLCBCR15 (MLB.LCBCR15)
#define MLBLCBCR16 (MLB.LCBCR16)
#define MLBLCBCR17 (MLB.LCBCR17)
#define MLBLCBCR18 (MLB.LCBCR18)
#define MLBLCBCR19 (MLB.LCBCR19)
#define MLBLCBCR20 (MLB.LCBCR20)
#define MLBLCBCR21 (MLB.LCBCR21)
#define MLBLCBCR22 (MLB.LCBCR22)
#define MLBLCBCR23 (MLB.LCBCR23)
#define MLBLCBCR24 (MLB.LCBCR24)
#define MLBLCBCR25 (MLB.LCBCR25)
#define MLBLCBCR26 (MLB.LCBCR26)
#define MLBLCBCR27 (MLB.LCBCR27)
#define MLBLCBCR28 (MLB.LCBCR28)
#define MLBLCBCR29 (MLB.LCBCR29)
#define MLBLCBCR30 (MLB.LCBCR30)
#define MLB_LCBCR0_COUNT (31)
typedef struct st_mlb
{
/* MLB */
volatile uint32_t DCCR; /* DCCR */
volatile uint32_t SSCR; /* SSCR */
volatile uint32_t SDCR; /* SDCR */
volatile uint32_t SMCR; /* SMCR */
volatile uint8_t dummy156[12]; /* */
volatile uint32_t VCCR; /* VCCR */
volatile uint32_t SBCR; /* SBCR */
volatile uint32_t ABCR; /* ABCR */
volatile uint32_t CBCR; /* CBCR */
volatile uint32_t IBCR; /* IBCR */
volatile uint32_t CICR; /* CICR */
volatile uint8_t dummy157[12]; /* */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR1; /* CECR1 */
volatile uint32_t CSCR1; /* CSCR1 */
volatile uint32_t CCBCR1; /* CCBCR1 */
volatile uint32_t CNBCR1; /* CNBCR1 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR2; /* CECR2 */
volatile uint32_t CSCR2; /* CSCR2 */
volatile uint32_t CCBCR2; /* CCBCR2 */
volatile uint32_t CNBCR2; /* CNBCR2 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR3; /* CECR3 */
volatile uint32_t CSCR3; /* CSCR3 */
volatile uint32_t CCBCR3; /* CCBCR3 */
volatile uint32_t CNBCR3; /* CNBCR3 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR4; /* CECR4 */
volatile uint32_t CSCR4; /* CSCR4 */
volatile uint32_t CCBCR4; /* CCBCR4 */
volatile uint32_t CNBCR4; /* CNBCR4 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR5; /* CECR5 */
volatile uint32_t CSCR5; /* CSCR5 */
volatile uint32_t CCBCR5; /* CCBCR5 */
volatile uint32_t CNBCR5; /* CNBCR5 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR6; /* CECR6 */
volatile uint32_t CSCR6; /* CSCR6 */
volatile uint32_t CCBCR6; /* CCBCR6 */
volatile uint32_t CNBCR6; /* CNBCR6 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR7; /* CECR7 */
volatile uint32_t CSCR7; /* CSCR7 */
volatile uint32_t CCBCR7; /* CCBCR7 */
volatile uint32_t CNBCR7; /* CNBCR7 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR8; /* CECR8 */
volatile uint32_t CSCR8; /* CSCR8 */
volatile uint32_t CCBCR8; /* CCBCR8 */
volatile uint32_t CNBCR8; /* CNBCR8 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR9; /* CECR9 */
volatile uint32_t CSCR9; /* CSCR9 */
volatile uint32_t CCBCR9; /* CCBCR9 */
volatile uint32_t CNBCR9; /* CNBCR9 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR10; /* CECR10 */
volatile uint32_t CSCR10; /* CSCR10 */
volatile uint32_t CCBCR10; /* CCBCR10 */
volatile uint32_t CNBCR10; /* CNBCR10 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR11; /* CECR11 */
volatile uint32_t CSCR11; /* CSCR11 */
volatile uint32_t CCBCR11; /* CCBCR11 */
volatile uint32_t CNBCR11; /* CNBCR11 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR12; /* CECR12 */
volatile uint32_t CSCR12; /* CSCR12 */
volatile uint32_t CCBCR12; /* CCBCR12 */
volatile uint32_t CNBCR12; /* CNBCR12 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR13; /* CECR13 */
volatile uint32_t CSCR13; /* CSCR13 */
volatile uint32_t CCBCR13; /* CCBCR13 */
volatile uint32_t CNBCR13; /* CNBCR13 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR14; /* CECR14 */
volatile uint32_t CSCR14; /* CSCR14 */
volatile uint32_t CCBCR14; /* CCBCR14 */
volatile uint32_t CNBCR14; /* CNBCR14 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR15; /* CECR15 */
volatile uint32_t CSCR15; /* CSCR15 */
volatile uint32_t CCBCR15; /* CCBCR15 */
volatile uint32_t CNBCR15; /* CNBCR15 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR16; /* CECR16 */
volatile uint32_t CSCR16; /* CSCR16 */
volatile uint32_t CCBCR16; /* CCBCR16 */
volatile uint32_t CNBCR16; /* CNBCR16 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR17; /* CECR17 */
volatile uint32_t CSCR17; /* CSCR17 */
volatile uint32_t CCBCR17; /* CCBCR17 */
volatile uint32_t CNBCR17; /* CNBCR17 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR18; /* CECR18 */
volatile uint32_t CSCR18; /* CSCR18 */
volatile uint32_t CCBCR18; /* CCBCR18 */
volatile uint32_t CNBCR18; /* CNBCR18 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR19; /* CECR19 */
volatile uint32_t CSCR19; /* CSCR19 */
volatile uint32_t CCBCR19; /* CCBCR19 */
volatile uint32_t CNBCR19; /* CNBCR19 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR20; /* CECR20 */
volatile uint32_t CSCR20; /* CSCR20 */
volatile uint32_t CCBCR20; /* CCBCR20 */
volatile uint32_t CNBCR20; /* CNBCR20 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR21; /* CECR21 */
volatile uint32_t CSCR21; /* CSCR21 */
volatile uint32_t CCBCR21; /* CCBCR21 */
volatile uint32_t CNBCR21; /* CNBCR21 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR22; /* CECR22 */
volatile uint32_t CSCR22; /* CSCR22 */
volatile uint32_t CCBCR22; /* CCBCR22 */
volatile uint32_t CNBCR22; /* CNBCR22 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR23; /* CECR23 */
volatile uint32_t CSCR23; /* CSCR23 */
volatile uint32_t CCBCR23; /* CCBCR23 */
volatile uint32_t CNBCR23; /* CNBCR23 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR24; /* CECR24 */
volatile uint32_t CSCR24; /* CSCR24 */
volatile uint32_t CCBCR24; /* CCBCR24 */
volatile uint32_t CNBCR24; /* CNBCR24 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR25; /* CECR25 */
volatile uint32_t CSCR25; /* CSCR25 */
volatile uint32_t CCBCR25; /* CCBCR25 */
volatile uint32_t CNBCR25; /* CNBCR25 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR26; /* CECR26 */
volatile uint32_t CSCR26; /* CSCR26 */
volatile uint32_t CCBCR26; /* CCBCR26 */
volatile uint32_t CNBCR26; /* CNBCR26 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR27; /* CECR27 */
volatile uint32_t CSCR27; /* CSCR27 */
volatile uint32_t CCBCR27; /* CCBCR27 */
volatile uint32_t CNBCR27; /* CNBCR27 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR28; /* CECR28 */
volatile uint32_t CSCR28; /* CSCR28 */
volatile uint32_t CCBCR28; /* CCBCR28 */
volatile uint32_t CNBCR28; /* CNBCR28 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR29; /* CECR29 */
volatile uint32_t CSCR29; /* CSCR29 */
volatile uint32_t CCBCR29; /* CCBCR29 */
volatile uint32_t CNBCR29; /* CNBCR29 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR30; /* CECR30 */
volatile uint32_t CSCR30; /* CSCR30 */
volatile uint32_t CCBCR30; /* CCBCR30 */
volatile uint32_t CNBCR30; /* CNBCR30 */
/* end of struct st_mlb_from_cecr0 */
volatile uint8_t dummy158[80]; /* */
/* #define MLB_LCBCR0_COUNT (31) */
volatile uint32_t LCBCR0; /* LCBCR0 */
volatile uint32_t LCBCR1; /* LCBCR1 */
volatile uint32_t LCBCR2; /* LCBCR2 */
volatile uint32_t LCBCR3; /* LCBCR3 */
volatile uint32_t LCBCR4; /* LCBCR4 */
volatile uint32_t LCBCR5; /* LCBCR5 */
volatile uint32_t LCBCR6; /* LCBCR6 */
volatile uint32_t LCBCR7; /* LCBCR7 */
volatile uint32_t LCBCR8; /* LCBCR8 */
volatile uint32_t LCBCR9; /* LCBCR9 */
volatile uint32_t LCBCR10; /* LCBCR10 */
volatile uint32_t LCBCR11; /* LCBCR11 */
volatile uint32_t LCBCR12; /* LCBCR12 */
volatile uint32_t LCBCR13; /* LCBCR13 */
volatile uint32_t LCBCR14; /* LCBCR14 */
volatile uint32_t LCBCR15; /* LCBCR15 */
volatile uint32_t LCBCR16; /* LCBCR16 */
volatile uint32_t LCBCR17; /* LCBCR17 */
volatile uint32_t LCBCR18; /* LCBCR18 */
volatile uint32_t LCBCR19; /* LCBCR19 */
volatile uint32_t LCBCR20; /* LCBCR20 */
volatile uint32_t LCBCR21; /* LCBCR21 */
volatile uint32_t LCBCR22; /* LCBCR22 */
volatile uint32_t LCBCR23; /* LCBCR23 */
volatile uint32_t LCBCR24; /* LCBCR24 */
volatile uint32_t LCBCR25; /* LCBCR25 */
volatile uint32_t LCBCR26; /* LCBCR26 */
volatile uint32_t LCBCR27; /* LCBCR27 */
volatile uint32_t LCBCR28; /* LCBCR28 */
volatile uint32_t LCBCR29; /* LCBCR29 */
volatile uint32_t LCBCR30; /* LCBCR30 */
} r_io_mlb_t;
typedef struct st_mlb_from_cecr0
{
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
} r_io_mlb_from_cecr0_t;
/* Channel array defines of MLB (2)*/
#ifdef DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS
volatile struct st_mlb_from_cecr0* MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
MLB_FROM_CECR0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */
/* End of channel array defines of MLB (2)*/
#define MLBDCCR MLB.DCCR
#define MLBSSCR MLB.SSCR
#define MLBSDCR MLB.SDCR
#define MLBSMCR MLB.SMCR
#define MLBVCCR MLB.VCCR
#define MLBSBCR MLB.SBCR
#define MLBABCR MLB.ABCR
#define MLBCBCR MLB.CBCR
#define MLBIBCR MLB.IBCR
#define MLBCICR MLB.CICR
#define MLBCECR0 MLB.CECR0
#define MLBCSCR0 MLB.CSCR0
#define MLBCCBCR0 MLB.CCBCR0
#define MLBCNBCR0 MLB.CNBCR0
#define MLBCECR1 MLB.CECR1
#define MLBCSCR1 MLB.CSCR1
#define MLBCCBCR1 MLB.CCBCR1
#define MLBCNBCR1 MLB.CNBCR1
#define MLBCECR2 MLB.CECR2
#define MLBCSCR2 MLB.CSCR2
#define MLBCCBCR2 MLB.CCBCR2
#define MLBCNBCR2 MLB.CNBCR2
#define MLBCECR3 MLB.CECR3
#define MLBCSCR3 MLB.CSCR3
#define MLBCCBCR3 MLB.CCBCR3
#define MLBCNBCR3 MLB.CNBCR3
#define MLBCECR4 MLB.CECR4
#define MLBCSCR4 MLB.CSCR4
#define MLBCCBCR4 MLB.CCBCR4
#define MLBCNBCR4 MLB.CNBCR4
#define MLBCECR5 MLB.CECR5
#define MLBCSCR5 MLB.CSCR5
#define MLBCCBCR5 MLB.CCBCR5
#define MLBCNBCR5 MLB.CNBCR5
#define MLBCECR6 MLB.CECR6
#define MLBCSCR6 MLB.CSCR6
#define MLBCCBCR6 MLB.CCBCR6
#define MLBCNBCR6 MLB.CNBCR6
#define MLBCECR7 MLB.CECR7
#define MLBCSCR7 MLB.CSCR7
#define MLBCCBCR7 MLB.CCBCR7
#define MLBCNBCR7 MLB.CNBCR7
#define MLBCECR8 MLB.CECR8
#define MLBCSCR8 MLB.CSCR8
#define MLBCCBCR8 MLB.CCBCR8
#define MLBCNBCR8 MLB.CNBCR8
#define MLBCECR9 MLB.CECR9
#define MLBCSCR9 MLB.CSCR9
#define MLBCCBCR9 MLB.CCBCR9
#define MLBCNBCR9 MLB.CNBCR9
#define MLBCECR10 MLB.CECR10
#define MLBCSCR10 MLB.CSCR10
#define MLBCCBCR10 MLB.CCBCR10
#define MLBCNBCR10 MLB.CNBCR10
#define MLBCECR11 MLB.CECR11
#define MLBCSCR11 MLB.CSCR11
#define MLBCCBCR11 MLB.CCBCR11
#define MLBCNBCR11 MLB.CNBCR11
#define MLBCECR12 MLB.CECR12
#define MLBCSCR12 MLB.CSCR12
#define MLBCCBCR12 MLB.CCBCR12
#define MLBCNBCR12 MLB.CNBCR12
#define MLBCECR13 MLB.CECR13
#define MLBCSCR13 MLB.CSCR13
#define MLBCCBCR13 MLB.CCBCR13
#define MLBCNBCR13 MLB.CNBCR13
#define MLBCECR14 MLB.CECR14
#define MLBCSCR14 MLB.CSCR14
#define MLBCCBCR14 MLB.CCBCR14
#define MLBCNBCR14 MLB.CNBCR14
#define MLBCECR15 MLB.CECR15
#define MLBCSCR15 MLB.CSCR15
#define MLBCCBCR15 MLB.CCBCR15
#define MLBCNBCR15 MLB.CNBCR15
#define MLBCECR16 MLB.CECR16
#define MLBCSCR16 MLB.CSCR16
#define MLBCCBCR16 MLB.CCBCR16
#define MLBCNBCR16 MLB.CNBCR16
#define MLBCECR17 MLB.CECR17
#define MLBCSCR17 MLB.CSCR17
#define MLBCCBCR17 MLB.CCBCR17
#define MLBCNBCR17 MLB.CNBCR17
#define MLBCECR18 MLB.CECR18
#define MLBCSCR18 MLB.CSCR18
#define MLBCCBCR18 MLB.CCBCR18
#define MLBCNBCR18 MLB.CNBCR18
#define MLBCECR19 MLB.CECR19
#define MLBCSCR19 MLB.CSCR19
#define MLBCCBCR19 MLB.CCBCR19
#define MLBCNBCR19 MLB.CNBCR19
#define MLBCECR20 MLB.CECR20
#define MLBCSCR20 MLB.CSCR20
#define MLBCCBCR20 MLB.CCBCR20
#define MLBCNBCR20 MLB.CNBCR20
#define MLBCECR21 MLB.CECR21
#define MLBCSCR21 MLB.CSCR21
#define MLBCCBCR21 MLB.CCBCR21
#define MLBCNBCR21 MLB.CNBCR21
#define MLBCECR22 MLB.CECR22
#define MLBCSCR22 MLB.CSCR22
#define MLBCCBCR22 MLB.CCBCR22
#define MLBCNBCR22 MLB.CNBCR22
#define MLBCECR23 MLB.CECR23
#define MLBCSCR23 MLB.CSCR23
#define MLBCCBCR23 MLB.CCBCR23
#define MLBCNBCR23 MLB.CNBCR23
#define MLBCECR24 MLB.CECR24
#define MLBCSCR24 MLB.CSCR24
#define MLBCCBCR24 MLB.CCBCR24
#define MLBCNBCR24 MLB.CNBCR24
#define MLBCECR25 MLB.CECR25
#define MLBCSCR25 MLB.CSCR25
#define MLBCCBCR25 MLB.CCBCR25
#define MLBCNBCR25 MLB.CNBCR25
#define MLBCECR26 MLB.CECR26
#define MLBCSCR26 MLB.CSCR26
#define MLBCCBCR26 MLB.CCBCR26
#define MLBCNBCR26 MLB.CNBCR26
#define MLBCECR27 MLB.CECR27
#define MLBCSCR27 MLB.CSCR27
#define MLBCCBCR27 MLB.CCBCR27
#define MLBCNBCR27 MLB.CNBCR27
#define MLBCECR28 MLB.CECR28
#define MLBCSCR28 MLB.CSCR28
#define MLBCCBCR28 MLB.CCBCR28
#define MLBCNBCR28 MLB.CNBCR28
#define MLBCECR29 MLB.CECR29
#define MLBCSCR29 MLB.CSCR29
#define MLBCCBCR29 MLB.CCBCR29
#define MLBCNBCR29 MLB.CNBCR29
#define MLBCECR30 MLB.CECR30
#define MLBCSCR30 MLB.CSCR30
#define MLBCCBCR30 MLB.CCBCR30
#define MLBCNBCR30 MLB.CNBCR30
#define MLBLCBCR0 MLB.LCBCR0
#define MLBLCBCR1 MLB.LCBCR1
#define MLBLCBCR2 MLB.LCBCR2
#define MLBLCBCR3 MLB.LCBCR3
#define MLBLCBCR4 MLB.LCBCR4
#define MLBLCBCR5 MLB.LCBCR5
#define MLBLCBCR6 MLB.LCBCR6
#define MLBLCBCR7 MLB.LCBCR7
#define MLBLCBCR8 MLB.LCBCR8
#define MLBLCBCR9 MLB.LCBCR9
#define MLBLCBCR10 MLB.LCBCR10
#define MLBLCBCR11 MLB.LCBCR11
#define MLBLCBCR12 MLB.LCBCR12
#define MLBLCBCR13 MLB.LCBCR13
#define MLBLCBCR14 MLB.LCBCR14
#define MLBLCBCR15 MLB.LCBCR15
#define MLBLCBCR16 MLB.LCBCR16
#define MLBLCBCR17 MLB.LCBCR17
#define MLBLCBCR18 MLB.LCBCR18
#define MLBLCBCR19 MLB.LCBCR19
#define MLBLCBCR20 MLB.LCBCR20
#define MLBLCBCR21 MLB.LCBCR21
#define MLBLCBCR22 MLB.LCBCR22
#define MLBLCBCR23 MLB.LCBCR23
#define MLBLCBCR24 MLB.LCBCR24
#define MLBLCBCR25 MLB.LCBCR25
#define MLBLCBCR26 MLB.LCBCR26
#define MLBLCBCR27 MLB.LCBCR27
#define MLBLCBCR28 MLB.LCBCR28
#define MLBLCBCR29 MLB.LCBCR29
#define MLBLCBCR30 MLB.LCBCR30
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

74
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h
View File

@ -18,20 +18,53 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mmc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef MMC_IODEFINE_H
#define MMC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_mmc
{ /* MMC */
#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
#define MMCCE_ARG (MMC.CE_ARG)
#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
#define MMCCE_RESP3 (MMC.CE_RESP3)
#define MMCCE_RESP2 (MMC.CE_RESP2)
#define MMCCE_RESP1 (MMC.CE_RESP1)
#define MMCCE_RESP0 (MMC.CE_RESP0)
#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
#define MMCCE_DATA (MMC.CE_DATA)
#define MMCCE_INT (MMC.CE_INT)
#define MMCCE_INT_EN (MMC.CE_INT_EN)
#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
#define MMCCE_DETECT (MMC.CE_DETECT)
#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
#define MMCCE_VERSION (MMC.CE_VERSION)
#define MMC_CE_RESPn_COUNT (4)
typedef struct st_mmc
{
/* MMC */
volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
volatile uint8_t dummy182[4]; /* */
@ -41,7 +74,8 @@ struct st_mmc
volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
#define MMC_CE_RESPn_COUNT 4
/* #define MMC_CE_RESPn_COUNT (4) */
volatile uint32_t CE_RESP3; /* CE_RESP3 */
volatile uint32_t CE_RESP2; /* CE_RESP2 */
volatile uint32_t CE_RESP1; /* CE_RESP1 */
@ -60,33 +94,11 @@ struct st_mmc
volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
volatile uint8_t dummy186[4]; /* */
volatile uint32_t CE_VERSION; /* CE_VERSION */
};
} r_io_mmc_t;
#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
#define MMCCE_ARG MMC.CE_ARG
#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
#define MMCCE_RESP3 MMC.CE_RESP3
#define MMCCE_RESP2 MMC.CE_RESP2
#define MMCCE_RESP1 MMC.CE_RESP1
#define MMCCE_RESP0 MMC.CE_RESP0
#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
#define MMCCE_DATA MMC.CE_DATA
#define MMCCE_INT MMC.CE_INT
#define MMCCE_INT_EN MMC.CE_INT_EN
#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
#define MMCCE_DETECT MMC.CE_DETECT
#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
#define MMCCE_VERSION MMC.CE_VERSION
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

183
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h
View File

@ -18,20 +18,108 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mtu2_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef MTU2_IODEFINE_H
#define MTU2_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_mtu2
{ /* MTU2 */
#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
#define MTU2TCR_2 (MTU2.TCR_2)
#define MTU2TMDR_2 (MTU2.TMDR_2)
#define MTU2TIOR_2 (MTU2.TIOR_2)
#define MTU2TIER_2 (MTU2.TIER_2)
#define MTU2TSR_2 (MTU2.TSR_2)
#define MTU2TCNT_2 (MTU2.TCNT_2)
#define MTU2TGRA_2 (MTU2.TGRA_2)
#define MTU2TGRB_2 (MTU2.TGRB_2)
#define MTU2TCR_3 (MTU2.TCR_3)
#define MTU2TCR_4 (MTU2.TCR_4)
#define MTU2TMDR_3 (MTU2.TMDR_3)
#define MTU2TMDR_4 (MTU2.TMDR_4)
#define MTU2TIORH_3 (MTU2.TIORH_3)
#define MTU2TIORL_3 (MTU2.TIORL_3)
#define MTU2TIORH_4 (MTU2.TIORH_4)
#define MTU2TIORL_4 (MTU2.TIORL_4)
#define MTU2TIER_3 (MTU2.TIER_3)
#define MTU2TIER_4 (MTU2.TIER_4)
#define MTU2TOER (MTU2.TOER)
#define MTU2TGCR (MTU2.TGCR)
#define MTU2TOCR1 (MTU2.TOCR1)
#define MTU2TOCR2 (MTU2.TOCR2)
#define MTU2TCNT_3 (MTU2.TCNT_3)
#define MTU2TCNT_4 (MTU2.TCNT_4)
#define MTU2TCDR (MTU2.TCDR)
#define MTU2TDDR (MTU2.TDDR)
#define MTU2TGRA_3 (MTU2.TGRA_3)
#define MTU2TGRB_3 (MTU2.TGRB_3)
#define MTU2TGRA_4 (MTU2.TGRA_4)
#define MTU2TGRB_4 (MTU2.TGRB_4)
#define MTU2TCNTS (MTU2.TCNTS)
#define MTU2TCBR (MTU2.TCBR)
#define MTU2TGRC_3 (MTU2.TGRC_3)
#define MTU2TGRD_3 (MTU2.TGRD_3)
#define MTU2TGRC_4 (MTU2.TGRC_4)
#define MTU2TGRD_4 (MTU2.TGRD_4)
#define MTU2TSR_3 (MTU2.TSR_3)
#define MTU2TSR_4 (MTU2.TSR_4)
#define MTU2TITCR (MTU2.TITCR)
#define MTU2TITCNT (MTU2.TITCNT)
#define MTU2TBTER (MTU2.TBTER)
#define MTU2TDER (MTU2.TDER)
#define MTU2TOLBR (MTU2.TOLBR)
#define MTU2TBTM_3 (MTU2.TBTM_3)
#define MTU2TBTM_4 (MTU2.TBTM_4)
#define MTU2TADCR (MTU2.TADCR)
#define MTU2TADCORA_4 (MTU2.TADCORA_4)
#define MTU2TADCORB_4 (MTU2.TADCORB_4)
#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
#define MTU2TWCR (MTU2.TWCR)
#define MTU2TSTR (MTU2.TSTR)
#define MTU2TSYR (MTU2.TSYR)
#define MTU2TRWER (MTU2.TRWER)
#define MTU2TCR_0 (MTU2.TCR_0)
#define MTU2TMDR_0 (MTU2.TMDR_0)
#define MTU2TIORH_0 (MTU2.TIORH_0)
#define MTU2TIORL_0 (MTU2.TIORL_0)
#define MTU2TIER_0 (MTU2.TIER_0)
#define MTU2TSR_0 (MTU2.TSR_0)
#define MTU2TCNT_0 (MTU2.TCNT_0)
#define MTU2TGRA_0 (MTU2.TGRA_0)
#define MTU2TGRB_0 (MTU2.TGRB_0)
#define MTU2TGRC_0 (MTU2.TGRC_0)
#define MTU2TGRD_0 (MTU2.TGRD_0)
#define MTU2TGRE_0 (MTU2.TGRE_0)
#define MTU2TGRF_0 (MTU2.TGRF_0)
#define MTU2TIER2_0 (MTU2.TIER2_0)
#define MTU2TSR2_0 (MTU2.TSR2_0)
#define MTU2TBTM_0 (MTU2.TBTM_0)
#define MTU2TCR_1 (MTU2.TCR_1)
#define MTU2TMDR_1 (MTU2.TMDR_1)
#define MTU2TIOR_1 (MTU2.TIOR_1)
#define MTU2TIER_1 (MTU2.TIER_1)
#define MTU2TSR_1 (MTU2.TSR_1)
#define MTU2TCNT_1 (MTU2.TCNT_1)
#define MTU2TGRA_1 (MTU2.TGRA_1)
#define MTU2TGRB_1 (MTU2.TGRB_1)
#define MTU2TICCR (MTU2.TICCR)
typedef struct st_mtu2
{
/* MTU2 */
volatile uint8_t TCR_2; /* TCR_2 */
volatile uint8_t TMDR_2; /* TMDR_2 */
volatile uint8_t TIOR_2; /* TIOR_2 */
@ -128,90 +216,11 @@ struct st_mtu2
volatile uint16_t TGRB_1; /* TGRB_1 */
volatile uint8_t dummy536[4]; /* */
volatile uint8_t TICCR; /* TICCR */
};
} r_io_mtu2_t;
#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
#define MTU2TCR_2 MTU2.TCR_2
#define MTU2TMDR_2 MTU2.TMDR_2
#define MTU2TIOR_2 MTU2.TIOR_2
#define MTU2TIER_2 MTU2.TIER_2
#define MTU2TSR_2 MTU2.TSR_2
#define MTU2TCNT_2 MTU2.TCNT_2
#define MTU2TGRA_2 MTU2.TGRA_2
#define MTU2TGRB_2 MTU2.TGRB_2
#define MTU2TCR_3 MTU2.TCR_3
#define MTU2TCR_4 MTU2.TCR_4
#define MTU2TMDR_3 MTU2.TMDR_3
#define MTU2TMDR_4 MTU2.TMDR_4
#define MTU2TIORH_3 MTU2.TIORH_3
#define MTU2TIORL_3 MTU2.TIORL_3
#define MTU2TIORH_4 MTU2.TIORH_4
#define MTU2TIORL_4 MTU2.TIORL_4
#define MTU2TIER_3 MTU2.TIER_3
#define MTU2TIER_4 MTU2.TIER_4
#define MTU2TOER MTU2.TOER
#define MTU2TGCR MTU2.TGCR
#define MTU2TOCR1 MTU2.TOCR1
#define MTU2TOCR2 MTU2.TOCR2
#define MTU2TCNT_3 MTU2.TCNT_3
#define MTU2TCNT_4 MTU2.TCNT_4
#define MTU2TCDR MTU2.TCDR
#define MTU2TDDR MTU2.TDDR
#define MTU2TGRA_3 MTU2.TGRA_3
#define MTU2TGRB_3 MTU2.TGRB_3
#define MTU2TGRA_4 MTU2.TGRA_4
#define MTU2TGRB_4 MTU2.TGRB_4
#define MTU2TCNTS MTU2.TCNTS
#define MTU2TCBR MTU2.TCBR
#define MTU2TGRC_3 MTU2.TGRC_3
#define MTU2TGRD_3 MTU2.TGRD_3
#define MTU2TGRC_4 MTU2.TGRC_4
#define MTU2TGRD_4 MTU2.TGRD_4
#define MTU2TSR_3 MTU2.TSR_3
#define MTU2TSR_4 MTU2.TSR_4
#define MTU2TITCR MTU2.TITCR
#define MTU2TITCNT MTU2.TITCNT
#define MTU2TBTER MTU2.TBTER
#define MTU2TDER MTU2.TDER
#define MTU2TOLBR MTU2.TOLBR
#define MTU2TBTM_3 MTU2.TBTM_3
#define MTU2TBTM_4 MTU2.TBTM_4
#define MTU2TADCR MTU2.TADCR
#define MTU2TADCORA_4 MTU2.TADCORA_4
#define MTU2TADCORB_4 MTU2.TADCORB_4
#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
#define MTU2TWCR MTU2.TWCR
#define MTU2TSTR MTU2.TSTR
#define MTU2TSYR MTU2.TSYR
#define MTU2TRWER MTU2.TRWER
#define MTU2TCR_0 MTU2.TCR_0
#define MTU2TMDR_0 MTU2.TMDR_0
#define MTU2TIORH_0 MTU2.TIORH_0
#define MTU2TIORL_0 MTU2.TIORL_0
#define MTU2TIER_0 MTU2.TIER_0
#define MTU2TSR_0 MTU2.TSR_0
#define MTU2TCNT_0 MTU2.TCNT_0
#define MTU2TGRA_0 MTU2.TGRA_0
#define MTU2TGRB_0 MTU2.TGRB_0
#define MTU2TGRC_0 MTU2.TGRC_0
#define MTU2TGRD_0 MTU2.TGRD_0
#define MTU2TGRE_0 MTU2.TGRE_0
#define MTU2TGRF_0 MTU2.TGRF_0
#define MTU2TIER2_0 MTU2.TIER2_0
#define MTU2TSR2_0 MTU2.TSR2_0
#define MTU2TBTM_0 MTU2.TBTM_0
#define MTU2TCR_1 MTU2.TCR_1
#define MTU2TMDR_1 MTU2.TMDR_1
#define MTU2TIOR_1 MTU2.TIOR_1
#define MTU2TIER_1 MTU2.TIER_1
#define MTU2TSR_1 MTU2.TSR_1
#define MTU2TCNT_1 MTU2.TCNT_1
#define MTU2TGRA_1 MTU2.TGRA_1
#define MTU2TGRB_1 MTU2.TGRB_1
#define MTU2TICCR MTU2.TICCR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

83
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h
View File

@ -18,20 +18,55 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef OSTM_IODEFINE_H
#define OSTM_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_ostm
{ /* OSTM */
#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */
#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */
/* Start of channel array defines of OSTM */
/* Channel array defines of OSTM */
/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
#define OSTM_COUNT (2)
#define OSTM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&OSTM0, &OSTM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of OSTM */
#define OSTM0CMP (OSTM0.OSTMnCMP)
#define OSTM0CNT (OSTM0.OSTMnCNT)
#define OSTM0TE (OSTM0.OSTMnTE)
#define OSTM0TS (OSTM0.OSTMnTS)
#define OSTM0TT (OSTM0.OSTMnTT)
#define OSTM0CTL (OSTM0.OSTMnCTL)
#define OSTM1CMP (OSTM1.OSTMnCMP)
#define OSTM1CNT (OSTM1.OSTMnCNT)
#define OSTM1TE (OSTM1.OSTMnTE)
#define OSTM1TS (OSTM1.OSTMnTS)
#define OSTM1TT (OSTM1.OSTMnTT)
#define OSTM1CTL (OSTM1.OSTMnCTL)
typedef struct st_ostm
{
/* OSTM */
volatile uint32_t OSTMnCMP; /* OSTMnCMP */
volatile uint32_t OSTMnCNT; /* OSTMnCNT */
volatile uint8_t dummy1[8]; /* */
@ -42,37 +77,21 @@ struct st_ostm
volatile uint8_t OSTMnTT; /* OSTMnTT */
volatile uint8_t dummy4[7]; /* */
volatile uint8_t OSTMnCTL; /* OSTMnCTL */
};
} r_io_ostm_t;
#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */
#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */
/* Channel array defines of OSTM (2)*/
#ifdef DECLARE_OSTM_CHANNELS
volatile struct st_ostm* OSTM[ OSTM_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
OSTM_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_OSTM_CHANNELS */
/* End of channel array defines of OSTM (2)*/
/* Start of channnel array defines of OSTM */
/* Channnel array defines of OSTM */
/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
#define OSTM_COUNT 2
#define OSTM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&OSTM0, &OSTM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of OSTM */
#define OSTM0CMP OSTM0.OSTMnCMP
#define OSTM0CNT OSTM0.OSTMnCNT
#define OSTM0TE OSTM0.OSTMnTE
#define OSTM0TS OSTM0.OSTMnTS
#define OSTM0TT OSTM0.OSTMnTT
#define OSTM0CTL OSTM0.OSTMnCTL
#define OSTM1CMP OSTM1.OSTMnCMP
#define OSTM1CNT OSTM1.OSTMnCNT
#define OSTM1TE OSTM1.OSTMnTE
#define OSTM1TS OSTM1.OSTMnTS
#define OSTM1TT OSTM1.OSTMnTT
#define OSTM1CTL OSTM1.OSTMnCTL
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

188
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h
View File

@ -18,25 +18,112 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : pfv_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef PFV_IODEFINE_H
#define PFV_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_pfv
{ /* PFV */
#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
/* Start of channel array defines of PFV */
/* Channel array defines of PFV */
/*(Sample) value = PFV[ channel ]->PFVCR; */
#define PFV_COUNT (2)
#define PFV_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PFV0, &PFV1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of PFV */
#define PFV0PFVCR (PFV0.PFVCR)
#define PFV0PFVICR (PFV0.PFVICR)
#define PFV0PFVISR (PFV0.PFVISR)
#define PFV0PFVID0 (PFV0.PFVID0)
#define PFV0PFVID1 (PFV0.PFVID1)
#define PFV0PFVID2 (PFV0.PFVID2)
#define PFV0PFVID3 (PFV0.PFVID3)
#define PFV0PFVID4 (PFV0.PFVID4)
#define PFV0PFVID5 (PFV0.PFVID5)
#define PFV0PFVID6 (PFV0.PFVID6)
#define PFV0PFVID7 (PFV0.PFVID7)
#define PFV0PFVOD0 (PFV0.PFVOD0)
#define PFV0PFVOD1 (PFV0.PFVOD1)
#define PFV0PFVOD2 (PFV0.PFVOD2)
#define PFV0PFVOD3 (PFV0.PFVOD3)
#define PFV0PFVOD4 (PFV0.PFVOD4)
#define PFV0PFVOD5 (PFV0.PFVOD5)
#define PFV0PFVOD6 (PFV0.PFVOD6)
#define PFV0PFVOD7 (PFV0.PFVOD7)
#define PFV0PFVIFSR (PFV0.PFVIFSR)
#define PFV0PFVOFSR (PFV0.PFVOFSR)
#define PFV0PFVACR (PFV0.PFVACR)
#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
#define PFV0PFVSZR (PFV0.PFVSZR)
#define PFV1PFVCR (PFV1.PFVCR)
#define PFV1PFVICR (PFV1.PFVICR)
#define PFV1PFVISR (PFV1.PFVISR)
#define PFV1PFVID0 (PFV1.PFVID0)
#define PFV1PFVID1 (PFV1.PFVID1)
#define PFV1PFVID2 (PFV1.PFVID2)
#define PFV1PFVID3 (PFV1.PFVID3)
#define PFV1PFVID4 (PFV1.PFVID4)
#define PFV1PFVID5 (PFV1.PFVID5)
#define PFV1PFVID6 (PFV1.PFVID6)
#define PFV1PFVID7 (PFV1.PFVID7)
#define PFV1PFVOD0 (PFV1.PFVOD0)
#define PFV1PFVOD1 (PFV1.PFVOD1)
#define PFV1PFVOD2 (PFV1.PFVOD2)
#define PFV1PFVOD3 (PFV1.PFVOD3)
#define PFV1PFVOD4 (PFV1.PFVOD4)
#define PFV1PFVOD5 (PFV1.PFVOD5)
#define PFV1PFVOD6 (PFV1.PFVOD6)
#define PFV1PFVOD7 (PFV1.PFVOD7)
#define PFV1PFVIFSR (PFV1.PFVIFSR)
#define PFV1PFVOFSR (PFV1.PFVOFSR)
#define PFV1PFVACR (PFV1.PFVACR)
#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
#define PFV1PFVSZR (PFV1.PFVSZR)
#define PFVID_COUNT (8)
#define PFVOD_COUNT (8)
typedef struct st_pfv
{
/* PFV */
volatile uint32_t PFVCR; /* PFVCR */
volatile uint32_t PFVICR; /* PFVICR */
volatile uint32_t PFVISR; /* PFVISR */
volatile uint8_t dummy1[20]; /* */
#define PFVID_COUNT 8
/* #define PFVID_COUNT (8) */
volatile uint32_t PFVID0; /* PFVID0 */
volatile uint32_t PFVID1; /* PFVID1 */
volatile uint32_t PFVID2; /* PFVID2 */
@ -45,7 +132,8 @@ struct st_pfv
volatile uint32_t PFVID5; /* PFVID5 */
volatile uint32_t PFVID6; /* PFVID6 */
volatile uint32_t PFVID7; /* PFVID7 */
#define PFVOD_COUNT 8
/* #define PFVOD_COUNT (8) */
volatile uint32_t PFVOD0; /* PFVOD0 */
volatile uint32_t PFVOD1; /* PFVOD1 */
volatile uint32_t PFVOD2; /* PFVOD2 */
@ -66,85 +154,21 @@ struct st_pfv
volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
volatile uint32_t PFVSZR; /* PFVSZR */
};
} r_io_pfv_t;
#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
/* Channel array defines of PFV (2)*/
#ifdef DECLARE_PFV_CHANNELS
volatile struct st_pfv* PFV[ PFV_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
PFV_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_PFV_CHANNELS */
/* End of channel array defines of PFV (2)*/
/* Start of channnel array defines of PFV */
/* Channnel array defines of PFV */
/*(Sample) value = PFV[ channel ]->PFVCR; */
#define PFV_COUNT 2
#define PFV_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PFV0, &PFV1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of PFV */
#define PFV0PFVCR PFV0.PFVCR
#define PFV0PFVICR PFV0.PFVICR
#define PFV0PFVISR PFV0.PFVISR
#define PFV0PFVID0 PFV0.PFVID0
#define PFV0PFVID1 PFV0.PFVID1
#define PFV0PFVID2 PFV0.PFVID2
#define PFV0PFVID3 PFV0.PFVID3
#define PFV0PFVID4 PFV0.PFVID4
#define PFV0PFVID5 PFV0.PFVID5
#define PFV0PFVID6 PFV0.PFVID6
#define PFV0PFVID7 PFV0.PFVID7
#define PFV0PFVOD0 PFV0.PFVOD0
#define PFV0PFVOD1 PFV0.PFVOD1
#define PFV0PFVOD2 PFV0.PFVOD2
#define PFV0PFVOD3 PFV0.PFVOD3
#define PFV0PFVOD4 PFV0.PFVOD4
#define PFV0PFVOD5 PFV0.PFVOD5
#define PFV0PFVOD6 PFV0.PFVOD6
#define PFV0PFVOD7 PFV0.PFVOD7
#define PFV0PFVIFSR PFV0.PFVIFSR
#define PFV0PFVOFSR PFV0.PFVOFSR
#define PFV0PFVACR PFV0.PFVACR
#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
#define PFV0PFVSZR PFV0.PFVSZR
#define PFV1PFVCR PFV1.PFVCR
#define PFV1PFVICR PFV1.PFVICR
#define PFV1PFVISR PFV1.PFVISR
#define PFV1PFVID0 PFV1.PFVID0
#define PFV1PFVID1 PFV1.PFVID1
#define PFV1PFVID2 PFV1.PFVID2
#define PFV1PFVID3 PFV1.PFVID3
#define PFV1PFVID4 PFV1.PFVID4
#define PFV1PFVID5 PFV1.PFVID5
#define PFV1PFVID6 PFV1.PFVID6
#define PFV1PFVID7 PFV1.PFVID7
#define PFV1PFVOD0 PFV1.PFVOD0
#define PFV1PFVOD1 PFV1.PFVOD1
#define PFV1PFVOD2 PFV1.PFVOD2
#define PFV1PFVOD3 PFV1.PFVOD3
#define PFV1PFVOD4 PFV1.PFVOD4
#define PFV1PFVOD5 PFV1.PFVOD5
#define PFV1PFVOD6 PFV1.PFVOD6
#define PFV1PFVOD7 PFV1.PFVOD7
#define PFV1PFVIFSR PFV1.PFVIFSR
#define PFV1PFVOFSR PFV1.PFVOFSR
#define PFV1PFVACR PFV1.PFVACR
#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
#define PFV1PFVSZR PFV1.PFVSZR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

176
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h
View File

@ -18,83 +18,29 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : pwm_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef PWM_IODEFINE_H
#define PWM_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
union reg16_8_t
{
volatile uint16_t UINT16; /* 16-bit Access */
volatile uint8_t UINT8[2]; /* 8-bit Access */
};
struct st_pwm
{ /* PWM */
volatile uint8_t dummy559[2]; /* */
union reg16_8_t PWBTCR; /* PWBTCR */
volatile uint8_t dummy560[216]; /* */
/* start of struct st_pwm_common */
union reg16_8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy561[2]; /* */
union reg16_8_t PWPR_1; /* PWPR_1 */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
/* end of struct st_pwm_common */
/* start of struct st_pwm_common */
union reg16_8_t PWCR_2; /* PWCR_2 */
volatile uint8_t dummy562[2]; /* */
union reg16_8_t PWPR_2; /* PWPR_2 */
volatile uint16_t PWCYR_2; /* PWCYR_2 */
volatile uint16_t PWBFR_2A; /* PWBFR_2A */
volatile uint16_t PWBFR_2C; /* PWBFR_2C */
volatile uint16_t PWBFR_2E; /* PWBFR_2E */
volatile uint16_t PWBFR_2G; /* PWBFR_2G */
/* end of struct st_pwm_common */
};
struct st_pwm_common
{
union reg16_8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy572[2]; /* */
union reg16_8_t PWPR_1; /* PWPR_1 */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
};
#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
/* Start of channnel array defines of PWM */
/* Start of channel array defines of PWM */
/* Channnel array defines of PWMn */
/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
#define PWMn_COUNT 2
/* Channel array defines of PWMn */
/*(Sample) value = PWMn[ channel ]->PWCR_1; */
#define PWMn_COUNT (2)
#define PWMn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PWM1, &PWM2 \
@ -102,34 +48,88 @@ struct st_pwm_common
#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
/* End of channnel array defines of PWM */
/* End of channel array defines of PWM */
#define PWMPWBTCR (PWM.PWBTCR)
#define PWMPWCR_1 (PWM.PWCR_1)
#define PWMPWPR_1 (PWM.PWPR_1)
#define PWMPWCYR_1 (PWM.PWCYR_1)
#define PWMPWBFR_1A (PWM.PWBFR_1A)
#define PWMPWBFR_1C (PWM.PWBFR_1C)
#define PWMPWBFR_1E (PWM.PWBFR_1E)
#define PWMPWBFR_1G (PWM.PWBFR_1G)
#define PWMPWCR_2 (PWM.PWCR_2)
#define PWMPWPR_2 (PWM.PWPR_2)
#define PWMPWCYR_2 (PWM.PWCYR_2)
#define PWMPWBFR_2A (PWM.PWBFR_2A)
#define PWMPWBFR_2C (PWM.PWBFR_2C)
#define PWMPWBFR_2E (PWM.PWBFR_2E)
#define PWMPWBFR_2G (PWM.PWBFR_2G)
typedef struct st_pwm
{
/* PWM */
volatile uint8_t dummy559[2]; /* */
volatile uint8_t PWBTCR; /* PWBTCR */
volatile uint8_t dummy560[217]; /* */
/* start of struct st_pwm_common */
volatile uint8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy561[3]; /* */
volatile uint8_t PWPR_1; /* PWPR_1 */
volatile uint8_t dummy562[1]; /* */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
/* end of struct st_pwm_common */
/* start of struct st_pwm_common */
volatile uint8_t PWCR_2; /* PWCR_2 */
volatile uint8_t dummy563[3]; /* */
volatile uint8_t PWPR_2; /* PWPR_2 */
volatile uint8_t dummy564[1]; /* */
volatile uint16_t PWCYR_2; /* PWCYR_2 */
volatile uint16_t PWBFR_2A; /* PWBFR_2A */
volatile uint16_t PWBFR_2C; /* PWBFR_2C */
volatile uint16_t PWBFR_2E; /* PWBFR_2E */
volatile uint16_t PWBFR_2G; /* PWBFR_2G */
/* end of struct st_pwm_common */
} r_io_pwm_t;
typedef struct st_pwm_common
{
volatile uint8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy562[3]; /* */
volatile uint8_t PWPR_1; /* PWPR_1 */
volatile uint8_t dummy563[1]; /* */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
} r_io_pwm_common_t;
/* Channel array defines of PWMn (2)*/
#ifdef DECLARE_PWMn_CHANNELS
volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
PWMn_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_PWMn_CHANNELS */
/* End of channel array defines of PWMn (2)*/
#define PWMPWBTCR PWM.PWBTCR.UINT16
#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
#define PWMPWCR_1 PWM.PWCR_1.UINT16
#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
#define PWMPWPR_1 PWM.PWPR_1.UINT16
#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
#define PWMPWCYR_1 PWM.PWCYR_1
#define PWMPWBFR_1A PWM.PWBFR_1A
#define PWMPWBFR_1C PWM.PWBFR_1C
#define PWMPWBFR_1E PWM.PWBFR_1E
#define PWMPWBFR_1G PWM.PWBFR_1G
#define PWMPWCR_2 PWM.PWCR_2.UINT16
#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
#define PWMPWPR_2 PWM.PWPR_2.UINT16
#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
#define PWMPWCYR_2 PWM.PWCYR_2
#define PWMPWBFR_2A PWM.PWBFR_2A
#define PWMPWBFR_2C PWM.PWBFR_2C
#define PWMPWBFR_2E PWM.PWBFR_2E
#define PWMPWBFR_2G PWM.PWBFR_2G
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

1050
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h
View File

File diff suppressed because it is too large Load Diff

168
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h
View File

@ -18,30 +18,104 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : romdec_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef ROMDEC_IODEFINE_H
#define ROMDEC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_romdec
{ /* ROMDEC */
#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
#define ROMDECCROMEN (ROMDEC.CROMEN)
#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
#define ROMDECCROMST0 (ROMDEC.CROMST0)
#define ROMDECCROMST1 (ROMDEC.CROMST1)
#define ROMDECCROMST3 (ROMDEC.CROMST3)
#define ROMDECCROMST4 (ROMDEC.CROMST4)
#define ROMDECCROMST5 (ROMDEC.CROMST5)
#define ROMDECCROMST6 (ROMDEC.CROMST6)
#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
#define ROMDECHEAD00 (ROMDEC.HEAD00)
#define ROMDECHEAD01 (ROMDEC.HEAD01)
#define ROMDECHEAD02 (ROMDEC.HEAD02)
#define ROMDECHEAD03 (ROMDEC.HEAD03)
#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
#define ROMDECHEAD20 (ROMDEC.HEAD20)
#define ROMDECHEAD21 (ROMDEC.HEAD21)
#define ROMDECHEAD22 (ROMDEC.HEAD22)
#define ROMDECHEAD23 (ROMDEC.HEAD23)
#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
#define ROMDECCROMST0M (ROMDEC.CROMST0M)
#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
#define ROMDECSSI (ROMDEC.SSI)
#define ROMDECINTHOLD (ROMDEC.INTHOLD)
#define ROMDECINHINT (ROMDEC.INHINT)
#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
#define ROMDEC_CROMCTL0_COUNT (2)
#define ROMDEC_CROMST0_COUNT (2)
#define ROMDEC_CBUFST0_COUNT (3)
#define ROMDEC_HEAD00_COUNT (4)
#define ROMDEC_SHEAD00_COUNT (8)
#define ROMDEC_HEAD20_COUNT (4)
#define ROMDEC_SHEAD20_COUNT (8)
#define ROMDEC_CBUFCTL0_COUNT (4)
#define ROMDEC_STRMDIN0_COUNT (2)
typedef struct st_romdec
{
/* ROMDEC */
volatile uint8_t CROMEN; /* CROMEN */
volatile uint8_t CROMSY0; /* CROMSY0 */
#define ROMDEC_CROMCTL0_COUNT 2
/* #define ROMDEC_CROMCTL0_COUNT (2) */
volatile uint8_t CROMCTL0; /* CROMCTL0 */
volatile uint8_t CROMCTL1; /* CROMCTL1 */
volatile uint8_t dummy23[1]; /* */
volatile uint8_t CROMCTL3; /* CROMCTL3 */
volatile uint8_t CROMCTL4; /* CROMCTL4 */
volatile uint8_t CROMCTL5; /* CROMCTL5 */
#define ROMDEC_CROMST0_COUNT 2
/* #define ROMDEC_CROMST0_COUNT (2) */
volatile uint8_t CROMST0; /* CROMST0 */
volatile uint8_t CROMST1; /* CROMST1 */
volatile uint8_t dummy24[1]; /* */
@ -50,17 +124,20 @@ struct st_romdec
volatile uint8_t CROMST5; /* CROMST5 */
volatile uint8_t CROMST6; /* CROMST6 */
volatile uint8_t dummy25[5]; /* */
#define ROMDEC_CBUFST0_COUNT 3
/* #define ROMDEC_CBUFST0_COUNT (3) */
volatile uint8_t CBUFST0; /* CBUFST0 */
volatile uint8_t CBUFST1; /* CBUFST1 */
volatile uint8_t CBUFST2; /* CBUFST2 */
volatile uint8_t dummy26[1]; /* */
#define ROMDEC_HEAD00_COUNT 4
/* #define ROMDEC_HEAD00_COUNT (4) */
volatile uint8_t HEAD00; /* HEAD00 */
volatile uint8_t HEAD01; /* HEAD01 */
volatile uint8_t HEAD02; /* HEAD02 */
volatile uint8_t HEAD03; /* HEAD03 */
#define ROMDEC_SHEAD00_COUNT 8
/* #define ROMDEC_SHEAD00_COUNT (8) */
volatile uint8_t SHEAD00; /* SHEAD00 */
volatile uint8_t SHEAD01; /* SHEAD01 */
volatile uint8_t SHEAD02; /* SHEAD02 */
@ -69,12 +146,14 @@ struct st_romdec
volatile uint8_t SHEAD05; /* SHEAD05 */
volatile uint8_t SHEAD06; /* SHEAD06 */
volatile uint8_t SHEAD07; /* SHEAD07 */
#define ROMDEC_HEAD20_COUNT 4
/* #define ROMDEC_HEAD20_COUNT (4) */
volatile uint8_t HEAD20; /* HEAD20 */
volatile uint8_t HEAD21; /* HEAD21 */
volatile uint8_t HEAD22; /* HEAD22 */
volatile uint8_t HEAD23; /* HEAD23 */
#define ROMDEC_SHEAD20_COUNT 8
/* #define ROMDEC_SHEAD20_COUNT (8) */
volatile uint8_t SHEAD20; /* SHEAD20 */
volatile uint8_t SHEAD21; /* SHEAD21 */
volatile uint8_t SHEAD22; /* SHEAD22 */
@ -84,7 +163,8 @@ struct st_romdec
volatile uint8_t SHEAD26; /* SHEAD26 */
volatile uint8_t SHEAD27; /* SHEAD27 */
volatile uint8_t dummy27[16]; /* */
#define ROMDEC_CBUFCTL0_COUNT 4
/* #define ROMDEC_CBUFCTL0_COUNT (4) */
volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
@ -99,68 +179,16 @@ struct st_romdec
volatile uint8_t INTHOLD; /* INTHOLD */
volatile uint8_t INHINT; /* INHINT */
volatile uint8_t dummy31[246]; /* */
#define ROMDEC_STRMDIN0_COUNT 2
/* #define ROMDEC_STRMDIN0_COUNT (2) */
volatile uint16_t STRMDIN0; /* STRMDIN0 */
volatile uint16_t STRMDIN2; /* STRMDIN2 */
volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
};
} r_io_romdec_t;
#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
#define ROMDECCROMEN ROMDEC.CROMEN
#define ROMDECCROMSY0 ROMDEC.CROMSY0
#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
#define ROMDECCROMST0 ROMDEC.CROMST0
#define ROMDECCROMST1 ROMDEC.CROMST1
#define ROMDECCROMST3 ROMDEC.CROMST3
#define ROMDECCROMST4 ROMDEC.CROMST4
#define ROMDECCROMST5 ROMDEC.CROMST5
#define ROMDECCROMST6 ROMDEC.CROMST6
#define ROMDECCBUFST0 ROMDEC.CBUFST0
#define ROMDECCBUFST1 ROMDEC.CBUFST1
#define ROMDECCBUFST2 ROMDEC.CBUFST2
#define ROMDECHEAD00 ROMDEC.HEAD00
#define ROMDECHEAD01 ROMDEC.HEAD01
#define ROMDECHEAD02 ROMDEC.HEAD02
#define ROMDECHEAD03 ROMDEC.HEAD03
#define ROMDECSHEAD00 ROMDEC.SHEAD00
#define ROMDECSHEAD01 ROMDEC.SHEAD01
#define ROMDECSHEAD02 ROMDEC.SHEAD02
#define ROMDECSHEAD03 ROMDEC.SHEAD03
#define ROMDECSHEAD04 ROMDEC.SHEAD04
#define ROMDECSHEAD05 ROMDEC.SHEAD05
#define ROMDECSHEAD06 ROMDEC.SHEAD06
#define ROMDECSHEAD07 ROMDEC.SHEAD07
#define ROMDECHEAD20 ROMDEC.HEAD20
#define ROMDECHEAD21 ROMDEC.HEAD21
#define ROMDECHEAD22 ROMDEC.HEAD22
#define ROMDECHEAD23 ROMDEC.HEAD23
#define ROMDECSHEAD20 ROMDEC.SHEAD20
#define ROMDECSHEAD21 ROMDEC.SHEAD21
#define ROMDECSHEAD22 ROMDEC.SHEAD22
#define ROMDECSHEAD23 ROMDEC.SHEAD23
#define ROMDECSHEAD24 ROMDEC.SHEAD24
#define ROMDECSHEAD25 ROMDEC.SHEAD25
#define ROMDECSHEAD26 ROMDEC.SHEAD26
#define ROMDECSHEAD27 ROMDEC.SHEAD27
#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
#define ROMDECCROMST0M ROMDEC.CROMST0M
#define ROMDECROMDECRST ROMDEC.ROMDECRST
#define ROMDECRSTSTAT ROMDEC.RSTSTAT
#define ROMDECSSI ROMDEC.SSI
#define ROMDECINTHOLD ROMDEC.INTHOLD
#define ROMDECINHINT ROMDEC.INHINT
#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

17794
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h
View File

File diff suppressed because it is too large Load Diff

312
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h
View File

@ -18,27 +18,173 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rspi_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef RSPI_IODEFINE_H
#define RSPI_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#include "reg32_t.h"
#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
struct st_rspi
{ /* RSPI */
/* Start of channel array defines of RSPI */
/* Channel array defines of RSPI */
/*(Sample) value = RSPI[ channel ]->SPCR; */
#define RSPI_COUNT (5)
#define RSPI_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of RSPI */
#define SPCR_0 (RSPI0.SPCR)
#define SSLP_0 (RSPI0.SSLP)
#define SPPCR_0 (RSPI0.SPPCR)
#define SPSR_0 (RSPI0.SPSR)
#define SPDR_0 (RSPI0.SPDR.UINT32)
#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L])
#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H])
#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
#define SPSCR_0 (RSPI0.SPSCR)
#define SPSSR_0 (RSPI0.SPSSR)
#define SPBR_0 (RSPI0.SPBR)
#define SPDCR_0 (RSPI0.SPDCR)
#define SPCKD_0 (RSPI0.SPCKD)
#define SSLND_0 (RSPI0.SSLND)
#define SPND_0 (RSPI0.SPND)
#define SPCMD0_0 (RSPI0.SPCMD0)
#define SPCMD1_0 (RSPI0.SPCMD1)
#define SPCMD2_0 (RSPI0.SPCMD2)
#define SPCMD3_0 (RSPI0.SPCMD3)
#define SPBFCR_0 (RSPI0.SPBFCR)
#define SPBFDR_0 (RSPI0.SPBFDR)
#define SPCR_1 (RSPI1.SPCR)
#define SSLP_1 (RSPI1.SSLP)
#define SPPCR_1 (RSPI1.SPPCR)
#define SPSR_1 (RSPI1.SPSR)
#define SPDR_1 (RSPI1.SPDR.UINT32)
#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L])
#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H])
#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
#define SPSCR_1 (RSPI1.SPSCR)
#define SPSSR_1 (RSPI1.SPSSR)
#define SPBR_1 (RSPI1.SPBR)
#define SPDCR_1 (RSPI1.SPDCR)
#define SPCKD_1 (RSPI1.SPCKD)
#define SSLND_1 (RSPI1.SSLND)
#define SPND_1 (RSPI1.SPND)
#define SPCMD0_1 (RSPI1.SPCMD0)
#define SPCMD1_1 (RSPI1.SPCMD1)
#define SPCMD2_1 (RSPI1.SPCMD2)
#define SPCMD3_1 (RSPI1.SPCMD3)
#define SPBFCR_1 (RSPI1.SPBFCR)
#define SPBFDR_1 (RSPI1.SPBFDR)
#define SPCR_2 (RSPI2.SPCR)
#define SSLP_2 (RSPI2.SSLP)
#define SPPCR_2 (RSPI2.SPPCR)
#define SPSR_2 (RSPI2.SPSR)
#define SPDR_2 (RSPI2.SPDR.UINT32)
#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L])
#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H])
#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
#define SPSCR_2 (RSPI2.SPSCR)
#define SPSSR_2 (RSPI2.SPSSR)
#define SPBR_2 (RSPI2.SPBR)
#define SPDCR_2 (RSPI2.SPDCR)
#define SPCKD_2 (RSPI2.SPCKD)
#define SSLND_2 (RSPI2.SSLND)
#define SPND_2 (RSPI2.SPND)
#define SPCMD0_2 (RSPI2.SPCMD0)
#define SPCMD1_2 (RSPI2.SPCMD1)
#define SPCMD2_2 (RSPI2.SPCMD2)
#define SPCMD3_2 (RSPI2.SPCMD3)
#define SPBFCR_2 (RSPI2.SPBFCR)
#define SPBFDR_2 (RSPI2.SPBFDR)
#define SPCR_3 (RSPI3.SPCR)
#define SSLP_3 (RSPI3.SSLP)
#define SPPCR_3 (RSPI3.SPPCR)
#define SPSR_3 (RSPI3.SPSR)
#define SPDR_3 (RSPI3.SPDR.UINT32)
#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L])
#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H])
#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
#define SPSCR_3 (RSPI3.SPSCR)
#define SPSSR_3 (RSPI3.SPSSR)
#define SPBR_3 (RSPI3.SPBR)
#define SPDCR_3 (RSPI3.SPDCR)
#define SPCKD_3 (RSPI3.SPCKD)
#define SSLND_3 (RSPI3.SSLND)
#define SPND_3 (RSPI3.SPND)
#define SPCMD0_3 (RSPI3.SPCMD0)
#define SPCMD1_3 (RSPI3.SPCMD1)
#define SPCMD2_3 (RSPI3.SPCMD2)
#define SPCMD3_3 (RSPI3.SPCMD3)
#define SPBFCR_3 (RSPI3.SPBFCR)
#define SPBFDR_3 (RSPI3.SPBFDR)
#define SPCR_4 (RSPI4.SPCR)
#define SSLP_4 (RSPI4.SSLP)
#define SPPCR_4 (RSPI4.SPPCR)
#define SPSR_4 (RSPI4.SPSR)
#define SPDR_4 (RSPI4.SPDR.UINT32)
#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L])
#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H])
#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
#define SPSCR_4 (RSPI4.SPSCR)
#define SPSSR_4 (RSPI4.SPSSR)
#define SPBR_4 (RSPI4.SPBR)
#define SPDCR_4 (RSPI4.SPDCR)
#define SPCKD_4 (RSPI4.SPCKD)
#define SSLND_4 (RSPI4.SSLND)
#define SPND_4 (RSPI4.SPND)
#define SPCMD0_4 (RSPI4.SPCMD0)
#define SPCMD1_4 (RSPI4.SPCMD1)
#define SPCMD2_4 (RSPI4.SPCMD2)
#define SPCMD3_4 (RSPI4.SPCMD3)
#define SPBFCR_4 (RSPI4.SPBFCR)
#define SPBFDR_4 (RSPI4.SPBFDR)
#define SPCMD_COUNT (4)
typedef struct st_rspi
{
/* RSPI */
volatile uint8_t SPCR; /* SPCR */
volatile uint8_t SSLP; /* SSLP */
volatile uint8_t SPPCR; /* SPPCR */
volatile uint8_t SPSR; /* SPSR */
union reg32_t SPDR; /* SPDR */
union iodefine_reg32_t SPDR; /* SPDR */
volatile uint8_t SPSCR; /* SPSCR */
volatile uint8_t SPSSR; /* SPSSR */
@ -48,7 +194,8 @@ struct st_rspi
volatile uint8_t SSLND; /* SSLND */
volatile uint8_t SPND; /* SPND */
volatile uint8_t dummy1[1]; /* */
#define SPCMD_COUNT 4
/* #define SPCMD_COUNT (4) */
volatile uint16_t SPCMD0; /* SPCMD0 */
volatile uint16_t SPCMD1; /* SPCMD1 */
volatile uint16_t SPCMD2; /* SPCMD2 */
@ -57,148 +204,21 @@ struct st_rspi
volatile uint8_t SPBFCR; /* SPBFCR */
volatile uint8_t dummy3[1]; /* */
volatile uint16_t SPBFDR; /* SPBFDR */
};
} r_io_rspi_t;
#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
/* Channel array defines of RSPI (2)*/
#ifdef DECLARE_RSPI_CHANNELS
volatile struct st_rspi* RSPI[ RSPI_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
RSPI_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_RSPI_CHANNELS */
/* End of channel array defines of RSPI (2)*/
/* Start of channnel array defines of RSPI */
/* Channnel array defines of RSPI */
/*(Sample) value = RSPI[ channel ]->SPCR; */
#define RSPI_COUNT 5
#define RSPI_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of RSPI */
#define SPCR_0 RSPI0.SPCR
#define SSLP_0 RSPI0.SSLP
#define SPPCR_0 RSPI0.SPPCR
#define SPSR_0 RSPI0.SPSR
#define SPDR_0 RSPI0.SPDR.UINT32
#define SPDR_0L RSPI0.SPDR.UINT16[L]
#define SPDR_0H RSPI0.SPDR.UINT16[H]
#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
#define SPSCR_0 RSPI0.SPSCR
#define SPSSR_0 RSPI0.SPSSR
#define SPBR_0 RSPI0.SPBR
#define SPDCR_0 RSPI0.SPDCR
#define SPCKD_0 RSPI0.SPCKD
#define SSLND_0 RSPI0.SSLND
#define SPND_0 RSPI0.SPND
#define SPCMD0_0 RSPI0.SPCMD0
#define SPCMD1_0 RSPI0.SPCMD1
#define SPCMD2_0 RSPI0.SPCMD2
#define SPCMD3_0 RSPI0.SPCMD3
#define SPBFCR_0 RSPI0.SPBFCR
#define SPBFDR_0 RSPI0.SPBFDR
#define SPCR_1 RSPI1.SPCR
#define SSLP_1 RSPI1.SSLP
#define SPPCR_1 RSPI1.SPPCR
#define SPSR_1 RSPI1.SPSR
#define SPDR_1 RSPI1.SPDR.UINT32
#define SPDR_1L RSPI1.SPDR.UINT16[L]
#define SPDR_1H RSPI1.SPDR.UINT16[H]
#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
#define SPSCR_1 RSPI1.SPSCR
#define SPSSR_1 RSPI1.SPSSR
#define SPBR_1 RSPI1.SPBR
#define SPDCR_1 RSPI1.SPDCR
#define SPCKD_1 RSPI1.SPCKD
#define SSLND_1 RSPI1.SSLND
#define SPND_1 RSPI1.SPND
#define SPCMD0_1 RSPI1.SPCMD0
#define SPCMD1_1 RSPI1.SPCMD1
#define SPCMD2_1 RSPI1.SPCMD2
#define SPCMD3_1 RSPI1.SPCMD3
#define SPBFCR_1 RSPI1.SPBFCR
#define SPBFDR_1 RSPI1.SPBFDR
#define SPCR_2 RSPI2.SPCR
#define SSLP_2 RSPI2.SSLP
#define SPPCR_2 RSPI2.SPPCR
#define SPSR_2 RSPI2.SPSR
#define SPDR_2 RSPI2.SPDR.UINT32
#define SPDR_2L RSPI2.SPDR.UINT16[L]
#define SPDR_2H RSPI2.SPDR.UINT16[H]
#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
#define SPSCR_2 RSPI2.SPSCR
#define SPSSR_2 RSPI2.SPSSR
#define SPBR_2 RSPI2.SPBR
#define SPDCR_2 RSPI2.SPDCR
#define SPCKD_2 RSPI2.SPCKD
#define SSLND_2 RSPI2.SSLND
#define SPND_2 RSPI2.SPND
#define SPCMD0_2 RSPI2.SPCMD0
#define SPCMD1_2 RSPI2.SPCMD1
#define SPCMD2_2 RSPI2.SPCMD2
#define SPCMD3_2 RSPI2.SPCMD3
#define SPBFCR_2 RSPI2.SPBFCR
#define SPBFDR_2 RSPI2.SPBFDR
#define SPCR_3 RSPI3.SPCR
#define SSLP_3 RSPI3.SSLP
#define SPPCR_3 RSPI3.SPPCR
#define SPSR_3 RSPI3.SPSR
#define SPDR_3 RSPI3.SPDR.UINT32
#define SPDR_3L RSPI3.SPDR.UINT16[L]
#define SPDR_3H RSPI3.SPDR.UINT16[H]
#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
#define SPSCR_3 RSPI3.SPSCR
#define SPSSR_3 RSPI3.SPSSR
#define SPBR_3 RSPI3.SPBR
#define SPDCR_3 RSPI3.SPDCR
#define SPCKD_3 RSPI3.SPCKD
#define SSLND_3 RSPI3.SSLND
#define SPND_3 RSPI3.SPND
#define SPCMD0_3 RSPI3.SPCMD0
#define SPCMD1_3 RSPI3.SPCMD1
#define SPCMD2_3 RSPI3.SPCMD2
#define SPCMD3_3 RSPI3.SPCMD3
#define SPBFCR_3 RSPI3.SPBFCR
#define SPBFDR_3 RSPI3.SPBFDR
#define SPCR_4 RSPI4.SPCR
#define SSLP_4 RSPI4.SSLP
#define SPPCR_4 RSPI4.SPPCR
#define SPSR_4 RSPI4.SPSR
#define SPDR_4 RSPI4.SPDR.UINT32
#define SPDR_4L RSPI4.SPDR.UINT16[L]
#define SPDR_4H RSPI4.SPDR.UINT16[H]
#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
#define SPSCR_4 RSPI4.SPSCR
#define SPSSR_4 RSPI4.SPSSR
#define SPBR_4 RSPI4.SPBR
#define SPDCR_4 RSPI4.SPDCR
#define SPCKD_4 RSPI4.SPCKD
#define SSLND_4 RSPI4.SSLND
#define SPND_4 RSPI4.SPND
#define SPCMD0_4 RSPI4.SPCMD0
#define SPCMD1_4 RSPI4.SPCMD1
#define SPCMD2_4 RSPI4.SPCMD2
#define SPCMD3_4 RSPI4.SPCMD3
#define SPBFCR_4 RSPI4.SPBFCR
#define SPBFDR_4 RSPI4.SPBFDR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

67
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h
View File

@ -18,20 +18,50 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rtc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef RTC_IODEFINE_H
#define RTC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_rtc
{ /* RTC */
#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
#define RTCR64CNT (RTC.R64CNT)
#define RTCRSECCNT (RTC.RSECCNT)
#define RTCRMINCNT (RTC.RMINCNT)
#define RTCRHRCNT (RTC.RHRCNT)
#define RTCRWKCNT (RTC.RWKCNT)
#define RTCRDAYCNT (RTC.RDAYCNT)
#define RTCRMONCNT (RTC.RMONCNT)
#define RTCRYRCNT (RTC.RYRCNT)
#define RTCRSECAR (RTC.RSECAR)
#define RTCRMINAR (RTC.RMINAR)
#define RTCRHRAR (RTC.RHRAR)
#define RTCRWKAR (RTC.RWKAR)
#define RTCRDAYAR (RTC.RDAYAR)
#define RTCRMONAR (RTC.RMONAR)
#define RTCRCR1 (RTC.RCR1)
#define RTCRCR2 (RTC.RCR2)
#define RTCRYRAR (RTC.RYRAR)
#define RTCRCR3 (RTC.RCR3)
#define RTCRCR5 (RTC.RCR5)
#define RTCRFRH (RTC.RFRH)
#define RTCRFRL (RTC.RFRL)
typedef struct st_rtc
{
/* RTC */
volatile uint8_t R64CNT; /* R64CNT */
volatile uint8_t dummy537[1]; /* */
volatile uint8_t RSECCNT; /* RSECCNT */
@ -71,32 +101,11 @@ struct st_rtc
volatile uint8_t dummy554[3]; /* */
volatile uint16_t RFRH; /* RFRH */
volatile uint16_t RFRL; /* RFRL */
};
} r_io_rtc_t;
#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
#define RTCR64CNT RTC.R64CNT
#define RTCRSECCNT RTC.RSECCNT
#define RTCRMINCNT RTC.RMINCNT
#define RTCRHRCNT RTC.RHRCNT
#define RTCRWKCNT RTC.RWKCNT
#define RTCRDAYCNT RTC.RDAYCNT
#define RTCRMONCNT RTC.RMONCNT
#define RTCRYRCNT RTC.RYRCNT
#define RTCRSECAR RTC.RSECAR
#define RTCRMINAR RTC.RMINAR
#define RTCRHRAR RTC.RHRAR
#define RTCRWKAR RTC.RWKAR
#define RTCRDAYAR RTC.RDAYAR
#define RTCRMONAR RTC.RMONAR
#define RTCRCR1 RTC.RCR1
#define RTCRCR2 RTC.RCR2
#define RTCRYRAR RTC.RYRAR
#define RTCRCR3 RTC.RCR3
#define RTCRCR5 RTC.RCR5
#define RTCRFRH RTC.RFRH
#define RTCRFRL RTC.RFRL
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

254
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h
View File

@ -18,21 +18,137 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SCIF_IODEFINE_H
#define SCIF_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_scif
{ /* SCIF */
#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
/* Start of channel array defines of SCIF */
/* Channel array defines of SCIF */
/*(Sample) value = SCIF[ channel ]->SCSMR; */
#define SCIF_COUNT (8)
#define SCIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SCIF */
#define SCSMR_0 (SCIF0.SCSMR)
#define SCBRR_0 (SCIF0.SCBRR)
#define SCSCR_0 (SCIF0.SCSCR)
#define SCFTDR_0 (SCIF0.SCFTDR)
#define SCFSR_0 (SCIF0.SCFSR)
#define SCFRDR_0 (SCIF0.SCFRDR)
#define SCFCR_0 (SCIF0.SCFCR)
#define SCFDR_0 (SCIF0.SCFDR)
#define SCSPTR_0 (SCIF0.SCSPTR)
#define SCLSR_0 (SCIF0.SCLSR)
#define SCEMR_0 (SCIF0.SCEMR)
#define SCSMR_1 (SCIF1.SCSMR)
#define SCBRR_1 (SCIF1.SCBRR)
#define SCSCR_1 (SCIF1.SCSCR)
#define SCFTDR_1 (SCIF1.SCFTDR)
#define SCFSR_1 (SCIF1.SCFSR)
#define SCFRDR_1 (SCIF1.SCFRDR)
#define SCFCR_1 (SCIF1.SCFCR)
#define SCFDR_1 (SCIF1.SCFDR)
#define SCSPTR_1 (SCIF1.SCSPTR)
#define SCLSR_1 (SCIF1.SCLSR)
#define SCEMR_1 (SCIF1.SCEMR)
#define SCSMR_2 (SCIF2.SCSMR)
#define SCBRR_2 (SCIF2.SCBRR)
#define SCSCR_2 (SCIF2.SCSCR)
#define SCFTDR_2 (SCIF2.SCFTDR)
#define SCFSR_2 (SCIF2.SCFSR)
#define SCFRDR_2 (SCIF2.SCFRDR)
#define SCFCR_2 (SCIF2.SCFCR)
#define SCFDR_2 (SCIF2.SCFDR)
#define SCSPTR_2 (SCIF2.SCSPTR)
#define SCLSR_2 (SCIF2.SCLSR)
#define SCEMR_2 (SCIF2.SCEMR)
#define SCSMR_3 (SCIF3.SCSMR)
#define SCBRR_3 (SCIF3.SCBRR)
#define SCSCR_3 (SCIF3.SCSCR)
#define SCFTDR_3 (SCIF3.SCFTDR)
#define SCFSR_3 (SCIF3.SCFSR)
#define SCFRDR_3 (SCIF3.SCFRDR)
#define SCFCR_3 (SCIF3.SCFCR)
#define SCFDR_3 (SCIF3.SCFDR)
#define SCSPTR_3 (SCIF3.SCSPTR)
#define SCLSR_3 (SCIF3.SCLSR)
#define SCEMR_3 (SCIF3.SCEMR)
#define SCSMR_4 (SCIF4.SCSMR)
#define SCBRR_4 (SCIF4.SCBRR)
#define SCSCR_4 (SCIF4.SCSCR)
#define SCFTDR_4 (SCIF4.SCFTDR)
#define SCFSR_4 (SCIF4.SCFSR)
#define SCFRDR_4 (SCIF4.SCFRDR)
#define SCFCR_4 (SCIF4.SCFCR)
#define SCFDR_4 (SCIF4.SCFDR)
#define SCSPTR_4 (SCIF4.SCSPTR)
#define SCLSR_4 (SCIF4.SCLSR)
#define SCEMR_4 (SCIF4.SCEMR)
#define SCSMR_5 (SCIF5.SCSMR)
#define SCBRR_5 (SCIF5.SCBRR)
#define SCSCR_5 (SCIF5.SCSCR)
#define SCFTDR_5 (SCIF5.SCFTDR)
#define SCFSR_5 (SCIF5.SCFSR)
#define SCFRDR_5 (SCIF5.SCFRDR)
#define SCFCR_5 (SCIF5.SCFCR)
#define SCFDR_5 (SCIF5.SCFDR)
#define SCSPTR_5 (SCIF5.SCSPTR)
#define SCLSR_5 (SCIF5.SCLSR)
#define SCEMR_5 (SCIF5.SCEMR)
#define SCSMR_6 (SCIF6.SCSMR)
#define SCBRR_6 (SCIF6.SCBRR)
#define SCSCR_6 (SCIF6.SCSCR)
#define SCFTDR_6 (SCIF6.SCFTDR)
#define SCFSR_6 (SCIF6.SCFSR)
#define SCFRDR_6 (SCIF6.SCFRDR)
#define SCFCR_6 (SCIF6.SCFCR)
#define SCFDR_6 (SCIF6.SCFDR)
#define SCSPTR_6 (SCIF6.SCSPTR)
#define SCLSR_6 (SCIF6.SCLSR)
#define SCEMR_6 (SCIF6.SCEMR)
#define SCSMR_7 (SCIF7.SCSMR)
#define SCBRR_7 (SCIF7.SCBRR)
#define SCSCR_7 (SCIF7.SCSCR)
#define SCFTDR_7 (SCIF7.SCFTDR)
#define SCFSR_7 (SCIF7.SCFSR)
#define SCFRDR_7 (SCIF7.SCFRDR)
#define SCFCR_7 (SCIF7.SCFCR)
#define SCFDR_7 (SCIF7.SCFDR)
#define SCSPTR_7 (SCIF7.SCSPTR)
#define SCLSR_7 (SCIF7.SCLSR)
#define SCEMR_7 (SCIF7.SCEMR)
typedef struct st_scif
{
/* SCIF */
volatile uint16_t SCSMR; /* SCSMR */
volatile uint8_t dummy1[2]; /* */
volatile uint8_t SCBRR; /* SCBRR */
@ -54,129 +170,21 @@ struct st_scif
volatile uint16_t SCLSR; /* SCLSR */
volatile uint8_t dummy10[2]; /* */
volatile uint16_t SCEMR; /* SCEMR */
};
} r_io_scif_t;
#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
#define P_SCIF0 (0xE8007000uL) /* SCIF0 */
#define P_SCIF1 (0xE8007800uL) /* SCIF1 */
#define P_SCIF2 (0xE8008000uL) /* SCIF2 */
#define P_SCIF3 (0xE8008800uL) /* SCIF3 */
#define P_SCIF4 (0xE8009000uL) /* SCIF4 */
#define P_SCIF5 (0xE8009800uL) /* SCIF5 */
#define P_SCIF6 (0xE800A000uL) /* SCIF6 */
#define P_SCIF7 (0xE800A800uL) /* SCIF7 */
/* Channel array defines of SCIF (2)*/
#ifdef DECLARE_SCIF_CHANNELS
volatile struct st_scif* SCIF[ SCIF_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCIF_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCIF_CHANNELS */
/* End of channel array defines of SCIF (2)*/
/* Start of channnel array defines of SCIF */
/* Channnel array defines of SCIF */
/*(Sample) value = SCIF[ channel ]->SCSMR; */
#define SCIF_COUNT 8
#define SCIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SCIF */
#define SCSMR_0 SCIF0.SCSMR
#define SCBRR_0 SCIF0.SCBRR
#define SCSCR_0 SCIF0.SCSCR
#define SCFTDR_0 SCIF0.SCFTDR
#define SCFSR_0 SCIF0.SCFSR
#define SCFRDR_0 SCIF0.SCFRDR
#define SCFCR_0 SCIF0.SCFCR
#define SCFDR_0 SCIF0.SCFDR
#define SCSPTR_0 SCIF0.SCSPTR
#define SCLSR_0 SCIF0.SCLSR
#define SCEMR_0 SCIF0.SCEMR
#define SCSMR_1 SCIF1.SCSMR
#define SCBRR_1 SCIF1.SCBRR
#define SCSCR_1 SCIF1.SCSCR
#define SCFTDR_1 SCIF1.SCFTDR
#define SCFSR_1 SCIF1.SCFSR
#define SCFRDR_1 SCIF1.SCFRDR
#define SCFCR_1 SCIF1.SCFCR
#define SCFDR_1 SCIF1.SCFDR
#define SCSPTR_1 SCIF1.SCSPTR
#define SCLSR_1 SCIF1.SCLSR
#define SCEMR_1 SCIF1.SCEMR
#define SCSMR_2 SCIF2.SCSMR
#define SCBRR_2 SCIF2.SCBRR
#define SCSCR_2 SCIF2.SCSCR
#define SCFTDR_2 SCIF2.SCFTDR
#define SCFSR_2 SCIF2.SCFSR
#define SCFRDR_2 SCIF2.SCFRDR
#define SCFCR_2 SCIF2.SCFCR
#define SCFDR_2 SCIF2.SCFDR
#define SCSPTR_2 SCIF2.SCSPTR
#define SCLSR_2 SCIF2.SCLSR
#define SCEMR_2 SCIF2.SCEMR
#define SCSMR_3 SCIF3.SCSMR
#define SCBRR_3 SCIF3.SCBRR
#define SCSCR_3 SCIF3.SCSCR
#define SCFTDR_3 SCIF3.SCFTDR
#define SCFSR_3 SCIF3.SCFSR
#define SCFRDR_3 SCIF3.SCFRDR
#define SCFCR_3 SCIF3.SCFCR
#define SCFDR_3 SCIF3.SCFDR
#define SCSPTR_3 SCIF3.SCSPTR
#define SCLSR_3 SCIF3.SCLSR
#define SCEMR_3 SCIF3.SCEMR
#define SCSMR_4 SCIF4.SCSMR
#define SCBRR_4 SCIF4.SCBRR
#define SCSCR_4 SCIF4.SCSCR
#define SCFTDR_4 SCIF4.SCFTDR
#define SCFSR_4 SCIF4.SCFSR
#define SCFRDR_4 SCIF4.SCFRDR
#define SCFCR_4 SCIF4.SCFCR
#define SCFDR_4 SCIF4.SCFDR
#define SCSPTR_4 SCIF4.SCSPTR
#define SCLSR_4 SCIF4.SCLSR
#define SCEMR_4 SCIF4.SCEMR
#define SCSMR_5 SCIF5.SCSMR
#define SCBRR_5 SCIF5.SCBRR
#define SCSCR_5 SCIF5.SCSCR
#define SCFTDR_5 SCIF5.SCFTDR
#define SCFSR_5 SCIF5.SCFSR
#define SCFRDR_5 SCIF5.SCFRDR
#define SCFCR_5 SCIF5.SCFCR
#define SCFDR_5 SCIF5.SCFDR
#define SCSPTR_5 SCIF5.SCSPTR
#define SCLSR_5 SCIF5.SCLSR
#define SCEMR_5 SCIF5.SCEMR
#define SCSMR_6 SCIF6.SCSMR
#define SCBRR_6 SCIF6.SCBRR
#define SCSCR_6 SCIF6.SCSCR
#define SCFTDR_6 SCIF6.SCFTDR
#define SCFSR_6 SCIF6.SCFSR
#define SCFRDR_6 SCIF6.SCFRDR
#define SCFCR_6 SCIF6.SCFCR
#define SCFDR_6 SCIF6.SCFDR
#define SCSPTR_6 SCIF6.SCSPTR
#define SCLSR_6 SCIF6.SCLSR
#define SCEMR_6 SCIF6.SCEMR
#define SCSMR_7 SCIF7.SCSMR
#define SCBRR_7 SCIF7.SCBRR
#define SCSCR_7 SCIF7.SCSCR
#define SCFTDR_7 SCIF7.SCFTDR
#define SCFSR_7 SCIF7.SCFSR
#define SCFRDR_7 SCIF7.SCFRDR
#define SCFCR_7 SCIF7.SCFCR
#define SCFDR_7 SCIF7.SCFDR
#define SCSPTR_7 SCIF7.SCSPTR
#define SCLSR_7 SCIF7.SCLSR
#define SCEMR_7 SCIF7.SCEMR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

99
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h
View File

@ -18,20 +18,63 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scim_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SCIM_IODEFINE_H
#define SCIM_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_scim
{ /* SCIM */
#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
/* Start of channel array defines of SCIM */
/* Channel array defines of SCIM */
/*(Sample) value = SCIM[ channel ]->SMR; */
#define SCIM_COUNT (2)
#define SCIM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIM0, &SCIM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SCIM */
#define SMR0 (SCIM0.SMR)
#define BRR0 (SCIM0.BRR)
#define SCR0 (SCIM0.SCR)
#define TDR0 (SCIM0.TDR)
#define SSR0 (SCIM0.SSR)
#define RDR0 (SCIM0.RDR)
#define SCMR0 (SCIM0.SCMR)
#define SEMR0 (SCIM0.SEMR)
#define SNFR0 (SCIM0.SNFR)
#define SECR0 (SCIM0.SECR)
#define SMR1 (SCIM1.SMR)
#define BRR1 (SCIM1.BRR)
#define SCR1 (SCIM1.SCR)
#define TDR1 (SCIM1.TDR)
#define SSR1 (SCIM1.SSR)
#define RDR1 (SCIM1.RDR)
#define SCMR1 (SCIM1.SCMR)
#define SEMR1 (SCIM1.SEMR)
#define SNFR1 (SCIM1.SNFR)
#define SECR1 (SCIM1.SECR)
typedef struct st_scim
{
/* SCIM */
volatile uint8_t SMR; /* SMR */
volatile uint8_t BRR; /* BRR */
volatile uint8_t SCR; /* SCR */
@ -43,45 +86,21 @@ struct st_scim
volatile uint8_t SNFR; /* SNFR */
volatile uint8_t dummy1[4]; /* */
volatile uint8_t SECR; /* SECR */
};
} r_io_scim_t;
#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
/* Channel array defines of SCIM (2)*/
#ifdef DECLARE_SCIM_CHANNELS
volatile struct st_scim* SCIM[ SCIM_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCIM_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCIM_CHANNELS */
/* End of channel array defines of SCIM (2)*/
/* Start of channnel array defines of SCIM */
/* Channnel array defines of SCIM */
/*(Sample) value = SCIM[ channel ]->SMR; */
#define SCIM_COUNT 2
#define SCIM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIM0, &SCIM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SCIM */
#define SMR0 SCIM0.SMR
#define BRR0 SCIM0.BRR
#define SCR0 SCIM0.SCR
#define TDR0 SCIM0.TDR
#define SSR0 SCIM0.SSR
#define RDR0 SCIM0.RDR
#define SCMR0 SCIM0.SCMR
#define SEMR0 SCIM0.SEMR
#define SNFR0 SCIM0.SNFR
#define SECR0 SCIM0.SECR
#define SMR1 SCIM1.SMR
#define BRR1 SCIM1.BRR
#define SCR1 SCIM1.SCR
#define TDR1 SCIM1.TDR
#define SSR1 SCIM1.SSR
#define RDR1 SCIM1.RDR
#define SCMR1 SCIM1.SCMR
#define SEMR1 SCIM1.SEMR
#define SNFR1 SCIM1.SNFR
#define SECR1 SCIM1.SECR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

829
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h
View File

File diff suppressed because it is too large Load Diff

103
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h
View File

@ -18,27 +18,20 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : sdg_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SDG_IODEFINE_H
#define SDG_IODEFINE_H
struct st_sdg
{ /* SDG */
volatile uint8_t SGCR1; /* SGCR1 */
volatile uint8_t SGCSR; /* SGCSR */
volatile uint8_t SGCR2; /* SGCR2 */
volatile uint8_t SGLR; /* SGLR */
volatile uint8_t SGTFR; /* SGTFR */
volatile uint8_t SGSFR; /* SGSFR */
};
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
@ -46,41 +39,69 @@ struct st_sdg
#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
/* Start of channnel array defines of SDG */
/* Start of channel array defines of SDG */
/* Channnel array defines of SDG */
/* Channel array defines of SDG */
/*(Sample) value = SDG[ channel ]->SGCR1; */
#define SDG_COUNT 4
#define SDG_COUNT (4)
#define SDG_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SDG0, &SDG1, &SDG2, &SDG3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SDG */
/* End of channel array defines of SDG */
#define SGCR1_0 SDG0.SGCR1
#define SGCSR_0 SDG0.SGCSR
#define SGCR2_0 SDG0.SGCR2
#define SGLR_0 SDG0.SGLR
#define SGTFR_0 SDG0.SGTFR
#define SGSFR_0 SDG0.SGSFR
#define SGCR1_1 SDG1.SGCR1
#define SGCSR_1 SDG1.SGCSR
#define SGCR2_1 SDG1.SGCR2
#define SGLR_1 SDG1.SGLR
#define SGTFR_1 SDG1.SGTFR
#define SGSFR_1 SDG1.SGSFR
#define SGCR1_2 SDG2.SGCR1
#define SGCSR_2 SDG2.SGCSR
#define SGCR2_2 SDG2.SGCR2
#define SGLR_2 SDG2.SGLR
#define SGTFR_2 SDG2.SGTFR
#define SGSFR_2 SDG2.SGSFR
#define SGCR1_3 SDG3.SGCR1
#define SGCSR_3 SDG3.SGCSR
#define SGCR2_3 SDG3.SGCR2
#define SGLR_3 SDG3.SGLR
#define SGTFR_3 SDG3.SGTFR
#define SGSFR_3 SDG3.SGSFR
#define SGCR1_0 (SDG0.SGCR1)
#define SGCSR_0 (SDG0.SGCSR)
#define SGCR2_0 (SDG0.SGCR2)
#define SGLR_0 (SDG0.SGLR)
#define SGTFR_0 (SDG0.SGTFR)
#define SGSFR_0 (SDG0.SGSFR)
#define SGCR1_1 (SDG1.SGCR1)
#define SGCSR_1 (SDG1.SGCSR)
#define SGCR2_1 (SDG1.SGCR2)
#define SGLR_1 (SDG1.SGLR)
#define SGTFR_1 (SDG1.SGTFR)
#define SGSFR_1 (SDG1.SGSFR)
#define SGCR1_2 (SDG2.SGCR1)
#define SGCSR_2 (SDG2.SGCSR)
#define SGCR2_2 (SDG2.SGCR2)
#define SGLR_2 (SDG2.SGLR)
#define SGTFR_2 (SDG2.SGTFR)
#define SGSFR_2 (SDG2.SGSFR)
#define SGCR1_3 (SDG3.SGCR1)
#define SGCSR_3 (SDG3.SGCSR)
#define SGCR2_3 (SDG3.SGCR2)
#define SGLR_3 (SDG3.SGLR)
#define SGTFR_3 (SDG3.SGTFR)
#define SGSFR_3 (SDG3.SGSFR)
typedef struct st_sdg
{
/* SDG */
volatile uint8_t SGCR1; /* SGCR1 */
volatile uint8_t SGCSR; /* SGCSR */
volatile uint8_t SGCR2; /* SGCR2 */
volatile uint8_t SGLR; /* SGLR */
volatile uint8_t SGTFR; /* SGTFR */
volatile uint8_t SGSFR; /* SGSFR */
} r_io_sdg_t;
/* Channel array defines of SDG (2)*/
#ifdef DECLARE_SDG_CHANNELS
volatile struct st_sdg* SDG[ SDG_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SDG_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SDG_CHANNELS */
/* End of channel array defines of SDG (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

55
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h
View File

@ -18,19 +18,43 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spdif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SPDIF_IODEFINE_H
#define SPDIF_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_spdif
{ /* SPDIF */
#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */
#define SPDIFTLCA (SPDIF.TLCA)
#define SPDIFTRCA (SPDIF.TRCA)
#define SPDIFTLCS (SPDIF.TLCS)
#define SPDIFTRCS (SPDIF.TRCS)
#define SPDIFTUI (SPDIF.TUI)
#define SPDIFRLCA (SPDIF.RLCA)
#define SPDIFRRCA (SPDIF.RRCA)
#define SPDIFRLCS (SPDIF.RLCS)
#define SPDIFRRCS (SPDIF.RRCS)
#define SPDIFRUI (SPDIF.RUI)
#define SPDIFCTRL (SPDIF.CTRL)
#define SPDIFSTAT (SPDIF.STAT)
#define SPDIFTDAD (SPDIF.TDAD)
#define SPDIFRDAD (SPDIF.RDAD)
typedef struct st_spdif
{
/* SPDIF */
volatile uint32_t TLCA; /* TLCA */
volatile uint32_t TRCA; /* TRCA */
volatile uint32_t TLCS; /* TLCS */
@ -45,24 +69,11 @@ struct st_spdif
volatile uint32_t STAT; /* STAT */
volatile uint32_t TDAD; /* TDAD */
volatile uint32_t RDAD; /* RDAD */
};
} r_io_spdif_t;
#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */
#define SPDIFTLCA SPDIF.TLCA
#define SPDIFTRCA SPDIF.TRCA
#define SPDIFTLCS SPDIF.TLCS
#define SPDIFTRCS SPDIF.TRCS
#define SPDIFTUI SPDIF.TUI
#define SPDIFRLCA SPDIF.RLCA
#define SPDIFRRCA SPDIF.RRCA
#define SPDIFRLCS SPDIF.RLCS
#define SPDIFRRCS SPDIF.RRCS
#define SPDIFRUI SPDIF.RUI
#define SPDIFCTRL SPDIF.CTRL
#define SPDIFSTAT SPDIF.STAT
#define SPDIFTDAD SPDIF.TDAD
#define SPDIFRDAD SPDIF.RDAD
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

252
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h
View File

@ -18,20 +18,139 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spibsc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SPIBSC_IODEFINE_H
#define SPIBSC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_spibsc
{ /* SPIBSC */
#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
/* Start of channel array defines of SPIBSC */
/* Channel array defines of SPIBSC */
/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
#define SPIBSC_COUNT (2)
#define SPIBSC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SPIBSC0, &SPIBSC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SPIBSC */
#define CMNCR_0 (SPIBSC0.CMNCR)
#define SSLDR_0 (SPIBSC0.SSLDR)
#define SPBCR_0 (SPIBSC0.SPBCR)
#define DRCR_0 (SPIBSC0.DRCR)
#define DRCMR_0 (SPIBSC0.DRCMR)
#define DREAR_0 (SPIBSC0.DREAR)
#define DROPR_0 (SPIBSC0.DROPR)
#define DRENR_0 (SPIBSC0.DRENR)
#define SMCR_0 (SPIBSC0.SMCR)
#define SMCMR_0 (SPIBSC0.SMCMR)
#define SMADR_0 (SPIBSC0.SMADR)
#define SMOPR_0 (SPIBSC0.SMOPR)
#define SMENR_0 (SPIBSC0.SMENR)
#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32)
#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L])
#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H])
#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32)
#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L])
#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H])
#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32)
#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L])
#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H])
#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32)
#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L])
#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H])
#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
#define CMNSR_0 (SPIBSC0.CMNSR)
#define CKDLY_0 (SPIBSC0.CKDLY)
#define DRDMCR_0 (SPIBSC0.DRDMCR)
#define DRDRENR_0 (SPIBSC0.DRDRENR)
#define SMDMCR_0 (SPIBSC0.SMDMCR)
#define SMDRENR_0 (SPIBSC0.SMDRENR)
#define SPODLY_0 (SPIBSC0.SPODLY)
#define CMNCR_1 (SPIBSC1.CMNCR)
#define SSLDR_1 (SPIBSC1.SSLDR)
#define SPBCR_1 (SPIBSC1.SPBCR)
#define DRCR_1 (SPIBSC1.DRCR)
#define DRCMR_1 (SPIBSC1.DRCMR)
#define DREAR_1 (SPIBSC1.DREAR)
#define DROPR_1 (SPIBSC1.DROPR)
#define DRENR_1 (SPIBSC1.DRENR)
#define SMCR_1 (SPIBSC1.SMCR)
#define SMCMR_1 (SPIBSC1.SMCMR)
#define SMADR_1 (SPIBSC1.SMADR)
#define SMOPR_1 (SPIBSC1.SMOPR)
#define SMENR_1 (SPIBSC1.SMENR)
#define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32)
#define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L])
#define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H])
#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
#define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32)
#define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L])
#define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H])
#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
#define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32)
#define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L])
#define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H])
#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
#define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32)
#define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L])
#define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H])
#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
#define CMNSR_1 (SPIBSC1.CMNSR)
#define CKDLY_1 (SPIBSC1.CKDLY)
#define DRDMCR_1 (SPIBSC1.DRDMCR)
#define DRDRENR_1 (SPIBSC1.DRDRENR)
#define SMDMCR_1 (SPIBSC1.SMDMCR)
#define SMDRENR_1 (SPIBSC1.SMDRENR)
#define SPODLY_1 (SPIBSC1.SPODLY)
typedef struct st_spibsc
{
/* SPIBSC */
volatile uint32_t CMNCR; /* CMNCR */
volatile uint32_t SSLDR; /* SSLDR */
volatile uint32_t SPBCR; /* SPBCR */
@ -52,122 +171,29 @@ struct st_spibsc
union iodefine_reg32_t SMWDR1; /* SMWDR1 */
volatile uint32_t CMNSR; /* CMNSR */
volatile uint8_t dummy2[12]; /* */
volatile uint8_t dummy2[4]; /* */
volatile uint32_t CKDLY; /* CKDLY */
volatile uint8_t dummy3[4]; /* */
volatile uint32_t DRDMCR; /* DRDMCR */
volatile uint32_t DRDRENR; /* DRDRENR */
volatile uint32_t SMDMCR; /* SMDMCR */
volatile uint32_t SMDRENR; /* SMDRENR */
};
volatile uint32_t SPODLY; /* SPODLY */
} r_io_spibsc_t;
#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
/* Channel array defines of SPIBSC (2)*/
#ifdef DECLARE_SPIBSC_CHANNELS
volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SPIBSC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SPIBSC_CHANNELS */
/* End of channel array defines of SPIBSC (2)*/
/* Start of channnel array defines of SPIBSC */
/* Channnel array defines of SPIBSC */
/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
#define SPIBSC_COUNT 2
#define SPIBSC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SPIBSC0, &SPIBSC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SPIBSC */
#define CMNCR_0 SPIBSC0.CMNCR
#define SSLDR_0 SPIBSC0.SSLDR
#define SPBCR_0 SPIBSC0.SPBCR
#define DRCR_0 SPIBSC0.DRCR
#define DRCMR_0 SPIBSC0.DRCMR
#define DREAR_0 SPIBSC0.DREAR
#define DROPR_0 SPIBSC0.DROPR
#define DRENR_0 SPIBSC0.DRENR
#define SMCR_0 SPIBSC0.SMCR
#define SMCMR_0 SPIBSC0.SMCMR
#define SMADR_0 SPIBSC0.SMADR
#define SMOPR_0 SPIBSC0.SMOPR
#define SMENR_0 SPIBSC0.SMENR
#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32
#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L]
#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H]
#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32
#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L]
#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H]
#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32
#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L]
#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H]
#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32
#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L]
#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H]
#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
#define CMNSR_0 SPIBSC0.CMNSR
#define DRDMCR_0 SPIBSC0.DRDMCR
#define DRDRENR_0 SPIBSC0.DRDRENR
#define SMDMCR_0 SPIBSC0.SMDMCR
#define SMDRENR_0 SPIBSC0.SMDRENR
#define CMNCR_1 SPIBSC1.CMNCR
#define SSLDR_1 SPIBSC1.SSLDR
#define SPBCR_1 SPIBSC1.SPBCR
#define DRCR_1 SPIBSC1.DRCR
#define DRCMR_1 SPIBSC1.DRCMR
#define DREAR_1 SPIBSC1.DREAR
#define DROPR_1 SPIBSC1.DROPR
#define DRENR_1 SPIBSC1.DRENR
#define SMCR_1 SPIBSC1.SMCR
#define SMCMR_1 SPIBSC1.SMCMR
#define SMADR_1 SPIBSC1.SMADR
#define SMOPR_1 SPIBSC1.SMOPR
#define SMENR_1 SPIBSC1.SMENR
#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32
#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L]
#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H]
#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32
#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L]
#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H]
#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32
#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L]
#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H]
#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32
#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L]
#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H]
#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
#define CMNSR_1 SPIBSC1.CMNSR
#define DRDMCR_1 SPIBSC1.DRDMCR
#define DRDRENR_1 SPIBSC1.DRDRENR
#define SMDMCR_1 SPIBSC1.SMDMCR
#define SMDRENR_1 SPIBSC1.SMDRENR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

187
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h
View File

@ -18,20 +18,107 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ssif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SSIF_IODEFINE_H
#define SSIF_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_ssif
{ /* SSIF */
#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
/* Start of channel array defines of SSIF */
/* Channel array defines of SSIF */
/*(Sample) value = SSIF[ channel ]->SSICR; */
#define SSIF_COUNT (6)
#define SSIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SSIF */
#define SSICR_0 (SSIF0.SSICR)
#define SSISR_0 (SSIF0.SSISR)
#define SSIFCR_0 (SSIF0.SSIFCR)
#define SSIFSR_0 (SSIF0.SSIFSR)
#define SSIFTDR_0 (SSIF0.SSIFTDR)
#define SSIFRDR_0 (SSIF0.SSIFRDR)
#define SSITDMR_0 (SSIF0.SSITDMR)
#define SSIFCCR_0 (SSIF0.SSIFCCR)
#define SSIFCMR_0 (SSIF0.SSIFCMR)
#define SSIFCSR_0 (SSIF0.SSIFCSR)
#define SSICR_1 (SSIF1.SSICR)
#define SSISR_1 (SSIF1.SSISR)
#define SSIFCR_1 (SSIF1.SSIFCR)
#define SSIFSR_1 (SSIF1.SSIFSR)
#define SSIFTDR_1 (SSIF1.SSIFTDR)
#define SSIFRDR_1 (SSIF1.SSIFRDR)
#define SSITDMR_1 (SSIF1.SSITDMR)
#define SSIFCCR_1 (SSIF1.SSIFCCR)
#define SSIFCMR_1 (SSIF1.SSIFCMR)
#define SSIFCSR_1 (SSIF1.SSIFCSR)
#define SSICR_2 (SSIF2.SSICR)
#define SSISR_2 (SSIF2.SSISR)
#define SSIFCR_2 (SSIF2.SSIFCR)
#define SSIFSR_2 (SSIF2.SSIFSR)
#define SSIFTDR_2 (SSIF2.SSIFTDR)
#define SSIFRDR_2 (SSIF2.SSIFRDR)
#define SSITDMR_2 (SSIF2.SSITDMR)
#define SSIFCCR_2 (SSIF2.SSIFCCR)
#define SSIFCMR_2 (SSIF2.SSIFCMR)
#define SSIFCSR_2 (SSIF2.SSIFCSR)
#define SSICR_3 (SSIF3.SSICR)
#define SSISR_3 (SSIF3.SSISR)
#define SSIFCR_3 (SSIF3.SSIFCR)
#define SSIFSR_3 (SSIF3.SSIFSR)
#define SSIFTDR_3 (SSIF3.SSIFTDR)
#define SSIFRDR_3 (SSIF3.SSIFRDR)
#define SSITDMR_3 (SSIF3.SSITDMR)
#define SSIFCCR_3 (SSIF3.SSIFCCR)
#define SSIFCMR_3 (SSIF3.SSIFCMR)
#define SSIFCSR_3 (SSIF3.SSIFCSR)
#define SSICR_4 (SSIF4.SSICR)
#define SSISR_4 (SSIF4.SSISR)
#define SSIFCR_4 (SSIF4.SSIFCR)
#define SSIFSR_4 (SSIF4.SSIFSR)
#define SSIFTDR_4 (SSIF4.SSIFTDR)
#define SSIFRDR_4 (SSIF4.SSIFRDR)
#define SSITDMR_4 (SSIF4.SSITDMR)
#define SSIFCCR_4 (SSIF4.SSIFCCR)
#define SSIFCMR_4 (SSIF4.SSIFCMR)
#define SSIFCSR_4 (SSIF4.SSIFCSR)
#define SSICR_5 (SSIF5.SSICR)
#define SSISR_5 (SSIF5.SSISR)
#define SSIFCR_5 (SSIF5.SSIFCR)
#define SSIFSR_5 (SSIF5.SSIFSR)
#define SSIFTDR_5 (SSIF5.SSIFTDR)
#define SSIFRDR_5 (SSIF5.SSIFRDR)
#define SSITDMR_5 (SSIF5.SSITDMR)
#define SSIFCCR_5 (SSIF5.SSIFCCR)
#define SSIFCMR_5 (SSIF5.SSIFCMR)
#define SSIFCSR_5 (SSIF5.SSIFCSR)
typedef struct st_ssif
{
/* SSIF */
volatile uint32_t SSICR; /* SSICR */
volatile uint32_t SSISR; /* SSISR */
volatile uint8_t dummy1[8]; /* */
@ -43,89 +130,21 @@ struct st_ssif
volatile uint32_t SSIFCCR; /* SSIFCCR */
volatile uint32_t SSIFCMR; /* SSIFCMR */
volatile uint32_t SSIFCSR; /* SSIFCSR */
};
} r_io_ssif_t;
#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
/* Channel array defines of SSIF (2)*/
#ifdef DECLARE_SSIF_CHANNELS
volatile struct st_ssif* SSIF[ SSIF_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SSIF_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SSIF_CHANNELS */
/* End of channel array defines of SSIF (2)*/
/* Start of channnel array defines of SSIF */
/* Channnel array defines of SSIF */
/*(Sample) value = SSIF[ channel ]->SSICR; */
#define SSIF_COUNT 6
#define SSIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channnel array defines of SSIF */
#define SSICR_0 SSIF0.SSICR
#define SSISR_0 SSIF0.SSISR
#define SSIFCR_0 SSIF0.SSIFCR
#define SSIFSR_0 SSIF0.SSIFSR
#define SSIFTDR_0 SSIF0.SSIFTDR
#define SSIFRDR_0 SSIF0.SSIFRDR
#define SSITDMR_0 SSIF0.SSITDMR
#define SSIFCCR_0 SSIF0.SSIFCCR
#define SSIFCMR_0 SSIF0.SSIFCMR
#define SSIFCSR_0 SSIF0.SSIFCSR
#define SSICR_1 SSIF1.SSICR
#define SSISR_1 SSIF1.SSISR
#define SSIFCR_1 SSIF1.SSIFCR
#define SSIFSR_1 SSIF1.SSIFSR
#define SSIFTDR_1 SSIF1.SSIFTDR
#define SSIFRDR_1 SSIF1.SSIFRDR
#define SSITDMR_1 SSIF1.SSITDMR
#define SSIFCCR_1 SSIF1.SSIFCCR
#define SSIFCMR_1 SSIF1.SSIFCMR
#define SSIFCSR_1 SSIF1.SSIFCSR
#define SSICR_2 SSIF2.SSICR
#define SSISR_2 SSIF2.SSISR
#define SSIFCR_2 SSIF2.SSIFCR
#define SSIFSR_2 SSIF2.SSIFSR
#define SSIFTDR_2 SSIF2.SSIFTDR
#define SSIFRDR_2 SSIF2.SSIFRDR
#define SSITDMR_2 SSIF2.SSITDMR
#define SSIFCCR_2 SSIF2.SSIFCCR
#define SSIFCMR_2 SSIF2.SSIFCMR
#define SSIFCSR_2 SSIF2.SSIFCSR
#define SSICR_3 SSIF3.SSICR
#define SSISR_3 SSIF3.SSISR
#define SSIFCR_3 SSIF3.SSIFCR
#define SSIFSR_3 SSIF3.SSIFSR
#define SSIFTDR_3 SSIF3.SSIFTDR
#define SSIFRDR_3 SSIF3.SSIFRDR
#define SSITDMR_3 SSIF3.SSITDMR
#define SSIFCCR_3 SSIF3.SSIFCCR
#define SSIFCMR_3 SSIF3.SSIFCMR
#define SSIFCSR_3 SSIF3.SSIFCSR
#define SSICR_4 SSIF4.SSICR
#define SSISR_4 SSIF4.SSISR
#define SSIFCR_4 SSIF4.SSIFCR
#define SSIFSR_4 SSIF4.SSIFSR
#define SSIFTDR_4 SSIF4.SSIFTDR
#define SSIFRDR_4 SSIF4.SSIFRDR
#define SSITDMR_4 SSIF4.SSITDMR
#define SSIFCCR_4 SSIF4.SSIFCCR
#define SSIFCMR_4 SSIF4.SSIFCMR
#define SSIFCSR_4 SSIF4.SSIFCSR
#define SSICR_5 SSIF5.SSICR
#define SSISR_5 SSIF5.SSISR
#define SSIFCR_5 SSIF5.SSIFCR
#define SSIFSR_5 SSIF5.SSIFSR
#define SSIFTDR_5 SSIF5.SSIFTDR
#define SSIFRDR_5 SSIF5.SSIFRDR
#define SSITDMR_5 SSIF5.SSITDMR
#define SSIFCCR_5 SSIF5.SSIFCCR
#define SSIFCMR_5 SSIF5.SSIFCMR
#define SSIFCSR_5 SSIF5.SSIFCSR
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

770
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h
View File

@ -18,20 +18,365 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : usb20_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef USB20_IODEFINE_H
#define USB20_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
struct st_usb20
{ /* USB20 */
#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */
#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */
/* Start of channel array defines of USB20 */
/* Channel array defines of USB20 */
/*(Sample) value = USB20[ channel ]->SYSCFG0; */
#define USB20_COUNT (2)
#define USB20_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&USB200, &USB201 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* Channel array defines of USB20_FROM_D0FIFOB0 */
/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
#define USB20_FROM_D0FIFOB0_COUNT (2)
#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
&USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
/* Channel array defines of USB20_FROM_PIPE1ATRE */
/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
#define USB20_FROM_PIPE1ATRE_COUNT (5)
#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
&USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
/* Channel array defines of USB20_FROM_D0FIFOSEL */
/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
#define USB20_FROM_D0FIFOSEL_COUNT (2)
#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
&USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
/* End of channel array defines of USB20 */
#define SYSCFG0_0 (USB200.SYSCFG0)
#define BUSWAIT_0 (USB200.BUSWAIT)
#define SYSSTS0_0 (USB200.SYSSTS0)
#define DVSTCTR0_0 (USB200.DVSTCTR0)
#define TESTMODE_0 (USB200.TESTMODE)
#define D0FBCFG_0 (USB200.D0FBCFG)
#define D1FBCFG_0 (USB200.D1FBCFG)
#define CFIFO_0 (USB200.CFIFO.UINT32)
#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L])
#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H])
#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL])
#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH])
#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL])
#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH])
#define D0FIFO_0 (USB200.D0FIFO.UINT32)
#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L])
#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H])
#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL])
#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH])
#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL])
#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH])
#define D1FIFO_0 (USB200.D1FIFO.UINT32)
#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L])
#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H])
#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL])
#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH])
#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL])
#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH])
#define CFIFOSEL_0 (USB200.CFIFOSEL)
#define CFIFOCTR_0 (USB200.CFIFOCTR)
#define D0FIFOSEL_0 (USB200.D0FIFOSEL)
#define D0FIFOCTR_0 (USB200.D0FIFOCTR)
#define D1FIFOSEL_0 (USB200.D1FIFOSEL)
#define D1FIFOCTR_0 (USB200.D1FIFOCTR)
#define INTENB0_0 (USB200.INTENB0)
#define INTENB1_0 (USB200.INTENB1)
#define BRDYENB_0 (USB200.BRDYENB)
#define NRDYENB_0 (USB200.NRDYENB)
#define BEMPENB_0 (USB200.BEMPENB)
#define SOFCFG_0 (USB200.SOFCFG)
#define INTSTS0_0 (USB200.INTSTS0)
#define INTSTS1_0 (USB200.INTSTS1)
#define BRDYSTS_0 (USB200.BRDYSTS)
#define NRDYSTS_0 (USB200.NRDYSTS)
#define BEMPSTS_0 (USB200.BEMPSTS)
#define FRMNUM_0 (USB200.FRMNUM)
#define UFRMNUM_0 (USB200.UFRMNUM)
#define USBADDR_0 (USB200.USBADDR)
#define USBREQ_0 (USB200.USBREQ)
#define USBVAL_0 (USB200.USBVAL)
#define USBINDX_0 (USB200.USBINDX)
#define USBLENG_0 (USB200.USBLENG)
#define DCPCFG_0 (USB200.DCPCFG)
#define DCPMAXP_0 (USB200.DCPMAXP)
#define DCPCTR_0 (USB200.DCPCTR)
#define PIPESEL_0 (USB200.PIPESEL)
#define PIPECFG_0 (USB200.PIPECFG)
#define PIPEBUF_0 (USB200.PIPEBUF)
#define PIPEMAXP_0 (USB200.PIPEMAXP)
#define PIPEPERI_0 (USB200.PIPEPERI)
#define PIPE1CTR_0 (USB200.PIPE1CTR)
#define PIPE2CTR_0 (USB200.PIPE2CTR)
#define PIPE3CTR_0 (USB200.PIPE3CTR)
#define PIPE4CTR_0 (USB200.PIPE4CTR)
#define PIPE5CTR_0 (USB200.PIPE5CTR)
#define PIPE6CTR_0 (USB200.PIPE6CTR)
#define PIPE7CTR_0 (USB200.PIPE7CTR)
#define PIPE8CTR_0 (USB200.PIPE8CTR)
#define PIPE9CTR_0 (USB200.PIPE9CTR)
#define PIPEACTR_0 (USB200.PIPEACTR)
#define PIPEBCTR_0 (USB200.PIPEBCTR)
#define PIPECCTR_0 (USB200.PIPECCTR)
#define PIPEDCTR_0 (USB200.PIPEDCTR)
#define PIPEECTR_0 (USB200.PIPEECTR)
#define PIPEFCTR_0 (USB200.PIPEFCTR)
#define PIPE1TRE_0 (USB200.PIPE1TRE)
#define PIPE1TRN_0 (USB200.PIPE1TRN)
#define PIPE2TRE_0 (USB200.PIPE2TRE)
#define PIPE2TRN_0 (USB200.PIPE2TRN)
#define PIPE3TRE_0 (USB200.PIPE3TRE)
#define PIPE3TRN_0 (USB200.PIPE3TRN)
#define PIPE4TRE_0 (USB200.PIPE4TRE)
#define PIPE4TRN_0 (USB200.PIPE4TRN)
#define PIPE5TRE_0 (USB200.PIPE5TRE)
#define PIPE5TRN_0 (USB200.PIPE5TRN)
#define PIPEBTRE_0 (USB200.PIPEBTRE)
#define PIPEBTRN_0 (USB200.PIPEBTRN)
#define PIPECTRE_0 (USB200.PIPECTRE)
#define PIPECTRN_0 (USB200.PIPECTRN)
#define PIPEDTRE_0 (USB200.PIPEDTRE)
#define PIPEDTRN_0 (USB200.PIPEDTRN)
#define PIPEETRE_0 (USB200.PIPEETRE)
#define PIPEETRN_0 (USB200.PIPEETRN)
#define PIPEFTRE_0 (USB200.PIPEFTRE)
#define PIPEFTRN_0 (USB200.PIPEFTRN)
#define PIPE9TRE_0 (USB200.PIPE9TRE)
#define PIPE9TRN_0 (USB200.PIPE9TRN)
#define PIPEATRE_0 (USB200.PIPEATRE)
#define PIPEATRN_0 (USB200.PIPEATRN)
#define DEVADD0_0 (USB200.DEVADD0)
#define DEVADD1_0 (USB200.DEVADD1)
#define DEVADD2_0 (USB200.DEVADD2)
#define DEVADD3_0 (USB200.DEVADD3)
#define DEVADD4_0 (USB200.DEVADD4)
#define DEVADD5_0 (USB200.DEVADD5)
#define DEVADD6_0 (USB200.DEVADD6)
#define DEVADD7_0 (USB200.DEVADD7)
#define DEVADD8_0 (USB200.DEVADD8)
#define DEVADD9_0 (USB200.DEVADD9)
#define DEVADDA_0 (USB200.DEVADDA)
#define SUSPMODE_0 (USB200.SUSPMODE)
#define D0FIFOB0_0 (USB200.D0FIFOB0)
#define D0FIFOB1_0 (USB200.D0FIFOB1)
#define D0FIFOB2_0 (USB200.D0FIFOB2)
#define D0FIFOB3_0 (USB200.D0FIFOB3)
#define D0FIFOB4_0 (USB200.D0FIFOB4)
#define D0FIFOB5_0 (USB200.D0FIFOB5)
#define D0FIFOB6_0 (USB200.D0FIFOB6)
#define D0FIFOB7_0 (USB200.D0FIFOB7)
#define D1FIFOB0_0 (USB200.D1FIFOB0)
#define D1FIFOB1_0 (USB200.D1FIFOB1)
#define D1FIFOB2_0 (USB200.D1FIFOB2)
#define D1FIFOB3_0 (USB200.D1FIFOB3)
#define D1FIFOB4_0 (USB200.D1FIFOB4)
#define D1FIFOB5_0 (USB200.D1FIFOB5)
#define D1FIFOB6_0 (USB200.D1FIFOB6)
#define D1FIFOB7_0 (USB200.D1FIFOB7)
#define SYSCFG0_1 (USB201.SYSCFG0)
#define BUSWAIT_1 (USB201.BUSWAIT)
#define SYSSTS0_1 (USB201.SYSSTS0)
#define DVSTCTR0_1 (USB201.DVSTCTR0)
#define TESTMODE_1 (USB201.TESTMODE)
#define D0FBCFG_1 (USB201.D0FBCFG)
#define D1FBCFG_1 (USB201.D1FBCFG)
#define CFIFO_1 (USB201.CFIFO.UINT32)
#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L])
#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H])
#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL])
#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH])
#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL])
#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH])
#define D0FIFO_1 (USB201.D0FIFO.UINT32)
#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L])
#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H])
#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL])
#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH])
#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL])
#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH])
#define D1FIFO_1 (USB201.D1FIFO.UINT32)
#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L])
#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H])
#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL])
#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH])
#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL])
#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH])
#define CFIFOSEL_1 (USB201.CFIFOSEL)
#define CFIFOCTR_1 (USB201.CFIFOCTR)
#define D0FIFOSEL_1 (USB201.D0FIFOSEL)
#define D0FIFOCTR_1 (USB201.D0FIFOCTR)
#define D1FIFOSEL_1 (USB201.D1FIFOSEL)
#define D1FIFOCTR_1 (USB201.D1FIFOCTR)
#define INTENB0_1 (USB201.INTENB0)
#define INTENB1_1 (USB201.INTENB1)
#define BRDYENB_1 (USB201.BRDYENB)
#define NRDYENB_1 (USB201.NRDYENB)
#define BEMPENB_1 (USB201.BEMPENB)
#define SOFCFG_1 (USB201.SOFCFG)
#define INTSTS0_1 (USB201.INTSTS0)
#define INTSTS1_1 (USB201.INTSTS1)
#define BRDYSTS_1 (USB201.BRDYSTS)
#define NRDYSTS_1 (USB201.NRDYSTS)
#define BEMPSTS_1 (USB201.BEMPSTS)
#define FRMNUM_1 (USB201.FRMNUM)
#define UFRMNUM_1 (USB201.UFRMNUM)
#define USBADDR_1 (USB201.USBADDR)
#define USBREQ_1 (USB201.USBREQ)
#define USBVAL_1 (USB201.USBVAL)
#define USBINDX_1 (USB201.USBINDX)
#define USBLENG_1 (USB201.USBLENG)
#define DCPCFG_1 (USB201.DCPCFG)
#define DCPMAXP_1 (USB201.DCPMAXP)
#define DCPCTR_1 (USB201.DCPCTR)
#define PIPESEL_1 (USB201.PIPESEL)
#define PIPECFG_1 (USB201.PIPECFG)
#define PIPEBUF_1 (USB201.PIPEBUF)
#define PIPEMAXP_1 (USB201.PIPEMAXP)
#define PIPEPERI_1 (USB201.PIPEPERI)
#define PIPE1CTR_1 (USB201.PIPE1CTR)
#define PIPE2CTR_1 (USB201.PIPE2CTR)
#define PIPE3CTR_1 (USB201.PIPE3CTR)
#define PIPE4CTR_1 (USB201.PIPE4CTR)
#define PIPE5CTR_1 (USB201.PIPE5CTR)
#define PIPE6CTR_1 (USB201.PIPE6CTR)
#define PIPE7CTR_1 (USB201.PIPE7CTR)
#define PIPE8CTR_1 (USB201.PIPE8CTR)
#define PIPE9CTR_1 (USB201.PIPE9CTR)
#define PIPEACTR_1 (USB201.PIPEACTR)
#define PIPEBCTR_1 (USB201.PIPEBCTR)
#define PIPECCTR_1 (USB201.PIPECCTR)
#define PIPEDCTR_1 (USB201.PIPEDCTR)
#define PIPEECTR_1 (USB201.PIPEECTR)
#define PIPEFCTR_1 (USB201.PIPEFCTR)
#define PIPE1TRE_1 (USB201.PIPE1TRE)
#define PIPE1TRN_1 (USB201.PIPE1TRN)
#define PIPE2TRE_1 (USB201.PIPE2TRE)
#define PIPE2TRN_1 (USB201.PIPE2TRN)
#define PIPE3TRE_1 (USB201.PIPE3TRE)
#define PIPE3TRN_1 (USB201.PIPE3TRN)
#define PIPE4TRE_1 (USB201.PIPE4TRE)
#define PIPE4TRN_1 (USB201.PIPE4TRN)
#define PIPE5TRE_1 (USB201.PIPE5TRE)
#define PIPE5TRN_1 (USB201.PIPE5TRN)
#define PIPEBTRE_1 (USB201.PIPEBTRE)
#define PIPEBTRN_1 (USB201.PIPEBTRN)
#define PIPECTRE_1 (USB201.PIPECTRE)
#define PIPECTRN_1 (USB201.PIPECTRN)
#define PIPEDTRE_1 (USB201.PIPEDTRE)
#define PIPEDTRN_1 (USB201.PIPEDTRN)
#define PIPEETRE_1 (USB201.PIPEETRE)
#define PIPEETRN_1 (USB201.PIPEETRN)
#define PIPEFTRE_1 (USB201.PIPEFTRE)
#define PIPEFTRN_1 (USB201.PIPEFTRN)
#define PIPE9TRE_1 (USB201.PIPE9TRE)
#define PIPE9TRN_1 (USB201.PIPE9TRN)
#define PIPEATRE_1 (USB201.PIPEATRE)
#define PIPEATRN_1 (USB201.PIPEATRN)
#define DEVADD0_1 (USB201.DEVADD0)
#define DEVADD1_1 (USB201.DEVADD1)
#define DEVADD2_1 (USB201.DEVADD2)
#define DEVADD3_1 (USB201.DEVADD3)
#define DEVADD4_1 (USB201.DEVADD4)
#define DEVADD5_1 (USB201.DEVADD5)
#define DEVADD6_1 (USB201.DEVADD6)
#define DEVADD7_1 (USB201.DEVADD7)
#define DEVADD8_1 (USB201.DEVADD8)
#define DEVADD9_1 (USB201.DEVADD9)
#define DEVADDA_1 (USB201.DEVADDA)
#define SUSPMODE_1 (USB201.SUSPMODE)
#define D0FIFOB0_1 (USB201.D0FIFOB0)
#define D0FIFOB1_1 (USB201.D0FIFOB1)
#define D0FIFOB2_1 (USB201.D0FIFOB2)
#define D0FIFOB3_1 (USB201.D0FIFOB3)
#define D0FIFOB4_1 (USB201.D0FIFOB4)
#define D0FIFOB5_1 (USB201.D0FIFOB5)
#define D0FIFOB6_1 (USB201.D0FIFOB6)
#define D0FIFOB7_1 (USB201.D0FIFOB7)
#define D1FIFOB0_1 (USB201.D1FIFOB0)
#define D1FIFOB1_1 (USB201.D1FIFOB1)
#define D1FIFOB2_1 (USB201.D1FIFOB2)
#define D1FIFOB3_1 (USB201.D1FIFOB3)
#define D1FIFOB4_1 (USB201.D1FIFOB4)
#define D1FIFOB5_1 (USB201.D1FIFOB5)
#define D1FIFOB6_1 (USB201.D1FIFOB6)
#define D1FIFOB7_1 (USB201.D1FIFOB7)
#define USB20_D0FBCFG_COUNT (2)
#define USB20_D0FIFO_COUNT (2)
#define USB20_INTENB0_COUNT (2)
#define USB20_INTSTS0_COUNT (2)
#define USB20_PIPE1CTR_COUNT (0xF)
#define USB20_DEVADD0_COUNT (0xB)
#define USB20_D0FIFOB0_COUNT (0x8)
typedef struct st_usb20
{
/* USB20 */
volatile uint16_t SYSCFG0; /* SYSCFG0 */
volatile uint16_t BUSWAIT; /* BUSWAIT */
volatile uint16_t SYSSTS0; /* SYSSTS0 */
@ -40,26 +385,33 @@ struct st_usb20
volatile uint8_t dummy2[2]; /* */
volatile uint16_t TESTMODE; /* TESTMODE */
volatile uint8_t dummy3[2]; /* */
#define USB20_D0FBCFG_COUNT 2
/* #define USB20_D0FBCFG_COUNT (2) */
volatile uint16_t D0FBCFG; /* D0FBCFG */
volatile uint16_t D1FBCFG; /* D1FBCFG */
union iodefine_reg32_t CFIFO; /* CFIFO */
#define USB20_D0FIFO_COUNT 2
/* #define USB20_D0FIFO_COUNT (2) */
union iodefine_reg32_t D0FIFO; /* D0FIFO */
union iodefine_reg32_t D1FIFO; /* D1FIFO */
volatile uint16_t CFIFOSEL; /* CFIFOSEL */
volatile uint16_t CFIFOCTR; /* CFIFOCTR */
volatile uint8_t dummy4[4]; /* */
/* start of struct st_usb20_from_d0fifosel */
volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
/* end of struct st_usb20_from_d0fifosel */
/* start of struct st_usb20_from_d0fifosel */
volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */
volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */
/* end of struct st_usb20_from_d0fifosel */
#define USB20_INTENB0_COUNT 2
/* #define USB20_INTENB0_COUNT (2) */
volatile uint16_t INTENB0; /* INTENB0 */
volatile uint16_t INTENB1; /* INTENB1 */
volatile uint8_t dummy5[2]; /* */
@ -68,7 +420,8 @@ struct st_usb20
volatile uint16_t BEMPENB; /* BEMPENB */
volatile uint16_t SOFCFG; /* SOFCFG */
volatile uint8_t dummy6[2]; /* */
#define USB20_INTSTS0_COUNT 2
/* #define USB20_INTSTS0_COUNT (2) */
volatile uint16_t INTSTS0; /* INTSTS0 */
volatile uint16_t INTSTS1; /* INTSTS1 */
volatile uint8_t dummy7[2]; /* */
@ -93,7 +446,8 @@ struct st_usb20
volatile uint16_t PIPEBUF; /* PIPEBUF */
volatile uint16_t PIPEMAXP; /* PIPEMAXP */
volatile uint16_t PIPEPERI; /* PIPEPERI */
#define USB20_PIPE1CTR_COUNT 0xF
/* #define USB20_PIPE1CTR_COUNT (0xF) */
volatile uint16_t PIPE1CTR; /* PIPE1CTR */
volatile uint16_t PIPE2CTR; /* PIPE2CTR */
volatile uint16_t PIPE3CTR; /* PIPE3CTR */
@ -110,25 +464,35 @@ struct st_usb20
volatile uint16_t PIPEECTR; /* PIPEECTR */
volatile uint16_t PIPEFCTR; /* PIPEFCTR */
volatile uint8_t dummy11[2]; /* */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE1TRE; /* PIPE1TRE */
volatile uint16_t PIPE1TRN; /* PIPE1TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE2TRE; /* PIPE2TRE */
volatile uint16_t PIPE2TRN; /* PIPE2TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE3TRE; /* PIPE3TRE */
volatile uint16_t PIPE3TRN; /* PIPE3TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE4TRE; /* PIPE4TRE */
volatile uint16_t PIPE4TRN; /* PIPE4TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE5TRE; /* PIPE5TRE */
volatile uint16_t PIPE5TRN; /* PIPE5TRN */
/* end of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPEBTRE; /* PIPEBTRE */
volatile uint16_t PIPEBTRN; /* PIPEBTRN */
@ -145,7 +509,8 @@ struct st_usb20
volatile uint16_t PIPEATRE; /* PIPEATRE */
volatile uint16_t PIPEATRN; /* PIPEATRN */
volatile uint8_t dummy12[16]; /* */
#define USB20_DEVADD0_COUNT 0xB
/* #define USB20_DEVADD0_COUNT (0xB) */
volatile uint16_t DEVADD0; /* DEVADD0 */
volatile uint16_t DEVADD1; /* DEVADD1 */
volatile uint16_t DEVADD2; /* DEVADD2 */
@ -160,6 +525,7 @@ struct st_usb20
volatile uint8_t dummy13[28]; /* */
volatile uint16_t SUSPMODE; /* SUSPMODE */
volatile uint8_t dummy14[92]; /* */
/* start of struct st_usb20_from_dmfifob0 */
volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
@ -169,7 +535,9 @@ struct st_usb20
volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
/* end of struct st_usb20_from_dmfifob0 */
/* start of struct st_usb20_from_dmfifob0 */
volatile uint32_t D1FIFOB0; /* D1FIFOB0 */
volatile uint32_t D1FIFOB1; /* D1FIFOB1 */
@ -179,27 +547,32 @@ struct st_usb20
volatile uint32_t D1FIFOB5; /* D1FIFOB5 */
volatile uint32_t D1FIFOB6; /* D1FIFOB6 */
volatile uint32_t D1FIFOB7; /* D1FIFOB7 */
/* end of struct st_usb20_from_dmfifob0 */
};
} r_io_usb20_t;
struct st_usb20_from_d0fifosel
typedef struct st_usb20_from_d0fifosel
{
volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
};
} r_io_usb20_from_d0fifosel_t;
struct st_usb20_from_pipe1tre
typedef struct st_usb20_from_pipe1tre
{
volatile uint16_t PIPE1TRE; /* PIPE1TRE */
volatile uint16_t PIPE1TRN; /* PIPE1TRN */
};
} r_io_usb20_from_pipe1tre_t;
struct st_usb20_from_dmfifob0
typedef struct st_usb20_from_dmfifob0
{
#define USB20_D0FIFOB0_COUNT 0x8
/* #define USB20_D0FIFOB0_COUNT (0x8) */
volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
@ -208,339 +581,42 @@ struct st_usb20_from_dmfifob0
volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
};
} r_io_usb20_from_dmfifob0_t;
#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */
#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */
/* Channel array defines of USB20 (2)*/
#ifdef DECLARE_USB20_CHANNELS
volatile struct st_usb20* USB20[ USB20_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_CHANNELS */
#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS
volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_FROM_D0FIFOB0_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */
#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS
volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_FROM_PIPE1ATRE_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */
#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS
volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_FROM_D0FIFOSEL_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */
/* End of channel array defines of USB20 (2)*/
/* Start of channnel array defines of USB20 */
/* Channnel array defines of USB20 */
/*(Sample) value = USB20[ channel ]->SYSCFG0; */
#define USB20_COUNT 2
#define USB20_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&USB200, &USB201 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* Channnel array defines of USB20_FROM_D0FIFOB0 */
/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
#define USB20_FROM_D0FIFOB0_COUNT 2
#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
&USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
/* Channnel array defines of USB20_FROM_PIPE1ATRE */
/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
#define USB20_FROM_PIPE1ATRE_COUNT 5
#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
&USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
/* Channnel array defines of USB20_FROM_D0FIFOSEL */
/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
#define USB20_FROM_D0FIFOSEL_COUNT 2
#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
&USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
/* End of channnel array defines of USB20 */
#define SYSCFG0_0 USB200.SYSCFG0
#define BUSWAIT_0 USB200.BUSWAIT
#define SYSSTS0_0 USB200.SYSSTS0
#define DVSTCTR0_0 USB200.DVSTCTR0
#define TESTMODE_0 USB200.TESTMODE
#define D0FBCFG_0 USB200.D0FBCFG
#define D1FBCFG_0 USB200.D1FBCFG
#define CFIFO_0 USB200.CFIFO.UINT32
#define CFIFO_0L USB200.CFIFO.UINT16[L]
#define CFIFO_0H USB200.CFIFO.UINT16[H]
#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
#define D0FIFO_0 USB200.D0FIFO.UINT32
#define D0FIFO_0L USB200.D0FIFO.UINT16[L]
#define D0FIFO_0H USB200.D0FIFO.UINT16[H]
#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
#define D1FIFO_0 USB200.D1FIFO.UINT32
#define D1FIFO_0L USB200.D1FIFO.UINT16[L]
#define D1FIFO_0H USB200.D1FIFO.UINT16[H]
#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
#define CFIFOSEL_0 USB200.CFIFOSEL
#define CFIFOCTR_0 USB200.CFIFOCTR
#define D0FIFOSEL_0 USB200.D0FIFOSEL
#define D0FIFOCTR_0 USB200.D0FIFOCTR
#define D1FIFOSEL_0 USB200.D1FIFOSEL
#define D1FIFOCTR_0 USB200.D1FIFOCTR
#define INTENB0_0 USB200.INTENB0
#define INTENB1_0 USB200.INTENB1
#define BRDYENB_0 USB200.BRDYENB
#define NRDYENB_0 USB200.NRDYENB
#define BEMPENB_0 USB200.BEMPENB
#define SOFCFG_0 USB200.SOFCFG
#define INTSTS0_0 USB200.INTSTS0
#define INTSTS1_0 USB200.INTSTS1
#define BRDYSTS_0 USB200.BRDYSTS
#define NRDYSTS_0 USB200.NRDYSTS
#define BEMPSTS_0 USB200.BEMPSTS
#define FRMNUM_0 USB200.FRMNUM
#define UFRMNUM_0 USB200.UFRMNUM
#define USBADDR_0 USB200.USBADDR
#define USBREQ_0 USB200.USBREQ
#define USBVAL_0 USB200.USBVAL
#define USBINDX_0 USB200.USBINDX
#define USBLENG_0 USB200.USBLENG
#define DCPCFG_0 USB200.DCPCFG
#define DCPMAXP_0 USB200.DCPMAXP
#define DCPCTR_0 USB200.DCPCTR
#define PIPESEL_0 USB200.PIPESEL
#define PIPECFG_0 USB200.PIPECFG
#define PIPEBUF_0 USB200.PIPEBUF
#define PIPEMAXP_0 USB200.PIPEMAXP
#define PIPEPERI_0 USB200.PIPEPERI
#define PIPE1CTR_0 USB200.PIPE1CTR
#define PIPE2CTR_0 USB200.PIPE2CTR
#define PIPE3CTR_0 USB200.PIPE3CTR
#define PIPE4CTR_0 USB200.PIPE4CTR
#define PIPE5CTR_0 USB200.PIPE5CTR
#define PIPE6CTR_0 USB200.PIPE6CTR
#define PIPE7CTR_0 USB200.PIPE7CTR
#define PIPE8CTR_0 USB200.PIPE8CTR
#define PIPE9CTR_0 USB200.PIPE9CTR
#define PIPEACTR_0 USB200.PIPEACTR
#define PIPEBCTR_0 USB200.PIPEBCTR
#define PIPECCTR_0 USB200.PIPECCTR
#define PIPEDCTR_0 USB200.PIPEDCTR
#define PIPEECTR_0 USB200.PIPEECTR
#define PIPEFCTR_0 USB200.PIPEFCTR
#define PIPE1TRE_0 USB200.PIPE1TRE
#define PIPE1TRN_0 USB200.PIPE1TRN
#define PIPE2TRE_0 USB200.PIPE2TRE
#define PIPE2TRN_0 USB200.PIPE2TRN
#define PIPE3TRE_0 USB200.PIPE3TRE
#define PIPE3TRN_0 USB200.PIPE3TRN
#define PIPE4TRE_0 USB200.PIPE4TRE
#define PIPE4TRN_0 USB200.PIPE4TRN
#define PIPE5TRE_0 USB200.PIPE5TRE
#define PIPE5TRN_0 USB200.PIPE5TRN
#define PIPEBTRE_0 USB200.PIPEBTRE
#define PIPEBTRN_0 USB200.PIPEBTRN
#define PIPECTRE_0 USB200.PIPECTRE
#define PIPECTRN_0 USB200.PIPECTRN
#define PIPEDTRE_0 USB200.PIPEDTRE
#define PIPEDTRN_0 USB200.PIPEDTRN
#define PIPEETRE_0 USB200.PIPEETRE
#define PIPEETRN_0 USB200.PIPEETRN
#define PIPEFTRE_0 USB200.PIPEFTRE
#define PIPEFTRN_0 USB200.PIPEFTRN
#define PIPE9TRE_0 USB200.PIPE9TRE
#define PIPE9TRN_0 USB200.PIPE9TRN
#define PIPEATRE_0 USB200.PIPEATRE
#define PIPEATRN_0 USB200.PIPEATRN
#define DEVADD0_0 USB200.DEVADD0
#define DEVADD1_0 USB200.DEVADD1
#define DEVADD2_0 USB200.DEVADD2
#define DEVADD3_0 USB200.DEVADD3
#define DEVADD4_0 USB200.DEVADD4
#define DEVADD5_0 USB200.DEVADD5
#define DEVADD6_0 USB200.DEVADD6
#define DEVADD7_0 USB200.DEVADD7
#define DEVADD8_0 USB200.DEVADD8
#define DEVADD9_0 USB200.DEVADD9
#define DEVADDA_0 USB200.DEVADDA
#define SUSPMODE_0 USB200.SUSPMODE
#define D0FIFOB0_0 USB200.D0FIFOB0
#define D0FIFOB1_0 USB200.D0FIFOB1
#define D0FIFOB2_0 USB200.D0FIFOB2
#define D0FIFOB3_0 USB200.D0FIFOB3
#define D0FIFOB4_0 USB200.D0FIFOB4
#define D0FIFOB5_0 USB200.D0FIFOB5
#define D0FIFOB6_0 USB200.D0FIFOB6
#define D0FIFOB7_0 USB200.D0FIFOB7
#define D1FIFOB0_0 USB200.D1FIFOB0
#define D1FIFOB1_0 USB200.D1FIFOB1
#define D1FIFOB2_0 USB200.D1FIFOB2
#define D1FIFOB3_0 USB200.D1FIFOB3
#define D1FIFOB4_0 USB200.D1FIFOB4
#define D1FIFOB5_0 USB200.D1FIFOB5
#define D1FIFOB6_0 USB200.D1FIFOB6
#define D1FIFOB7_0 USB200.D1FIFOB7
#define SYSCFG0_1 USB201.SYSCFG0
#define BUSWAIT_1 USB201.BUSWAIT
#define SYSSTS0_1 USB201.SYSSTS0
#define DVSTCTR0_1 USB201.DVSTCTR0
#define TESTMODE_1 USB201.TESTMODE
#define D0FBCFG_1 USB201.D0FBCFG
#define D1FBCFG_1 USB201.D1FBCFG
#define CFIFO_1 USB201.CFIFO.UINT32
#define CFIFO_1L USB201.CFIFO.UINT16[L]
#define CFIFO_1H USB201.CFIFO.UINT16[H]
#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
#define D0FIFO_1 USB201.D0FIFO.UINT32
#define D0FIFO_1L USB201.D0FIFO.UINT16[L]
#define D0FIFO_1H USB201.D0FIFO.UINT16[H]
#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
#define D1FIFO_1 USB201.D1FIFO.UINT32
#define D1FIFO_1L USB201.D1FIFO.UINT16[L]
#define D1FIFO_1H USB201.D1FIFO.UINT16[H]
#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
#define CFIFOSEL_1 USB201.CFIFOSEL
#define CFIFOCTR_1 USB201.CFIFOCTR
#define D0FIFOSEL_1 USB201.D0FIFOSEL
#define D0FIFOCTR_1 USB201.D0FIFOCTR
#define D1FIFOSEL_1 USB201.D1FIFOSEL
#define D1FIFOCTR_1 USB201.D1FIFOCTR
#define INTENB0_1 USB201.INTENB0
#define INTENB1_1 USB201.INTENB1
#define BRDYENB_1 USB201.BRDYENB
#define NRDYENB_1 USB201.NRDYENB
#define BEMPENB_1 USB201.BEMPENB
#define SOFCFG_1 USB201.SOFCFG
#define INTSTS0_1 USB201.INTSTS0
#define INTSTS1_1 USB201.INTSTS1
#define BRDYSTS_1 USB201.BRDYSTS
#define NRDYSTS_1 USB201.NRDYSTS
#define BEMPSTS_1 USB201.BEMPSTS
#define FRMNUM_1 USB201.FRMNUM
#define UFRMNUM_1 USB201.UFRMNUM
#define USBADDR_1 USB201.USBADDR
#define USBREQ_1 USB201.USBREQ
#define USBVAL_1 USB201.USBVAL
#define USBINDX_1 USB201.USBINDX
#define USBLENG_1 USB201.USBLENG
#define DCPCFG_1 USB201.DCPCFG
#define DCPMAXP_1 USB201.DCPMAXP
#define DCPCTR_1 USB201.DCPCTR
#define PIPESEL_1 USB201.PIPESEL
#define PIPECFG_1 USB201.PIPECFG
#define PIPEBUF_1 USB201.PIPEBUF
#define PIPEMAXP_1 USB201.PIPEMAXP
#define PIPEPERI_1 USB201.PIPEPERI
#define PIPE1CTR_1 USB201.PIPE1CTR
#define PIPE2CTR_1 USB201.PIPE2CTR
#define PIPE3CTR_1 USB201.PIPE3CTR
#define PIPE4CTR_1 USB201.PIPE4CTR
#define PIPE5CTR_1 USB201.PIPE5CTR
#define PIPE6CTR_1 USB201.PIPE6CTR
#define PIPE7CTR_1 USB201.PIPE7CTR
#define PIPE8CTR_1 USB201.PIPE8CTR
#define PIPE9CTR_1 USB201.PIPE9CTR
#define PIPEACTR_1 USB201.PIPEACTR
#define PIPEBCTR_1 USB201.PIPEBCTR
#define PIPECCTR_1 USB201.PIPECCTR
#define PIPEDCTR_1 USB201.PIPEDCTR
#define PIPEECTR_1 USB201.PIPEECTR
#define PIPEFCTR_1 USB201.PIPEFCTR
#define PIPE1TRE_1 USB201.PIPE1TRE
#define PIPE1TRN_1 USB201.PIPE1TRN
#define PIPE2TRE_1 USB201.PIPE2TRE
#define PIPE2TRN_1 USB201.PIPE2TRN
#define PIPE3TRE_1 USB201.PIPE3TRE
#define PIPE3TRN_1 USB201.PIPE3TRN
#define PIPE4TRE_1 USB201.PIPE4TRE
#define PIPE4TRN_1 USB201.PIPE4TRN
#define PIPE5TRE_1 USB201.PIPE5TRE
#define PIPE5TRN_1 USB201.PIPE5TRN
#define PIPEBTRE_1 USB201.PIPEBTRE
#define PIPEBTRN_1 USB201.PIPEBTRN
#define PIPECTRE_1 USB201.PIPECTRE
#define PIPECTRN_1 USB201.PIPECTRN
#define PIPEDTRE_1 USB201.PIPEDTRE
#define PIPEDTRN_1 USB201.PIPEDTRN
#define PIPEETRE_1 USB201.PIPEETRE
#define PIPEETRN_1 USB201.PIPEETRN
#define PIPEFTRE_1 USB201.PIPEFTRE
#define PIPEFTRN_1 USB201.PIPEFTRN
#define PIPE9TRE_1 USB201.PIPE9TRE
#define PIPE9TRN_1 USB201.PIPE9TRN
#define PIPEATRE_1 USB201.PIPEATRE
#define PIPEATRN_1 USB201.PIPEATRN
#define DEVADD0_1 USB201.DEVADD0
#define DEVADD1_1 USB201.DEVADD1
#define DEVADD2_1 USB201.DEVADD2
#define DEVADD3_1 USB201.DEVADD3
#define DEVADD4_1 USB201.DEVADD4
#define DEVADD5_1 USB201.DEVADD5
#define DEVADD6_1 USB201.DEVADD6
#define DEVADD7_1 USB201.DEVADD7
#define DEVADD8_1 USB201.DEVADD8
#define DEVADD9_1 USB201.DEVADD9
#define DEVADDA_1 USB201.DEVADDA
#define SUSPMODE_1 USB201.SUSPMODE
#define D0FIFOB0_1 USB201.D0FIFOB0
#define D0FIFOB1_1 USB201.D0FIFOB1
#define D0FIFOB2_1 USB201.D0FIFOB2
#define D0FIFOB3_1 USB201.D0FIFOB3
#define D0FIFOB4_1 USB201.D0FIFOB4
#define D0FIFOB5_1 USB201.D0FIFOB5
#define D0FIFOB6_1 USB201.D0FIFOB6
#define D0FIFOB7_1 USB201.D0FIFOB7
#define D1FIFOB0_1 USB201.D1FIFOB0
#define D1FIFOB1_1 USB201.D1FIFOB1
#define D1FIFOB2_1 USB201.D1FIFOB2
#define D1FIFOB3_1 USB201.D1FIFOB3
#define D1FIFOB4_1 USB201.D1FIFOB4
#define D1FIFOB5_1 USB201.D1FIFOB5
#define D1FIFOB6_1 USB201.D1FIFOB6
#define D1FIFOB7_1 USB201.D1FIFOB7
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

2172
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h
View File

File diff suppressed because it is too large Load Diff

37
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h
View File

@ -18,29 +18,40 @@
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : wdt_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register (V1.00a)
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef WDT_IODEFINE_H
#define WDT_IODEFINE_H
struct st_wdt
{ /* WDT */
volatile uint16_t WTCSR; /* WTCSR */
volatile uint16_t WTCNT; /* WTCNT */
volatile uint16_t WRCSR; /* WRCSR */
};
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */
#define WDTWTCSR WDT.WTCSR
#define WDTWTCNT WDT.WTCNT
#define WDTWRCSR WDT.WRCSR
#define WDTWTCSR (WDT.WTCSR)
#define WDTWTCNT (WDT.WTCNT)
#define WDTWRCSR (WDT.WRCSR)
typedef struct st_wdt
{
/* WDT */
volatile uint16_t WTCSR; /* WTCSR */
volatile uint16_t WTCNT; /* WTCNT */
volatile uint16_t WRCSR; /* WRCSR */
} r_io_wdt_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

243
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c
View File

@ -1,243 +0,0 @@
/**************************************************************************//**
* @file mmu_Renesas_RZ_A1.c
* @brief MMU Startup File for
* mmu_Renesas_RZ_A1 Device Series
* @version V1.01
* @date 2 Aug 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors place all memory in domain 0
//There are no restrictions by privilege level (PL0 can access all memory)
#include <stdint.h>
#include "VKRZA1H.h"
//Import symbols from linker
extern uint32_t Image$$VECTORS$$Base;
extern uint32_t Image$$RO_DATA$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$ZI_DATA$$Base;
#if !defined ( __ICCARM__ )
extern uint32_t Image$$TTB$$ZI$$Base;
#endif
#if defined( __CC_ARM )
#elif defined( __ICCARM__ )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
extern uint32_t Image$$ZI_DATA_NC$$Base;
#endif
extern uint32_t Image$$VECTORS$$Limit;
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$ZI_DATA$$Limit;
#if defined( __CC_ARM )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
#endif
#if defined( __ICCARM__ )
#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
#define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
#else
#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
#endif
#if defined( __CC_ARM )
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
#endif
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
#if defined ( __ICCARM__ )
__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
uint32_t Image$$VECTORS$$Base;
uint32_t Image$$RO_DATA$$Base;
uint32_t Image$$RW_DATA$$Base;
uint32_t Image$$ZI_DATA$$Base;
uint32_t Image$$VECTORS$$Limit;
uint32_t Image$$RO_DATA$$Limit;
uint32_t Image$$RW_DATA$$Limit;
uint32_t Image$$ZI_DATA$$Limit;
#endif
void create_translation_table(void)
{
mmu_region_attributes_Type region;
#if defined ( __ICCARM__ )
#pragma section=".intvec"
#pragma section=".rodata"
#pragma section=".rwdata"
#pragma section=".bss"
Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");
Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
#endif
/*
* Generate descriptors. Refer to VKRZA1H.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
section_normal_nc(Sect_Normal_NC, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Create 4GB of faulting entries
__TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
// R7S72100 memory map.
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
#if defined( __ICCARM__ )
//Define Image
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
#else
//Define Image
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
#endif
#if defined( __CC_ARM )
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
__TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC);
#else
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
__TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
#endif
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x0 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x1 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x1 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
}
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

281
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c Normal file
View File

@ -0,0 +1,281 @@
/**************************************************************************//**
* @file mmu_VK_RZ_A1H.c
* @brief MMU Configuration for RZ_A1H Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
Memory Type
0xffffffff |--------------------------| ------------
| Peripherals | Device
0xfcf00000 |--------------------------| ------------
| Page Fault | Fault
0xe8300000 |--------------------------| ------------
| Peripherals | Device
0xe8000000 |--------------------------| ------------
| Page Fault | Fault
0x60A00000 |--------------------------| ------------
| On Chip RAM (10M) Mirror | Fault
0x60000000 |--------------------------| ------------
| SPI multi I/O 64MB | Fault
0x5c000000 |--------------------------| ------------
| SPI multi I/O 64MB | Fault
0x58000000 |--------------------------| ------------
| CS5 Mirror | Fault
0x54000000 |--------------------------| ------------
| CS4 Mirror | Fault
0x50000000 |--------------------------| ------------
| CS3 Mirror | Fault
0x4c000000 |--------------------------| ------------
| CS2 Mirror | Fault
0x48000000 |--------------------------| ------------
| CS1 Mirror | Fault
0x44000000 |--------------------------| ------------
| CS0 Mirror | Fault
0x40000000 |--------------------------| ------------
| BSC | RW
0x3ff00000 |--------------------------| ------------
| SPI_MIO_BASE | RW
0x3fe00000 |--------------------------| ------------
| Page Fault | Fault
0x20A00000 |--------------------------| ------------
| On Chip RAM (10M) | RW
0x20000000 |--------------------------| ------------
| SPI multi I/O 64MB | RO
0x1c000000 |--------------------------| ------------
| SPI multi I/O 64MB | RO
0x18000000 |--------------------------| ------------
| CS5 User Area 64MB | RW
0x14000000 |--------------------------| ------------
| CS4 User Area 64MB | RW
0x10000000 |--------------------------| ------------
| CS3 SDRAM 64MB | RW
0x0c000000 |--------------------------| ------------
| CS2 SDRAM 64MB | RW
0x08000000 |--------------------------| ------------
| CS1 NOR Flash 64MB | RO
0x04000000 |--------------------------| ------------
| CS0 NOR Flash 64MB | RO
0x00000000 |--------------------------| ------------
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors should place all memory in domain 0
//There are no restrictions by privilege level (PL0 can access all memory)
#include "VK_RZ_A1H.h"
//Import symbols from linker
extern uint32_t Image$$VECTORS$$Base;
extern uint32_t Image$$RO_DATA$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$RW_IRAM1$$Base;
#if !defined ( __ICCARM__ )
extern uint32_t Image$$TTB$$ZI$$Base;
#endif
#if defined( __CC_ARM )
#elif defined( __ICCARM__ )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
extern uint32_t Image$$ZI_DATA_NC$$Base;
#endif
extern uint32_t Image$$VECTORS$$Limit;
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$RW_IRAM1$$Limit;
#if defined( __CC_ARM )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
#endif
#if defined( __ICCARM__ )
#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
#else
#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
#endif
#if defined( __CC_ARM )
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
#endif
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
#if defined ( __ICCARM__ )
__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
uint32_t Image$$VECTORS$$Base;
uint32_t Image$$RO_DATA$$Base;
uint32_t Image$$RW_DATA$$Base;
uint32_t Image$$RW_IRAM1$$Base;
uint32_t Image$$VECTORS$$Limit;
uint32_t Image$$RO_DATA$$Limit;
uint32_t Image$$RW_DATA$$Limit;
uint32_t Image$$RW_IRAM1$$Limit;
#endif
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
#if defined ( __ICCARM__ )
#pragma section=".intvec"
#pragma section=".rodata"
#pragma section=".rwdata"
#pragma section=".bss"
Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");
Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
#endif
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
section_normal_nc(Sect_Normal_NC, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Create 4GB of faulting entries
MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
// R7S72100 memory map.
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
#if defined( __ICCARM__ )
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#else
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#endif
#if defined( __CC_ARM )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#else
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
#endif
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x0 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x1 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x1 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}

9
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c
View File

@ -33,7 +33,6 @@ Includes <System Includes> , "Project Includes"
#include "VKRZA1H.h"
#include "wdt_iodefine.h"
#include "nvic_wrapper.h"
#include "gic.h"
/******************************************************************************
Typedef definitions
@ -71,7 +70,7 @@ void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
uint32_t NVIC_GetPriorityGrouping(void)
{
return GIC_GetBinaryPoint(0);
return GIC_GetBinaryPoint();
}
@ -214,14 +213,16 @@ uint32_t ITM_SendChar (uint32_t ch)
}
int32_t ITM_ReceiveChar (void) {
int32_t ITM_ReceiveChar (void)
{
/* Not support this function */
/* Use mbed Serial */
return (-1); /* no character available */
}
int32_t ITM_CheckChar (void) {
int32_t ITM_CheckChar (void)
{
/* Not support this function */
/* Use mbed Serial */
return (0); /* no character available */

201
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c Normal file
View File

@ -0,0 +1,201 @@
/**************************************************************************//**
* @file os_tick_ostm.c
* @brief CMSIS OS Tick implementation for OS Timer
* @version V1.0.1
* @date 19. September 2017
******************************************************************************/
/*
* Copyright (c) 2017-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifdef MBED_CONF_RTOS_PRESENT
#include "os_tick.h"
#include "irq_ctrl.h"
#include <VKRZA1H.h>
#include <cmsis.h>
// Define OS TImer interrupt priority
#ifndef OSTM_IRQ_PRIORITY
#define OSTM_IRQ_PRIORITY 0xFFU
#endif
// Define OS Timer channel and interrupt number
#define OSTM (OSTM0)
#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn)
static uint32_t OSTM_Clock; // Timer tick frequency
static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag
// Setup OS Tick.
int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
{
uint32_t clock;
uint32_t prio;
uint32_t bits;
if (freq == 0U) {
return (-1);
}
OSTM_PendIRQ = 0U;
// Get CPG.FRQCR[IFC] bits
clock = (CPG.FRQCR >> 8) & 0x03;
// Determine Divider 2 output clock by using SystemCoreClock
if (clock == 0x03U) {
clock = (SystemCoreClock * 3U);
}
else if (clock == 0x01U) {
clock = (SystemCoreClock * 3U)/2U;
}
else {
clock = SystemCoreClock;
}
// Determine tick frequency
clock = clock / freq;
// Save frequency for later
OSTM_Clock = clock;
// Enable OSTM clock
CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51);
// Stop the OSTM counter
OSTM.OSTMnTT = 0x01U;
// Set interval timer mode and disable interrupts when counting starts
OSTM.OSTMnCTL = 0x00U;
// Set compare value
OSTM.OSTMnCMP = clock - 1U;
// Disable corresponding IRQ
IRQ_Disable (OSTM_IRQn);
IRQ_ClearPending(OSTM_IRQn);
// Determine number of implemented priority bits
IRQ_SetPriority (OSTM_IRQn, 0xFFU);
prio = IRQ_GetPriority (OSTM_IRQn);
// At least bits [7:4] must be implemented
if ((prio & 0xF0U) == 0U) {
return (-1);
}
for (bits = 0; bits < 4; bits++) {
if ((prio & 0x01) != 0) {
break;
}
prio >>= 1;
}
// Adjust configured priority to the number of implemented priority bits
prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL;
// Set OSTM interrupt priority
IRQ_SetPriority(OSTM_IRQn, prio-1U);
// Set edge-triggered, non-secure, single CPU targeted IRQ
IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE);
// Register tick interrupt handler function
IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler);
// Enable corresponding IRQ
IRQ_Enable (OSTM_IRQn);
return (0);
}
/// Enable OS Tick.
int32_t OS_Tick_Enable (void)
{
if (OSTM_PendIRQ != 0U) {
OSTM_PendIRQ = 0U;
IRQ_SetPending (OSTM_IRQn);
}
// Start the OSTM counter
OSTM.OSTMnTS = 0x01U;
return (0);
}
/// Disable OS Tick.
int32_t OS_Tick_Disable (void)
{
// Stop the OSTM counter
OSTM.OSTMnTT = 0x01U;
if (IRQ_GetPending(OSTM_IRQn) != 0) {
IRQ_ClearPending (OSTM_IRQn);
OSTM_PendIRQ = 1U;
}
return (0);
}
// Acknowledge OS Tick IRQ.
int32_t OS_Tick_AcknowledgeIRQ (void)
{
return (IRQ_ClearPending (OSTM_IRQn));
}
// Get OS Tick IRQ number.
int32_t OS_Tick_GetIRQn (void)
{
return (OSTM_IRQn);
}
// Get OS Tick clock.
uint32_t OS_Tick_GetClock (void)
{
return (OSTM_Clock);
}
// Get OS Tick interval.
uint32_t OS_Tick_GetInterval (void)
{
return (OSTM.OSTMnCMP + 1U);
}
// Get OS Tick count value.
uint32_t OS_Tick_GetCount (void)
{
uint32_t cmp = OSTM.OSTMnCMP;
return (cmp - OSTM.OSTMnCNT);
}
// Get OS Tick overflow status.
uint32_t OS_Tick_GetOverflow (void)
{
return (IRQ_GetPending(OSTM_IRQn));
}
#endif

128
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c
View File

@ -1,128 +0,0 @@
/**************************************************************************//**
* @file pl310.c
* @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions
* @version
* @date 3 December 2014
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "VKRZA1H.h"
//Cache Sync operation
void PL310_Sync(void)
{
PL310->CACHE_SYNC = 0x0;
}
//return Cache controller cache ID
int PL310_GetID (void)
{
return PL310->CACHE_ID;
}
//return Cache controller cache Type
int PL310_GetType (void)
{
return PL310->CACHE_TYPE;
}
//Invalidate all cache by way
void PL310_InvAllByWay (void)
{
unsigned int assoc;
if (PL310->AUX_CNT & (1<<16))
assoc = 16;
else
assoc = 8;
PL310->INV_WAY = (1 << assoc) - 1;
while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
PL310_Sync();
}
//Clean and Invalidate all cache by way
void PL310_CleanInvAllByWay (void)
{
unsigned int assoc;
if (PL310->AUX_CNT & (1<<16))
assoc = 16;
else
assoc = 8;
PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
PL310_Sync();
}
//Enable Cache
void PL310_Enable(void)
{
PL310->CONTROL = 0;
PL310->INTERRUPT_CLEAR = 0x000001FFuL;
PL310->DEBUG_CONTROL = 0;
PL310->DATA_LOCK_0_WAY = 0;
PL310->CACHE_SYNC = 0;
PL310->CONTROL = 0x01;
PL310_Sync();
}
//Disable Cache
void PL310_Disable(void)
{
PL310->CONTROL = 0x00;
PL310_Sync();
}
//Invalidate cache by physical address
void PL310_InvPa (void *pa)
{
PL310->INV_LINE_PA = (unsigned int)pa;
PL310_Sync();
}
//Clean cache by physical address
void PL310_CleanPa (void *pa)
{
PL310->CLEAN_LINE_PA = (unsigned int)pa;
PL310_Sync();
}
//Clean and invalidate cache by physical address
void PL310_CleanInvPa (void *pa)
{
PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
PL310_Sync();
}

114
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h
View File

@ -1,114 +0,0 @@
/**************************************************************************//**
* @file pl310.h
* @brief Implementation of pl310 functions
* @version
* @date 11 June 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __PL310
#define __PL310
typedef struct
{
__I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */
__I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */
uint32_t RESERVED0[0x3e];
__IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */
__IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */
uint32_t RESERVED1[0x3e];
__IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */
__IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */
__IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */
uint32_t RESERVED2[0x2];
__IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */
__I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */
__I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */
__O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */
uint32_t RESERVED3[0x143];
__IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */
uint32_t RESERVED4[0xf];
__IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */
uint32_t RESERVED6[2];
__IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */
uint32_t RESERVED5[0xc];
__IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */
uint32_t RESERVED7[1];
__IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */
__IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */
uint32_t RESERVED8[0xc];
__IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */
uint32_t RESERVED9[1];
__IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */
__IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */
uint32_t RESERVED10[0x40];
__IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */
__IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */
__IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */
__IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */
__IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */
__IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */
__IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */
__IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */
__IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */
__IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */
__IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */
__IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */
__IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */
__IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */
__IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */
__IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */
uint32_t RESERVED11[0x4];
__IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */
__IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */
uint32_t RESERVED12[0xaa];
__IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */
__IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */
uint32_t RESERVED13[0xce];
__IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */
} PL310_TypeDef;
#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
extern int PL310_GetID (void);
extern int PL310_GetType (void);
extern void PL310_InvAllByWay (void);
extern void PL310_CleanInvAllByWay(void);
extern void PL310_Enable(void);
extern void PL310_Disable(void);
extern void PL310_InvPa (void *);
extern void PL310_CleanPa (void *);
extern void PL310_CleanInvPa (void *);
#endif

521
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c
View File

@ -1,521 +0,0 @@
/**************************************************************************//**
* @file system_VKRZA1H.c
* @brief CMSIS Device System Source File for
* ARM Cortex-A9 Device Series
* @version V1.00
* @date 09 January 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include <stdint.h>
#include "VKRZA1H.h"
#include "RZ_A1_Init.h"
#if defined(__ARMCC_VERSION)
extern void $Super$$main(void);
__asm void FPUEnable(void);
#else
void FPUEnable(void);
#endif
#define FRQCR_IFC_MSK (0x0030)
#define FRQCR_IFC_SHFT (8)
#define FRQCR_IFC_1P1 (0) /* x1/1 */
#define FRQCR_IFC_2P3 (1) /* x2/3 */
#define FRQCR_IFC_1P3 (3) /* x1/3 */
uint32_t IRQNestLevel;
unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the cache.
*
* @param none
* @return none
*
* @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma arm
void InitMemorySubsystem(void) {
/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
* You are not required to invalidate the main TLB, even though it is recommended for safety
* reasons. This ensures compatibility with future revisions of the processor. */
unsigned int l2_id;
/* Invalidate undefined data */
__ca9u_inv_tlb_all();
__v7_inv_icache_all();
__v7_inv_dcache_all();
__v7_inv_btac();
/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
* invalidate in order to flush the valid data to the next level cache.
*/
__enable_mmu();
/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
__enable_caches();
__enable_btac();
/* If present, you may also need to Invalidate and Enable L2 cache here */
l2_id = PL310_GetID();
if (l2_id)
{
PL310_InvAllByWay();
PL310_Enable();
}
}
#pragma pop
#elif defined(__GNUC__)
void InitMemorySubsystem(void) {
/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
* You are not required to invalidate the main TLB, even though it is recommended for safety
* reasons. This ensures compatibility with future revisions of the processor. */
unsigned int l2_id;
/* Invalidate undefined data */
__ca9u_inv_tlb_all();
__v7_inv_icache_all();
__v7_inv_dcache_all();
__v7_inv_btac();
/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
* invalidate in order to flush the valid data to the next level cache.
*/
__enable_mmu();
/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
__enable_caches();
__enable_btac();
/* If present, you may also need to Invalidate and Enable L2 cache here */
l2_id = PL310_GetID();
if (l2_id)
{
PL310_InvAllByWay();
PL310_Enable();
}
}
#elif defined ( __ICCARM__ )
void InitMemorySubsystem(void) {
/* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
* enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
* You are not required to invalidate the main TLB, even though it is recommended for safety
* reasons. This ensures compatibility with future revisions of the processor. */
unsigned int l2_id;
/* Invalidate undefined data */
__ca9u_inv_tlb_all();
__v7_inv_icache_all();
__v7_inv_dcache_all();
__v7_inv_btac();
/* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
* invalidate in order to flush the valid data to the next level cache.
*/
__enable_mmu();
/* After MMU is enabled and data has been invalidated, enable caches and BTAC */
__enable_caches();
__enable_btac();
/* If present, you may also need to Invalidate and Enable L2 cache here */
l2_id = PL310_GetID();
if (l2_id)
{
PL310_InvAllByWay();
PL310_Enable();
}
}
#else
#endif
IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
uint32_t IRQCount = sizeof IRQTable / 4;
uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
{
if (irq < IRQCount) {
IRQTable[irq] = handler;
return 0;
}
else {
return 1;
}
}
uint32_t InterruptHandlerUnregister (IRQn_Type irq)
{
if (irq < IRQCount) {
IRQTable[irq] = 0;
return 0;
}
else {
return 1;
}
}
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock.
*/
void SystemCoreClockUpdate (void)
{
uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
switch (frqcr_ifc) {
case FRQCR_IFC_1P1:
SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
break;
case FRQCR_IFC_2P3:
SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
break;
case FRQCR_IFC_1P3:
SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3;
break;
default:
/* do nothing */
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
IRQNestLevel = 0;
/* do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
RZ_A1_InitClock();
RZ_A1_InitBus();
//Configure GIC ICDICFR GIC_SetICDICFR()
GIC_Enable();
__enable_irq();
}
//Fault Status Register (IFSR/DFSR) definitions
#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
#define FSR_DEBUG_EVENT 0x02 //internal
#define FSR_SYNC_EXT_ABORT 0x08 //sync/external
#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
#define FSR_LOCKDOWN 0x14 //internal
#define FSR_COPROCESSOR_ABORT 0x1a //internal
#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in DFAR is invalid for some fault statuses.
case FSR_ALIGNMENT_FAULT:
case FSR_INSTRUCTION_CACHE_MAINTENANCE:
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISION_FAULT_FIRST:
case FSR_PERMISION_FAULT_SECOND:
case FSR_DEBUG_EVENT:
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
default:
while(1);
}
}
void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
switch(FS) {
//Synchronous parity errors - retry
case FSR_SYNC_PARITY_ERROR:
case FSR_SYNC_PARITY_TTB_WALK_FIRST:
case FSR_SYNC_PARITY_TTB_WALK_SECOND:
return;
//Your code here. Value in IFAR is invalid for some fault statuses.
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
case FSR_TRANSLATION_FAULT_SECOND:
case FSR_ACCESS_FLAG_FAULT_FIRST:
case FSR_ACCESS_FLAG_FAULT_SECOND:
case FSR_DOMAIN_FAULT_FIRST:
case FSR_DOMAIN_FAULT_SECOND:
case FSR_PERMISION_FAULT_FIRST:
case FSR_PERMISION_FAULT_SECOND:
case FSR_DEBUG_EVENT: //IFAR invalid
case FSR_SYNC_EXT_ABORT:
case FSR_TLB_CONFLICT_ABORT:
case FSR_LOCKDOWN:
case FSR_COPROCESSOR_ABORT:
default:
while(1);
}
}
//returns amount to decrement lr by
//this will be 0 when we have emulated the instruction and want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const unsigned int THUMB = 2;
const unsigned int ARM = 4;
//Lazy VFP/NEON initialisation and switching
// (ARM ARM section A7.5) VFP data processing instruction?
// (ARM ARM section A7.6) VFP/NEON register load/store instruction?
// (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
// (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
(state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
if (((opcode & 0x00000E00) >> 9) == 5) {
FPUEnable();
return state;
}
}
// (ARM ARM section A7.4) NEON data processing instruction?
if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
(state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
// (ARM ARM section A7.7) NEON load/store instruction?
(state == ARM && ((opcode >> 24) == 0xF4)) ||
(state == THUMB && ((opcode >> 24) == 0xF9))) {
FPUEnable();
return state;
}
//Add code here for other Undef cases
while(1);
}
#if defined(__ARMCC_VERSION)
#pragma push
#pragma arm
//Critical section, called from undef handler, so systick is disabled
__asm void FPUEnable(void) {
ARM
//Permit access to VFP/NEON, registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
ISB
//Enable VFP/NEON
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
//Initialise VFP/NEON registers to 0
MOV R2,#0
//Initialise D16 registers to 0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
VMOV D3, R2,R2
VMOV D4, R2,R2
VMOV D5, R2,R2
VMOV D6, R2,R2
VMOV D7, R2,R2
VMOV D8, R2,R2
VMOV D9, R2,R2
VMOV D10,R2,R2
VMOV D11,R2,R2
VMOV D12,R2,R2
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
//Initialise D32 registers to 0
VMOV D16,R2,R2
VMOV D17,R2,R2
VMOV D18,R2,R2
VMOV D19,R2,R2
VMOV D20,R2,R2
VMOV D21,R2,R2
VMOV D22,R2,R2
VMOV D23,R2,R2
VMOV D24,R2,R2
VMOV D25,R2,R2
VMOV D26,R2,R2
VMOV D27,R2,R2
VMOV D28,R2,R2
VMOV D29,R2,R2
VMOV D30,R2,R2
VMOV D31,R2,R2
//Initialise FPSCR to a known state
VMRS R2,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AND R2,R2,R3
VMSR FPSCR,R2
BX LR
}
#pragma pop
#elif defined(__GNUC__)
void FPUEnable(void) {
__asm__ (
".ARM;"
//Permit access to VFP/NEON, registers by modifying CPACR
"MRC p15,0,R1,c1,c0,2;"
"ORR R1,R1,#0x00F00000;"
"MCR p15,0,R1,c1,c0,2;"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
"ISB;"
//Enable VFP/NEON
"VMRS R1,FPEXC;"
"ORR R1,R1,#0x40000000;"
"VMSR FPEXC,R1;"
//Initialise VFP/NEON registers to 0
"MOV R2,#0;"
//Initialise D16 registers to 0
"VMOV D0, R2,R2;"
"VMOV D1, R2,R2;"
"VMOV D2, R2,R2;"
"VMOV D3, R2,R2;"
"VMOV D4, R2,R2;"
"VMOV D5, R2,R2;"
"VMOV D6, R2,R2;"
"VMOV D7, R2,R2;"
"VMOV D8, R2,R2;"
"VMOV D9, R2,R2;"
"VMOV D10,R2,R2;"
"VMOV D11,R2,R2;"
"VMOV D12,R2,R2;"
"VMOV D13,R2,R2;"
"VMOV D14,R2,R2;"
"VMOV D15,R2,R2;"
//Initialise D32 registers to 0
"VMOV D16,R2,R2;"
"VMOV D17,R2,R2;"
"VMOV D18,R2,R2;"
"VMOV D19,R2,R2;"
"VMOV D20,R2,R2;"
"VMOV D21,R2,R2;"
"VMOV D22,R2,R2;"
"VMOV D23,R2,R2;"
"VMOV D24,R2,R2;"
"VMOV D25,R2,R2;"
"VMOV D26,R2,R2;"
"VMOV D27,R2,R2;"
"VMOV D28,R2,R2;"
"VMOV D29,R2,R2;"
"VMOV D30,R2,R2;"
"VMOV D31,R2,R2;"
//Initialise FPSCR to a known state
"VMRS R2,FPSCR;"
"LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
"AND R2,R2,R3;"
"VMSR FPSCR,R2;"
//"BX LR;"
:
:
:"r1", "r2", "r3");
return;
}
#else
#endif

67
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h
View File

@ -1,67 +0,0 @@
/**************************************************************************//**
* @file system_VKRZA1H.h
* @brief CMSIS Device System Header File for
* ARMCA9 Device Series
* @version V1.00
* @date 11 June 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __SYSTEM_VKRZA1H
#define __SYSTEM_VKRZA1H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
typedef void(*IRQHandler)();
uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
uint32_t InterruptHandlerUnregister(IRQn_Type);
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the Systd short int16_t;emCoreClock variable.
*/
extern void SystemInit (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_VKRZA1H */

157
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c Normal file
View File

@ -0,0 +1,157 @@
/******************************************************************************
* @file system_VK_RZ_A1H_H.c
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <VK_RZ_A1H.h>
#include "RZ_A1_Init.h"
#include "irq_ctrl.h"
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
/*
Port 0 (P0) MD pin assignment
P0_0: MD_BOOT0
P0_1: MD_BOOT1
P0_2: MD_CLK
P0_3: MD_CLKS
*/
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
uint32_t freq;
uint16_t mode;
uint16_t ifc;
mode = (GPIO.PPR0 >> 2U) & 0x01U;
if (mode == 0) {
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
} else {
/* Clock Mode 1 */
/* CLKIN is 48MHz */
/* Divider 1 uses 1/4 ratio, PLL x32 is ON */
freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
}
/* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U;
/* Determine Divider 2 output clock */
if (ifc == 0x03U) {
/* Division ratio is 1/3 */
freq = (freq / 3U);
}
else {
if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
}
}
SystemCoreClock = freq;
}
/*----------------------------------------------------------------------------
IRQ Handler Register/Unregister
*----------------------------------------------------------------------------*/
uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
{
return IRQ_SetHandler(irq, handler);
}
uint32_t InterruptHandlerUnregister (IRQn_Type irq)
{
return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
}
/*----------------------------------------------------------------------------
System Initialization
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
// Enable SRAM write access
CPG.SYSCR3 = 0x0F;
RZ_A1_InitClock();
RZ_A1_InitBus();
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
L2C_InvAllByWay();
// Enable L2C
L2C_Enable();
#endif
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}

81
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h Normal file
View File

@ -0,0 +1,81 @@
/******************************************************************************
* @file system_VK_RZ_A1H.h
* @brief CMSIS Device System Header File for ARM Cortex-A Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __SYSTEM_VK_RZ_A1H_H
#define __SYSTEM_VK_RZ_A1H_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Interrupt Handler Register.
Registers an Interrupt Handler into the IRQ Table.
*/
extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
/**
\brief Interrupt Handler Unregister.
Unregisters an Interrupt Handler from the IRQ Table.
*/
extern uint32_t InterruptHandlerUnregister(IRQn_Type);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_VK_RZ_A1H_H */

2
targets/TARGET_RENESAS/mbed_rtx.h
View File

@ -18,7 +18,7 @@
#include <stdint.h>
#if defined(TARGET_RZ_A1H) || defined(TARGET_GR_LYCHEE)
#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE)
#define OS_IDLE_THREAD_STACK_SIZE 512
#if defined(__CC_ARM)

4
targets/targets.json
View File

@ -2698,8 +2698,8 @@
},
"VK_RZ_A1H": {
"inherits": ["RZ_A1XX"],
"extra_labels": ["RZA1H", "VKRZA1H"],
"release_versions": []
"extra_labels_add": ["RZA1H", "VKRZA1H"],
"release_versions": ["2", "5"]
},
"GR_LYCHEE": {
"inherits": ["RZ_A1XX"],