From cf8fd20f9bfb539fcb9ac6565edaa0eebc62f836 Mon Sep 17 00:00:00 2001 From: mbedNoobNinja Date: Thu, 1 Mar 2018 16:06:18 +0200 Subject: [PATCH] Enabled os5 support for VK_RZ_A1H & synced with rest Renesas targets ! Mbed-os 5.4.7 was the last unofficial working support for this target. Since Mbed-os 5.6.0, the support is now official and VK_RZ_A1H is now "codebase aligned" with GR_PEACH (RZ_A1H) & GR_LYCHEE (RZ_A1LU) ! --- .../TARGET_MBED_VKRZA1H/reserved_pins.h | 16 + .../TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h | 15 +- .../TARGET_VK_RZ_A1H/device/RZ_A1_Init.c | 2 + .../device/TOOLCHAIN_ARM_STD/VKRZA1H.sct | 64 +- .../device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h | 95 + .../TOOLCHAIN_ARM_STD/startup_VKRZA1H.S | 454 - .../TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c | 162 + .../device/TOOLCHAIN_ARM_STD/sys.cpp | 61 + .../device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld | 78 +- .../TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S | 326 +- .../device/TOOLCHAIN_IAR/VKRZA1H.icf | 5 +- .../device/TOOLCHAIN_IAR/startup_VKRZA1H.S | 339 +- .../TARGET_VK_RZ_A1H/device/VKRZA1H.h | 1076 +- .../TARGET_VK_RZ_A1H/device/cmsis.h | 1 + .../TARGET_VK_RZ_A1H/device/cmsis_nvic.c | 11 +- .../TARGET_VK_RZ_A1H/device/gic.c | 305 - .../TARGET_VK_RZ_A1H/device/gic.h | 316 - .../TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h | 922 + .../TARGET_VK_RZ_A1H/device/inc/iodefine.h | 151 +- .../device/inc/iodefines/adc_iodefine.h | 79 +- .../device/inc/iodefines/bsc_iodefine.h | 88 +- .../device/inc/iodefines/ceu_iodefine.h | 198 +- .../device/inc/iodefines/cpg_iodefine.h | 252 +- .../device/inc/iodefines/disc_iodefine.h | 107 +- .../device/inc/iodefines/dmac_iodefine.h | 1384 +- .../device/inc/iodefines/dvdec_iodefine.h | 532 +- .../device/inc/iodefines/ether_iodefine.h | 424 +- .../device/inc/iodefines/flctl_iodefine.h | 52 +- .../device/inc/iodefines/gpio_iodefine.h | 2011 +- .../device/inc/iodefines/ieb_iodefine.h | 77 +- .../device/inc/iodefines/inb_iodefine.h | 92 +- .../device/inc/iodefines/intc_iodefine.h | 1022 +- .../device/inc/iodefines/iodefine_typedef.h | 118 + .../device/inc/iodefines/irda_iodefine.h | 29 +- .../device/inc/iodefines/jcu_iodefine.h | 162 +- .../device/inc/iodefines/l2c_iodefine.h | 188 +- .../device/inc/iodefines/lin_iodefine.h | 205 +- .../device/inc/iodefines/lvds_iodefine.h | 35 +- .../device/inc/iodefines/mlb_iodefine.h | 913 +- .../device/inc/iodefines/mmc_iodefine.h | 74 +- .../device/inc/iodefines/mtu2_iodefine.h | 183 +- .../device/inc/iodefines/ostm_iodefine.h | 83 +- .../device/inc/iodefines/pfv_iodefine.h | 188 +- .../device/inc/iodefines/pwm_iodefine.h | 176 +- .../device/inc/iodefines/riic_iodefine.h | 1050 +- .../device/inc/iodefines/romdec_iodefine.h | 168 +- .../device/inc/iodefines/rscan0_iodefine.h | 17794 ++++++++-------- .../device/inc/iodefines/rspi_iodefine.h | 312 +- .../device/inc/iodefines/rtc_iodefine.h | 67 +- .../device/inc/iodefines/scif_iodefine.h | 254 +- .../device/inc/iodefines/scim_iodefine.h | 99 +- .../device/inc/iodefines/scux_iodefine.h | 829 +- .../device/inc/iodefines/sdg_iodefine.h | 103 +- .../device/inc/iodefines/spdif_iodefine.h | 55 +- .../device/inc/iodefines/spibsc_iodefine.h | 252 +- .../device/inc/iodefines/ssif_iodefine.h | 187 +- .../device/inc/iodefines/usb20_iodefine.h | 770 +- .../device/inc/iodefines/vdc5_iodefine.h | 2172 +- .../device/inc/iodefines/wdt_iodefine.h | 37 +- .../device/mmu_Renesas_RZ_A1.c | 243 - .../TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c | 281 + .../TARGET_VK_RZ_A1H/device/nvic_wrapper.c | 9 +- .../TARGET_VK_RZ_A1H/device/os_tick_ostm.c | 201 + .../TARGET_VK_RZ_A1H/device/pl310.c | 128 - .../TARGET_VK_RZ_A1H/device/pl310.h | 114 - .../TARGET_VK_RZ_A1H/device/system_VKRZA1H.c | 521 - .../TARGET_VK_RZ_A1H/device/system_VKRZA1H.h | 67 - .../device/system_VK_RZ_A1H.c | 157 + .../device/system_VK_RZ_A1H.h | 81 + targets/TARGET_RENESAS/mbed_rtx.h | 2 +- targets/targets.json | 4 +- 71 files changed, 19583 insertions(+), 19445 deletions(-) create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c delete mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c create mode 100644 targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h index 10d094ce32..201e6fb008 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h @@ -1,3 +1,19 @@ +/* mbed Microcontroller Library + * Copyright (c) 2006-2017 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + #ifndef RESERVED_PINS_H #define RESERVED_PINS_H diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h index 76739b32c4..20024dad86 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h @@ -26,23 +26,12 @@ #endif /* <-Take measures about optimization problems of web compiler */ - - - - - - - - - +#define TRANSACTION_QUEUE_SIZE_SPI 16 #define DEVICE_ID_LENGTH 32 #define DEVICE_MAC_OFFSET 20 - - - - #include "objects.h" +#include "dma_api.h" #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c index 69364aaee7..ff7b5d66e2 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c @@ -47,7 +47,9 @@ Macro definitions #define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) +#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM)) #define CS2_SDRAM +#endif /****************************************************************************** Imported global variables and functions (from other files) diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct index 71b59832d6..fafb1bae33 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct @@ -1,42 +1,62 @@ +#! armcc -E -I"../" +;************************************************** +; Copyright (c) 2017 ARM Ltd. All rights reserved. +;************************************************** +; Scatter-file for RTX Example on Versatile Express -LOAD_TTB 0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM +; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. + +#include "mbed_config.h" +#include "mem_VK_RZ_A1H.h" + +LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM { TTB +0 EMPTY 0x4000 { } ; Level-1 Translation Table for MMU } -SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region +SFLASH __ROM_BASE __ROM_SIZE ; load region size_region { -} + VECTORS __VECTOR_BASE FIXED + { + * (RESET, +FIRST) ; Vector table and other startup code + * (InRoot$$Sections) ; All (library) code that must be in a root region + * (+RO-CODE) ; Application RO code (.text) + } -SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024) -{ - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - ; S-Flash ROM : Executable cached region - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + RO_DATA +0 + { * (+RO-DATA) } ; Application RO data (.constdata) - VECTORS 0x18020000 FIXED - { - * (RESET, +FIRST) ; Vector table and other (assembler) startup code - * (InRoot$$Sections) ; All (library) code that must be in a root region - * (+RO-CODE) ; Application RO code (.text) - } + RW_DATA __DATA_BASE + { * (+RW) } ; Application RW data (.data) - RO_DATA +0 - { * (+RO-DATA) } ; Application RO data (.constdata) + RW_IRAM1 +0 ALIGN 0x10 + { * (+ZI) } ; Application ZI data (.bss) - RW_DATA 0x20020000 - { * (+RW) } ; Application RW data (.data) + ARM_LIB_HEAP +0 + { * (HEAP) } ; Application heap area (HEAP) - ZI_DATA +0 ALIGN 0x400 - { * (+ZI) } ; Application ZI data (.bss) + ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down + { } - RW_DATA_NC 0x60900000 0x00100000 + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; RAM-NC : Internal non-cached RAM region + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE { * (NC_DATA) } ; Application RW data Non cached area ZI_DATA_NC +0 { * (NC_BSS) } ; Application ZI data Non cached area } - +#ifndef RUN_FROM_SDRAM +SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region +{ +} +#else +SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!) +{ +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h new file mode 100644 index 0000000000..63feb75a7a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h @@ -0,0 +1,95 @@ +/**************************************************************************//** + * @file mem_VK_RZ_A1H.h + * @brief Memory base and size definitions (used in scatter file) + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __MEM_VK_RZ_A1H_H +#define __MEM_VK_RZ_A1H_H + +/*---------------------------------------------------------------------------- + User Stack & Heap size definition + *----------------------------------------------------------------------------*/ +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- ROM Configuration ------------------------------------ +// +// ROM Configuration +// ROM Base Address <0x0-0xFFFFFFFF:8> +// ROM Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#ifdef RUN_FROM_SDRAM + #define __ROM_BASE 0x08000000 + #define __ROM_SIZE 0x02000000 + #define __VECTOR_BASE 0x08000000 + #define __DATA_BASE +0 ALIGN 0x100000 +#elif defined (RUN_FROM_SRAM) + #define __ROM_BASE 0x200A0000 + #define __ROM_SIZE 0x00960000 + #define __VECTOR_BASE 0x200A0000 + #define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS +#else + #define __ROM_BASE 0x18020000 + #define __ROM_SIZE 0x01FE0000 + #define __VECTOR_BASE 0x18020000 + #define __DATA_BASE 0x20020000 +#endif + +/*--------------------- RAM Configuration ----------------------------------- + *----------------------------------------------------------------------------*/ +#ifdef RUN_FROM_SDRAM +#define __RAM_BASE 0x08000000 +#define __RAM_SIZE 0x02000000 +#define __NC_RAM_SIZE 0x00200000 +#else +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00A00000 +#define __NC_RAM_SIZE 0x00100000 +#endif +#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE) +#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000) + +#define __UND_STACK_SIZE 0x00000100 +#define __SVC_STACK_SIZE 0x00008000 +#define __ABT_STACK_SIZE 0x00000100 +#define __FIQ_STACK_SIZE 0x00000100 +#define __IRQ_STACK_SIZE 0x0000F000 +#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE) + +/*----------------------------------------------------------------------------*/ + +/*--------------------- TTB Configuration ------------------------------------ +// +// TTB Configuration +// TTB Base Address <0x0-0xFFFFFFFF:8> +// TTB Size (in Bytes) <0x0-0xFFFFFFFF:8> +// + *----------------------------------------------------------------------------*/ +#define __TTB_BASE 0x20000000 +#define __TTB_SIZE 0x00004000 + +#endif /* __MEM_VK_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S deleted file mode 100644 index 3f4776384e..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S +++ /dev/null @@ -1,454 +0,0 @@ -;/***************************************************************************** -; * @file: startup_VKRZA1H.s -; * @purpose: CMSIS Cortex-A9 Core Device Startup File -; * for the Renesas RZA1H Device Series -; * @version: V1.02, modified for mbed -; * @date: 27. July 2009, modified 3rd Aug 2009 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2009 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - -GICI_BASE EQU 0xe8202000 -ICCIAR_OFFSET EQU 0x0000000C -ICCEOIR_OFFSET EQU 0x00000010 -ICCHPIR_OFFSET EQU 0x00000018 - -GICD_BASE EQU 0xe8201000 -ICDISER0_OFFSET EQU 0x00000100 -ICDICER0_OFFSET EQU 0x00000180 -ICDISPR0_OFFSET EQU 0x00000200 -ICDABR0_OFFSET EQU 0x00000300 -ICDIPR0_OFFSET EQU 0x00000400 - -Mode_USR EQU 0x10 -Mode_FIQ EQU 0x11 -Mode_IRQ EQU 0x12 -Mode_SVC EQU 0x13 -Mode_ABT EQU 0x17 -Mode_UND EQU 0x1B -Mode_SYS EQU 0x1F - -I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled -F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled -T_Bit EQU 0x20 ; when T bit is set, core is in Thumb state - -GIC_ERRATA_CHECK_1 EQU 0x000003FE -GIC_ERRATA_CHECK_2 EQU 0x000003FF - - -Sect_Normal EQU 0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -Sect_Normal_Cod EQU 0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -Sect_Normal_RO EQU 0x0000dc16 ;as Sect_Normal_Cod, but not executable -Sect_Normal_RW EQU 0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable -Sect_SO EQU 0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -Sect_Device_RO EQU 0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0 -Sect_Device_RW EQU 0x00000c12 ;as Sect_Device_RO, but writeable -Sect_Fault EQU 0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored) - -RAM_BASE EQU 0x80000000 -VRAM_BASE EQU 0x18000000 -SRAM_BASE EQU 0x2e000000 -ETHERNET EQU 0x1a000000 -CS3_PERIPHERAL_BASE EQU 0x1c000000 - -; Stack Configuration -; Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8> -; - -UND_Stack_Size EQU 0x00000100 -SVC_Stack_Size EQU 0x00008000 -ABT_Stack_Size EQU 0x00000100 -FIQ_Stack_Size EQU 0x00000100 -IRQ_Stack_Size EQU 0x00008000 -USR_Stack_Size EQU 0x00004000 - -ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE USR_Stack_Size -__initial_sp SPACE ISR_Stack_Size - -Stack_Top - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00080000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - ARM - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, CODE, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors LDR PC, Reset_Addr ; Address of Reset Handler - LDR PC, Undef_Addr ; Address of Undef Handler - LDR PC, SVC_Addr ; Address of SVC Handler - LDR PC, PAbt_Addr ; Address of Prefetch Abort Handler - LDR PC, DAbt_Addr ; Address of Data Abort Handler - NOP ; Reserved Vector - LDR PC, IRQ_Addr ; Address of IRQ Handler - LDR PC, FIQ_Addr ; Address of FIQ Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -Reset_Addr DCD Reset_Handler -Undef_Addr DCD Undef_Handler -SVC_Addr DCD SVC_Handler -PAbt_Addr DCD PAbt_Handler -DAbt_Addr DCD DAbt_Handler -IRQ_Addr DCD IRQ_Handler -FIQ_Addr DCD FIQ_Handler - - AREA |.text|, CODE, READONLY - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT InitMemorySubsystem - IMPORT __main - IMPORT RZ_A1_SetSramWriteEnable - - ; Put any cores other than 0 to sleep - MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR - ANDS R0, R0, #3 -goToSleep - WFINE - BNE goToSleep - -; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -; Enables Full Access i.e. in both privileged and non privileged modes - MRC p15, 0, r0, c1, c0, 2 ; Read Coprocessor Access Control Register (CPACR) - ORR r0, r0, #(0xF << 20) ; Enable access to CP 10 & 11 - MCR p15, 0, r0, c1, c0, 2 ; Write Coprocessor Access Control Register (CPACR) - ISB - -; Switch on the VFP and NEON hardware - MOV r0, #0x40000000 - VMSR FPEXC, r0 ; Write FPEXC register, EN bit set - - MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register - BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache - BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache - BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU - BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction - BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs - MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register - ISB - -; Set Vector Base Address Register (VBAR) to point to this application's vector table - LDR R0, =__Vectors - MCR p15, 0, R0, c12, c0, 0 - -; Setup Stack for each exceptional mode - LDR R0, =Stack_Top - -; Enter Undefined Instruction Mode and set its Stack Pointer - MSR CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #UND_Stack_Size - -; Enter Abort Mode and set its Stack Pointer - MSR CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #ABT_Stack_Size - -; Enter FIQ Mode and set its Stack Pointer - MSR CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #FIQ_Stack_Size - -; Enter IRQ Mode and set its Stack Pointer - MSR CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit - MOV SP, R0 - SUB R0, R0, #IRQ_Stack_Size - -; Enter Supervisor Mode and set its Stack Pointer - MSR CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit - MOV SP, R0 - -; Enter System Mode to complete initialization and enter kernel - MSR CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit - MOV SP, R0 - - ISB - - LDR R0, =RZ_A1_SetSramWriteEnable - BLX R0 - - IMPORT create_translation_table - BL create_translation_table - -; USR/SYS stack pointer will be set during kernel init - - LDR R0, =SystemInit - BLX R0 - LDR R0, =InitMemorySubsystem - BLX R0 - LDR R0, =__main - BLX R0 - - ENDP - -Undef_Handler\ - PROC - EXPORT Undef_Handler [WEAK] - IMPORT CUndefHandler - SRSFD SP!, #Mode_UND - PUSH {R0-R4, R12} ; Save APCS corruptible registers to UND mode stack - - MRS R0, SPSR - TST R0, #T_Bit ; Check mode - MOVEQ R1, #4 ; R1 = 4 ARM mode - MOVNE R1, #2 ; R1 = 2 Thumb mode - SUB R0, LR, R1 - LDREQ R0, [R0] ; ARM mode - R0 points to offending instruction - BEQ undef_cont - - ;Thumb instruction - ;Determine if it is a 32-bit Thumb instruction - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont ;16-bit Thumb instruction - - ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - ;R0 Offending instruction - ;R1 =2 (Thumb) or =4 (ARM) - BL CUndefHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - LDR LR, [SP, #24] ; Restore stacked LR and possibly adjust for retry - SUB LR, LR, R0 - LDR R0, [SP, #28] ; Restore stacked SPSR - MSR SPSR_CXSF, R0 - POP {R0-R4, R12} ; Restore stacked APCS registers - ADD SP, SP, #8 ; Adjust SP for already-restored banked registers - MOVS PC, LR - ENDP - -PAbt_Handler\ - PROC - EXPORT PAbt_Handler [WEAK] - IMPORT CPAbtHandler - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack - PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack - MRC p15, 0, R0, c5, c0, 1 ; IFSR - MRC p15, 0, R1, c6, c0, 2 ; IFAR - - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - BL CPAbtHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - POP {R0-R4, R12} ; Restore stack APCS registers - RFEFD SP! ; Return from exception - ENDP - - -DAbt_Handler\ - PROC - EXPORT DAbt_Handler [WEAK] - IMPORT CDAbtHandler - SUB LR, LR, #8 ; Pre-adjust LR - SRSFD SP!, #Mode_ABT ; Save LR and SPRS to ABT mode stack - PUSH {R0-R4, R12} ; Save APCS corruptible registers to ABT mode stack - CLREX ; State of exclusive monitors unknown after taken data abort - MRC p15, 0, R0, c5, c0, 0 ; DFSR - MRC p15, 0, R1, c6, c0, 0 ; DFAR - - MOV R2, LR ; Set LR to third argument - -; AND R12, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R12, R3, #4 - SUB SP, SP, R12 ; Adjust stack - PUSH {R12, LR} ; Store stack adjustment and dummy LR - - BL CDAbtHandler - - POP {R12, LR} ; Get stack adjustment & discard dummy LR - ADD SP, SP, R12 ; Unadjust stack - - POP {R0-R4, R12} ; Restore stacked APCS registers - RFEFD SP! ; Return from exception - ENDP - -FIQ_Handler\ - PROC - EXPORT FIQ_Handler [WEAK] - ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - ;; so if a real FIQ Handler is implemented, this will be needed before returning: - ;; LDR R1, =GICI_BASE - ;; LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - B . - ENDP - -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -IRQ_Handler\ - PROC - EXPORT IRQ_Handler [WEAK] - IMPORT IRQCount - IMPORT IRQTable - IMPORT IRQNestLevel - - ;prologue - SUB LR, LR, #4 ; Pre-adjust LR - SRSFD SP!, #Mode_SVC ; Save LR_IRQ and SPRS_IRQ to SVC mode stack - CPS #Mode_SVC ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL - PUSH {R0-R3, R12} ; Save remaining APCS corruptible registers to SVC stack - -; AND R1, SP, #4 ; Ensure stack is 8-byte aligned - MOV R3, SP ; Ensure stack is 8-byte aligned - AND R1, R3, #4 - SUB SP, SP, R1 ; Adjust stack - PUSH {R1, LR} ; Store stack adjustment and LR_SVC to SVC stack - - LDR R0, =IRQNestLevel ; Get address of nesting counter - LDR R1, [R0] - ADD R1, R1, #1 ; Increment nesting counter - STR R1, [R0] - - ;identify and acknowledge interrupt - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - LDR R0, [R1, #ICCIAR_OFFSET] ; Read ICCIAR (GIC CPU Interface register) - DSB ; Ensure that interrupt acknowledge completes before re-enabling interrupts - - ; Workaround GIC 390 errata 733075 - ; If the ID is not 0, then service the interrupt as normal. - ; If the ID is 0 and active, then service interrupt ID 0 as normal. - ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - ; with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - ; - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active ; If the ID is not 0, then service the interrupt - LDR R3, [R2, #ICDABR0_OFFSET] ; Get the interrupt state - TST R3, #1 - BNE int_active ; If active, then service the interrupt -unlock_cpu - LDR R3, [R2, #ICDIPR0_OFFSET] ; Not active, so unlock the CPU interface - STR R3, [R2, #ICDIPR0_OFFSET] ; with a dummy write - DSB ; Ensure the write completes before continuing - B ret_irq ; Do not service the spurious interrupt - ; End workaround - -int_active - LDR R2, =IRQCount ; Read number of IRQs - LDR R2, [R2] - CMP R0, R2 ; Clean up and return if no handler - BHS ret_irq ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling - LDR R2, =IRQTable ; Get address of handler - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 ; Clean up and return if handler address is 0 - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i ; Now safe to re-enable interrupts - BLX R2 ; Call handler. R0 will be IRQ number - CPSID i ; Disable interrupts again - - ;write EOIR (GIC CPU Interface register) - POP {R0,R1} - DSB ; Ensure that interrupt source is cleared before we write the EOIR -ret_irq - ;epilogue - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel ; Get address of nesting counter - LDR R1, [R0] - SUB R1, R1, #1 ; Decrement nesting counter - STR R1, [R0] - - POP {R1, LR} ; Get stack adjustment and restore LR_SVC - ADD SP, SP, R1 ; Unadjust stack - - POP {R0-R3,R12} ; Restore stacked APCS registers - RFEFD SP! ; Return from exception - ENDP - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + USR_Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ENDIF - - - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c new file mode 100644 index 0000000000..a83d7a235e --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c @@ -0,0 +1,162 @@ +/****************************************************************************** + * @file startup_RZ_A1H_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "VKRZA1H.h" +#include "mem_VK_RZ_A1H.h" + +/*---------------------------------------------------------------------------- + Definitions + *----------------------------------------------------------------------------*/ +#define USR_MODE 0x10 // User mode +#define FIQ_MODE 0x11 // Fast Interrupt Request mode +#define IRQ_MODE 0x12 // Interrupt Request mode +#define SVC_MODE 0x13 // Supervisor mode +#define ABT_MODE 0x17 // Abort mode +#define UND_MODE 0x1B // Undefined Instruction mode +#define SYS_MODE 0x1F // System mode + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void Vectors (void) __attribute__ ((section("RESET"))); +void Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void DAbt_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void IRQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void FIQ_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector Table + *----------------------------------------------------------------------------*/ +__ASM void Vectors(void) { + IMPORT Undef_Handler + IMPORT SVC_Handler + IMPORT PAbt_Handler + IMPORT DAbt_Handler + IMPORT IRQ_Handler + IMPORT FIQ_Handler + LDR PC, =Reset_Handler + LDR PC, =Undef_Handler + LDR PC, =SVC_Handler + LDR PC, =PAbt_Handler + LDR PC, =DAbt_Handler + NOP + LDR PC, =IRQ_Handler + LDR PC, =FIQ_Handler +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__ASM void Reset_Handler(void) { + + // Mask interrupts + CPSID if + + // Put any cores other than 0 to sleep + MRC p15, 0, R0, c0, c0, 5 // Read MPIDR + ANDS R0, R0, #3 +goToSleep + WFINE + BNE goToSleep + + // Reset SCTLR Settings + MRC p15, 0, R0, c1, c0, 0 // Read CP15 System Control register + BIC R0, R0, #(0x1 << 12) // Clear I bit 12 to disable I Cache + BIC R0, R0, #(0x1 << 2) // Clear C bit 2 to disable D Cache + BIC R0, R0, #0x1 // Clear M bit 0 to disable MMU + BIC R0, R0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction + BIC R0, R0, #(0x1 << 13) // Clear V bit 13 to disable hivecs + MCR p15, 0, R0, c1, c0, 0 // Write value back to CP15 System Control register + ISB + + // Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 // Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) // Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 // Write CP15 Auxiliary Control Register + + // Set Vector Base Address Register (VBAR) to point to this application's vector table + LDR R0, =Vectors + MCR p15, 0, R0, c12, c0, 0 + + // Setup Stack for each exceptional mode + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit| + + //Enter Undefined Instruction Mode and set its Stack Pointer + CPS #UND_MODE + MOV SP, R0 + SUB R0, R0, #__UND_STACK_SIZE + + // Enter Abort Mode and set its Stack Pointer + CPS #ABT_MODE + MOV SP, R0 + SUB R0, R0, #__ABT_STACK_SIZE + + // Enter FIQ Mode and set its Stack Pointer + CPS #FIQ_MODE + MOV SP, R0 + SUB R0, R0, #__FIQ_STACK_SIZE + + // Enter IRQ Mode and set its Stack Pointer + CPS #IRQ_MODE + MOV SP, R0 + SUB R0, R0, #__IRQ_STACK_SIZE + + // Enter Supervisor Mode and set its Stack Pointer + CPS #SVC_MODE + MOV SP, R0 + SUB R0, R0, #__SVC_STACK_SIZE + + // Enter System Mode to complete initialization and enter kernel + CPS #SYS_MODE + MOV SP, R0 + + // Call SystemInit + IMPORT SystemInit + BL SystemInit + + // Unmask interrupts + CPSIE if + + // Call __main + IMPORT __main + BL __main +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) { + while(1); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp new file mode 100644 index 0000000000..dfa0bc6f1f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp @@ -0,0 +1,61 @@ +/* mbed Microcontroller Library - stackheap + * Setup a fixed single stack/heap memory model, + * between the top of the RW/ZI region and the stackpointer + ******************************************************************************* + * Copyright (c) 2017 ARM Limited. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of ARM Limited nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#include +#endif + +#include +#include + +extern char Image$$ARM_LIB_HEAP$$Base[]; +extern char Image$$ARM_LIB_STACK$$Base[]; + +extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) { + uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base; + uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base; + + zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned + + struct __initial_stackheap r; + r.heap_base = zi_limit; + r.heap_limit = sp_limit; + return r; +} + +#ifdef __cplusplus +} +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld index 12afcc6c7a..b2a7fa5caa 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld @@ -1,15 +1,40 @@ /* Linker script for mbed VK_RZ_A1H */ /* Linker script to configure memory regions. */ +/* +#ifdef RUN_FROM_SDRAM +MEMORY +{ + L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 + RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x01E00000 + RAM_NC (rwx) : ORIGIN = 0x49E00000, LENGTH = 0x00200000 + SRAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00960000 +} +REGION_ALIAS("SFLASH", RAM); +TTBOFFSET = 1M; + +#elif defined (RUN_FROM_SRAM) +MEMORY +{ + L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 + RAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00860000 + RAM_NC (rwx) : ORIGIN = 0x60900000, LENGTH = 0x00100000 + SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 +} +REGION_ALIAS("SFLASH", RAM); +TTBOFFSET = 1M; +#else +*/ MEMORY { ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000 - SFLASH_DUAL (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 + SFLASH (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000 - RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000 + RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000 RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000 SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000 } +/*#endif*/ /* Linker script to place sections and symbol values. Should be used together * with other linker script that defines memory regions FLASH and RAM. @@ -45,8 +70,7 @@ SECTIONS { Image$$VECTORS$$Base = .; - *(.isr_vector) - Image$$VECTORS$$Limit = .; + KEEP(*(.isr_vector)) *(SVC_TABLE) *(.text*) @@ -66,24 +90,25 @@ SECTIONS *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) *(SORT(.dtors.*)) *(.dtors) + Image$$VECTORS$$Limit = .; Image$$RO_DATA$$Base = .; *(.rodata*) Image$$RO_DATA$$Limit = .; KEEP(*(.eh_frame*)) - } > SFLASH_DUAL + } > SFLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > SFLASH_DUAL + } > SFLASH __exidx_start = .; .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > SFLASH_DUAL + } > SFLASH __exidx_end = .; @@ -98,7 +123,7 @@ SECTIONS LONG (__nc_data_start) LONG (__nc_data_end - __nc_data_start) __copy_table_end__ = .; - } > SFLASH_DUAL + } > SFLASH .zero.table : { @@ -109,7 +134,7 @@ SECTIONS LONG (__nc_bss_start) LONG (__nc_bss_end - __nc_bss_start) __zero_table_end__ = .; - } > SFLASH_DUAL + } > SFLASH __etext = .; @@ -155,34 +180,42 @@ SECTIONS } > RAM - - .bss ALIGN(0x400): + .bss ALIGN(0x10): { - Image$$ZI_DATA$$Base = .; + Image$$RW_IRAM1$$Base = .; __bss_start__ = .; *(.bss*) *(COMMON) __bss_end__ = .; - Image$$ZI_DATA$$Limit = .; + Image$$RW_IRAM1$$Limit = .; } > RAM - .heap : { __end__ = .; end = __end__; *(.heap*) - __HeapLimit = .; } > RAM /* .stack_dummy section doesn't contains any symbols. It is only * used for linker to calculate size of stack sections, and assign * values to stack symbols later */ - .stack_dummy : + .stack_dummy (COPY): { - *(.stack) + *(.stack*) } > RAM + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + _estack = __StackTop; + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + __HeapLimit = __StackLimit; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + __etext2 = __etext + SIZEOF(.data); .nc_data : AT (__etext2) { @@ -205,15 +238,4 @@ SECTIONS __nc_bss_end = .; Image$$ZI_DATA_NC$$Limit = .; } > RAM_NC - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") - - } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S index c74cccba81..0506dd8c68 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S @@ -19,26 +19,6 @@ .extern _start @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs - .equ USR_MODE , 0x10 - .equ FIQ_MODE , 0x11 - .equ IRQ_MODE , 0x12 - .equ SVC_MODE , 0x13 - .equ ABT_MODE , 0x17 - .equ UND_MODE , 0x1b - .equ SYS_MODE , 0x1f - .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit - - .equ GICI_BASE , 0xe8202000 - .equ ICCIAR_OFFSET , 0x0000000C - .equ ICCEOIR_OFFSET , 0x00000010 - .equ ICCHPIR_OFFSET , 0x00000018 - .equ GICD_BASE , 0xe8201000 - .equ ICDISER0_OFFSET , 0x00000100 - .equ ICDICER0_OFFSET , 0x00000180 - .equ ICDISPR0_OFFSET , 0x00000200 - .equ ICDABR0_OFFSET , 0x00000300 - .equ ICDIPR0_OFFSET , 0x00000400 - .equ Mode_USR , 0x10 .equ Mode_FIQ , 0x11 .equ Mode_IRQ , 0x12 @@ -51,33 +31,13 @@ .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state - .equ GIC_ERRATA_CHECK_1, 0x000003FE - .equ GIC_ERRATA_CHECK_2, 0x000003FF - - .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 - .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 - .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable - .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable - .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 - .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0 - .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable - .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored) - - .equ RAM_BASE , 0x80000000 - .equ VRAM_BASE , 0x18000000 - .equ SRAM_BASE , 0x2e000000 - .equ ETHERNET , 0x1a000000 - .equ CS3_PERIPHERAL_BASE, 0x1c000000 - - @ Stack Configuration .EQU UND_Stack_Size , 0x00000100 .EQU SVC_Stack_Size , 0x00008000 .EQU ABT_Stack_Size , 0x00000100 .EQU FIQ_Stack_Size , 0x00000100 - .EQU IRQ_Stack_Size , 0x00008000 - .EQU USR_Stack_Size , 0x00004000 + .EQU IRQ_Stack_Size , 0x0000F000 .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) @@ -88,7 +48,6 @@ __StackLimit: .space ISR_Stack_Size __initial_sp: - .space USR_Stack_Size .size __StackLimit, . - __StackLimit __StackTop: .size __StackTop, . - __StackTop @@ -139,25 +98,17 @@ __isr_vector: .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: + @ Mask interrupts + CPSID if + @ Put any cores other than 0 to sleep mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR ands r0, r0, #3 - goToSleep: wfine bne goToSleep -@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR) - isb - -@ Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 @ Write FPEXC register, EN bit set - + @ Reset SCTLR Settings mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache @@ -167,13 +118,17 @@ goToSleep: mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register isb + @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register + @ Set Vector Base Address Register (VBAR) to point to this application's vector table ldr r0, =__isr_vector mcr p15, 0, r0, c12, c0, 0 @ Setup Stack for each exceptional mode -/* ldr r0, =__StackTop */ - ldr r0, =(__StackTop - USR_Stack_Size) + ldr r0, =__StackTop @ Enter Undefined Instruction Mode and set its Stack Pointer msr cpsr_c, #(Mode_UND | I_Bit | F_Bit) @@ -203,23 +158,12 @@ goToSleep: msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit) mov sp, r0 - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - .extern create_translation_table - bl create_translation_table - @ USR/SYS stack pointer will be set during kernel init ldr r0, =SystemInit blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -@ fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 + @ Unmask interrupts + CPSIE if @ data sections copy ldr r4, =__copy_table_start__ @@ -269,227 +213,12 @@ goToSleep: ldr r0, =_start bx r0 - ldr r0, sf_boot @ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - .word 0x18020000 - .pool .size Reset_Handler, . - Reset_Handler .text -Undef_Handler: - .global Undef_Handler - .func Undef_Handler - .extern CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - .endfunc - -PAbt_Handler: - .global PAbt_Handler - .func PAbt_Handler - .extern CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -DAbt_Handler: - .global DAbt_Handler - .func DAbt_Handler - .extern CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - -FIQ_Handler: - .global FIQ_Handler - .func FIQ_Handler - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ - B . - .endfunc - - .extern SVC_Handler /* refer RTX function */ - -IRQ_Handler: - .global IRQ_Handler - .func IRQ_Handler - .extern IRQCount - .extern IRQTable - .extern IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ - .endfunc - /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ @@ -503,30 +232,11 @@ ret_irq: .size \handler_name, . - \handler_name .endm + def_default_handler Undef_Handler def_default_handler SVC_Handler - - -/* User Initial Stack & Heap */ - - .ifdef __MICROLIB - - .global __initial_sp - .global __heap_base - .global __heap_limit - - .else - - .extern __use_two_region_memory - .global __user_initial_stackheap -__user_initial_stackheap: - - LDR R0, = __HeapBase - LDR R1, =(__StackTop) - LDR R2, = (__HeapBase + Heap_Size) - LDR R3, = (__StackTop - USR_Stack_Size) - BX LR - - .endif - + def_default_handler PAbt_Handler + def_default_handler DAbt_Handler + def_default_handler IRQ_Handler + def_default_handler FIQ_Handler .END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf index 30addf8e44..d00e9df287 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf @@ -41,6 +41,7 @@ define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__]; define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__]; +define block ROM_FIXED_ORDER with fixed order { ro code, ro data }; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; @@ -51,11 +52,11 @@ define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; initialize by copy { readwrite }; do not initialize { section .noinit }; -do not initialize { section MMU_TT }; +do not initialize { section .retram }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; +place in ROM_region { readonly, block ROM_FIXED_ORDER }; place in RAM_region { readwrite, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, block UND_STACK, block ABT_STACK, block HEAP }; diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S index 94f605c124..521dc5f116 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S @@ -29,30 +29,21 @@ SECTION .intvec:CODE:NOROOT(2) - PUBLIC __vector_core_a9 - PUBWEAK __iar_program_start - PUBLIC Undefined_Handler - EXTERN SWI_Handler - PUBLIC Prefetch_Handler - PUBLIC Abort_Handler - PUBLIC IRQ_Handler + PUBLIC __vector_table + PUBLIC __RST_Handler + EXTERN Undef_Handler + EXTERN SVC_Handler + EXTERN PAbt_Handler + EXTERN DAbt_Handler + EXTERN IRQ_Handler PUBLIC FIQ_Handler - EXTERN VbarInit - EXTERN SetLowVectors - EXTERN init_TTB - EXTERN enable_mmu - EXTERN Peripheral_BasicInit - EXTERN initsct - EXTERN PowerON_Reset - PUBLIC FPUEnable - DATA __iar_init$$done: ; The vector table is not needed ; until after copy initialization is done -__vector_core_a9: ; Make this a DATA label, so that stack usage +__vector_table: ; Make this a DATA label, so that stack usage ; analysis doesn't consider it an uncalled fun ARM @@ -71,11 +62,11 @@ __vector_core_a9: ; Make this a DATA label, so that stack usage DATA -Reset_Addr: DCD __iar_program_start -Undefined_Addr: DCD Undefined_Handler -SWI_Addr: DCD SWI_Handler -Prefetch_Addr: DCD Prefetch_Handler -Abort_Addr: DCD Abort_Handler +Reset_Addr: DCD __RST_Handler +Undefined_Addr: DCD Undef_Handler +SWI_Addr: DCD SVC_Handler +Prefetch_Addr: DCD PAbt_Handler +Abort_Addr: DCD DAbt_Handler IRQ_Addr: DCD IRQ_Handler FIQ_Addr: DCD FIQ_Handler @@ -90,21 +81,20 @@ FIQ_Addr: DCD FIQ_Handler SECTION .text:CODE:NOROOT(2) - EXTERN RZ_A1_SetSramWriteEnable - EXTERN create_translation_table EXTERN SystemInit - EXTERN InitMemorySubsystem - EXTERN __cmain - REQUIRE __vector_core_a9 + EXTERN __iar_program_start + REQUIRE __vector_table EXTWEAK __iar_init_core EXTWEAK __iar_init_vfp ARM -__iar_program_start: +__RST_Handler: ?cstartup: +;;; @ Mask interrupts + CPSID if ;;; @ Put any cores other than 0 to sleep mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR @@ -114,19 +104,7 @@ goToSleep: wfine bne goToSleep - -//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. -//@ Enables Full Access i.e. in both privileged and non privileged modes - mrc p15, 0, r0, c1, c0, 2 ;@ Read Coprocessor Access Control Register (CPACR) - orr r0, r0, #(0xF << 20) ;@ Enable access to CP 10 & 11 - mcr p15, 0, r0, c1, c0, 2 ;@ Write Coprocessor Access Control Register (CPACR) - isb - - -;; Switch on the VFP and NEON hardware - mov r0, #0x40000000 - vmsr fpexc, r0 ;@ Write FPEXC register, EN bit set - +;;; @ Reset SCTLR Settings mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache @@ -136,9 +114,13 @@ goToSleep: mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register isb +;;; @ Configure ACTLR + MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register + ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1) + MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register ;; Set Vector Base Address Register (VBAR) to point to this application's vector table - ldr r0, =__vector_core_a9 + ldr r0, =__vector_table mcr p15, 0, r0, c12, c0, 0 @@ -169,20 +151,6 @@ goToSleep: #define UND_MODE 0x1B ; Undefined Instruction mode #define SYS_MODE 0x1F ; System mode -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define GICI_BASE 0xe8202000 -#define ICCIAR_OFFSET 0x0000000C -#define ICCEOIR_OFFSET 0x00000010 -#define ICCHPIR_OFFSET 0x00000018 -#define GICD_BASE 0xe8201000 -#define GIC_ERRATA_CHECK_1 0x000003FE -#define GIC_ERRATA_CHECK_2 0x000003FF -#define ICDABR0_OFFSET 0x00000300 -#define ICDIPR0_OFFSET 0x00000400 -#define T_Bit 0x20 ; when T bit is set, core is in Thumb state - MRS r0, cpsr ; Original PSR value ;; Set up the SVC stack pointer. @@ -235,271 +203,16 @@ goToSleep: BIC sp,sp,#0x7 ; Make sure SP is 8 aligned ;;; - - isb - ldr r0, =RZ_A1_SetSramWriteEnable - blx r0 - - bl create_translation_table - ; USR/SYS stack pointer will be set during kernel init ldr r0, =SystemInit blx r0 - ldr r0, =InitMemorySubsystem - blx r0 - -; fp_init - mov r0, #0x3000000 - vmsr fpscr, r0 - - ;;; Continue to __cmain for C-level initialization. - FUNCALL __iar_program_start, __cmain - B __cmain - - - ldr r0, sf_boot ;@ dummy to keep boot loader area -loop_here: - b loop_here - -sf_boot: - DC32 0x00000001 - -Undefined_Handler: - EXTERN CUndefHandler - SRSDB SP!, #Mode_UND - PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */ - - MRS R0, SPSR - TST R0, #T_Bit /* Check mode */ - MOVEQ R1, #4 /* R1 = 4 ARM mode */ - MOVNE R1, #2 /* R1 = 2 Thumb mode */ - SUB R0, LR, R1 - LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */ - BEQ undef_cont - - /* Thumb instruction */ - /* Determine if it is a 32-bit Thumb instruction */ - LDRH R0, [R0] - MOV R2, #0x1c - CMP R2, R0, LSR #11 - BHS undef_cont /* 16-bit Thumb instruction */ - - /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */ - LDRH R2, [LR] - ORR R0, R2, R0, LSL #16 -undef_cont: - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - /* R0 Offending instruction */ - /* R1 =2 (Thumb) or =4 (ARM) */ - BL CUndefHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */ - SUB LR, LR, R0 - LDR R0, [SP, #28] /* Restore stacked SPSR */ - MSR SPSR_cxsf, R0 - POP {R0-R4, R12} /* Restore stacked APCS registers */ - ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */ - MOVS PC, LR - -Prefetch_Handler: - EXTERN CPAbtHandler - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - MRC p15, 0, R0, c5, c0, 1 /* IFSR */ - MRC p15, 0, R1, c6, c0, 2 /* IFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CPAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stack APCS registers */ - RFEFD SP! /* Return from exception */ - -Abort_Handler: - EXTERN CDAbtHandler - SUB LR, LR, #8 /* Pre-adjust LR */ - SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */ - PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */ - CLREX /* State of exclusive monitors unknown after taken data abort */ - MRC p15, 0, R0, c5, c0, 0 /* DFSR */ - MRC p15, 0, R1, c6, c0, 0 /* DFAR */ - - MOV R2, LR /* Set LR to third argument */ - -/* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R12, R3, #4 - SUB SP, SP, R12 /* Adjust stack */ - PUSH {R12, LR} /* Store stack adjustment and dummy LR */ - - BL CDAbtHandler - - POP {R12, LR} /* Get stack adjustment & discard dummy LR */ - ADD SP, SP, R12 /* Unadjust stack */ - - POP {R0-R4, R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ + FUNCALL __RST_Handler, __iar_program_start + B __iar_program_start FIQ_Handler: - /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler, - * so if a real FIQ Handler is implemented, this will be needed before returning: - */ - /* LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 - */ B . - EXTERN SVC_Handler /* refer RTX function */ - -IRQ_Handler: - EXTERN IRQCount - EXTERN IRQTable - EXTERN IRQNestLevel - - /* prologue */ - SUB LR, LR, #4 /* Pre-adjust LR */ - SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */ - CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */ - PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */ - -/* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */ - MOV R3, SP /* Ensure stack is 8-byte aligned */ - AND R1, R3, #4 - SUB SP, SP, R1 /* Adjust stack */ - PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */ - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - ADD R1, R1, #1 /* Increment nesting counter */ - STR R1, [R0] - - /* identify and acknowledge interrupt */ - LDR R1, =GICI_BASE - LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */ - LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */ - DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */ - - /* Workaround GIC 390 errata 733075 - * If the ID is not 0, then service the interrupt as normal. - * If the ID is 0 and active, then service interrupt ID 0 as normal. - * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it - * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced. - */ - LDR R2, =GICD_BASE - LDR R3, =GIC_ERRATA_CHECK_1 - CMP R0, R3 - BEQ unlock_cpu - LDR R3, =GIC_ERRATA_CHECK_2 - CMP R0, R3 - BEQ unlock_cpu - CMP R0, #0 - BNE int_active /* If the ID is not 0, then service the interrupt */ - LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */ - TST R3, #1 - BNE int_active /* If active, then service the interrupt */ -unlock_cpu: - LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */ - STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */ - DSB /* Ensure the write completes before continuing */ - B ret_irq /* Do not service the spurious interrupt */ - /* End workaround */ - -int_active: - LDR R2, =IRQCount /* Read number of IRQs */ - LDR R2, [R2] - CMP R0, R2 /* Clean up and return if no handler */ - BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */ - LDR R2, =IRQTable /* Get address of handler */ - LDR R2, [R2, R0, LSL #2] - CMP R2, #0 /* Clean up and return if handler address is 0 */ - BEQ ret_irq - PUSH {R0,R1} - - CPSIE i /* Now safe to re-enable interrupts */ - BLX R2 /* Call handler. R0 will be IRQ number */ - CPSID i /* Disable interrupts again */ - - /* write EOIR (GIC CPU Interface register) */ - POP {R0,R1} - DSB /* Ensure that interrupt source is cleared before we write the EOIR */ -ret_irq: - /* epilogue */ - STR R0, [R1, #ICCEOIR_OFFSET] - - LDR R0, =IRQNestLevel /* Get address of nesting counter */ - LDR R1, [R0] - SUB R1, R1, #1 /* Decrement nesting counter */ - STR R1, [R0] - - POP {R1, LR} /* Get stack adjustment and restore LR_SVC */ - ADD SP, SP, R1 /* Unadjust stack */ - - POP {R0-R3,R12} /* Restore stacked APCS registers */ - RFEFD SP! /* Return from exception */ -;;; -;;; Add more initialization here -;;; -FPUEnable: - ARM - - //Permit access to VFP registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Enable VFP - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP registers to 0 - MOV R2,#0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR - END diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h index 0a79f4c8e8..089284dc1c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h @@ -1,1075 +1 @@ -/******************************************************************************* -* DISCLAIMER -* This software is supplied by Renesas Electronics Corporation and is only -* intended for use with Renesas products. No other uses are authorized. This -* software is owned by Renesas Electronics Corporation and is protected under -* all applicable laws, including copyright laws. -* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING -* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT -* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE -* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. -* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS -* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE -* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR -* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE -* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. -* Renesas reserves the right, without notice, to make changes to this software -* and to discontinue the availability of this software. By using this software, -* you agree to the additional terms and conditions found by accessing the -* following link: -* http://www.renesas.com/disclaimer -* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved. -*******************************************************************************/ -/**************************************************************************//** - * @file VKRZA1H.h - * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for - * Renesas RZA1H Device Series - * @version - * @date 19 Sept 2013 - * - * @note - * - ******************************************************************************/ - -#ifndef __VKRZA1H_H__ -#define __VKRZA1H_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum IRQn -{ -/****** SGI Interrupts Numbers ****************************************/ - SGI0_IRQn = 0, - SGI1_IRQn = 1, - SGI2_IRQn = 2, - SGI3_IRQn = 3, - SGI4_IRQn = 4, - SGI5_IRQn = 5, - SGI6_IRQn = 6, - SGI7_IRQn = 7, - SGI8_IRQn = 8, - SGI9_IRQn = 9, - SGI10_IRQn = 10, - SGI11_IRQn = 11, - SGI12_IRQn = 12, - SGI13_IRQn = 13, - SGI14_IRQn = 14, - SGI15_IRQn = 15, - -/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ - /* 16 - 578 */ - PMUIRQ0_IRQn = 16, - COMMRX0_IRQn = 17, - COMMTX0_IRQn = 18, - CTIIRQ0_IRQn = 19, - - IRQ0_IRQn = 32, - IRQ1_IRQn = 33, - IRQ2_IRQn = 34, - IRQ3_IRQn = 35, - IRQ4_IRQn = 36, - IRQ5_IRQn = 37, - IRQ6_IRQn = 38, - IRQ7_IRQn = 39, - - PL310ERR_IRQn = 40, - - DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ - DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ - DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ - DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ - DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ - DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ - DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ - DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ - DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ - DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ - DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ - DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ - DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ - DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ - DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ - DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ - DMAERR_IRQn = 57, /*!< DMAC Interrupt */ - - /* 58-72 Reserved */ - - USBI0_IRQn = 73, - USBI1_IRQn = 74, - - S0_VI_VSYNC0_IRQn = 75, - S0_LO_VSYNC0_IRQn = 76, - S0_VSYNCERR0_IRQn = 77, - GR3_VLINE0_IRQn = 78, - S0_VFIELD0_IRQn = 79, - IV1_VBUFERR0_IRQn = 80, - IV3_VBUFERR0_IRQn = 81, - IV5_VBUFERR0_IRQn = 82, - IV6_VBUFERR0_IRQn = 83, - S0_WLINE0_IRQn = 84, - S1_VI_VSYNC0_IRQn = 85, - S1_LO_VSYNC0_IRQn = 86, - S1_VSYNCERR0_IRQn = 87, - S1_VFIELD0_IRQn = 88, - IV2_VBUFERR0_IRQn = 89, - IV4_VBUFERR0_IRQn = 90, - S1_WLINE0_IRQn = 91, - OIR_VI_VSYNC0_IRQn = 92, - OIR_LO_VSYNC0_IRQn = 93, - OIR_VSYNCERR0_IRQn = 94, - OIR_VFIELD0_IRQn = 95, - IV7_VBUFERR0_IRQn = 96, - IV8_VBUFERR0_IRQn = 97, - /* 98 Reserved */ - S0_VI_VSYNC1_IRQn = 99, - S0_LO_VSYNC1_IRQn = 100, - S0_VSYNCERR1_IRQn = 101, - GR3_VLINE1_IRQn = 102, - S0_VFIELD1_IRQn = 103, - IV1_VBUFERR1_IRQn = 104, - IV3_VBUFERR1_IRQn = 105, - IV5_VBUFERR1_IRQn = 106, - IV6_VBUFERR1_IRQn = 107, - S0_WLINE1_IRQn = 108, - S1_VI_VSYNC1_IRQn = 109, - S1_LO_VSYNC1_IRQn = 110, - S1_VSYNCERR1_IRQn = 111, - S1_VFIELD1_IRQn = 112, - IV2_VBUFERR1_IRQn = 113, - IV4_VBUFERR1_IRQn = 114, - S1_WLINE1_IRQn = 115, - OIR_VI_VSYNC1_IRQn = 116, - OIR_LO_VSYNC1_IRQn = 117, - OIR_VSYNCERR1_IRQn = 118, - OIR_VFIELD1_IRQn = 119, - IV7_VBUFERR1_IRQn = 120, - IV8_VBUFERR1_IRQn = 121, - /* Reserved = 122 */ - - IMRDI_IRQn = 123, - IMR2I0_IRQn = 124, - IMR2I1_IRQn = 125, - - JEDI_IRQn = 126, - JDTI_IRQn = 127, - - CMP0_IRQn = 128, - CMP1_IRQn = 129, - - INT0_IRQn = 130, - INT1_IRQn = 131, - INT2_IRQn = 132, - INT3_IRQn = 133, - - OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ - OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ - - CMI_IRQn = 136, - WTOUT_IRQn = 137, - - ITI_IRQn = 138, - - TGI0A_IRQn = 139, - TGI0B_IRQn = 140, - TGI0C_IRQn = 141, - TGI0D_IRQn = 142, - TGI0V_IRQn = 143, - TGI0E_IRQn = 144, - TGI0F_IRQn = 145, - TGI1A_IRQn = 146, - TGI1B_IRQn = 147, - TGI1V_IRQn = 148, - TGI1U_IRQn = 149, - TGI2A_IRQn = 150, - TGI2B_IRQn = 151, - TGI2V_IRQn = 152, - TGI2U_IRQn = 153, - TGI3A_IRQn = 154, - TGI3B_IRQn = 155, - TGI3C_IRQn = 156, - TGI3D_IRQn = 157, - TGI3V_IRQn = 158, - TGI4A_IRQn = 159, - TGI4B_IRQn = 160, - TGI4C_IRQn = 161, - TGI4D_IRQn = 162, - TGI4V_IRQn = 163, - - CMI1_IRQn = 164, - CMI2_IRQn = 165, - - SGDEI0_IRQn = 166, - SGDEI1_IRQn = 167, - SGDEI2_IRQn = 168, - SGDEI3_IRQn = 169, - - ADI_IRQn = 170, - LMTI_IRQn = 171, - - SSII0_IRQn = 172, /*!< SSIF Interrupt */ - SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ - SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ - SSII1_IRQn = 175, /*!< SSIF Interrupt */ - SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ - SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ - SSII2_IRQn = 178, /*!< SSIF Interrupt */ - SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ - SSII3_IRQn = 180, /*!< SSIF Interrupt */ - SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ - SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ - SSII4_IRQn = 183, /*!< SSIF Interrupt */ - SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ - SSII5_IRQn = 185, /*!< SSIF Interrupt */ - SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ - SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ - - SPDIFI_IRQn = 188, - - INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ - INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ - INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ - INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ - INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ - INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ - INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ - INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ - INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ - INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ - INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ - INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ - INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ - INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ - INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ - INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ - INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ - INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ - INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ - INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ - INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ - INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ - INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ - INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ - INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ - INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ - INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ - INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ - INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ - INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ - INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ - INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ - - SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ - SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ - SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ - SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ - SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ - SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ - SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ - SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ - SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ - SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ - SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ - SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ - SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ - SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ - SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ - SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ - SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ - SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ - SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ - SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ - SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ - SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ - SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ - SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ - SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ - SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ - SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ - SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ - SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ - SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ - SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ - SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ - - INTRCANGERR_IRQn = 253, - INTRCANGRECC_IRQn = 254, - INTRCAN0REC_IRQn = 255, - INTRCAN0ERR_IRQn = 256, - INTRCAN0TRX_IRQn = 257, - INTRCAN1REC_IRQn = 258, - INTRCAN1ERR_IRQn = 259, - INTRCAN1TRX_IRQn = 260, - INTRCAN2REC_IRQn = 261, - INTRCAN2ERR_IRQn = 262, - INTRCAN2TRX_IRQn = 263, - INTRCAN3REC_IRQn = 264, - INTRCAN3ERR_IRQn = 265, - INTRCAN3TRX_IRQn = 266, - INTRCAN4REC_IRQn = 267, - INTRCAN4ERR_IRQn = 268, - INTRCAN4TRX_IRQn = 269, - - RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ - RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ - RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ - RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ - RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ - RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ - RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ - RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ - RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ - RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ - RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ - RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ - RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ - RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ - RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ - - IEBBTD_IRQn = 285, - IEBBTERR_IRQn = 286, - IEBBTSTA_IRQn = 287, - IEBBTV_IRQn = 288, - - ISY_IRQn = 289, - IERR_IRQn = 290, - ITARG_IRQn = 291, - ISEC_IRQn = 292, - IBUF_IRQn = 293, - IREADY_IRQn = 294, - - STERB_IRQn = 295, - FLTENDI_IRQn = 296, - FLTREQ0I_IRQn = 297, - FLTREQ1I_IRQn = 298, - - MMC0_IRQn = 299, - MMC1_IRQn = 300, - MMC2_IRQn = 301, - - SCHI0_3_IRQn = 302, - SDHI0_0_IRQn = 303, - SDHI0_1_IRQn = 304, - SCHI1_3_IRQn = 305, - SDHI1_0_IRQn = 306, - SDHI1_1_IRQn = 307, - - ARM_IRQn = 308, - PRD_IRQn = 309, - CUP_IRQn = 310, - - SCUAI0_IRQn = 311, - SCUAI1_IRQn = 312, - SCUFDI0_IRQn = 313, - SCUFDI1_IRQn = 314, - SCUFDI2_IRQn = 315, - SCUFDI3_IRQn = 316, - SCUFUI0_IRQn = 317, - SCUFUI1_IRQn = 318, - SCUFUI2_IRQn = 319, - SCUFUI3_IRQn = 320, - SCUDVI0_IRQn = 321, - SCUDVI1_IRQn = 322, - SCUDVI2_IRQn = 323, - SCUDVI3_IRQn = 324, - - MLB_CINT_IRQn = 325, - MLB_SINT_IRQn = 326, - - DRC10_IRQn = 327, - DRC11_IRQn = 328, - - /* 329-330 Reserved */ - - LINI0_INT_T_IRQn = 331, - LINI0_INT_R_IRQn = 332, - LINI0_INT_S_IRQn = 333, - LINI0_INT_M_IRQn = 334, - LINI1_INT_T_IRQn = 335, - LINI1_INT_R_IRQn = 336, - LINI1_INT_S_IRQn = 337, - LINI1_INT_M_IRQn = 338, - - /* 339-346 Reserved */ - - SCIERI0_IRQn = 347, - SCIRXI0_IRQn = 348, - SCITXI0_IRQn = 349, - SCITEI0_IRQn = 350, - SCIERI1_IRQn = 351, - SCIRXI1_IRQn = 352, - SCITXI1_IRQn = 353, - SCITEI1_IRQn = 354, - - AVBI_DATA = 355, - AVBI_ERROR = 356, - AVBI_MANAGE = 357, - AVBI_MAC = 358, - - ETHERI_IRQn = 359, - - /* 360-363 Reserved */ - - CEUI_IRQn = 364, - - /* 365-380 Reserved */ - - - H2XMLB_ERRINT_IRQn = 381, - H2XIC1_ERRINT_IRQn = 382, - X2HPERI1_ERRINT_IRQn = 383, - X2HPERR2_ERRINT_IRQn = 384, - X2HPERR34_ERRINT_IRQn= 385, - X2HPERR5_ERRINT_IRQn = 386, - X2HPERR67_ERRINT_IRQn= 387, - X2HDBGR_ERRINT_IRQn = 388, - X2HBSC_ERRINT_IRQn = 389, - X2HSPI1_ERRINT_IRQn = 390, - X2HSPI2_ERRINT_IRQn = 391, - PRRI_IRQn = 392, - - IFEI0_IRQn = 393, - OFFI0_IRQn = 394, - PFVEI0_IRQn = 395, - IFEI1_IRQn = 396, - OFFI1_IRQn = 397, - PFVEI1_IRQn = 398, - - /* 399-415 Reserved */ - TINT0_IRQn = 416, - TINT1_IRQn = 417, - TINT2_IRQn = 418, - TINT3_IRQn = 419, - TINT4_IRQn = 420, - TINT5_IRQn = 421, - TINT6_IRQn = 422, - TINT7_IRQn = 423, - TINT8_IRQn = 424, - TINT9_IRQn = 425, - TINT10_IRQn = 426, - TINT11_IRQn = 427, - TINT12_IRQn = 428, - TINT13_IRQn = 429, - TINT14_IRQn = 430, - TINT15_IRQn = 431, - TINT16_IRQn = 432, - TINT17_IRQn = 433, - TINT18_IRQn = 434, - TINT19_IRQn = 435, - TINT20_IRQn = 436, - TINT21_IRQn = 437, - TINT22_IRQn = 438, - TINT23_IRQn = 439, - TINT24_IRQn = 440, - TINT25_IRQn = 441, - TINT26_IRQn = 442, - TINT27_IRQn = 443, - TINT28_IRQn = 444, - TINT29_IRQn = 445, - TINT30_IRQn = 446, - TINT31_IRQn = 447, - TINT32_IRQn = 448, - TINT33_IRQn = 449, - TINT34_IRQn = 450, - TINT35_IRQn = 451, - TINT36_IRQn = 452, - TINT37_IRQn = 453, - TINT38_IRQn = 454, - TINT39_IRQn = 455, - TINT40_IRQn = 456, - TINT41_IRQn = 457, - TINT42_IRQn = 458, - TINT43_IRQn = 459, - TINT44_IRQn = 460, - TINT45_IRQn = 461, - TINT46_IRQn = 462, - TINT47_IRQn = 463, - TINT48_IRQn = 464, - TINT49_IRQn = 465, - TINT50_IRQn = 466, - TINT51_IRQn = 467, - TINT52_IRQn = 468, - TINT53_IRQn = 469, - TINT54_IRQn = 470, - TINT55_IRQn = 471, - TINT56_IRQn = 472, - TINT57_IRQn = 473, - TINT58_IRQn = 474, - TINT59_IRQn = 475, - TINT60_IRQn = 476, - TINT61_IRQn = 477, - TINT62_IRQn = 478, - TINT63_IRQn = 479, - TINT64_IRQn = 480, - TINT65_IRQn = 481, - TINT66_IRQn = 482, - TINT67_IRQn = 483, - TINT68_IRQn = 484, - TINT69_IRQn = 485, - TINT70_IRQn = 486, - TINT71_IRQn = 487, - TINT72_IRQn = 488, - TINT73_IRQn = 489, - TINT74_IRQn = 490, - TINT75_IRQn = 491, - TINT76_IRQn = 492, - TINT77_IRQn = 493, - TINT78_IRQn = 494, - TINT79_IRQn = 495, - TINT80_IRQn = 496, - TINT81_IRQn = 497, - TINT82_IRQn = 498, - TINT83_IRQn = 499, - TINT84_IRQn = 500, - TINT85_IRQn = 501, - TINT86_IRQn = 502, - TINT87_IRQn = 503, - TINT88_IRQn = 504, - TINT89_IRQn = 505, - TINT90_IRQn = 506, - TINT91_IRQn = 507, - TINT92_IRQn = 508, - TINT93_IRQn = 509, - TINT94_IRQn = 510, - TINT95_IRQn = 511, - TINT96_IRQn = 512, - TINT97_IRQn = 513, - TINT98_IRQn = 514, - TINT99_IRQn = 515, - TINT100_IRQn = 516, - TINT101_IRQn = 517, - TINT102_IRQn = 518, - TINT103_IRQn = 519, - TINT104_IRQn = 520, - TINT105_IRQn = 521, - TINT106_IRQn = 522, - TINT107_IRQn = 523, - TINT108_IRQn = 524, - TINT109_IRQn = 525, - TINT110_IRQn = 526, - TINT111_IRQn = 527, - TINT112_IRQn = 528, - TINT113_IRQn = 529, - TINT114_IRQn = 530, - TINT115_IRQn = 531, - TINT116_IRQn = 532, - TINT117_IRQn = 533, - TINT118_IRQn = 534, - TINT119_IRQn = 535, - TINT120_IRQn = 536, - TINT121_IRQn = 537, - TINT122_IRQn = 538, - TINT123_IRQn = 539, - TINT124_IRQn = 540, - TINT125_IRQn = 541, - TINT126_IRQn = 542, - TINT127_IRQn = 543, - TINT128_IRQn = 544, - TINT129_IRQn = 545, - TINT130_IRQn = 546, - TINT131_IRQn = 547, - TINT132_IRQn = 548, - TINT133_IRQn = 549, - TINT134_IRQn = 550, - TINT135_IRQn = 551, - TINT136_IRQn = 552, - TINT137_IRQn = 553, - TINT138_IRQn = 554, - TINT139_IRQn = 555, - TINT140_IRQn = 556, - TINT141_IRQn = 557, - TINT142_IRQn = 558, - TINT143_IRQn = 559, - TINT144_IRQn = 560, - TINT145_IRQn = 561, - TINT146_IRQn = 562, - TINT147_IRQn = 563, - TINT148_IRQn = 564, - TINT149_IRQn = 565, - TINT150_IRQn = 566, - TINT151_IRQn = 567, - TINT152_IRQn = 568, - TINT153_IRQn = 569, - TINT154_IRQn = 570, - TINT155_IRQn = 571, - TINT156_IRQn = 572, - TINT157_IRQn = 573, - TINT158_IRQn = 574, - TINT159_IRQn = 575, - TINT160_IRQn = 576, - TINT161_IRQn = 577, - TINT162_IRQn = 578, - TINT163_IRQn = 579, - TINT164_IRQn = 580, - TINT165_IRQn = 581, - TINT166_IRQn = 582, - TINT167_IRQn = 583, - TINT168_IRQn = 584, - TINT169_IRQn = 585, - TINT170_IRQn = 586 - -} IRQn_Type; - -#define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn - -/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ -#define __CA9_REV 0x0000 /*!< Core revision r0 */ - -#define __MPU_PRESENT 1 /*!< MPU present or not */ - -#define __FPU_PRESENT 1 /*!< FPU present or not */ - -#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -#include "core_ca.h" -#include "system_VKRZA1H.h" -#include "iodefine.h" - -/******************************************************************************/ -/* Device Specific Peripheral Section */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals - Renesas_RZ_A1 Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -#include "pl310.h" -#include "gic.h" -#include "nvic_wrapper.h" -#include "cmsis_nvic.h" - -#include "ostm_iodefine.h" -#include "gpio_iodefine.h" -#include "cpg_iodefine.h" -#include "l2c_iodefine.h" - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */ - - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping - @{ -*/ - -/* R7S72100 CPU board */ -#define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ -#define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ -#define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ -#define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ -#define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ -#define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ -#define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ -#define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ -#define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ -#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ -#define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ -#define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ -#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ - -//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map -//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0. -#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = NORMAL; \ - region.sec_t = SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0. -#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Normal_RO. Sect_Normal_Cod, but not executable -#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -#ifdef __RAM_DEBUG__ -//Sect_Normal_RWX. Sect_Normal_Cod, but writeable -#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -#else -//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable -#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = WB_WA; \ - region.outer_norm_t = WB_WA; \ - region.mem_t = NORMAL; \ - region.sec_t = NON_SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -#endif - -//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 -#define section_so(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0 -#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = READ; \ - region.user_t = READ; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); - -//Sect_Device_RW. Sect_Device_RO, but writeable -#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = STRONGLY_ORDERED; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_section_descriptor(&descriptor_l1, region); -//Page_4k_Device_RW. Shared device, not executable, rw, domain 0 -#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); - -//Page_64k_Device_RW. Shared device, not executable, rw, domain 0 -#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \ - region.domain = 0x0; \ - region.e_t = ECC_DISABLED; \ - region.g_t = GLOBAL; \ - region.inner_norm_t = NON_CACHEABLE; \ - region.outer_norm_t = NON_CACHEABLE; \ - region.mem_t = SHARED_DEVICE; \ - region.sec_t = SECURE; \ - region.xn_t = NON_EXECUTE; \ - region.priv_t = RW; \ - region.user_t = RW; \ - region.sh_t = NON_SHARED; \ - __get_page_descriptor(&descriptor_l1, &descriptor_l2, region); - -/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */ - -/******************************************************************************/ -/* Clock Settings */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions - @{ -*/ - -/* - * Clock Mode 0 settings - * SW1-4(MD_CLK):ON - * SW1-5(MD_CLKS):ON - * FRQCR=0x1035 - * CLKEN2 = 0b - unstable - * CLKEN[1:0]=01b - Output, Low, Low - * IFC[1:0] =00b - CPU clock is 1/1 PLL clock - * FRQCR2=0x0001 - * GFC[1:0] =01b - Graphic clock is 2/3 bus clock - */ -#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) -#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) -#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) -#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) -#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) -#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) -#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) - -/* - * Clock Mode 1 settings - * SW1-4(MD_CLK):OFF - * SW1-5(MD_CLKS):ON - * FRQCR=0x1335 - * CLKEN2 = 0b - unstable - * CLKEN[1:0]=01b - Output, Low, Low - * IFC[1:0] =11b - CPU clock is 1/3 PLL clock - * FRQCR2=0x0003 - * GFC[1:0] =11b - graphic clock is 1/3 bus clock - */ -#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) -#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) -#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) -#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) -#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) - -/*@}*/ /* end of group Renesas_RZ_A1_Clocks */ - -/******************************************************************************/ -/* CPG Settings */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions - @{ -*/ - -#define CPG_FRQCR_SHIFT_CKOEN2 (14) -#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) -#define CPG_FRQCR_SHIFT_CKOEN0 (12) -#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) -#define CPG_FRQCR_SHIFT_IFC (8) -#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) - -#define CPG_FRQCR2_SHIFT_GFC (0) -#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) - - -#define CPG_STBCR1_BIT_STBY (0x80u) -#define CPG_STBCR1_BIT_DEEP (0x40u) -#define CPG_STBCR2_BIT_HIZ (0x80u) -#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ -#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ -#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ -#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ -#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ -#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ -#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ -#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ -#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ -#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ -#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ -#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ -#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ -#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ -#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ -#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ -#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ -#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ -#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ -#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ -#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ -#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ -#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ -#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ -#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */ -#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ -#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ -#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ -#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */ -#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */ -#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ -#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ -#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ -#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ -#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */ -#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ -#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ -#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ -#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ -#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ -#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ -#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ -#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ -#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ -#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ -#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ -#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ -#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ -#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ -#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ -#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ -#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ -#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ -#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ -#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ -#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ -#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ -#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ -#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ -#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ -#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ -#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ -#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ -#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ -#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ -#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ -#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ -#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ -#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ -#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ -#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */ -#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ -#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ -#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ -#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ -#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ -#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ -#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ -#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */ -#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */ -#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */ -#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */ -#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */ -#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */ -#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ -#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */ -#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */ -#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */ -#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */ -#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ -#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */ -#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */ -#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */ -#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ -#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ -#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ -#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ -#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ -#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ -#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ -#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ -#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ -#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ -#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ -#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ -#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ -#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ - -/*@}*/ /* end of group Renesas_RZ_A1_CPG */ - -/******************************************************************************/ -/* GPIO Settings */ -/******************************************************************************/ -/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions - @{ -*/ - -#define GPIO_BIT_N0 (1u << 0) -#define GPIO_BIT_N1 (1u << 1) -#define GPIO_BIT_N2 (1u << 2) -#define GPIO_BIT_N3 (1u << 3) -#define GPIO_BIT_N4 (1u << 4) -#define GPIO_BIT_N5 (1u << 5) -#define GPIO_BIT_N6 (1u << 6) -#define GPIO_BIT_N7 (1u << 7) -#define GPIO_BIT_N8 (1u << 8) -#define GPIO_BIT_N9 (1u << 9) -#define GPIO_BIT_N10 (1u << 10) -#define GPIO_BIT_N11 (1u << 11) -#define GPIO_BIT_N12 (1u << 12) -#define GPIO_BIT_N13 (1u << 13) -#define GPIO_BIT_N14 (1u << 14) -#define GPIO_BIT_N15 (1u << 15) - - -#define MD_BOOT10_MASK (0x3) - -#define MD_BOOT10_BM0 (0x0) -#define MD_BOOT10_BM1 (0x2) -#define MD_BOOT10_BM3 (0x1) -#define MD_BOOT10_BM4_5 (0x3) - -#define MD_CLK (1u << 2) -#define MD_CLKS (1u << 3) - -/*@}*/ /* end of group Renesas_RZ_A1_GPIO */ - -#ifdef __cplusplus -} -#endif - -#endif // __VKRZA1H_H__ +#include "VK_RZ_A1H.h" diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h index aa64c1d768..701c856fa4 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h @@ -8,5 +8,6 @@ #define MBED_CMSIS_H #include "VKRZA1H.h" +#include "cmsis_nvic.h" #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c index ad6ac0fb8f..1fa680598c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c @@ -29,14 +29,15 @@ ******************************************************************************* */ #include "VKRZA1H.h" +#include "irq_ctrl.h" -extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ InterruptHandlerRegister(IRQn, (IRQHandler)vector); } -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t vectors = (uint32_t)IRQTable[IRQn]; +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn); return vectors; } diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c deleted file mode 100644 index 9c68da0b4f..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c +++ /dev/null @@ -1,305 +0,0 @@ -/**************************************************************************//** - * @file gic.c - * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 19 Sept 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#include "VKRZA1H.h" - -#define GICDistributor ((GICDistributor_Type *) Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */ -#define GICInterface ((GICInterface_Type *) Renesas_RZ_A1_GIC_INTERFACE_BASE ) /*!< GIC Interface configuration struct */ - -/* Globals for use of post-scatterloading code that must access GIC */ -const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE; -const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE; - -void GIC_EnableDistributor(void) -{ - GICDistributor->ICDDCR |= 1; //enable distributor -} - -void GIC_DisableDistributor(void) -{ - GICDistributor->ICDDCR &=~1; //disable distributor -} - -uint32_t GIC_DistributorInfo(void) -{ - return (uint32_t)(GICDistributor->ICDICTR); -} - -uint32_t GIC_DistributorImplementer(void) -{ - return (uint32_t)(GICDistributor->ICDIIDR); -} - -void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - *field = (uint8_t)cpu_target & 0xf; -} - -void GIC_SetICDICFR (const uint32_t *ICDICFRn) -{ - uint32_t i, num_irq; - - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - for (i = 0; i < (num_irq/16); i++) - { - GICDistributor->ICDISPR[i] = *ICDICFRn++; - } -} - -uint32_t GIC_GetTarget(IRQn_Type IRQn) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]); - field += IRQn % 4; - return ((uint32_t)*field & 0xf); -} - -void GIC_EnableInterface(void) -{ - GICInterface->ICCICR |= 1; //enable interface -} - -void GIC_DisableInterface(void) -{ - GICInterface->ICCICR &=~1; //disable distributor -} - -IRQn_Type GIC_AcknowledgePending(void) -{ - return (IRQn_Type)(GICInterface->ICCIAR); -} - -void GIC_EndInterrupt(IRQn_Type IRQn) -{ - GICInterface->ICCEOIR = IRQn; -} - -void GIC_EnableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_DisableIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_SetPendingIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32); -} - -void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]); - int bit_shift = (IRQn % 16)<<1; - uint8_t save_byte; - - field += (bit_shift / 8); - bit_shift %= 8; - - save_byte = *field; - save_byte &= ((uint8_t)~(3u << bit_shift)); - - *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift); -} - -void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += (IRQn % 4); - *field = (uint8_t)priority; -} - -uint32_t GIC_GetPriority(IRQn_Type IRQn) -{ - volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]); - field += (IRQn % 4); - return (uint32_t)*field; -} - -void GIC_InterfacePriorityMask(uint32_t priority) -{ - GICInterface->ICCPMR = priority & 0xff; //set priority mask -} - -void GIC_SetBinaryPoint(uint32_t binary_point) -{ - GICInterface->ICCBPR = binary_point & 0x07; //set binary point -} - -uint32_t GIC_GetBinaryPoint(uint32_t binary_point) -{ - return (uint32_t)GICInterface->ICCBPR; -} - -uint32_t GIC_GetIRQStatus(IRQn_Type IRQn) -{ - uint32_t pending, active; - - active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1; - - return ((active<<1) | pending); -} - -void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list) -{ - GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf); -} - -void GIC_DistInit(void) -{ - //IRQn_Type i; - uint32_t i; - uint32_t num_irq = 0; - uint32_t priority_field; - - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableDistributor(); - //Get the maximum number of interrupts that the GIC supports - num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); - - for (i = 32; i < num_irq; i++) - { - //Disable all SPI the interrupts - GIC_DisableIRQ((IRQn_Type)i); - //Set level-sensitive and N-N model - //GIC_SetLevelModel(i, 0, 0); - //Set priority - GIC_SetPriority((IRQn_Type)i, priority_field/2); - //Set target list to "all cpus" - GIC_SetTarget((IRQn_Type)i, 0xff); - } - /* Set level-edge and 1-N model */ - /* GICDistributor->ICDICFR[ 0] is read only */ - GICDistributor->ICDICFR[ 1] = 0x00000055; - GICDistributor->ICDICFR[ 2] = 0xFFFD5555; - GICDistributor->ICDICFR[ 3] = 0x555FFFFF; - GICDistributor->ICDICFR[ 4] = 0x55555555; - GICDistributor->ICDICFR[ 5] = 0x55555555; - GICDistributor->ICDICFR[ 6] = 0x55555555; - GICDistributor->ICDICFR[ 7] = 0x55555555; - GICDistributor->ICDICFR[ 8] = 0x5555F555; - GICDistributor->ICDICFR[ 9] = 0x55555555; - GICDistributor->ICDICFR[10] = 0x55555555; - GICDistributor->ICDICFR[11] = 0xF5555555; - GICDistributor->ICDICFR[12] = 0xF555F555; - GICDistributor->ICDICFR[13] = 0x5555F555; - GICDistributor->ICDICFR[14] = 0x55555555; - GICDistributor->ICDICFR[15] = 0x55555555; - GICDistributor->ICDICFR[16] = 0x55555555; - GICDistributor->ICDICFR[17] = 0xFD555555; - GICDistributor->ICDICFR[18] = 0x55555557; - GICDistributor->ICDICFR[19] = 0x55555555; - GICDistributor->ICDICFR[20] = 0xFFD55555; - GICDistributor->ICDICFR[21] = 0x5F55557F; - GICDistributor->ICDICFR[22] = 0xFD55555F; - GICDistributor->ICDICFR[23] = 0x55555557; - GICDistributor->ICDICFR[24] = 0x55555555; - GICDistributor->ICDICFR[25] = 0x55555555; - GICDistributor->ICDICFR[26] = 0x55555555; - GICDistributor->ICDICFR[27] = 0x55555555; - GICDistributor->ICDICFR[28] = 0x55555555; - GICDistributor->ICDICFR[29] = 0x55555555; - GICDistributor->ICDICFR[30] = 0x55555555; - GICDistributor->ICDICFR[31] = 0x55555555; - GICDistributor->ICDICFR[32] = 0x55555555; - GICDistributor->ICDICFR[33] = 0x55555555; - - //Enable distributor - GIC_EnableDistributor(); -} - -void GIC_CPUInterfaceInit(void) -{ - IRQn_Type i; - uint32_t priority_field; - - //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0, - //configuring all of the interrupts as Secure. - - //Disable interrupt forwarding - GIC_DisableInterface(); - - /* Priority level is implementation defined. - To determine the number of priority bits implemented write 0xFF to an ICDIPR - priority field and read back the value stored.*/ - GIC_SetPriority((IRQn_Type)0, 0xff); - priority_field = GIC_GetPriority((IRQn_Type)0); - - //SGI and PPI - for (i = (IRQn_Type)0; i < 32; i++) - { - //Set level-sensitive and N-N model for PPI - //if(i > 15) - //GIC_SetLevelModel(i, 0, 0); - //Disable SGI and PPI interrupts - GIC_DisableIRQ(i); - //Set priority - GIC_SetPriority(i, priority_field/2); - } - //Enable interface - GIC_EnableInterface(); - //Set binary point to 0 - GIC_SetBinaryPoint(0); - //Set priority mask - GIC_InterfacePriorityMask(0xff); -} - -void GIC_Enable(void) -{ - GIC_DistInit(); - GIC_CPUInterfaceInit(); //per CPU -} - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h deleted file mode 100644 index d4cbfd81ab..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h +++ /dev/null @@ -1,316 +0,0 @@ -/**************************************************************************//** - * @file gic.h - * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File - * @version - * @date 29 August 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef GIC_H_ -#define GIC_H_ - -/* IO definitions (access restrictions to peripheral registers) */ -/** -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD) - */ -typedef struct -{ - __IO uint32_t ICDDCR; - __I uint32_t ICDICTR; - __I uint32_t ICDIIDR; - uint32_t RESERVED0[29]; - __IO uint32_t ICDISR[32]; - __IO uint32_t ICDISER[32]; - __IO uint32_t ICDICER[32]; - __IO uint32_t ICDISPR[32]; - __IO uint32_t ICDICPR[32]; - __I uint32_t ICDABR[32]; - uint32_t RESERVED1[32]; - __IO uint32_t ICDIPR[256]; - __IO uint32_t ICDIPTR[256]; - __IO uint32_t ICDICFR[64]; - uint32_t RESERVED2[128]; - __IO uint32_t ICDSGIR; -} GICDistributor_Type; - -/** \brief Structure type to access the Controller Interface (GICC) - */ -typedef struct -{ - __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register - __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register - __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register - __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register - __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register - __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register - __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register - __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register - - uint32_t RESERVED[55]; - - __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register -} GICInterface_Type; - -/*@} end of GICD */ - -/* ########################## GIC functions #################################### */ -/** \brief Functions that manage interrupts via the GIC. - @{ - */ - -/** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface - - Enables the forwarding of pending interrupts to the CPU interfaces. - - */ -void GIC_EnableDistributor(void); - -/** \brief Disable Distributor - - Disables the forwarding of pending interrupts to the CPU interfaces. - - */ -void GIC_DisableDistributor(void); - -/** \brief Provides information about the configuration of the GIC. - Provides information about the configuration of the GIC. - - whether the GIC implements the Security Extensions - - the maximum number of interrupt IDs that the GIC supports - - the number of CPU interfaces implemented - - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). - - \return Distributor Information. - */ -uint32_t GIC_DistributorInfo(void); - -/** \brief Distributor Implementer Identification Register. - - Distributor Implementer Identification Register - - \return Implementer Information. - */ -uint32_t GIC_DistributorImplementer(void); - -/** \brief Set list of processors that the interrupt is sent to if it is asserted. - - The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. - This field stores the list of processors that the interrupt is sent to if it is asserted. - - \param [in] IRQn Interrupt number. - \param [in] target CPU target - */ -void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target); - -/** \brief Get list of processors that the interrupt is sent to if it is asserted. - - The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC. - This field stores the list of processors that the interrupt is sent to if it is asserted. - - \param [in] IRQn Interrupt number. - \param [in] target CPU target -*/ -uint32_t GIC_GetTarget(IRQn_Type IRQn); - -/** \brief Enable Interface - - Enables the signalling of interrupts to the target processors. - - */ -void GIC_EnableInterface(void); - -/** \brief Disable Interface - - Disables the signalling of interrupts to the target processors. - - */ -void GIC_DisableInterface(void); - -/** \brief Acknowledge Interrupt - - The function acknowledges the highest priority pending interrupt and returns its IRQ number. - - \return Interrupt number - */ -IRQn_Type GIC_AcknowledgePending(void); - -/** \brief End Interrupt - - The function writes the end of interrupt register, indicating that handling of the interrupt is complete. - - \param [in] IRQn Interrupt number. - */ -void GIC_EndInterrupt(IRQn_Type IRQn); - - -/** \brief Enable Interrupt - - Set-enable bit for each interrupt supported by the GIC. - - \param [in] IRQn External interrupt number. - */ -void GIC_EnableIRQ(IRQn_Type IRQn); - -/** \brief Disable Interrupt - - Clear-enable bit for each interrupt supported by the GIC. - - \param [in] IRQn Number of the external interrupt to disable - */ -void GIC_DisableIRQ(IRQn_Type IRQn); - -/** \brief Set Pending Interrupt - - Set-pending bit for each interrupt supported by the GIC. - - \param [in] IRQn Interrupt number. - */ -void GIC_SetPendingIRQ(IRQn_Type IRQn); - -/** \brief Clear Pending Interrupt - - Clear-pending bit for each interrupt supported by the GIC - - \param [in] IRQn Number of the interrupt for clear pending - */ -void GIC_ClearPendingIRQ(IRQn_Type IRQn); - -/** \brief Int_config field for each interrupt supported by the GIC. - - This field identifies whether the corresponding interrupt is: - (1) edge-triggered or (0) level-sensitive - (1) 1-N model or (0) N-N model - - \param [in] IRQn Interrupt number. - \param [in] edge_level (1) edge-triggered or (0) level-sensitive - \param [in] model (1) 1-N model or (0) N-N model - */ -void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model); - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority); - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - */ -uint32_t GIC_GetPriority(IRQn_Type IRQn); - -/** \brief CPU Interface Priority Mask Register - - The priority mask level for the CPU interface. If the priority of an interrupt is higher than the - value indicated by this field, the interface signals the interrupt to the processor. - - \param [in] Mask. - */ -void GIC_InterfacePriorityMask(uint32_t priority); - -/** \brief Set the binary point. - - Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field. - - \param [in] Mask. - */ -void GIC_SetBinaryPoint(uint32_t binary_point); - -/** \brief Get the binary point. - - Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field. - - \return Binary point. - */ -uint32_t GIC_GetBinaryPoint(uint32_t binary_point); - -/** \brief Get Interrupt state. - - Get the interrupt state, whether pending and/or active - - \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active - */ -uint32_t GIC_GetIRQStatus(IRQn_Type IRQn); - -/** \brief Send Software Generated interrupt - - Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor. -GIC_InterfacePriorityMask - \param [in] IRQn The Interrupt ID of the SGI. - \param [in] target_list CPUTargetList - \param [in] filter_list TargetListFilter - */ -void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list); - -/** \brief API call to initialise the interrupt distributor - - API call to initialise the interrupt distributor - - */ -void GIC_DistInit(void); - -/** \brief API call to initialise the CPU interface - - API call to initialise the CPU interface - - */ -void GIC_CPUInterfaceInit(void); - -/** \brief API call to set the Interrupt Configuration Registers - - API call to initialise the Interrupt Configuration Registers - - */ -void GIC_SetICDICFR (const uint32_t *ICDICFRn); - -/** \brief API call to Enable the GIC - - API call to Enable the GIC - - */ -void GIC_Enable(void); - -#endif /* GIC_H_ */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h new file mode 100644 index 0000000000..faca6ce56c --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h @@ -0,0 +1,922 @@ +/****************************************************************************** + * @file VK_RZ_A1H.h + * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File + * @version V1.00 + * @data 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __VK_RZ_A1H_H__ +#define __VK_RZ_A1H_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ +/****** SGI Interrupts Numbers ****************************************/ + SGI0_IRQn = 0, + SGI1_IRQn = 1, + SGI2_IRQn = 2, + SGI3_IRQn = 3, + SGI4_IRQn = 4, + SGI5_IRQn = 5, + SGI6_IRQn = 6, + SGI7_IRQn = 7, + SGI8_IRQn = 8, + SGI9_IRQn = 9, + SGI10_IRQn = 10, + SGI11_IRQn = 11, + SGI12_IRQn = 12, + SGI13_IRQn = 13, + SGI14_IRQn = 14, + SGI15_IRQn = 15, + +/****** Cortex-A9 Processor Exceptions Numbers ****************************************/ + /* 16 - 578 */ + PMUIRQ0_IRQn = 16, + COMMRX0_IRQn = 17, + COMMTX0_IRQn = 18, + CTIIRQ0_IRQn = 19, + + IRQ0_IRQn = 32, + IRQ1_IRQn = 33, + IRQ2_IRQn = 34, + IRQ3_IRQn = 35, + IRQ4_IRQn = 36, + IRQ5_IRQn = 37, + IRQ6_IRQn = 38, + IRQ7_IRQn = 39, + + PL310ERR_IRQn = 40, + + DMAINT0_IRQn = 41, /*!< DMAC Interrupt */ + DMAINT1_IRQn = 42, /*!< DMAC Interrupt */ + DMAINT2_IRQn = 43, /*!< DMAC Interrupt */ + DMAINT3_IRQn = 44, /*!< DMAC Interrupt */ + DMAINT4_IRQn = 45, /*!< DMAC Interrupt */ + DMAINT5_IRQn = 46, /*!< DMAC Interrupt */ + DMAINT6_IRQn = 47, /*!< DMAC Interrupt */ + DMAINT7_IRQn = 48, /*!< DMAC Interrupt */ + DMAINT8_IRQn = 49, /*!< DMAC Interrupt */ + DMAINT9_IRQn = 50, /*!< DMAC Interrupt */ + DMAINT10_IRQn = 51, /*!< DMAC Interrupt */ + DMAINT11_IRQn = 52, /*!< DMAC Interrupt */ + DMAINT12_IRQn = 53, /*!< DMAC Interrupt */ + DMAINT13_IRQn = 54, /*!< DMAC Interrupt */ + DMAINT14_IRQn = 55, /*!< DMAC Interrupt */ + DMAINT15_IRQn = 56, /*!< DMAC Interrupt */ + DMAERR_IRQn = 57, /*!< DMAC Interrupt */ + + /* 58-72 Reserved */ + + USBI0_IRQn = 73, + USBI1_IRQn = 74, + + S0_VI_VSYNC0_IRQn = 75, + S0_LO_VSYNC0_IRQn = 76, + S0_VSYNCERR0_IRQn = 77, + GR3_VLINE0_IRQn = 78, + S0_VFIELD0_IRQn = 79, + IV1_VBUFERR0_IRQn = 80, + IV3_VBUFERR0_IRQn = 81, + IV5_VBUFERR0_IRQn = 82, + IV6_VBUFERR0_IRQn = 83, + S0_WLINE0_IRQn = 84, + S1_VI_VSYNC0_IRQn = 85, + S1_LO_VSYNC0_IRQn = 86, + S1_VSYNCERR0_IRQn = 87, + S1_VFIELD0_IRQn = 88, + IV2_VBUFERR0_IRQn = 89, + IV4_VBUFERR0_IRQn = 90, + S1_WLINE0_IRQn = 91, + OIR_VI_VSYNC0_IRQn = 92, + OIR_LO_VSYNC0_IRQn = 93, + OIR_VSYNCERR0_IRQn = 94, + OIR_VFIELD0_IRQn = 95, + IV7_VBUFERR0_IRQn = 96, + IV8_VBUFERR0_IRQn = 97, + /* 98 Reserved */ + S0_VI_VSYNC1_IRQn = 99, + S0_LO_VSYNC1_IRQn = 100, + S0_VSYNCERR1_IRQn = 101, + GR3_VLINE1_IRQn = 102, + S0_VFIELD1_IRQn = 103, + IV1_VBUFERR1_IRQn = 104, + IV3_VBUFERR1_IRQn = 105, + IV5_VBUFERR1_IRQn = 106, + IV6_VBUFERR1_IRQn = 107, + S0_WLINE1_IRQn = 108, + S1_VI_VSYNC1_IRQn = 109, + S1_LO_VSYNC1_IRQn = 110, + S1_VSYNCERR1_IRQn = 111, + S1_VFIELD1_IRQn = 112, + IV2_VBUFERR1_IRQn = 113, + IV4_VBUFERR1_IRQn = 114, + S1_WLINE1_IRQn = 115, + OIR_VI_VSYNC1_IRQn = 116, + OIR_LO_VSYNC1_IRQn = 117, + OIR_VSYNCERR1_IRQn = 118, + OIR_VFIELD1_IRQn = 119, + IV7_VBUFERR1_IRQn = 120, + IV8_VBUFERR1_IRQn = 121, + /* Reserved = 122 */ + + IMRDI_IRQn = 123, + IMR2I0_IRQn = 124, + IMR2I1_IRQn = 125, + + JEDI_IRQn = 126, + JDTI_IRQn = 127, + + CMP0_IRQn = 128, + CMP1_IRQn = 129, + + INT0_IRQn = 130, + INT1_IRQn = 131, + INT2_IRQn = 132, + INT3_IRQn = 133, + + OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */ + OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */ + + CMI_IRQn = 136, + WTOUT_IRQn = 137, + + ITI_IRQn = 138, + + TGI0A_IRQn = 139, + TGI0B_IRQn = 140, + TGI0C_IRQn = 141, + TGI0D_IRQn = 142, + TGI0V_IRQn = 143, + TGI0E_IRQn = 144, + TGI0F_IRQn = 145, + TGI1A_IRQn = 146, + TGI1B_IRQn = 147, + TGI1V_IRQn = 148, + TGI1U_IRQn = 149, + TGI2A_IRQn = 150, + TGI2B_IRQn = 151, + TGI2V_IRQn = 152, + TGI2U_IRQn = 153, + TGI3A_IRQn = 154, + TGI3B_IRQn = 155, + TGI3C_IRQn = 156, + TGI3D_IRQn = 157, + TGI3V_IRQn = 158, + TGI4A_IRQn = 159, + TGI4B_IRQn = 160, + TGI4C_IRQn = 161, + TGI4D_IRQn = 162, + TGI4V_IRQn = 163, + + CMI1_IRQn = 164, + CMI2_IRQn = 165, + + SGDEI0_IRQn = 166, + SGDEI1_IRQn = 167, + SGDEI2_IRQn = 168, + SGDEI3_IRQn = 169, + + ADI_IRQn = 170, + LMTI_IRQn = 171, + + SSII0_IRQn = 172, /*!< SSIF Interrupt */ + SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */ + SSITXI0_IRQn = 174, /*!< SSIF Interrupt */ + SSII1_IRQn = 175, /*!< SSIF Interrupt */ + SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */ + SSITXI1_IRQn = 177, /*!< SSIF Interrupt */ + SSII2_IRQn = 178, /*!< SSIF Interrupt */ + SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */ + SSII3_IRQn = 180, /*!< SSIF Interrupt */ + SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */ + SSITXI3_IRQn = 182, /*!< SSIF Interrupt */ + SSII4_IRQn = 183, /*!< SSIF Interrupt */ + SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */ + SSII5_IRQn = 185, /*!< SSIF Interrupt */ + SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */ + SSITXI5_IRQn = 187, /*!< SSIF Interrupt */ + + SPDIFI_IRQn = 188, + + INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */ + INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */ + INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */ + INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */ + INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */ + INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */ + INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */ + INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */ + INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */ + INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */ + INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */ + INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */ + INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */ + INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */ + INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */ + INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */ + INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */ + INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */ + INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */ + INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */ + INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */ + INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */ + INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */ + INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */ + INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */ + INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */ + INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */ + INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */ + INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */ + INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */ + INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */ + INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */ + + SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */ + SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */ + SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */ + SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */ + SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */ + SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */ + SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */ + SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */ + SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */ + SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */ + SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */ + SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */ + SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */ + SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */ + SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */ + SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */ + SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */ + SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */ + SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */ + SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */ + SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */ + SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */ + SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */ + SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */ + SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */ + SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */ + SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */ + SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */ + SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */ + SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */ + SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */ + SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */ + + INTRCANGERR_IRQn = 253, + INTRCANGRECC_IRQn = 254, + INTRCAN0REC_IRQn = 255, + INTRCAN0ERR_IRQn = 256, + INTRCAN0TRX_IRQn = 257, + INTRCAN1REC_IRQn = 258, + INTRCAN1ERR_IRQn = 259, + INTRCAN1TRX_IRQn = 260, + INTRCAN2REC_IRQn = 261, + INTRCAN2ERR_IRQn = 262, + INTRCAN2TRX_IRQn = 263, + INTRCAN3REC_IRQn = 264, + INTRCAN3ERR_IRQn = 265, + INTRCAN3TRX_IRQn = 266, + INTRCAN4REC_IRQn = 267, + INTRCAN4ERR_IRQn = 268, + INTRCAN4TRX_IRQn = 269, + + RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */ + RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */ + RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */ + RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */ + RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */ + RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */ + RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */ + RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */ + RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */ + RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */ + RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */ + RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */ + RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */ + RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */ + RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */ + + IEBBTD_IRQn = 285, + IEBBTERR_IRQn = 286, + IEBBTSTA_IRQn = 287, + IEBBTV_IRQn = 288, + + ISY_IRQn = 289, + IERR_IRQn = 290, + ITARG_IRQn = 291, + ISEC_IRQn = 292, + IBUF_IRQn = 293, + IREADY_IRQn = 294, + + STERB_IRQn = 295, + FLTENDI_IRQn = 296, + FLTREQ0I_IRQn = 297, + FLTREQ1I_IRQn = 298, + + MMC0_IRQn = 299, + MMC1_IRQn = 300, + MMC2_IRQn = 301, + + SCHI0_3_IRQn = 302, + SDHI0_0_IRQn = 303, + SDHI0_1_IRQn = 304, + SCHI1_3_IRQn = 305, + SDHI1_0_IRQn = 306, + SDHI1_1_IRQn = 307, + + ARM_IRQn = 308, + PRD_IRQn = 309, + CUP_IRQn = 310, + + SCUAI0_IRQn = 311, + SCUAI1_IRQn = 312, + SCUFDI0_IRQn = 313, + SCUFDI1_IRQn = 314, + SCUFDI2_IRQn = 315, + SCUFDI3_IRQn = 316, + SCUFUI0_IRQn = 317, + SCUFUI1_IRQn = 318, + SCUFUI2_IRQn = 319, + SCUFUI3_IRQn = 320, + SCUDVI0_IRQn = 321, + SCUDVI1_IRQn = 322, + SCUDVI2_IRQn = 323, + SCUDVI3_IRQn = 324, + + MLB_CINT_IRQn = 325, + MLB_SINT_IRQn = 326, + + DRC10_IRQn = 327, + DRC11_IRQn = 328, + + /* 329-330 Reserved */ + + LINI0_INT_T_IRQn = 331, + LINI0_INT_R_IRQn = 332, + LINI0_INT_S_IRQn = 333, + LINI0_INT_M_IRQn = 334, + LINI1_INT_T_IRQn = 335, + LINI1_INT_R_IRQn = 336, + LINI1_INT_S_IRQn = 337, + LINI1_INT_M_IRQn = 338, + + /* 339-346 Reserved */ + + SCIERI0_IRQn = 347, + SCIRXI0_IRQn = 348, + SCITXI0_IRQn = 349, + SCITEI0_IRQn = 350, + SCIERI1_IRQn = 351, + SCIRXI1_IRQn = 352, + SCITXI1_IRQn = 353, + SCITEI1_IRQn = 354, + + AVBI_DATA = 355, + AVBI_ERROR = 356, + AVBI_MANAGE = 357, + AVBI_MAC = 358, + + ETHERI_IRQn = 359, + + /* 360-363 Reserved */ + + CEUI_IRQn = 364, + + /* 365-380 Reserved */ + + H2XMLB_ERRINT_IRQn = 381, + H2XIC1_ERRINT_IRQn = 382, + X2HPERI1_ERRINT_IRQn = 383, + X2HPERR2_ERRINT_IRQn = 384, + X2HPERR34_ERRINT_IRQn= 385, + X2HPERR5_ERRINT_IRQn = 386, + X2HPERR67_ERRINT_IRQn= 387, + X2HDBGR_ERRINT_IRQn = 388, + X2HBSC_ERRINT_IRQn = 389, + X2HSPI1_ERRINT_IRQn = 390, + X2HSPI2_ERRINT_IRQn = 391, + PRRI_IRQn = 392, + + IFEI0_IRQn = 393, + OFFI0_IRQn = 394, + PFVEI0_IRQn = 395, + IFEI1_IRQn = 396, + OFFI1_IRQn = 397, + PFVEI1_IRQn = 398, + + /* 399-415 Reserved */ + + TINT0_IRQn = 416, + TINT1_IRQn = 417, + TINT2_IRQn = 418, + TINT3_IRQn = 419, + TINT4_IRQn = 420, + TINT5_IRQn = 421, + TINT6_IRQn = 422, + TINT7_IRQn = 423, + TINT8_IRQn = 424, + TINT9_IRQn = 425, + TINT10_IRQn = 426, + TINT11_IRQn = 427, + TINT12_IRQn = 428, + TINT13_IRQn = 429, + TINT14_IRQn = 430, + TINT15_IRQn = 431, + TINT16_IRQn = 432, + TINT17_IRQn = 433, + TINT18_IRQn = 434, + TINT19_IRQn = 435, + TINT20_IRQn = 436, + TINT21_IRQn = 437, + TINT22_IRQn = 438, + TINT23_IRQn = 439, + TINT24_IRQn = 440, + TINT25_IRQn = 441, + TINT26_IRQn = 442, + TINT27_IRQn = 443, + TINT28_IRQn = 444, + TINT29_IRQn = 445, + TINT30_IRQn = 446, + TINT31_IRQn = 447, + TINT32_IRQn = 448, + TINT33_IRQn = 449, + TINT34_IRQn = 450, + TINT35_IRQn = 451, + TINT36_IRQn = 452, + TINT37_IRQn = 453, + TINT38_IRQn = 454, + TINT39_IRQn = 455, + TINT40_IRQn = 456, + TINT41_IRQn = 457, + TINT42_IRQn = 458, + TINT43_IRQn = 459, + TINT44_IRQn = 460, + TINT45_IRQn = 461, + TINT46_IRQn = 462, + TINT47_IRQn = 463, + TINT48_IRQn = 464, + TINT49_IRQn = 465, + TINT50_IRQn = 466, + TINT51_IRQn = 467, + TINT52_IRQn = 468, + TINT53_IRQn = 469, + TINT54_IRQn = 470, + TINT55_IRQn = 471, + TINT56_IRQn = 472, + TINT57_IRQn = 473, + TINT58_IRQn = 474, + TINT59_IRQn = 475, + TINT60_IRQn = 476, + TINT61_IRQn = 477, + TINT62_IRQn = 478, + TINT63_IRQn = 479, + TINT64_IRQn = 480, + TINT65_IRQn = 481, + TINT66_IRQn = 482, + TINT67_IRQn = 483, + TINT68_IRQn = 484, + TINT69_IRQn = 485, + TINT70_IRQn = 486, + TINT71_IRQn = 487, + TINT72_IRQn = 488, + TINT73_IRQn = 489, + TINT74_IRQn = 490, + TINT75_IRQn = 491, + TINT76_IRQn = 492, + TINT77_IRQn = 493, + TINT78_IRQn = 494, + TINT79_IRQn = 495, + TINT80_IRQn = 496, + TINT81_IRQn = 497, + TINT82_IRQn = 498, + TINT83_IRQn = 499, + TINT84_IRQn = 500, + TINT85_IRQn = 501, + TINT86_IRQn = 502, + TINT87_IRQn = 503, + TINT88_IRQn = 504, + TINT89_IRQn = 505, + TINT90_IRQn = 506, + TINT91_IRQn = 507, + TINT92_IRQn = 508, + TINT93_IRQn = 509, + TINT94_IRQn = 510, + TINT95_IRQn = 511, + TINT96_IRQn = 512, + TINT97_IRQn = 513, + TINT98_IRQn = 514, + TINT99_IRQn = 515, + TINT100_IRQn = 516, + TINT101_IRQn = 517, + TINT102_IRQn = 518, + TINT103_IRQn = 519, + TINT104_IRQn = 520, + TINT105_IRQn = 521, + TINT106_IRQn = 522, + TINT107_IRQn = 523, + TINT108_IRQn = 524, + TINT109_IRQn = 525, + TINT110_IRQn = 526, + TINT111_IRQn = 527, + TINT112_IRQn = 528, + TINT113_IRQn = 529, + TINT114_IRQn = 530, + TINT115_IRQn = 531, + TINT116_IRQn = 532, + TINT117_IRQn = 533, + TINT118_IRQn = 534, + TINT119_IRQn = 535, + TINT120_IRQn = 536, + TINT121_IRQn = 537, + TINT122_IRQn = 538, + TINT123_IRQn = 539, + TINT124_IRQn = 540, + TINT125_IRQn = 541, + TINT126_IRQn = 542, + TINT127_IRQn = 543, + TINT128_IRQn = 544, + TINT129_IRQn = 545, + TINT130_IRQn = 546, + TINT131_IRQn = 547, + TINT132_IRQn = 548, + TINT133_IRQn = 549, + TINT134_IRQn = 550, + TINT135_IRQn = 551, + TINT136_IRQn = 552, + TINT137_IRQn = 553, + TINT138_IRQn = 554, + TINT139_IRQn = 555, + TINT140_IRQn = 556, + TINT141_IRQn = 557, + TINT142_IRQn = 558, + TINT143_IRQn = 559, + TINT144_IRQn = 560, + TINT145_IRQn = 561, + TINT146_IRQn = 562, + TINT147_IRQn = 563, + TINT148_IRQn = 564, + TINT149_IRQn = 565, + TINT150_IRQn = 566, + TINT151_IRQn = 567, + TINT152_IRQn = 568, + TINT153_IRQn = 569, + TINT154_IRQn = 570, + TINT155_IRQn = 571, + TINT156_IRQn = 572, + TINT157_IRQn = 573, + TINT158_IRQn = 574, + TINT159_IRQn = 575, + TINT160_IRQn = 576, + TINT161_IRQn = 577, + TINT162_IRQn = 578, + TINT163_IRQn = 579, + TINT164_IRQn = 580, + TINT165_IRQn = 581, + TINT166_IRQn = 582, + TINT167_IRQn = 583, + TINT168_IRQn = 584, + TINT169_IRQn = 585, + TINT170_IRQn = 586 + +} IRQn_Type; + +#define RZ_A1_IRQ_MAX TINT170_IRQn + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ + +#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */ +#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */ +#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */ +#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */ +#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */ +#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */ +#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */ +#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ +#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ +#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ +#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ +#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */ +#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */ +#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */ +#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */ +#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */ +#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE +#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE +#define L2C_310_BASE RZ_A1_PL310_BASE +#define TIMER_BASE RZ_A1_PRIVATE_TIMER + +/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */ +#define __CA_REV 0x0000U /*!< Core revision r0p0 */ +#define __CORTEX_A 9U /*!< Cortex-A9 Core */ +#if (__FPU_PRESENT != 1) +#undef __FPU_PRESENT +#define __FPU_PRESENT 1U /* FPU present */ +#endif +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca.h" +#include "nvic_wrapper.h" +#include +#include "iodefine.h" + +/******************************************************************************/ +/* Clock Settings */ +/******************************************************************************/ +/* + * Clock Mode 0 settings + * SW1-4(MD_CLK):ON + * SW1-5(MD_CLKS):ON + * FRQCR=0x1035 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =00b - CPU clock is 1/1 PLL clock + * FRQCR2=0x0001 + * GFC[1:0] =01b - Graphic clock is 2/3 bus clock + */ +#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u) +#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u) +#define CM0_RENESAS_RZ_A1_I_CLK (400000000u) +#define CM0_RENESAS_RZ_A1_G_CLK (266666666u) +#define CM0_RENESAS_RZ_A1_B_CLK (133333333u) +#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u) +#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) + +/* + * Clock Mode 1 settings + * SW1-4(MD_CLK):OFF + * SW1-5(MD_CLKS):ON + * FRQCR=0x1335 + * CLKEN2 = 0b - unstable + * CLKEN[1:0]=01b - Output, Low, Low + * IFC[1:0] =11b - CPU clock is 1/3 PLL clock + * FRQCR2=0x0003 + * GFC[1:0] =11b - graphic clock is 1/3 bus clock + */ +#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u) +#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u) +#define CM1_RENESAS_RZ_A1_I_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_G_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_B_CLK (128000000u) +#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u) +#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) + +/******************************************************************************/ +/* CPG Settings */ +/******************************************************************************/ +#define CPG_FRQCR_SHIFT_CKOEN2 (14) +#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2) +#define CPG_FRQCR_SHIFT_CKOEN0 (12) +#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0) +#define CPG_FRQCR_SHIFT_IFC (8) +#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC) + +#define CPG_FRQCR2_SHIFT_GFC (0) +#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC) + + +#define CPG_STBCR1_BIT_STBY (0x80u) +#define CPG_STBCR1_BIT_DEEP (0x40u) +#define CPG_STBCR2_BIT_HIZ (0x80u) +#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */ +#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */ +#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */ +#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */ +#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */ +#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */ +#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */ +#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */ +#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */ +#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */ +#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */ +#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */ +#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */ +#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */ +#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */ +#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */ +#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */ +#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */ +#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */ +#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */ +#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */ +#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */ +#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */ +#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ +#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ +#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */ +#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */ +#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */ +#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */ +#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */ +#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */ +#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */ +#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */ +#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */ +#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */ +#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */ +#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */ +#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */ +#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */ +#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */ +#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */ +#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */ +#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */ +#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */ +#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */ +#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */ +#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */ +#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */ +#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */ +#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */ +#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */ +#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */ +#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */ +#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */ +#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */ +#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */ +#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */ +#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */ +#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */ +#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */ +#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */ +#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */ +#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */ +#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */ +#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */ +#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */ +#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */ +#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */ +#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */ +#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */ +#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */ +#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */ +#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */ +#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */ +#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */ +#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */ +#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */ +#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */ +#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */ +#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */ +#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */ +#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */ +#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */ +#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */ +#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */ +#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */ +#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */ +#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */ +#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */ +#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */ +#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */ +#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */ +#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */ +#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */ +#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */ +#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */ +#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */ +#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */ +#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */ +#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */ +#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */ +#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */ +#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */ +#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */ +#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */ +#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */ +#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */ +#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */ +#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */ +#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */ +#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */ +#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */ +#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */ +#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */ +#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */ +#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */ +#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */ +#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */ +#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */ +#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */ +#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */ +#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */ +#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */ +#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */ +#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */ +#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */ +#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */ +#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */ +#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */ +#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */ +#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */ +#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */ +#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */ +#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */ +#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */ +#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */ +#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */ +#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */ +#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */ +#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */ +#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */ +#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */ +#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */ +#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */ +#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */ +#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */ +#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */ +#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */ +#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */ +#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */ +#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */ +#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */ +#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */ +#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */ +#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */ +#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */ +#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */ +#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */ +#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */ +#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */ +#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */ +#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */ +#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */ +#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */ +#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */ +#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */ +#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */ +#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */ +#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */ +#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */ + +/******************************************************************************/ +/* GPIO Settings */ +/******************************************************************************/ +#define GPIO_BIT_N0 (1u << 0) +#define GPIO_BIT_N1 (1u << 1) +#define GPIO_BIT_N2 (1u << 2) +#define GPIO_BIT_N3 (1u << 3) +#define GPIO_BIT_N4 (1u << 4) +#define GPIO_BIT_N5 (1u << 5) +#define GPIO_BIT_N6 (1u << 6) +#define GPIO_BIT_N7 (1u << 7) +#define GPIO_BIT_N8 (1u << 8) +#define GPIO_BIT_N9 (1u << 9) +#define GPIO_BIT_N10 (1u << 10) +#define GPIO_BIT_N11 (1u << 11) +#define GPIO_BIT_N12 (1u << 12) +#define GPIO_BIT_N13 (1u << 13) +#define GPIO_BIT_N14 (1u << 14) +#define GPIO_BIT_N15 (1u << 15) + +#define MD_BOOT10_MASK (0x3) + +#define MD_BOOT10_BM0 (0x0) +#define MD_BOOT10_BM1 (0x2) +#define MD_BOOT10_BM3 (0x1) +#define MD_BOOT10_BM4_5 (0x3) + +#define MD_CLK (1u << 2) +#define MD_CLKS (1u << 3) + + +#ifdef __cplusplus +} +#endif + +#endif // __VK_RZ_A1H_H__ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h index 2d18559982..d01d74b0e6 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h @@ -18,119 +18,56 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ -#ifndef R7S72100_IODEFINE_H -#define R7S72100_IODEFINE_H -#define IODEFINE_H_VERSION 100 +#ifndef R7S721000_IODEFINE_H +#define R7S721000_IODEFINE_H -enum iodefine_byte_select_t -{ - L = 0, H = 1, - LL= 0, LH = 1, HL = 2, HH = 3 -}; +#include "iodefines/iodefine_typedef.h" /* (V2.00h) */ -/*********************************************************************** - <<< [iodefine_reg32_t] >>> -- Padding : sizeof(iodefine_reg32_t) == 4 -- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -- &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg32_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ - volatile uint8_t UINT8[4]; /* 8-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - -/*********************************************************************** - <<< [iodefine_reg32_16_t] >>> -- Padding : sizeof(iodefine_reg32_16_t) == 4 -- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg32_16_t -{ - volatile uint32_t UINT32; /* 32-bit Access */ - volatile uint16_t UINT16[2]; /* 16-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - -/*********************************************************************** - <<< [iodefine_reg16_8_t] >>> -- Padding : sizeof(iodefine_reg16_8_t) == 2 -- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 -- Endian : Independent (Same as CPU endian as register endian) -- Bit-Order : Independent -************************************************************************/ -/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ -/* ->SEC M1.10.1 : Not magic number */ -union iodefine_reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -}; -/* <-SEC M1.10.1 */ -/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ - - - - - - -#include "adc_iodefine.h" /* (V1.00a) */ -#include "bsc_iodefine.h" /* (V1.00a) */ -#include "ceu_iodefine.h" /* (V1.00a) */ -#include "cpg_iodefine.h" /* (V1.00a) */ -#include "disc_iodefine.h" /* (V1.00a) */ -#include "dmac_iodefine.h" /* (V1.00a) */ -#include "dvdec_iodefine.h" /* (V1.00a) */ -#include "ether_iodefine.h" /* (V1.00a) */ -#include "flctl_iodefine.h" /* (V1.00a) */ -#include "gpio_iodefine.h" /* (V1.00a) */ -#include "ieb_iodefine.h" /* (V1.00a) */ -#include "inb_iodefine.h" /* (V1.00a) */ -#include "intc_iodefine.h" /* (V1.00a) */ -#include "irda_iodefine.h" /* (V1.00a) */ -#include "jcu_iodefine.h" /* (V1.00a) */ -#include "l2c_iodefine.h" /* (V1.00a) */ -#include "lin_iodefine.h" /* (V1.00a) */ -#include "lvds_iodefine.h" /* (V1.00a) */ -#include "mlb_iodefine.h" /* (V1.00a) */ -#include "mmc_iodefine.h" /* (V1.00a) */ -#include "mtu2_iodefine.h" /* (V1.00a) */ -#include "ostm_iodefine.h" /* (V1.00a) */ -#include "pfv_iodefine.h" /* (V1.00a) */ -#include "pwm_iodefine.h" /* (V1.00a) */ -#include "riic_iodefine.h" /* (V1.00a) */ -#include "romdec_iodefine.h" /* (V1.00a) */ -#include "rscan0_iodefine.h" /* (V1.00a) */ -#include "rspi_iodefine.h" /* (V1.00a) */ -#include "rtc_iodefine.h" /* (V1.00a) */ -#include "scif_iodefine.h" /* (V1.00a) */ -#include "scim_iodefine.h" /* (V1.00a) */ -#include "scux_iodefine.h" /* (V1.00a) */ -#include "sdg_iodefine.h" /* (V1.00a) */ -#include "spdif_iodefine.h" /* (V1.00a) */ -#include "spibsc_iodefine.h" /* (V1.00a) */ -#include "ssif_iodefine.h" /* (V1.00a) */ -#include "usb20_iodefine.h" /* (V1.00a) */ -#include "vdc5_iodefine.h" /* (V1.00a) */ -#include "wdt_iodefine.h" /* (V1.00a) */ +#include "iodefines/adc_iodefine.h" /* (V2.00h) */ +#include "iodefines/bsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ceu_iodefine.h" /* (V2.00h) */ +#include "iodefines/cpg_iodefine.h" /* (V2.00h) */ +#include "iodefines/disc_iodefine.h" /* (V2.00h) */ +#include "iodefines/dmac_iodefine.h" /* (V2.00h) */ +#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/ether_iodefine.h" /* (V2.00h) */ +#include "iodefines/flctl_iodefine.h" /* (V2.00h) */ +#include "iodefines/gpio_iodefine.h" /* (V2.00h) */ +#include "iodefines/ieb_iodefine.h" /* (V2.00h) */ +#include "iodefines/inb_iodefine.h" /* (V2.00h) */ +#include "iodefines/intc_iodefine.h" /* (V2.00h) */ +#include "iodefines/irda_iodefine.h" /* (V2.00h) */ +#include "iodefines/jcu_iodefine.h" /* (V2.00h) */ +#include "iodefines/l2c_iodefine.h" /* (V2.00h) */ +#include "iodefines/lin_iodefine.h" /* (V2.00h) */ +#include "iodefines/lvds_iodefine.h" /* (V2.00h) */ +#include "iodefines/mlb_iodefine.h" /* (V2.00h) */ +#include "iodefines/mmc_iodefine.h" /* (V2.00h) */ +#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */ +#include "iodefines/ostm_iodefine.h" /* (V2.00h) */ +#include "iodefines/pfv_iodefine.h" /* (V2.00h) */ +#include "iodefines/pwm_iodefine.h" /* (V2.00h) */ +#include "iodefines/riic_iodefine.h" /* (V2.00h) */ +#include "iodefines/romdec_iodefine.h" /* (V2.00h) */ +#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */ +#include "iodefines/rspi_iodefine.h" /* (V2.00h) */ +#include "iodefines/rtc_iodefine.h" /* (V2.00h) */ +#include "iodefines/scif_iodefine.h" /* (V2.00h) */ +#include "iodefines/scim_iodefine.h" /* (V2.00h) */ +#include "iodefines/scux_iodefine.h" /* (V2.00h) */ +#include "iodefines/sdg_iodefine.h" /* (V2.00h) */ +#include "iodefines/spdif_iodefine.h" /* (V2.00h) */ +#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */ +#include "iodefines/ssif_iodefine.h" /* (V2.00h) */ +#include "iodefines/usb20_iodefine.h" /* (V2.00h) */ +#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */ +#include "iodefines/wdt_iodefine.h" /* (V2.00h) */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h index 55bc7ddd26..a16183efcc 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h @@ -18,20 +18,56 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : adc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ADC_IODEFINE_H #define ADC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_adc -{ /* ADC */ +#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ + + +#define ADCADDRA (ADC.ADDRA) +#define ADCADDRB (ADC.ADDRB) +#define ADCADDRC (ADC.ADDRC) +#define ADCADDRD (ADC.ADDRD) +#define ADCADDRE (ADC.ADDRE) +#define ADCADDRF (ADC.ADDRF) +#define ADCADDRG (ADC.ADDRG) +#define ADCADDRH (ADC.ADDRH) +#define ADCADCMPHA (ADC.ADCMPHA) +#define ADCADCMPLA (ADC.ADCMPLA) +#define ADCADCMPHB (ADC.ADCMPHB) +#define ADCADCMPLB (ADC.ADCMPLB) +#define ADCADCMPHC (ADC.ADCMPHC) +#define ADCADCMPLC (ADC.ADCMPLC) +#define ADCADCMPHD (ADC.ADCMPHD) +#define ADCADCMPLD (ADC.ADCMPLD) +#define ADCADCMPHE (ADC.ADCMPHE) +#define ADCADCMPLE (ADC.ADCMPLE) +#define ADCADCMPHF (ADC.ADCMPHF) +#define ADCADCMPLF (ADC.ADCMPLF) +#define ADCADCMPHG (ADC.ADCMPHG) +#define ADCADCMPLG (ADC.ADCMPLG) +#define ADCADCMPHH (ADC.ADCMPHH) +#define ADCADCMPLH (ADC.ADCMPLH) +#define ADCADCSR (ADC.ADCSR) +#define ADCADCMPER (ADC.ADCMPER) +#define ADCADCMPSR (ADC.ADCMPSR) + + +typedef struct st_adc +{ + /* ADC */ volatile uint16_t ADDRA; /* ADDRA */ volatile uint16_t ADDRB; /* ADDRB */ volatile uint16_t ADDRC; /* ADDRC */ @@ -61,38 +97,11 @@ struct st_adc volatile uint16_t ADCSR; /* ADCSR */ volatile uint16_t ADCMPER; /* ADCMPER */ volatile uint16_t ADCMPSR; /* ADCMPSR */ -}; +} r_io_adc_t; -#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */ - - -#define ADCADDRA ADC.ADDRA -#define ADCADDRB ADC.ADDRB -#define ADCADDRC ADC.ADDRC -#define ADCADDRD ADC.ADDRD -#define ADCADDRE ADC.ADDRE -#define ADCADDRF ADC.ADDRF -#define ADCADDRG ADC.ADDRG -#define ADCADDRH ADC.ADDRH -#define ADCADCMPHA ADC.ADCMPHA -#define ADCADCMPLA ADC.ADCMPLA -#define ADCADCMPHB ADC.ADCMPHB -#define ADCADCMPLB ADC.ADCMPLB -#define ADCADCMPHC ADC.ADCMPHC -#define ADCADCMPLC ADC.ADCMPLC -#define ADCADCMPHD ADC.ADCMPHD -#define ADCADCMPLD ADC.ADCMPLD -#define ADCADCMPHE ADC.ADCMPHE -#define ADCADCMPLE ADC.ADCMPLE -#define ADCADCMPHF ADC.ADCMPHF -#define ADCADCMPLF ADC.ADCMPLF -#define ADCADCMPHG ADC.ADCMPHG -#define ADCADCMPLG ADC.ADCMPLG -#define ADCADCMPHH ADC.ADCMPHH -#define ADCADCMPLH ADC.ADCMPLH -#define ADCADCSR ADC.ADCSR -#define ADCADCMPER ADC.ADCMPER -#define ADCADCMPSR ADC.ADCMPSR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h index 0d327ac760..6665787ee7 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h @@ -18,22 +18,61 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : bsc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef BSC_IODEFINE_H #define BSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_bsc -{ /* BSC */ +#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ + + +#define BSCCMNCR (BSC.CMNCR) +#define BSCCS0BCR (BSC.CS0BCR) +#define BSCCS1BCR (BSC.CS1BCR) +#define BSCCS2BCR (BSC.CS2BCR) +#define BSCCS3BCR (BSC.CS3BCR) +#define BSCCS4BCR (BSC.CS4BCR) +#define BSCCS5BCR (BSC.CS5BCR) +#define BSCCS0WCR (BSC.CS0WCR) +#define BSCCS1WCR (BSC.CS1WCR) +#define BSCCS2WCR (BSC.CS2WCR) +#define BSCCS3WCR (BSC.CS3WCR) +#define BSCCS4WCR (BSC.CS4WCR) +#define BSCCS5WCR (BSC.CS5WCR) +#define BSCSDCR (BSC.SDCR) +#define BSCRTCSR (BSC.RTCSR) +#define BSCRTCNT (BSC.RTCNT) +#define BSCRTCOR (BSC.RTCOR) +#define BSCTOSCOR0 (BSC.TOSCOR0) +#define BSCTOSCOR1 (BSC.TOSCOR1) +#define BSCTOSCOR2 (BSC.TOSCOR2) +#define BSCTOSCOR3 (BSC.TOSCOR3) +#define BSCTOSCOR4 (BSC.TOSCOR4) +#define BSCTOSCOR5 (BSC.TOSCOR5) +#define BSCTOSTR (BSC.TOSTR) +#define BSCTOENR (BSC.TOENR) + +#define BSC_CSnBCR_COUNT (6) +#define BSC_CSnWCR_COUNT (6) +#define BSC_TOSCORn_COUNT (6) + + +typedef struct st_bsc +{ + /* BSC */ volatile uint32_t CMNCR; /* CMNCR */ -#define BSC_CSnBCR_COUNT 6 + +/* #define BSC_CSnBCR_COUNT (6) */ volatile uint32_t CS0BCR; /* CS0BCR */ volatile uint32_t CS1BCR; /* CS1BCR */ volatile uint32_t CS2BCR; /* CS2BCR */ @@ -41,7 +80,8 @@ struct st_bsc volatile uint32_t CS4BCR; /* CS4BCR */ volatile uint32_t CS5BCR; /* CS5BCR */ volatile uint8_t dummy4[12]; /* */ -#define BSC_CSnWCR_COUNT 6 + +/* #define BSC_CSnWCR_COUNT (6) */ volatile uint32_t CS0WCR; /* CS0WCR */ volatile uint32_t CS1WCR; /* CS1WCR */ volatile uint32_t CS2WCR; /* CS2WCR */ @@ -54,7 +94,8 @@ struct st_bsc volatile uint32_t RTCNT; /* RTCNT */ volatile uint32_t RTCOR; /* RTCOR */ volatile uint8_t dummy6[4]; /* */ -#define BSC_TOSCORn_COUNT 6 + +/* #define BSC_TOSCORn_COUNT (6) */ volatile uint32_t TOSCOR0; /* TOSCOR0 */ volatile uint32_t TOSCOR1; /* TOSCOR1 */ volatile uint32_t TOSCOR2; /* TOSCOR2 */ @@ -64,36 +105,11 @@ struct st_bsc volatile uint8_t dummy7[8]; /* */ volatile uint32_t TOSTR; /* TOSTR */ volatile uint32_t TOENR; /* TOENR */ -}; +} r_io_bsc_t; -#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */ - - -#define BSCCMNCR BSC.CMNCR -#define BSCCS0BCR BSC.CS0BCR -#define BSCCS1BCR BSC.CS1BCR -#define BSCCS2BCR BSC.CS2BCR -#define BSCCS3BCR BSC.CS3BCR -#define BSCCS4BCR BSC.CS4BCR -#define BSCCS5BCR BSC.CS5BCR -#define BSCCS0WCR BSC.CS0WCR -#define BSCCS1WCR BSC.CS1WCR -#define BSCCS2WCR BSC.CS2WCR -#define BSCCS3WCR BSC.CS3WCR -#define BSCCS4WCR BSC.CS4WCR -#define BSCCS5WCR BSC.CS5WCR -#define BSCSDCR BSC.SDCR -#define BSCRTCSR BSC.RTCSR -#define BSCRTCNT BSC.RTCNT -#define BSCRTCOR BSC.RTCOR -#define BSCTOSCOR0 BSC.TOSCOR0 -#define BSCTOSCOR1 BSC.TOSCOR1 -#define BSCTOSCOR2 BSC.TOSCOR2 -#define BSCTOSCOR3 BSC.TOSCOR3 -#define BSCTOSCOR4 BSC.TOSCOR4 -#define BSCTOSCOR5 BSC.TOSCOR5 -#define BSCTOSTR BSC.TOSTR -#define BSCTOENR BSC.TOENR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h index 535b18bed0..a970bfd807 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h @@ -18,20 +18,108 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ceu_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef CEU_IODEFINE_H #define CEU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ceu -{ /* CEU */ +#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ + + +/* Start of channel array defines of CEU */ + +/* Channel array defines of CEUn */ +/*(Sample) value = CEUn[ channel ]->CAMOR; */ +#define CEUn_COUNT (3) +#define CEUn_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + (volatile struct st_ceu_n*)&CEU_A, \ + (volatile struct st_ceu_n*)&CEU_B, \ + (volatile struct st_ceu_n*)&CEU_M \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ +#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ +#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ + +/* End of channel array defines of CEU */ + + +#define CEUCAPSR (CEU.CAPSR) +#define CEUCAPCR (CEU.CAPCR) +#define CEUCAMCR (CEU.CAMCR) +#define CEUCMCYR (CEU.CMCYR) +#define CEUCAMOR_A (CEU.CAMOR_A) +#define CEUCAPWR_A (CEU.CAPWR_A) +#define CEUCAIFR (CEU.CAIFR) +#define CEUCRCNTR (CEU.CRCNTR) +#define CEUCRCMPR (CEU.CRCMPR) +#define CEUCFLCR_A (CEU.CFLCR_A) +#define CEUCFSZR_A (CEU.CFSZR_A) +#define CEUCDWDR_A (CEU.CDWDR_A) +#define CEUCDAYR_A (CEU.CDAYR_A) +#define CEUCDACR_A (CEU.CDACR_A) +#define CEUCDBYR_A (CEU.CDBYR_A) +#define CEUCDBCR_A (CEU.CDBCR_A) +#define CEUCBDSR_A (CEU.CBDSR_A) +#define CEUCFWCR (CEU.CFWCR) +#define CEUCLFCR_A (CEU.CLFCR_A) +#define CEUCDOCR_A (CEU.CDOCR_A) +#define CEUCEIER (CEU.CEIER) +#define CEUCETCR (CEU.CETCR) +#define CEUCSTSR (CEU.CSTSR) +#define CEUCDSSR (CEU.CDSSR) +#define CEUCDAYR2_A (CEU.CDAYR2_A) +#define CEUCDACR2_A (CEU.CDACR2_A) +#define CEUCDBYR2_A (CEU.CDBYR2_A) +#define CEUCDBCR2_A (CEU.CDBCR2_A) +#define CEUCAMOR_B (CEU.CAMOR_B) +#define CEUCAPWR_B (CEU.CAPWR_B) +#define CEUCFLCR_B (CEU.CFLCR_B) +#define CEUCFSZR_B (CEU.CFSZR_B) +#define CEUCDWDR_B (CEU.CDWDR_B) +#define CEUCDAYR_B (CEU.CDAYR_B) +#define CEUCDACR_B (CEU.CDACR_B) +#define CEUCDBYR_B (CEU.CDBYR_B) +#define CEUCDBCR_B (CEU.CDBCR_B) +#define CEUCBDSR_B (CEU.CBDSR_B) +#define CEUCLFCR_B (CEU.CLFCR_B) +#define CEUCDOCR_B (CEU.CDOCR_B) +#define CEUCDAYR2_B (CEU.CDAYR2_B) +#define CEUCDACR2_B (CEU.CDACR2_B) +#define CEUCDBYR2_B (CEU.CDBYR2_B) +#define CEUCDBCR2_B (CEU.CDBCR2_B) +#define CEUCAMOR_M (CEU.CAMOR_M) +#define CEUCAPWR_M (CEU.CAPWR_M) +#define CEUCFLCR_M (CEU.CFLCR_M) +#define CEUCFSZR_M (CEU.CFSZR_M) +#define CEUCDWDR_M (CEU.CDWDR_M) +#define CEUCDAYR_M (CEU.CDAYR_M) +#define CEUCDACR_M (CEU.CDACR_M) +#define CEUCDBYR_M (CEU.CDBYR_M) +#define CEUCDBCR_M (CEU.CDBCR_M) +#define CEUCBDSR_M (CEU.CBDSR_M) +#define CEUCLFCR_M (CEU.CLFCR_M) +#define CEUCDOCR_M (CEU.CDOCR_M) +#define CEUCDAYR2_M (CEU.CDAYR2_M) +#define CEUCDACR2_M (CEU.CDACR2_M) +#define CEUCDBYR2_M (CEU.CDBYR2_M) +#define CEUCDBCR2_M (CEU.CDBCR2_M) + + +typedef struct st_ceu +{ + /* CEU */ + /* start of struct st_ceu_n */ volatile uint32_t CAPSR; /* CAPSR */ volatile uint32_t CAPCR; /* CAPCR */ @@ -67,8 +155,10 @@ struct st_ceu volatile uint32_t CDACR2_A; /* CDACR2_A */ volatile uint32_t CDBYR2_A; /* CDBYR2_A */ volatile uint32_t CDBCR2_A; /* CDBCR2_A */ + /* end of struct st_ceu_n */ volatile uint8_t dummy3110[3936]; /* */ + /* start of struct st_ceu_n */ volatile uint8_t dummy3111[4]; /* */ volatile uint8_t dummy3112[4]; /* */ @@ -104,8 +194,10 @@ struct st_ceu volatile uint32_t CDACR2_B; /* CDACR2_B */ volatile uint32_t CDBYR2_B; /* CDBYR2_B */ volatile uint32_t CDBCR2_B; /* CDBCR2_B */ + /* end of struct st_ceu_n */ volatile uint8_t dummy3150[3936]; /* */ + /* start of struct st_ceu_n */ volatile uint8_t dummy3151[4]; /* */ volatile uint8_t dummy3152[4]; /* */ @@ -141,12 +233,14 @@ struct st_ceu volatile uint32_t CDACR2_M; /* CDACR2_M */ volatile uint32_t CDBYR2_M; /* CDBYR2_M */ volatile uint32_t CDBCR2_M; /* CDBCR2_M */ + /* end of struct st_ceu_n */ -}; +} r_io_ceu_t; -struct st_ceu_n +typedef struct st_ceu_n { + volatile uint32_t not_common1; /* */ volatile uint32_t not_common2; /* */ volatile uint32_t not_common3; /* */ @@ -181,89 +275,21 @@ struct st_ceu_n volatile uint32_t CDACR2; /* CDACR2 */ volatile uint32_t CDBYR2; /* CDBYR2 */ volatile uint32_t CDBCR2; /* CDBCR2 */ -}; +} r_io_ceu_n_t; -#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */ +/* Channel array defines of CEUn (2)*/ +#ifdef DECLARE_CEUn_CHANNELS +volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CEUn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CEUn_CHANNELS */ +/* End of channel array defines of CEUn (2)*/ -/* Start of channnel array defines of CEU */ - -/* Channnel array defines of CEUn */ -/*(Sample) value = CEUn[ channel ]->CAMOR; */ -#define CEUn_COUNT 3 -#define CEUn_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - (volatile struct st_ceu_n*)&CEU_A, \ - (volatile struct st_ceu_n*)&CEU_B, \ - (volatile struct st_ceu_n*)&CEU_M \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */ -#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */ -#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */ - -/* End of channnel array defines of CEU */ - - -#define CEUCAPSR CEU.CAPSR -#define CEUCAPCR CEU.CAPCR -#define CEUCAMCR CEU.CAMCR -#define CEUCMCYR CEU.CMCYR -#define CEUCAMOR_A CEU.CAMOR_A -#define CEUCAPWR_A CEU.CAPWR_A -#define CEUCAIFR CEU.CAIFR -#define CEUCRCNTR CEU.CRCNTR -#define CEUCRCMPR CEU.CRCMPR -#define CEUCFLCR_A CEU.CFLCR_A -#define CEUCFSZR_A CEU.CFSZR_A -#define CEUCDWDR_A CEU.CDWDR_A -#define CEUCDAYR_A CEU.CDAYR_A -#define CEUCDACR_A CEU.CDACR_A -#define CEUCDBYR_A CEU.CDBYR_A -#define CEUCDBCR_A CEU.CDBCR_A -#define CEUCBDSR_A CEU.CBDSR_A -#define CEUCFWCR CEU.CFWCR -#define CEUCLFCR_A CEU.CLFCR_A -#define CEUCDOCR_A CEU.CDOCR_A -#define CEUCEIER CEU.CEIER -#define CEUCETCR CEU.CETCR -#define CEUCSTSR CEU.CSTSR -#define CEUCDSSR CEU.CDSSR -#define CEUCDAYR2_A CEU.CDAYR2_A -#define CEUCDACR2_A CEU.CDACR2_A -#define CEUCDBYR2_A CEU.CDBYR2_A -#define CEUCDBCR2_A CEU.CDBCR2_A -#define CEUCAMOR_B CEU.CAMOR_B -#define CEUCAPWR_B CEU.CAPWR_B -#define CEUCFLCR_B CEU.CFLCR_B -#define CEUCFSZR_B CEU.CFSZR_B -#define CEUCDWDR_B CEU.CDWDR_B -#define CEUCDAYR_B CEU.CDAYR_B -#define CEUCDACR_B CEU.CDACR_B -#define CEUCDBYR_B CEU.CDBYR_B -#define CEUCDBCR_B CEU.CDBCR_B -#define CEUCBDSR_B CEU.CBDSR_B -#define CEUCLFCR_B CEU.CLFCR_B -#define CEUCDOCR_B CEU.CDOCR_B -#define CEUCDAYR2_B CEU.CDAYR2_B -#define CEUCDACR2_B CEU.CDACR2_B -#define CEUCDBYR2_B CEU.CDBYR2_B -#define CEUCDBCR2_B CEU.CDBCR2_B -#define CEUCAMOR_M CEU.CAMOR_M -#define CEUCAPWR_M CEU.CAPWR_M -#define CEUCFLCR_M CEU.CFLCR_M -#define CEUCFSZR_M CEU.CFSZR_M -#define CEUCDWDR_M CEU.CDWDR_M -#define CEUCDAYR_M CEU.CDAYR_M -#define CEUCDACR_M CEU.CDACR_M -#define CEUCDBYR_M CEU.CDBYR_M -#define CEUCDBCR_M CEU.CDBCR_M -#define CEUCBDSR_M CEU.CBDSR_M -#define CEUCLFCR_M CEU.CLFCR_M -#define CEUCDOCR_M CEU.CDOCR_M -#define CEUCDAYR2_M CEU.CDAYR2_M -#define CEUCDACR2_M CEU.CDACR2_M -#define CEUCDBYR2_M CEU.CDBYR2_M -#define CEUCDBCR2_M CEU.CDBCR2_M /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h index 5fc9890ff5..6260ad010e 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h @@ -18,20 +18,109 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : cpg_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef CPG_IODEFINE_H #define CPG_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_cpg -{ /* CPG */ +#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ + + +/* Start of channel array defines of CPG */ + +/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ +#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3) +#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ +#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ +#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ + + +/* Channel array defines of CPG_FROM_STBCR3_ARRAY */ +/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ +#define CPG_FROM_STBCR3_ARRAY_COUNT (10) +#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ + &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ +#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ +#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ +#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ +#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ +#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ +#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ +#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ +#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ +#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ + + +/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */ +/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ +#define CPG_FROM_SYSCR1_ARRAY_COUNT (3) +#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ +#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ +#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ + +/* End of channel array defines of CPG */ + + +#define CPGFRQCR (CPG.FRQCR) +#define CPGFRQCR2 (CPG.FRQCR2) +#define CPGCPUSTS (CPG.CPUSTS) +#define CPGSTBCR1 (CPG.STBCR1) +#define CPGSTBCR2 (CPG.STBCR2) +#define CPGSTBREQ1 (CPG.STBREQ1) +#define CPGSTBREQ2 (CPG.STBREQ2) +#define CPGSTBACK1 (CPG.STBACK1) +#define CPGSTBACK2 (CPG.STBACK2) +#define CPGSYSCR1 (CPG.SYSCR1) +#define CPGSYSCR2 (CPG.SYSCR2) +#define CPGSYSCR3 (CPG.SYSCR3) +#define CPGSTBCR3 (CPG.STBCR3) +#define CPGSTBCR4 (CPG.STBCR4) +#define CPGSTBCR5 (CPG.STBCR5) +#define CPGSTBCR6 (CPG.STBCR6) +#define CPGSTBCR7 (CPG.STBCR7) +#define CPGSTBCR8 (CPG.STBCR8) +#define CPGSTBCR9 (CPG.STBCR9) +#define CPGSTBCR10 (CPG.STBCR10) +#define CPGSTBCR11 (CPG.STBCR11) +#define CPGSTBCR12 (CPG.STBCR12) +#define CPGSWRSTCR1 (CPG.SWRSTCR1) +#define CPGSWRSTCR2 (CPG.SWRSTCR2) +#define CPGSWRSTCR3 (CPG.SWRSTCR3) +#define CPGSTBCR13 (CPG.STBCR13) +#define CPGRRAMKP (CPG.RRAMKP) +#define CPGDSCTR (CPG.DSCTR) +#define CPGDSSSR (CPG.DSSSR) +#define CPGDSESR (CPG.DSESR) +#define CPGDSFR (CPG.DSFR) +#define CPGXTALCTR (CPG.XTALCTR) + + +typedef struct st_cpg +{ + /* CPG */ volatile uint16_t FRQCR; /* FRQCR */ volatile uint8_t dummy319[2]; /* */ volatile uint16_t FRQCR2; /* FRQCR2 */ @@ -50,71 +139,103 @@ struct st_cpg volatile uint8_t dummy326[3]; /* */ volatile uint8_t STBACK2; /* STBACK2 */ volatile uint8_t dummy327[955]; /* */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR1; /* SYSCR1 */ volatile uint8_t dummy328[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR2; /* SYSCR2 */ volatile uint8_t dummy329[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ + /* start of struct st_cpg_from_syscr1 */ volatile uint8_t SYSCR3; /* SYSCR3 */ volatile uint8_t dummy3300[3]; /* */ + /* end of struct st_cpg_from_syscr1 */ volatile uint8_t dummy3301[20]; /* */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR3; /* STBCR3 */ volatile uint8_t dummy331[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR4; /* STBCR4 */ volatile uint8_t dummy332[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR5; /* STBCR5 */ volatile uint8_t dummy333[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR6; /* STBCR6 */ volatile uint8_t dummy334[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR7; /* STBCR7 */ volatile uint8_t dummy335[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR8; /* STBCR8 */ volatile uint8_t dummy336[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR9; /* STBCR9 */ volatile uint8_t dummy337[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR10; /* STBCR10 */ volatile uint8_t dummy338[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR11; /* STBCR11 */ volatile uint8_t dummy339[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ + /* start of struct st_cpg_from_stbcr3 */ volatile uint8_t STBCR12; /* STBCR12 */ volatile uint8_t dummy3400[3]; /* */ + /* end of struct st_cpg_from_stbcr3 */ volatile uint8_t dummy3401[24]; /* */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ volatile uint8_t dummy341[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR2; /* SWRSTCR2 */ volatile uint8_t dummy342[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ + /* start of struct st_cpg_from_swrstcr1 */ volatile uint8_t SWRSTCR3; /* SWRSTCR3 */ volatile uint8_t dummy3430[3]; /* */ + /* end of struct st_cpg_from_swrstcr1 */ volatile uint8_t dummy3431[4]; /* */ volatile uint8_t STBCR13; /* STBCR13 */ @@ -128,112 +249,59 @@ struct st_cpg volatile uint16_t DSFR; /* DSFR */ volatile uint8_t dummy347[6]; /* */ volatile uint8_t XTALCTR; /* XTALCTR */ -}; +} r_io_cpg_t; -struct st_cpg_from_syscr1 +typedef struct st_cpg_from_syscr1 { + volatile uint8_t SYSCR1; /* SYSCR1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_syscr1_t; -struct st_cpg_from_stbcr3 +typedef struct st_cpg_from_stbcr3 { + volatile uint8_t STBCR3; /* STBCR3 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_stbcr3_t; -struct st_cpg_from_swrstcr1 +typedef struct st_cpg_from_swrstcr1 { + volatile uint8_t SWRSTCR1; /* SWRSTCR1 */ volatile uint8_t dummy1[3]; /* */ -}; +} r_io_cpg_from_swrstcr1_t; -#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */ +/* Channel array defines of CPG (2)*/ +#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */ + +#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS +volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */ + +#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS +volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */ +/* End of channel array defines of CPG (2)*/ -/* Start of channnel array defines of CPG */ - -/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */ -#define CPG_FROM_SWRSTCR1_ARRAY_COUNT 3 -#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */ -#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */ -#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */ - - -/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */ -/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */ -#define CPG_FROM_STBCR3_ARRAY_COUNT 10 -#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \ - &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */ -#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */ -#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */ -#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */ -#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */ -#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */ -#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */ -#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */ -#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */ -#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */ - - -/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */ -/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */ -#define CPG_FROM_SYSCR1_ARRAY_COUNT 3 -#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */ -#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */ -#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */ - -/* End of channnel array defines of CPG */ - - -#define CPGFRQCR CPG.FRQCR -#define CPGFRQCR2 CPG.FRQCR2 -#define CPGCPUSTS CPG.CPUSTS -#define CPGSTBCR1 CPG.STBCR1 -#define CPGSTBCR2 CPG.STBCR2 -#define CPGSTBREQ1 CPG.STBREQ1 -#define CPGSTBREQ2 CPG.STBREQ2 -#define CPGSTBACK1 CPG.STBACK1 -#define CPGSTBACK2 CPG.STBACK2 -#define CPGSYSCR1 CPG.SYSCR1 -#define CPGSYSCR2 CPG.SYSCR2 -#define CPGSYSCR3 CPG.SYSCR3 -#define CPGSTBCR3 CPG.STBCR3 -#define CPGSTBCR4 CPG.STBCR4 -#define CPGSTBCR5 CPG.STBCR5 -#define CPGSTBCR6 CPG.STBCR6 -#define CPGSTBCR7 CPG.STBCR7 -#define CPGSTBCR8 CPG.STBCR8 -#define CPGSTBCR9 CPG.STBCR9 -#define CPGSTBCR10 CPG.STBCR10 -#define CPGSTBCR11 CPG.STBCR11 -#define CPGSTBCR12 CPG.STBCR12 -#define CPGSWRSTCR1 CPG.SWRSTCR1 -#define CPGSWRSTCR2 CPG.SWRSTCR2 -#define CPGSWRSTCR3 CPG.SWRSTCR3 -#define CPGSTBCR13 CPG.STBCR13 -#define CPGRRAMKP CPG.RRAMKP -#define CPGDSCTR CPG.DSCTR -#define CPGDSSSR CPG.DSSSR -#define CPGDSESR CPG.DSESR -#define CPGDSFR CPG.DSFR -#define CPGXTALCTR CPG.XTALCTR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h index 8844fa2afb..dd2abd5e75 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h @@ -18,20 +18,67 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : disc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DISC_IODEFINE_H #define DISC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_disc -{ /* DISC */ +#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ +#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ + + +/* Start of channel array defines of DISC */ + +/* Channel array defines of DISC */ +/*(Sample) value = DISC[ channel ]->DOCMCR; */ +#define DISC_COUNT (2) +#define DISC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DISC0, &DISC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of DISC */ + + +#define DISC0DOCMCR (DISC0.DOCMCR) +#define DISC0DOCMSTR (DISC0.DOCMSTR) +#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR) +#define DISC0DOCMIENR (DISC0.DOCMIENR) +#define DISC0DOCMPMR (DISC0.DOCMPMR) +#define DISC0DOCMECRCR (DISC0.DOCMECRCR) +#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR) +#define DISC0DOCMSPXR (DISC0.DOCMSPXR) +#define DISC0DOCMSPYR (DISC0.DOCMSPYR) +#define DISC0DOCMSZXR (DISC0.DOCMSZXR) +#define DISC0DOCMSZYR (DISC0.DOCMSZYR) +#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR) +#define DISC1DOCMCR (DISC1.DOCMCR) +#define DISC1DOCMSTR (DISC1.DOCMSTR) +#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR) +#define DISC1DOCMIENR (DISC1.DOCMIENR) +#define DISC1DOCMPMR (DISC1.DOCMPMR) +#define DISC1DOCMECRCR (DISC1.DOCMECRCR) +#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR) +#define DISC1DOCMSPXR (DISC1.DOCMSPXR) +#define DISC1DOCMSPYR (DISC1.DOCMSPYR) +#define DISC1DOCMSZXR (DISC1.DOCMSZXR) +#define DISC1DOCMSZYR (DISC1.DOCMSZYR) +#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR) + + +typedef struct st_disc +{ + /* DISC */ volatile uint32_t DOCMCR; /* DOCMCR */ volatile uint32_t DOCMSTR; /* DOCMSTR */ volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */ @@ -45,49 +92,21 @@ struct st_disc volatile uint32_t DOCMSZXR; /* DOCMSZXR */ volatile uint32_t DOCMSZYR; /* DOCMSZYR */ volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */ -}; +} r_io_disc_t; -#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */ -#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */ +/* Channel array defines of DISC (2)*/ +#ifdef DECLARE_DISC_CHANNELS +volatile struct st_disc* DISC[ DISC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DISC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DISC_CHANNELS */ +/* End of channel array defines of DISC (2)*/ -/* Start of channnel array defines of DISC */ - -/* Channnel array defines of DISC */ -/*(Sample) value = DISC[ channel ]->DOCMCR; */ -#define DISC_COUNT 2 -#define DISC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DISC0, &DISC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of DISC */ - - -#define DISC0DOCMCR DISC0.DOCMCR -#define DISC0DOCMSTR DISC0.DOCMSTR -#define DISC0DOCMCLSTR DISC0.DOCMCLSTR -#define DISC0DOCMIENR DISC0.DOCMIENR -#define DISC0DOCMPMR DISC0.DOCMPMR -#define DISC0DOCMECRCR DISC0.DOCMECRCR -#define DISC0DOCMCCRCR DISC0.DOCMCCRCR -#define DISC0DOCMSPXR DISC0.DOCMSPXR -#define DISC0DOCMSPYR DISC0.DOCMSPYR -#define DISC0DOCMSZXR DISC0.DOCMSZXR -#define DISC0DOCMSZYR DISC0.DOCMSZYR -#define DISC0DOCMCRCIR DISC0.DOCMCRCIR -#define DISC1DOCMCR DISC1.DOCMCR -#define DISC1DOCMSTR DISC1.DOCMSTR -#define DISC1DOCMCLSTR DISC1.DOCMCLSTR -#define DISC1DOCMIENR DISC1.DOCMIENR -#define DISC1DOCMPMR DISC1.DOCMPMR -#define DISC1DOCMECRCR DISC1.DOCMECRCR -#define DISC1DOCMCCRCR DISC1.DOCMCCRCR -#define DISC1DOCMSPXR DISC1.DOCMSPXR -#define DISC1DOCMSPYR DISC1.DOCMSPYR -#define DISC1DOCMSZXR DISC1.DOCMSZXR -#define DISC1DOCMSZYR DISC1.DOCMSZYR -#define DISC1DOCMCRCIR DISC1.DOCMCRCIR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h index 0faf27fbe0..a6d6865f86 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h @@ -18,383 +18,48 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : dmac_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DMAC_IODEFINE_H #define DMAC_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_dmac -{ /* DMAC */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_0; /* N0SA_0 */ - volatile uint32_t N0DA_0; /* N0DA_0 */ - volatile uint32_t N0TB_0; /* N0TB_0 */ - volatile uint32_t N1SA_0; /* N1SA_0 */ - volatile uint32_t N1DA_0; /* N1DA_0 */ - volatile uint32_t N1TB_0; /* N1TB_0 */ - volatile uint32_t CRSA_0; /* CRSA_0 */ - volatile uint32_t CRDA_0; /* CRDA_0 */ - volatile uint32_t CRTB_0; /* CRTB_0 */ - volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ - volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ - volatile uint32_t CHCFG_0; /* CHCFG_0 */ - volatile uint32_t CHITVL_0; /* CHITVL_0 */ - volatile uint32_t CHEXT_0; /* CHEXT_0 */ - volatile uint32_t NXLA_0; /* NXLA_0 */ - volatile uint32_t CRLA_0; /* CRLA_0 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_1; /* N0SA_1 */ - volatile uint32_t N0DA_1; /* N0DA_1 */ - volatile uint32_t N0TB_1; /* N0TB_1 */ - volatile uint32_t N1SA_1; /* N1SA_1 */ - volatile uint32_t N1DA_1; /* N1DA_1 */ - volatile uint32_t N1TB_1; /* N1TB_1 */ - volatile uint32_t CRSA_1; /* CRSA_1 */ - volatile uint32_t CRDA_1; /* CRDA_1 */ - volatile uint32_t CRTB_1; /* CRTB_1 */ - volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ - volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ - volatile uint32_t CHCFG_1; /* CHCFG_1 */ - volatile uint32_t CHITVL_1; /* CHITVL_1 */ - volatile uint32_t CHEXT_1; /* CHEXT_1 */ - volatile uint32_t NXLA_1; /* NXLA_1 */ - volatile uint32_t CRLA_1; /* CRLA_1 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_2; /* N0SA_2 */ - volatile uint32_t N0DA_2; /* N0DA_2 */ - volatile uint32_t N0TB_2; /* N0TB_2 */ - volatile uint32_t N1SA_2; /* N1SA_2 */ - volatile uint32_t N1DA_2; /* N1DA_2 */ - volatile uint32_t N1TB_2; /* N1TB_2 */ - volatile uint32_t CRSA_2; /* CRSA_2 */ - volatile uint32_t CRDA_2; /* CRDA_2 */ - volatile uint32_t CRTB_2; /* CRTB_2 */ - volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ - volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ - volatile uint32_t CHCFG_2; /* CHCFG_2 */ - volatile uint32_t CHITVL_2; /* CHITVL_2 */ - volatile uint32_t CHEXT_2; /* CHEXT_2 */ - volatile uint32_t NXLA_2; /* NXLA_2 */ - volatile uint32_t CRLA_2; /* CRLA_2 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_3; /* N0SA_3 */ - volatile uint32_t N0DA_3; /* N0DA_3 */ - volatile uint32_t N0TB_3; /* N0TB_3 */ - volatile uint32_t N1SA_3; /* N1SA_3 */ - volatile uint32_t N1DA_3; /* N1DA_3 */ - volatile uint32_t N1TB_3; /* N1TB_3 */ - volatile uint32_t CRSA_3; /* CRSA_3 */ - volatile uint32_t CRDA_3; /* CRDA_3 */ - volatile uint32_t CRTB_3; /* CRTB_3 */ - volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ - volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ - volatile uint32_t CHCFG_3; /* CHCFG_3 */ - volatile uint32_t CHITVL_3; /* CHITVL_3 */ - volatile uint32_t CHEXT_3; /* CHEXT_3 */ - volatile uint32_t NXLA_3; /* NXLA_3 */ - volatile uint32_t CRLA_3; /* CRLA_3 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_4; /* N0SA_4 */ - volatile uint32_t N0DA_4; /* N0DA_4 */ - volatile uint32_t N0TB_4; /* N0TB_4 */ - volatile uint32_t N1SA_4; /* N1SA_4 */ - volatile uint32_t N1DA_4; /* N1DA_4 */ - volatile uint32_t N1TB_4; /* N1TB_4 */ - volatile uint32_t CRSA_4; /* CRSA_4 */ - volatile uint32_t CRDA_4; /* CRDA_4 */ - volatile uint32_t CRTB_4; /* CRTB_4 */ - volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ - volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ - volatile uint32_t CHCFG_4; /* CHCFG_4 */ - volatile uint32_t CHITVL_4; /* CHITVL_4 */ - volatile uint32_t CHEXT_4; /* CHEXT_4 */ - volatile uint32_t NXLA_4; /* NXLA_4 */ - volatile uint32_t CRLA_4; /* CRLA_4 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_5; /* N0SA_5 */ - volatile uint32_t N0DA_5; /* N0DA_5 */ - volatile uint32_t N0TB_5; /* N0TB_5 */ - volatile uint32_t N1SA_5; /* N1SA_5 */ - volatile uint32_t N1DA_5; /* N1DA_5 */ - volatile uint32_t N1TB_5; /* N1TB_5 */ - volatile uint32_t CRSA_5; /* CRSA_5 */ - volatile uint32_t CRDA_5; /* CRDA_5 */ - volatile uint32_t CRTB_5; /* CRTB_5 */ - volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ - volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ - volatile uint32_t CHCFG_5; /* CHCFG_5 */ - volatile uint32_t CHITVL_5; /* CHITVL_5 */ - volatile uint32_t CHEXT_5; /* CHEXT_5 */ - volatile uint32_t NXLA_5; /* NXLA_5 */ - volatile uint32_t CRLA_5; /* CRLA_5 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_6; /* N0SA_6 */ - volatile uint32_t N0DA_6; /* N0DA_6 */ - volatile uint32_t N0TB_6; /* N0TB_6 */ - volatile uint32_t N1SA_6; /* N1SA_6 */ - volatile uint32_t N1DA_6; /* N1DA_6 */ - volatile uint32_t N1TB_6; /* N1TB_6 */ - volatile uint32_t CRSA_6; /* CRSA_6 */ - volatile uint32_t CRDA_6; /* CRDA_6 */ - volatile uint32_t CRTB_6; /* CRTB_6 */ - volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ - volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ - volatile uint32_t CHCFG_6; /* CHCFG_6 */ - volatile uint32_t CHITVL_6; /* CHITVL_6 */ - volatile uint32_t CHEXT_6; /* CHEXT_6 */ - volatile uint32_t NXLA_6; /* NXLA_6 */ - volatile uint32_t CRLA_6; /* CRLA_6 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_7; /* N0SA_7 */ - volatile uint32_t N0DA_7; /* N0DA_7 */ - volatile uint32_t N0TB_7; /* N0TB_7 */ - volatile uint32_t N1SA_7; /* N1SA_7 */ - volatile uint32_t N1DA_7; /* N1DA_7 */ - volatile uint32_t N1TB_7; /* N1TB_7 */ - volatile uint32_t CRSA_7; /* CRSA_7 */ - volatile uint32_t CRDA_7; /* CRDA_7 */ - volatile uint32_t CRTB_7; /* CRTB_7 */ - volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ - volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ - volatile uint32_t CHCFG_7; /* CHCFG_7 */ - volatile uint32_t CHITVL_7; /* CHITVL_7 */ - volatile uint32_t CHEXT_7; /* CHEXT_7 */ - volatile uint32_t NXLA_7; /* NXLA_7 */ - volatile uint32_t CRLA_7; /* CRLA_7 */ -/* end of struct st_dmac_n */ - volatile uint8_t dummy187[256]; /* */ -/* start of struct st_dmaccommon_n */ - volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ - volatile uint8_t dummy188[12]; /* */ - volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ - volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ - volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ - volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ - volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ -/* end of struct st_dmaccommon_n */ - volatile uint8_t dummy189[220]; /* */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_8; /* N0SA_8 */ - volatile uint32_t N0DA_8; /* N0DA_8 */ - volatile uint32_t N0TB_8; /* N0TB_8 */ - volatile uint32_t N1SA_8; /* N1SA_8 */ - volatile uint32_t N1DA_8; /* N1DA_8 */ - volatile uint32_t N1TB_8; /* N1TB_8 */ - volatile uint32_t CRSA_8; /* CRSA_8 */ - volatile uint32_t CRDA_8; /* CRDA_8 */ - volatile uint32_t CRTB_8; /* CRTB_8 */ - volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ - volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ - volatile uint32_t CHCFG_8; /* CHCFG_8 */ - volatile uint32_t CHITVL_8; /* CHITVL_8 */ - volatile uint32_t CHEXT_8; /* CHEXT_8 */ - volatile uint32_t NXLA_8; /* NXLA_8 */ - volatile uint32_t CRLA_8; /* CRLA_8 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_9; /* N0SA_9 */ - volatile uint32_t N0DA_9; /* N0DA_9 */ - volatile uint32_t N0TB_9; /* N0TB_9 */ - volatile uint32_t N1SA_9; /* N1SA_9 */ - volatile uint32_t N1DA_9; /* N1DA_9 */ - volatile uint32_t N1TB_9; /* N1TB_9 */ - volatile uint32_t CRSA_9; /* CRSA_9 */ - volatile uint32_t CRDA_9; /* CRDA_9 */ - volatile uint32_t CRTB_9; /* CRTB_9 */ - volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ - volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ - volatile uint32_t CHCFG_9; /* CHCFG_9 */ - volatile uint32_t CHITVL_9; /* CHITVL_9 */ - volatile uint32_t CHEXT_9; /* CHEXT_9 */ - volatile uint32_t NXLA_9; /* NXLA_9 */ - volatile uint32_t CRLA_9; /* CRLA_9 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_10; /* N0SA_10 */ - volatile uint32_t N0DA_10; /* N0DA_10 */ - volatile uint32_t N0TB_10; /* N0TB_10 */ - volatile uint32_t N1SA_10; /* N1SA_10 */ - volatile uint32_t N1DA_10; /* N1DA_10 */ - volatile uint32_t N1TB_10; /* N1TB_10 */ - volatile uint32_t CRSA_10; /* CRSA_10 */ - volatile uint32_t CRDA_10; /* CRDA_10 */ - volatile uint32_t CRTB_10; /* CRTB_10 */ - volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ - volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ - volatile uint32_t CHCFG_10; /* CHCFG_10 */ - volatile uint32_t CHITVL_10; /* CHITVL_10 */ - volatile uint32_t CHEXT_10; /* CHEXT_10 */ - volatile uint32_t NXLA_10; /* NXLA_10 */ - volatile uint32_t CRLA_10; /* CRLA_10 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_11; /* N0SA_11 */ - volatile uint32_t N0DA_11; /* N0DA_11 */ - volatile uint32_t N0TB_11; /* N0TB_11 */ - volatile uint32_t N1SA_11; /* N1SA_11 */ - volatile uint32_t N1DA_11; /* N1DA_11 */ - volatile uint32_t N1TB_11; /* N1TB_11 */ - volatile uint32_t CRSA_11; /* CRSA_11 */ - volatile uint32_t CRDA_11; /* CRDA_11 */ - volatile uint32_t CRTB_11; /* CRTB_11 */ - volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ - volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ - volatile uint32_t CHCFG_11; /* CHCFG_11 */ - volatile uint32_t CHITVL_11; /* CHITVL_11 */ - volatile uint32_t CHEXT_11; /* CHEXT_11 */ - volatile uint32_t NXLA_11; /* NXLA_11 */ - volatile uint32_t CRLA_11; /* CRLA_11 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_12; /* N0SA_12 */ - volatile uint32_t N0DA_12; /* N0DA_12 */ - volatile uint32_t N0TB_12; /* N0TB_12 */ - volatile uint32_t N1SA_12; /* N1SA_12 */ - volatile uint32_t N1DA_12; /* N1DA_12 */ - volatile uint32_t N1TB_12; /* N1TB_12 */ - volatile uint32_t CRSA_12; /* CRSA_12 */ - volatile uint32_t CRDA_12; /* CRDA_12 */ - volatile uint32_t CRTB_12; /* CRTB_12 */ - volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ - volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ - volatile uint32_t CHCFG_12; /* CHCFG_12 */ - volatile uint32_t CHITVL_12; /* CHITVL_12 */ - volatile uint32_t CHEXT_12; /* CHEXT_12 */ - volatile uint32_t NXLA_12; /* NXLA_12 */ - volatile uint32_t CRLA_12; /* CRLA_12 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_13; /* N0SA_13 */ - volatile uint32_t N0DA_13; /* N0DA_13 */ - volatile uint32_t N0TB_13; /* N0TB_13 */ - volatile uint32_t N1SA_13; /* N1SA_13 */ - volatile uint32_t N1DA_13; /* N1DA_13 */ - volatile uint32_t N1TB_13; /* N1TB_13 */ - volatile uint32_t CRSA_13; /* CRSA_13 */ - volatile uint32_t CRDA_13; /* CRDA_13 */ - volatile uint32_t CRTB_13; /* CRTB_13 */ - volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ - volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ - volatile uint32_t CHCFG_13; /* CHCFG_13 */ - volatile uint32_t CHITVL_13; /* CHITVL_13 */ - volatile uint32_t CHEXT_13; /* CHEXT_13 */ - volatile uint32_t NXLA_13; /* NXLA_13 */ - volatile uint32_t CRLA_13; /* CRLA_13 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_14; /* N0SA_14 */ - volatile uint32_t N0DA_14; /* N0DA_14 */ - volatile uint32_t N0TB_14; /* N0TB_14 */ - volatile uint32_t N1SA_14; /* N1SA_14 */ - volatile uint32_t N1DA_14; /* N1DA_14 */ - volatile uint32_t N1TB_14; /* N1TB_14 */ - volatile uint32_t CRSA_14; /* CRSA_14 */ - volatile uint32_t CRDA_14; /* CRDA_14 */ - volatile uint32_t CRTB_14; /* CRTB_14 */ - volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ - volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ - volatile uint32_t CHCFG_14; /* CHCFG_14 */ - volatile uint32_t CHITVL_14; /* CHITVL_14 */ - volatile uint32_t CHEXT_14; /* CHEXT_14 */ - volatile uint32_t NXLA_14; /* NXLA_14 */ - volatile uint32_t CRLA_14; /* CRLA_14 */ -/* end of struct st_dmac_n */ -/* start of struct st_dmac_n */ - volatile uint32_t N0SA_15; /* N0SA_15 */ - volatile uint32_t N0DA_15; /* N0DA_15 */ - volatile uint32_t N0TB_15; /* N0TB_15 */ - volatile uint32_t N1SA_15; /* N1SA_15 */ - volatile uint32_t N1DA_15; /* N1DA_15 */ - volatile uint32_t N1TB_15; /* N1TB_15 */ - volatile uint32_t CRSA_15; /* CRSA_15 */ - volatile uint32_t CRDA_15; /* CRDA_15 */ - volatile uint32_t CRTB_15; /* CRTB_15 */ - volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ - volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ - volatile uint32_t CHCFG_15; /* CHCFG_15 */ - volatile uint32_t CHITVL_15; /* CHITVL_15 */ - volatile uint32_t CHEXT_15; /* CHEXT_15 */ - volatile uint32_t NXLA_15; /* NXLA_15 */ - volatile uint32_t CRLA_15; /* CRLA_15 */ -/* end of struct st_dmac_n */ - volatile uint8_t dummy190[256]; /* */ -/* start of struct st_dmaccommon_n */ - volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ - volatile uint8_t dummy191[12]; /* */ - volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ - volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ - volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ - volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ - volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ -/* end of struct st_dmaccommon_n */ - volatile uint8_t dummy192[350095580]; /* */ - volatile uint32_t DMARS0; /* DMARS0 */ - volatile uint32_t DMARS1; /* DMARS1 */ - volatile uint32_t DMARS2; /* DMARS2 */ - volatile uint32_t DMARS3; /* DMARS3 */ - volatile uint32_t DMARS4; /* DMARS4 */ - volatile uint32_t DMARS5; /* DMARS5 */ - volatile uint32_t DMARS6; /* DMARS6 */ - volatile uint32_t DMARS7; /* DMARS7 */ -}; -struct st_dmaccommon_n -{ - volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ - volatile uint8_t dummy1[12]; /* */ - volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ - volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ - volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ - volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ - volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ -}; - - -struct st_dmac_n -{ - volatile uint32_t N0SA_n; /* N0SA_n */ - volatile uint32_t N0DA_n; /* N0DA_n */ - volatile uint32_t N0TB_n; /* N0TB_n */ - volatile uint32_t N1SA_n; /* N1SA_n */ - volatile uint32_t N1DA_n; /* N1DA_n */ - volatile uint32_t N1TB_n; /* N1TB_n */ - volatile uint32_t CRSA_n; /* CRSA_n */ - volatile uint32_t CRDA_n; /* CRDA_n */ - volatile uint32_t CRTB_n; /* CRTB_n */ - volatile uint32_t CHSTAT_n; /* CHSTAT_n */ - volatile uint32_t CHCTRL_n; /* CHCTRL_n */ - volatile uint32_t CHCFG_n; /* CHCFG_n */ - volatile uint32_t CHITVL_n; /* CHITVL_n */ - volatile uint32_t CHEXT_n; /* CHEXT_n */ - volatile uint32_t NXLA_n; /* NXLA_n */ - volatile uint32_t CRLA_n; /* CRLA_n */ -}; +/* Channel array defines of DMACmm */ +#define DMACmm_COUNT (8) +#define DMACmm_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ +#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ +#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ +#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ +#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ +#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ +#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ +#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ +/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ #define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */ -/* Start of channnel array defines of DMAC */ +/* Start of channel array defines of DMAC */ -/* Channnel array defines of DMACn */ +/* Channel array defines of DMACn */ /*(Sample) value = DMACn[ channel ]->N0SA_n; */ -#define DMACn_COUNT 16 +#define DMACn_COUNT (16) #define DMACn_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \ @@ -418,9 +83,9 @@ struct st_dmac_n #define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */ -/* Channnel array defines of DMACnn */ +/* Channel array defines of DMACnn */ /*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */ -#define DMACnn_COUNT 2 +#define DMACnn_COUNT (2) #define DMACnn_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &DMAC07, &DMAC815 \ @@ -428,306 +93,715 @@ struct st_dmac_n #define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */ #define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */ +/* End of channel array defines of DMAC */ -/* Channnel array defines of DMACmm */ -/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */ -struct st_dmars_mm + +#define DMACN0SA_0 (DMAC.N0SA_0) +#define DMACN0DA_0 (DMAC.N0DA_0) +#define DMACN0TB_0 (DMAC.N0TB_0) +#define DMACN1SA_0 (DMAC.N1SA_0) +#define DMACN1DA_0 (DMAC.N1DA_0) +#define DMACN1TB_0 (DMAC.N1TB_0) +#define DMACCRSA_0 (DMAC.CRSA_0) +#define DMACCRDA_0 (DMAC.CRDA_0) +#define DMACCRTB_0 (DMAC.CRTB_0) +#define DMACCHSTAT_0 (DMAC.CHSTAT_0) +#define DMACCHCTRL_0 (DMAC.CHCTRL_0) +#define DMACCHCFG_0 (DMAC.CHCFG_0) +#define DMACCHITVL_0 (DMAC.CHITVL_0) +#define DMACCHEXT_0 (DMAC.CHEXT_0) +#define DMACNXLA_0 (DMAC.NXLA_0) +#define DMACCRLA_0 (DMAC.CRLA_0) +#define DMACN0SA_1 (DMAC.N0SA_1) +#define DMACN0DA_1 (DMAC.N0DA_1) +#define DMACN0TB_1 (DMAC.N0TB_1) +#define DMACN1SA_1 (DMAC.N1SA_1) +#define DMACN1DA_1 (DMAC.N1DA_1) +#define DMACN1TB_1 (DMAC.N1TB_1) +#define DMACCRSA_1 (DMAC.CRSA_1) +#define DMACCRDA_1 (DMAC.CRDA_1) +#define DMACCRTB_1 (DMAC.CRTB_1) +#define DMACCHSTAT_1 (DMAC.CHSTAT_1) +#define DMACCHCTRL_1 (DMAC.CHCTRL_1) +#define DMACCHCFG_1 (DMAC.CHCFG_1) +#define DMACCHITVL_1 (DMAC.CHITVL_1) +#define DMACCHEXT_1 (DMAC.CHEXT_1) +#define DMACNXLA_1 (DMAC.NXLA_1) +#define DMACCRLA_1 (DMAC.CRLA_1) +#define DMACN0SA_2 (DMAC.N0SA_2) +#define DMACN0DA_2 (DMAC.N0DA_2) +#define DMACN0TB_2 (DMAC.N0TB_2) +#define DMACN1SA_2 (DMAC.N1SA_2) +#define DMACN1DA_2 (DMAC.N1DA_2) +#define DMACN1TB_2 (DMAC.N1TB_2) +#define DMACCRSA_2 (DMAC.CRSA_2) +#define DMACCRDA_2 (DMAC.CRDA_2) +#define DMACCRTB_2 (DMAC.CRTB_2) +#define DMACCHSTAT_2 (DMAC.CHSTAT_2) +#define DMACCHCTRL_2 (DMAC.CHCTRL_2) +#define DMACCHCFG_2 (DMAC.CHCFG_2) +#define DMACCHITVL_2 (DMAC.CHITVL_2) +#define DMACCHEXT_2 (DMAC.CHEXT_2) +#define DMACNXLA_2 (DMAC.NXLA_2) +#define DMACCRLA_2 (DMAC.CRLA_2) +#define DMACN0SA_3 (DMAC.N0SA_3) +#define DMACN0DA_3 (DMAC.N0DA_3) +#define DMACN0TB_3 (DMAC.N0TB_3) +#define DMACN1SA_3 (DMAC.N1SA_3) +#define DMACN1DA_3 (DMAC.N1DA_3) +#define DMACN1TB_3 (DMAC.N1TB_3) +#define DMACCRSA_3 (DMAC.CRSA_3) +#define DMACCRDA_3 (DMAC.CRDA_3) +#define DMACCRTB_3 (DMAC.CRTB_3) +#define DMACCHSTAT_3 (DMAC.CHSTAT_3) +#define DMACCHCTRL_3 (DMAC.CHCTRL_3) +#define DMACCHCFG_3 (DMAC.CHCFG_3) +#define DMACCHITVL_3 (DMAC.CHITVL_3) +#define DMACCHEXT_3 (DMAC.CHEXT_3) +#define DMACNXLA_3 (DMAC.NXLA_3) +#define DMACCRLA_3 (DMAC.CRLA_3) +#define DMACN0SA_4 (DMAC.N0SA_4) +#define DMACN0DA_4 (DMAC.N0DA_4) +#define DMACN0TB_4 (DMAC.N0TB_4) +#define DMACN1SA_4 (DMAC.N1SA_4) +#define DMACN1DA_4 (DMAC.N1DA_4) +#define DMACN1TB_4 (DMAC.N1TB_4) +#define DMACCRSA_4 (DMAC.CRSA_4) +#define DMACCRDA_4 (DMAC.CRDA_4) +#define DMACCRTB_4 (DMAC.CRTB_4) +#define DMACCHSTAT_4 (DMAC.CHSTAT_4) +#define DMACCHCTRL_4 (DMAC.CHCTRL_4) +#define DMACCHCFG_4 (DMAC.CHCFG_4) +#define DMACCHITVL_4 (DMAC.CHITVL_4) +#define DMACCHEXT_4 (DMAC.CHEXT_4) +#define DMACNXLA_4 (DMAC.NXLA_4) +#define DMACCRLA_4 (DMAC.CRLA_4) +#define DMACN0SA_5 (DMAC.N0SA_5) +#define DMACN0DA_5 (DMAC.N0DA_5) +#define DMACN0TB_5 (DMAC.N0TB_5) +#define DMACN1SA_5 (DMAC.N1SA_5) +#define DMACN1DA_5 (DMAC.N1DA_5) +#define DMACN1TB_5 (DMAC.N1TB_5) +#define DMACCRSA_5 (DMAC.CRSA_5) +#define DMACCRDA_5 (DMAC.CRDA_5) +#define DMACCRTB_5 (DMAC.CRTB_5) +#define DMACCHSTAT_5 (DMAC.CHSTAT_5) +#define DMACCHCTRL_5 (DMAC.CHCTRL_5) +#define DMACCHCFG_5 (DMAC.CHCFG_5) +#define DMACCHITVL_5 (DMAC.CHITVL_5) +#define DMACCHEXT_5 (DMAC.CHEXT_5) +#define DMACNXLA_5 (DMAC.NXLA_5) +#define DMACCRLA_5 (DMAC.CRLA_5) +#define DMACN0SA_6 (DMAC.N0SA_6) +#define DMACN0DA_6 (DMAC.N0DA_6) +#define DMACN0TB_6 (DMAC.N0TB_6) +#define DMACN1SA_6 (DMAC.N1SA_6) +#define DMACN1DA_6 (DMAC.N1DA_6) +#define DMACN1TB_6 (DMAC.N1TB_6) +#define DMACCRSA_6 (DMAC.CRSA_6) +#define DMACCRDA_6 (DMAC.CRDA_6) +#define DMACCRTB_6 (DMAC.CRTB_6) +#define DMACCHSTAT_6 (DMAC.CHSTAT_6) +#define DMACCHCTRL_6 (DMAC.CHCTRL_6) +#define DMACCHCFG_6 (DMAC.CHCFG_6) +#define DMACCHITVL_6 (DMAC.CHITVL_6) +#define DMACCHEXT_6 (DMAC.CHEXT_6) +#define DMACNXLA_6 (DMAC.NXLA_6) +#define DMACCRLA_6 (DMAC.CRLA_6) +#define DMACN0SA_7 (DMAC.N0SA_7) +#define DMACN0DA_7 (DMAC.N0DA_7) +#define DMACN0TB_7 (DMAC.N0TB_7) +#define DMACN1SA_7 (DMAC.N1SA_7) +#define DMACN1DA_7 (DMAC.N1DA_7) +#define DMACN1TB_7 (DMAC.N1TB_7) +#define DMACCRSA_7 (DMAC.CRSA_7) +#define DMACCRDA_7 (DMAC.CRDA_7) +#define DMACCRTB_7 (DMAC.CRTB_7) +#define DMACCHSTAT_7 (DMAC.CHSTAT_7) +#define DMACCHCTRL_7 (DMAC.CHCTRL_7) +#define DMACCHCFG_7 (DMAC.CHCFG_7) +#define DMACCHITVL_7 (DMAC.CHITVL_7) +#define DMACCHEXT_7 (DMAC.CHEXT_7) +#define DMACNXLA_7 (DMAC.NXLA_7) +#define DMACCRLA_7 (DMAC.CRLA_7) +#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7) +#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7) +#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7) +#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7) +#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7) +#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7) +#define DMACN0SA_8 (DMAC.N0SA_8) +#define DMACN0DA_8 (DMAC.N0DA_8) +#define DMACN0TB_8 (DMAC.N0TB_8) +#define DMACN1SA_8 (DMAC.N1SA_8) +#define DMACN1DA_8 (DMAC.N1DA_8) +#define DMACN1TB_8 (DMAC.N1TB_8) +#define DMACCRSA_8 (DMAC.CRSA_8) +#define DMACCRDA_8 (DMAC.CRDA_8) +#define DMACCRTB_8 (DMAC.CRTB_8) +#define DMACCHSTAT_8 (DMAC.CHSTAT_8) +#define DMACCHCTRL_8 (DMAC.CHCTRL_8) +#define DMACCHCFG_8 (DMAC.CHCFG_8) +#define DMACCHITVL_8 (DMAC.CHITVL_8) +#define DMACCHEXT_8 (DMAC.CHEXT_8) +#define DMACNXLA_8 (DMAC.NXLA_8) +#define DMACCRLA_8 (DMAC.CRLA_8) +#define DMACN0SA_9 (DMAC.N0SA_9) +#define DMACN0DA_9 (DMAC.N0DA_9) +#define DMACN0TB_9 (DMAC.N0TB_9) +#define DMACN1SA_9 (DMAC.N1SA_9) +#define DMACN1DA_9 (DMAC.N1DA_9) +#define DMACN1TB_9 (DMAC.N1TB_9) +#define DMACCRSA_9 (DMAC.CRSA_9) +#define DMACCRDA_9 (DMAC.CRDA_9) +#define DMACCRTB_9 (DMAC.CRTB_9) +#define DMACCHSTAT_9 (DMAC.CHSTAT_9) +#define DMACCHCTRL_9 (DMAC.CHCTRL_9) +#define DMACCHCFG_9 (DMAC.CHCFG_9) +#define DMACCHITVL_9 (DMAC.CHITVL_9) +#define DMACCHEXT_9 (DMAC.CHEXT_9) +#define DMACNXLA_9 (DMAC.NXLA_9) +#define DMACCRLA_9 (DMAC.CRLA_9) +#define DMACN0SA_10 (DMAC.N0SA_10) +#define DMACN0DA_10 (DMAC.N0DA_10) +#define DMACN0TB_10 (DMAC.N0TB_10) +#define DMACN1SA_10 (DMAC.N1SA_10) +#define DMACN1DA_10 (DMAC.N1DA_10) +#define DMACN1TB_10 (DMAC.N1TB_10) +#define DMACCRSA_10 (DMAC.CRSA_10) +#define DMACCRDA_10 (DMAC.CRDA_10) +#define DMACCRTB_10 (DMAC.CRTB_10) +#define DMACCHSTAT_10 (DMAC.CHSTAT_10) +#define DMACCHCTRL_10 (DMAC.CHCTRL_10) +#define DMACCHCFG_10 (DMAC.CHCFG_10) +#define DMACCHITVL_10 (DMAC.CHITVL_10) +#define DMACCHEXT_10 (DMAC.CHEXT_10) +#define DMACNXLA_10 (DMAC.NXLA_10) +#define DMACCRLA_10 (DMAC.CRLA_10) +#define DMACN0SA_11 (DMAC.N0SA_11) +#define DMACN0DA_11 (DMAC.N0DA_11) +#define DMACN0TB_11 (DMAC.N0TB_11) +#define DMACN1SA_11 (DMAC.N1SA_11) +#define DMACN1DA_11 (DMAC.N1DA_11) +#define DMACN1TB_11 (DMAC.N1TB_11) +#define DMACCRSA_11 (DMAC.CRSA_11) +#define DMACCRDA_11 (DMAC.CRDA_11) +#define DMACCRTB_11 (DMAC.CRTB_11) +#define DMACCHSTAT_11 (DMAC.CHSTAT_11) +#define DMACCHCTRL_11 (DMAC.CHCTRL_11) +#define DMACCHCFG_11 (DMAC.CHCFG_11) +#define DMACCHITVL_11 (DMAC.CHITVL_11) +#define DMACCHEXT_11 (DMAC.CHEXT_11) +#define DMACNXLA_11 (DMAC.NXLA_11) +#define DMACCRLA_11 (DMAC.CRLA_11) +#define DMACN0SA_12 (DMAC.N0SA_12) +#define DMACN0DA_12 (DMAC.N0DA_12) +#define DMACN0TB_12 (DMAC.N0TB_12) +#define DMACN1SA_12 (DMAC.N1SA_12) +#define DMACN1DA_12 (DMAC.N1DA_12) +#define DMACN1TB_12 (DMAC.N1TB_12) +#define DMACCRSA_12 (DMAC.CRSA_12) +#define DMACCRDA_12 (DMAC.CRDA_12) +#define DMACCRTB_12 (DMAC.CRTB_12) +#define DMACCHSTAT_12 (DMAC.CHSTAT_12) +#define DMACCHCTRL_12 (DMAC.CHCTRL_12) +#define DMACCHCFG_12 (DMAC.CHCFG_12) +#define DMACCHITVL_12 (DMAC.CHITVL_12) +#define DMACCHEXT_12 (DMAC.CHEXT_12) +#define DMACNXLA_12 (DMAC.NXLA_12) +#define DMACCRLA_12 (DMAC.CRLA_12) +#define DMACN0SA_13 (DMAC.N0SA_13) +#define DMACN0DA_13 (DMAC.N0DA_13) +#define DMACN0TB_13 (DMAC.N0TB_13) +#define DMACN1SA_13 (DMAC.N1SA_13) +#define DMACN1DA_13 (DMAC.N1DA_13) +#define DMACN1TB_13 (DMAC.N1TB_13) +#define DMACCRSA_13 (DMAC.CRSA_13) +#define DMACCRDA_13 (DMAC.CRDA_13) +#define DMACCRTB_13 (DMAC.CRTB_13) +#define DMACCHSTAT_13 (DMAC.CHSTAT_13) +#define DMACCHCTRL_13 (DMAC.CHCTRL_13) +#define DMACCHCFG_13 (DMAC.CHCFG_13) +#define DMACCHITVL_13 (DMAC.CHITVL_13) +#define DMACCHEXT_13 (DMAC.CHEXT_13) +#define DMACNXLA_13 (DMAC.NXLA_13) +#define DMACCRLA_13 (DMAC.CRLA_13) +#define DMACN0SA_14 (DMAC.N0SA_14) +#define DMACN0DA_14 (DMAC.N0DA_14) +#define DMACN0TB_14 (DMAC.N0TB_14) +#define DMACN1SA_14 (DMAC.N1SA_14) +#define DMACN1DA_14 (DMAC.N1DA_14) +#define DMACN1TB_14 (DMAC.N1TB_14) +#define DMACCRSA_14 (DMAC.CRSA_14) +#define DMACCRDA_14 (DMAC.CRDA_14) +#define DMACCRTB_14 (DMAC.CRTB_14) +#define DMACCHSTAT_14 (DMAC.CHSTAT_14) +#define DMACCHCTRL_14 (DMAC.CHCTRL_14) +#define DMACCHCFG_14 (DMAC.CHCFG_14) +#define DMACCHITVL_14 (DMAC.CHITVL_14) +#define DMACCHEXT_14 (DMAC.CHEXT_14) +#define DMACNXLA_14 (DMAC.NXLA_14) +#define DMACCRLA_14 (DMAC.CRLA_14) +#define DMACN0SA_15 (DMAC.N0SA_15) +#define DMACN0DA_15 (DMAC.N0DA_15) +#define DMACN0TB_15 (DMAC.N0TB_15) +#define DMACN1SA_15 (DMAC.N1SA_15) +#define DMACN1DA_15 (DMAC.N1DA_15) +#define DMACN1TB_15 (DMAC.N1TB_15) +#define DMACCRSA_15 (DMAC.CRSA_15) +#define DMACCRDA_15 (DMAC.CRDA_15) +#define DMACCRTB_15 (DMAC.CRTB_15) +#define DMACCHSTAT_15 (DMAC.CHSTAT_15) +#define DMACCHCTRL_15 (DMAC.CHCTRL_15) +#define DMACCHCFG_15 (DMAC.CHCFG_15) +#define DMACCHITVL_15 (DMAC.CHITVL_15) +#define DMACCHEXT_15 (DMAC.CHEXT_15) +#define DMACNXLA_15 (DMAC.NXLA_15) +#define DMACCRLA_15 (DMAC.CRLA_15) +#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15) +#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15) +#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15) +#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15) +#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15) +#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15) +#define DMACDMARS0 (DMAC.DMARS0) +#define DMACDMARS1 (DMAC.DMARS1) +#define DMACDMARS2 (DMAC.DMARS2) +#define DMACDMARS3 (DMAC.DMARS3) +#define DMACDMARS4 (DMAC.DMARS4) +#define DMACDMARS5 (DMAC.DMARS5) +#define DMACDMARS6 (DMAC.DMARS6) +#define DMACDMARS7 (DMAC.DMARS7) + + +typedef struct st_dmars_mm { - uint32_t DMARS; /* DMARS */ -}; -#define DMACmm_COUNT 8 -#define DMACmm_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */ -#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */ -#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */ -#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */ -#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */ -#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */ -#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */ -#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */ - -/* End of channnel array defines of DMAC */ + + volatile uint32_t DMARS; /* DMARS */ +} r_io_dmars_mm_t; + + +typedef struct st_dmac +{ + /* DMAC */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_0; /* N0SA_0 */ + volatile uint32_t N0DA_0; /* N0DA_0 */ + volatile uint32_t N0TB_0; /* N0TB_0 */ + volatile uint32_t N1SA_0; /* N1SA_0 */ + volatile uint32_t N1DA_0; /* N1DA_0 */ + volatile uint32_t N1TB_0; /* N1TB_0 */ + volatile uint32_t CRSA_0; /* CRSA_0 */ + volatile uint32_t CRDA_0; /* CRDA_0 */ + volatile uint32_t CRTB_0; /* CRTB_0 */ + volatile uint32_t CHSTAT_0; /* CHSTAT_0 */ + volatile uint32_t CHCTRL_0; /* CHCTRL_0 */ + volatile uint32_t CHCFG_0; /* CHCFG_0 */ + volatile uint32_t CHITVL_0; /* CHITVL_0 */ + volatile uint32_t CHEXT_0; /* CHEXT_0 */ + volatile uint32_t NXLA_0; /* NXLA_0 */ + volatile uint32_t CRLA_0; /* CRLA_0 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_1; /* N0SA_1 */ + volatile uint32_t N0DA_1; /* N0DA_1 */ + volatile uint32_t N0TB_1; /* N0TB_1 */ + volatile uint32_t N1SA_1; /* N1SA_1 */ + volatile uint32_t N1DA_1; /* N1DA_1 */ + volatile uint32_t N1TB_1; /* N1TB_1 */ + volatile uint32_t CRSA_1; /* CRSA_1 */ + volatile uint32_t CRDA_1; /* CRDA_1 */ + volatile uint32_t CRTB_1; /* CRTB_1 */ + volatile uint32_t CHSTAT_1; /* CHSTAT_1 */ + volatile uint32_t CHCTRL_1; /* CHCTRL_1 */ + volatile uint32_t CHCFG_1; /* CHCFG_1 */ + volatile uint32_t CHITVL_1; /* CHITVL_1 */ + volatile uint32_t CHEXT_1; /* CHEXT_1 */ + volatile uint32_t NXLA_1; /* NXLA_1 */ + volatile uint32_t CRLA_1; /* CRLA_1 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_2; /* N0SA_2 */ + volatile uint32_t N0DA_2; /* N0DA_2 */ + volatile uint32_t N0TB_2; /* N0TB_2 */ + volatile uint32_t N1SA_2; /* N1SA_2 */ + volatile uint32_t N1DA_2; /* N1DA_2 */ + volatile uint32_t N1TB_2; /* N1TB_2 */ + volatile uint32_t CRSA_2; /* CRSA_2 */ + volatile uint32_t CRDA_2; /* CRDA_2 */ + volatile uint32_t CRTB_2; /* CRTB_2 */ + volatile uint32_t CHSTAT_2; /* CHSTAT_2 */ + volatile uint32_t CHCTRL_2; /* CHCTRL_2 */ + volatile uint32_t CHCFG_2; /* CHCFG_2 */ + volatile uint32_t CHITVL_2; /* CHITVL_2 */ + volatile uint32_t CHEXT_2; /* CHEXT_2 */ + volatile uint32_t NXLA_2; /* NXLA_2 */ + volatile uint32_t CRLA_2; /* CRLA_2 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_3; /* N0SA_3 */ + volatile uint32_t N0DA_3; /* N0DA_3 */ + volatile uint32_t N0TB_3; /* N0TB_3 */ + volatile uint32_t N1SA_3; /* N1SA_3 */ + volatile uint32_t N1DA_3; /* N1DA_3 */ + volatile uint32_t N1TB_3; /* N1TB_3 */ + volatile uint32_t CRSA_3; /* CRSA_3 */ + volatile uint32_t CRDA_3; /* CRDA_3 */ + volatile uint32_t CRTB_3; /* CRTB_3 */ + volatile uint32_t CHSTAT_3; /* CHSTAT_3 */ + volatile uint32_t CHCTRL_3; /* CHCTRL_3 */ + volatile uint32_t CHCFG_3; /* CHCFG_3 */ + volatile uint32_t CHITVL_3; /* CHITVL_3 */ + volatile uint32_t CHEXT_3; /* CHEXT_3 */ + volatile uint32_t NXLA_3; /* NXLA_3 */ + volatile uint32_t CRLA_3; /* CRLA_3 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_4; /* N0SA_4 */ + volatile uint32_t N0DA_4; /* N0DA_4 */ + volatile uint32_t N0TB_4; /* N0TB_4 */ + volatile uint32_t N1SA_4; /* N1SA_4 */ + volatile uint32_t N1DA_4; /* N1DA_4 */ + volatile uint32_t N1TB_4; /* N1TB_4 */ + volatile uint32_t CRSA_4; /* CRSA_4 */ + volatile uint32_t CRDA_4; /* CRDA_4 */ + volatile uint32_t CRTB_4; /* CRTB_4 */ + volatile uint32_t CHSTAT_4; /* CHSTAT_4 */ + volatile uint32_t CHCTRL_4; /* CHCTRL_4 */ + volatile uint32_t CHCFG_4; /* CHCFG_4 */ + volatile uint32_t CHITVL_4; /* CHITVL_4 */ + volatile uint32_t CHEXT_4; /* CHEXT_4 */ + volatile uint32_t NXLA_4; /* NXLA_4 */ + volatile uint32_t CRLA_4; /* CRLA_4 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_5; /* N0SA_5 */ + volatile uint32_t N0DA_5; /* N0DA_5 */ + volatile uint32_t N0TB_5; /* N0TB_5 */ + volatile uint32_t N1SA_5; /* N1SA_5 */ + volatile uint32_t N1DA_5; /* N1DA_5 */ + volatile uint32_t N1TB_5; /* N1TB_5 */ + volatile uint32_t CRSA_5; /* CRSA_5 */ + volatile uint32_t CRDA_5; /* CRDA_5 */ + volatile uint32_t CRTB_5; /* CRTB_5 */ + volatile uint32_t CHSTAT_5; /* CHSTAT_5 */ + volatile uint32_t CHCTRL_5; /* CHCTRL_5 */ + volatile uint32_t CHCFG_5; /* CHCFG_5 */ + volatile uint32_t CHITVL_5; /* CHITVL_5 */ + volatile uint32_t CHEXT_5; /* CHEXT_5 */ + volatile uint32_t NXLA_5; /* NXLA_5 */ + volatile uint32_t CRLA_5; /* CRLA_5 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_6; /* N0SA_6 */ + volatile uint32_t N0DA_6; /* N0DA_6 */ + volatile uint32_t N0TB_6; /* N0TB_6 */ + volatile uint32_t N1SA_6; /* N1SA_6 */ + volatile uint32_t N1DA_6; /* N1DA_6 */ + volatile uint32_t N1TB_6; /* N1TB_6 */ + volatile uint32_t CRSA_6; /* CRSA_6 */ + volatile uint32_t CRDA_6; /* CRDA_6 */ + volatile uint32_t CRTB_6; /* CRTB_6 */ + volatile uint32_t CHSTAT_6; /* CHSTAT_6 */ + volatile uint32_t CHCTRL_6; /* CHCTRL_6 */ + volatile uint32_t CHCFG_6; /* CHCFG_6 */ + volatile uint32_t CHITVL_6; /* CHITVL_6 */ + volatile uint32_t CHEXT_6; /* CHEXT_6 */ + volatile uint32_t NXLA_6; /* NXLA_6 */ + volatile uint32_t CRLA_6; /* CRLA_6 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_7; /* N0SA_7 */ + volatile uint32_t N0DA_7; /* N0DA_7 */ + volatile uint32_t N0TB_7; /* N0TB_7 */ + volatile uint32_t N1SA_7; /* N1SA_7 */ + volatile uint32_t N1DA_7; /* N1DA_7 */ + volatile uint32_t N1TB_7; /* N1TB_7 */ + volatile uint32_t CRSA_7; /* CRSA_7 */ + volatile uint32_t CRDA_7; /* CRDA_7 */ + volatile uint32_t CRTB_7; /* CRTB_7 */ + volatile uint32_t CHSTAT_7; /* CHSTAT_7 */ + volatile uint32_t CHCTRL_7; /* CHCTRL_7 */ + volatile uint32_t CHCFG_7; /* CHCFG_7 */ + volatile uint32_t CHITVL_7; /* CHITVL_7 */ + volatile uint32_t CHEXT_7; /* CHEXT_7 */ + volatile uint32_t NXLA_7; /* NXLA_7 */ + volatile uint32_t CRLA_7; /* CRLA_7 */ + +/* end of struct st_dmac_n */ + volatile uint8_t dummy187[256]; /* */ + +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy188[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ + +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy189[220]; /* */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_8; /* N0SA_8 */ + volatile uint32_t N0DA_8; /* N0DA_8 */ + volatile uint32_t N0TB_8; /* N0TB_8 */ + volatile uint32_t N1SA_8; /* N1SA_8 */ + volatile uint32_t N1DA_8; /* N1DA_8 */ + volatile uint32_t N1TB_8; /* N1TB_8 */ + volatile uint32_t CRSA_8; /* CRSA_8 */ + volatile uint32_t CRDA_8; /* CRDA_8 */ + volatile uint32_t CRTB_8; /* CRTB_8 */ + volatile uint32_t CHSTAT_8; /* CHSTAT_8 */ + volatile uint32_t CHCTRL_8; /* CHCTRL_8 */ + volatile uint32_t CHCFG_8; /* CHCFG_8 */ + volatile uint32_t CHITVL_8; /* CHITVL_8 */ + volatile uint32_t CHEXT_8; /* CHEXT_8 */ + volatile uint32_t NXLA_8; /* NXLA_8 */ + volatile uint32_t CRLA_8; /* CRLA_8 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_9; /* N0SA_9 */ + volatile uint32_t N0DA_9; /* N0DA_9 */ + volatile uint32_t N0TB_9; /* N0TB_9 */ + volatile uint32_t N1SA_9; /* N1SA_9 */ + volatile uint32_t N1DA_9; /* N1DA_9 */ + volatile uint32_t N1TB_9; /* N1TB_9 */ + volatile uint32_t CRSA_9; /* CRSA_9 */ + volatile uint32_t CRDA_9; /* CRDA_9 */ + volatile uint32_t CRTB_9; /* CRTB_9 */ + volatile uint32_t CHSTAT_9; /* CHSTAT_9 */ + volatile uint32_t CHCTRL_9; /* CHCTRL_9 */ + volatile uint32_t CHCFG_9; /* CHCFG_9 */ + volatile uint32_t CHITVL_9; /* CHITVL_9 */ + volatile uint32_t CHEXT_9; /* CHEXT_9 */ + volatile uint32_t NXLA_9; /* NXLA_9 */ + volatile uint32_t CRLA_9; /* CRLA_9 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_10; /* N0SA_10 */ + volatile uint32_t N0DA_10; /* N0DA_10 */ + volatile uint32_t N0TB_10; /* N0TB_10 */ + volatile uint32_t N1SA_10; /* N1SA_10 */ + volatile uint32_t N1DA_10; /* N1DA_10 */ + volatile uint32_t N1TB_10; /* N1TB_10 */ + volatile uint32_t CRSA_10; /* CRSA_10 */ + volatile uint32_t CRDA_10; /* CRDA_10 */ + volatile uint32_t CRTB_10; /* CRTB_10 */ + volatile uint32_t CHSTAT_10; /* CHSTAT_10 */ + volatile uint32_t CHCTRL_10; /* CHCTRL_10 */ + volatile uint32_t CHCFG_10; /* CHCFG_10 */ + volatile uint32_t CHITVL_10; /* CHITVL_10 */ + volatile uint32_t CHEXT_10; /* CHEXT_10 */ + volatile uint32_t NXLA_10; /* NXLA_10 */ + volatile uint32_t CRLA_10; /* CRLA_10 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_11; /* N0SA_11 */ + volatile uint32_t N0DA_11; /* N0DA_11 */ + volatile uint32_t N0TB_11; /* N0TB_11 */ + volatile uint32_t N1SA_11; /* N1SA_11 */ + volatile uint32_t N1DA_11; /* N1DA_11 */ + volatile uint32_t N1TB_11; /* N1TB_11 */ + volatile uint32_t CRSA_11; /* CRSA_11 */ + volatile uint32_t CRDA_11; /* CRDA_11 */ + volatile uint32_t CRTB_11; /* CRTB_11 */ + volatile uint32_t CHSTAT_11; /* CHSTAT_11 */ + volatile uint32_t CHCTRL_11; /* CHCTRL_11 */ + volatile uint32_t CHCFG_11; /* CHCFG_11 */ + volatile uint32_t CHITVL_11; /* CHITVL_11 */ + volatile uint32_t CHEXT_11; /* CHEXT_11 */ + volatile uint32_t NXLA_11; /* NXLA_11 */ + volatile uint32_t CRLA_11; /* CRLA_11 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_12; /* N0SA_12 */ + volatile uint32_t N0DA_12; /* N0DA_12 */ + volatile uint32_t N0TB_12; /* N0TB_12 */ + volatile uint32_t N1SA_12; /* N1SA_12 */ + volatile uint32_t N1DA_12; /* N1DA_12 */ + volatile uint32_t N1TB_12; /* N1TB_12 */ + volatile uint32_t CRSA_12; /* CRSA_12 */ + volatile uint32_t CRDA_12; /* CRDA_12 */ + volatile uint32_t CRTB_12; /* CRTB_12 */ + volatile uint32_t CHSTAT_12; /* CHSTAT_12 */ + volatile uint32_t CHCTRL_12; /* CHCTRL_12 */ + volatile uint32_t CHCFG_12; /* CHCFG_12 */ + volatile uint32_t CHITVL_12; /* CHITVL_12 */ + volatile uint32_t CHEXT_12; /* CHEXT_12 */ + volatile uint32_t NXLA_12; /* NXLA_12 */ + volatile uint32_t CRLA_12; /* CRLA_12 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_13; /* N0SA_13 */ + volatile uint32_t N0DA_13; /* N0DA_13 */ + volatile uint32_t N0TB_13; /* N0TB_13 */ + volatile uint32_t N1SA_13; /* N1SA_13 */ + volatile uint32_t N1DA_13; /* N1DA_13 */ + volatile uint32_t N1TB_13; /* N1TB_13 */ + volatile uint32_t CRSA_13; /* CRSA_13 */ + volatile uint32_t CRDA_13; /* CRDA_13 */ + volatile uint32_t CRTB_13; /* CRTB_13 */ + volatile uint32_t CHSTAT_13; /* CHSTAT_13 */ + volatile uint32_t CHCTRL_13; /* CHCTRL_13 */ + volatile uint32_t CHCFG_13; /* CHCFG_13 */ + volatile uint32_t CHITVL_13; /* CHITVL_13 */ + volatile uint32_t CHEXT_13; /* CHEXT_13 */ + volatile uint32_t NXLA_13; /* NXLA_13 */ + volatile uint32_t CRLA_13; /* CRLA_13 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_14; /* N0SA_14 */ + volatile uint32_t N0DA_14; /* N0DA_14 */ + volatile uint32_t N0TB_14; /* N0TB_14 */ + volatile uint32_t N1SA_14; /* N1SA_14 */ + volatile uint32_t N1DA_14; /* N1DA_14 */ + volatile uint32_t N1TB_14; /* N1TB_14 */ + volatile uint32_t CRSA_14; /* CRSA_14 */ + volatile uint32_t CRDA_14; /* CRDA_14 */ + volatile uint32_t CRTB_14; /* CRTB_14 */ + volatile uint32_t CHSTAT_14; /* CHSTAT_14 */ + volatile uint32_t CHCTRL_14; /* CHCTRL_14 */ + volatile uint32_t CHCFG_14; /* CHCFG_14 */ + volatile uint32_t CHITVL_14; /* CHITVL_14 */ + volatile uint32_t CHEXT_14; /* CHEXT_14 */ + volatile uint32_t NXLA_14; /* NXLA_14 */ + volatile uint32_t CRLA_14; /* CRLA_14 */ + +/* end of struct st_dmac_n */ + +/* start of struct st_dmac_n */ + volatile uint32_t N0SA_15; /* N0SA_15 */ + volatile uint32_t N0DA_15; /* N0DA_15 */ + volatile uint32_t N0TB_15; /* N0TB_15 */ + volatile uint32_t N1SA_15; /* N1SA_15 */ + volatile uint32_t N1DA_15; /* N1DA_15 */ + volatile uint32_t N1TB_15; /* N1TB_15 */ + volatile uint32_t CRSA_15; /* CRSA_15 */ + volatile uint32_t CRDA_15; /* CRDA_15 */ + volatile uint32_t CRTB_15; /* CRTB_15 */ + volatile uint32_t CHSTAT_15; /* CHSTAT_15 */ + volatile uint32_t CHCTRL_15; /* CHCTRL_15 */ + volatile uint32_t CHCFG_15; /* CHCFG_15 */ + volatile uint32_t CHITVL_15; /* CHITVL_15 */ + volatile uint32_t CHEXT_15; /* CHEXT_15 */ + volatile uint32_t NXLA_15; /* NXLA_15 */ + volatile uint32_t CRLA_15; /* CRLA_15 */ + +/* end of struct st_dmac_n */ + volatile uint8_t dummy190[256]; /* */ + +/* start of struct st_dmaccommon_n */ + volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */ + volatile uint8_t dummy191[12]; /* */ + volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */ + volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */ + volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */ + volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */ + volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */ + +/* end of struct st_dmaccommon_n */ + volatile uint8_t dummy192[350095580]; /* */ + volatile uint32_t DMARS0; /* DMARS0 */ + volatile uint32_t DMARS1; /* DMARS1 */ + volatile uint32_t DMARS2; /* DMARS2 */ + volatile uint32_t DMARS3; /* DMARS3 */ + volatile uint32_t DMARS4; /* DMARS4 */ + volatile uint32_t DMARS5; /* DMARS5 */ + volatile uint32_t DMARS6; /* DMARS6 */ + volatile uint32_t DMARS7; /* DMARS7 */ +} r_io_dmac_t; + + +typedef struct st_dmaccommon_n +{ + + volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */ + volatile uint8_t dummy1[12]; /* */ + volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */ + volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */ + volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */ + volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */ + volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */ +} r_io_dmaccommon_n_t; + + +typedef struct st_dmac_n +{ + + volatile uint32_t N0SA_n; /* N0SA_n */ + volatile uint32_t N0DA_n; /* N0DA_n */ + volatile uint32_t N0TB_n; /* N0TB_n */ + volatile uint32_t N1SA_n; /* N1SA_n */ + volatile uint32_t N1DA_n; /* N1DA_n */ + volatile uint32_t N1TB_n; /* N1TB_n */ + volatile uint32_t CRSA_n; /* CRSA_n */ + volatile uint32_t CRDA_n; /* CRDA_n */ + volatile uint32_t CRTB_n; /* CRTB_n */ + volatile uint32_t CHSTAT_n; /* CHSTAT_n */ + volatile uint32_t CHCTRL_n; /* CHCTRL_n */ + volatile uint32_t CHCFG_n; /* CHCFG_n */ + volatile uint32_t CHITVL_n; /* CHITVL_n */ + volatile uint32_t CHEXT_n; /* CHEXT_n */ + volatile uint32_t NXLA_n; /* NXLA_n */ + volatile uint32_t CRLA_n; /* CRLA_n */ +} r_io_dmac_n_t; + + +/* Channel array defines of DMAC (2)*/ +#ifdef DECLARE_DMACmm_CHANNELS +volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACmm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACmm_CHANNELS */ + +#ifdef DECLARE_DMACn_CHANNELS +volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACn_CHANNELS */ + +#ifdef DECLARE_DMACnn_CHANNELS +volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DMACnn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DMACnn_CHANNELS */ +/* End of channel array defines of DMAC (2)*/ -#define DMACN0SA_0 DMAC.N0SA_0 -#define DMACN0DA_0 DMAC.N0DA_0 -#define DMACN0TB_0 DMAC.N0TB_0 -#define DMACN1SA_0 DMAC.N1SA_0 -#define DMACN1DA_0 DMAC.N1DA_0 -#define DMACN1TB_0 DMAC.N1TB_0 -#define DMACCRSA_0 DMAC.CRSA_0 -#define DMACCRDA_0 DMAC.CRDA_0 -#define DMACCRTB_0 DMAC.CRTB_0 -#define DMACCHSTAT_0 DMAC.CHSTAT_0 -#define DMACCHCTRL_0 DMAC.CHCTRL_0 -#define DMACCHCFG_0 DMAC.CHCFG_0 -#define DMACCHITVL_0 DMAC.CHITVL_0 -#define DMACCHEXT_0 DMAC.CHEXT_0 -#define DMACNXLA_0 DMAC.NXLA_0 -#define DMACCRLA_0 DMAC.CRLA_0 -#define DMACN0SA_1 DMAC.N0SA_1 -#define DMACN0DA_1 DMAC.N0DA_1 -#define DMACN0TB_1 DMAC.N0TB_1 -#define DMACN1SA_1 DMAC.N1SA_1 -#define DMACN1DA_1 DMAC.N1DA_1 -#define DMACN1TB_1 DMAC.N1TB_1 -#define DMACCRSA_1 DMAC.CRSA_1 -#define DMACCRDA_1 DMAC.CRDA_1 -#define DMACCRTB_1 DMAC.CRTB_1 -#define DMACCHSTAT_1 DMAC.CHSTAT_1 -#define DMACCHCTRL_1 DMAC.CHCTRL_1 -#define DMACCHCFG_1 DMAC.CHCFG_1 -#define DMACCHITVL_1 DMAC.CHITVL_1 -#define DMACCHEXT_1 DMAC.CHEXT_1 -#define DMACNXLA_1 DMAC.NXLA_1 -#define DMACCRLA_1 DMAC.CRLA_1 -#define DMACN0SA_2 DMAC.N0SA_2 -#define DMACN0DA_2 DMAC.N0DA_2 -#define DMACN0TB_2 DMAC.N0TB_2 -#define DMACN1SA_2 DMAC.N1SA_2 -#define DMACN1DA_2 DMAC.N1DA_2 -#define DMACN1TB_2 DMAC.N1TB_2 -#define DMACCRSA_2 DMAC.CRSA_2 -#define DMACCRDA_2 DMAC.CRDA_2 -#define DMACCRTB_2 DMAC.CRTB_2 -#define DMACCHSTAT_2 DMAC.CHSTAT_2 -#define DMACCHCTRL_2 DMAC.CHCTRL_2 -#define DMACCHCFG_2 DMAC.CHCFG_2 -#define DMACCHITVL_2 DMAC.CHITVL_2 -#define DMACCHEXT_2 DMAC.CHEXT_2 -#define DMACNXLA_2 DMAC.NXLA_2 -#define DMACCRLA_2 DMAC.CRLA_2 -#define DMACN0SA_3 DMAC.N0SA_3 -#define DMACN0DA_3 DMAC.N0DA_3 -#define DMACN0TB_3 DMAC.N0TB_3 -#define DMACN1SA_3 DMAC.N1SA_3 -#define DMACN1DA_3 DMAC.N1DA_3 -#define DMACN1TB_3 DMAC.N1TB_3 -#define DMACCRSA_3 DMAC.CRSA_3 -#define DMACCRDA_3 DMAC.CRDA_3 -#define DMACCRTB_3 DMAC.CRTB_3 -#define DMACCHSTAT_3 DMAC.CHSTAT_3 -#define DMACCHCTRL_3 DMAC.CHCTRL_3 -#define DMACCHCFG_3 DMAC.CHCFG_3 -#define DMACCHITVL_3 DMAC.CHITVL_3 -#define DMACCHEXT_3 DMAC.CHEXT_3 -#define DMACNXLA_3 DMAC.NXLA_3 -#define DMACCRLA_3 DMAC.CRLA_3 -#define DMACN0SA_4 DMAC.N0SA_4 -#define DMACN0DA_4 DMAC.N0DA_4 -#define DMACN0TB_4 DMAC.N0TB_4 -#define DMACN1SA_4 DMAC.N1SA_4 -#define DMACN1DA_4 DMAC.N1DA_4 -#define DMACN1TB_4 DMAC.N1TB_4 -#define DMACCRSA_4 DMAC.CRSA_4 -#define DMACCRDA_4 DMAC.CRDA_4 -#define DMACCRTB_4 DMAC.CRTB_4 -#define DMACCHSTAT_4 DMAC.CHSTAT_4 -#define DMACCHCTRL_4 DMAC.CHCTRL_4 -#define DMACCHCFG_4 DMAC.CHCFG_4 -#define DMACCHITVL_4 DMAC.CHITVL_4 -#define DMACCHEXT_4 DMAC.CHEXT_4 -#define DMACNXLA_4 DMAC.NXLA_4 -#define DMACCRLA_4 DMAC.CRLA_4 -#define DMACN0SA_5 DMAC.N0SA_5 -#define DMACN0DA_5 DMAC.N0DA_5 -#define DMACN0TB_5 DMAC.N0TB_5 -#define DMACN1SA_5 DMAC.N1SA_5 -#define DMACN1DA_5 DMAC.N1DA_5 -#define DMACN1TB_5 DMAC.N1TB_5 -#define DMACCRSA_5 DMAC.CRSA_5 -#define DMACCRDA_5 DMAC.CRDA_5 -#define DMACCRTB_5 DMAC.CRTB_5 -#define DMACCHSTAT_5 DMAC.CHSTAT_5 -#define DMACCHCTRL_5 DMAC.CHCTRL_5 -#define DMACCHCFG_5 DMAC.CHCFG_5 -#define DMACCHITVL_5 DMAC.CHITVL_5 -#define DMACCHEXT_5 DMAC.CHEXT_5 -#define DMACNXLA_5 DMAC.NXLA_5 -#define DMACCRLA_5 DMAC.CRLA_5 -#define DMACN0SA_6 DMAC.N0SA_6 -#define DMACN0DA_6 DMAC.N0DA_6 -#define DMACN0TB_6 DMAC.N0TB_6 -#define DMACN1SA_6 DMAC.N1SA_6 -#define DMACN1DA_6 DMAC.N1DA_6 -#define DMACN1TB_6 DMAC.N1TB_6 -#define DMACCRSA_6 DMAC.CRSA_6 -#define DMACCRDA_6 DMAC.CRDA_6 -#define DMACCRTB_6 DMAC.CRTB_6 -#define DMACCHSTAT_6 DMAC.CHSTAT_6 -#define DMACCHCTRL_6 DMAC.CHCTRL_6 -#define DMACCHCFG_6 DMAC.CHCFG_6 -#define DMACCHITVL_6 DMAC.CHITVL_6 -#define DMACCHEXT_6 DMAC.CHEXT_6 -#define DMACNXLA_6 DMAC.NXLA_6 -#define DMACCRLA_6 DMAC.CRLA_6 -#define DMACN0SA_7 DMAC.N0SA_7 -#define DMACN0DA_7 DMAC.N0DA_7 -#define DMACN0TB_7 DMAC.N0TB_7 -#define DMACN1SA_7 DMAC.N1SA_7 -#define DMACN1DA_7 DMAC.N1DA_7 -#define DMACN1TB_7 DMAC.N1TB_7 -#define DMACCRSA_7 DMAC.CRSA_7 -#define DMACCRDA_7 DMAC.CRDA_7 -#define DMACCRTB_7 DMAC.CRTB_7 -#define DMACCHSTAT_7 DMAC.CHSTAT_7 -#define DMACCHCTRL_7 DMAC.CHCTRL_7 -#define DMACCHCFG_7 DMAC.CHCFG_7 -#define DMACCHITVL_7 DMAC.CHITVL_7 -#define DMACCHEXT_7 DMAC.CHEXT_7 -#define DMACNXLA_7 DMAC.NXLA_7 -#define DMACCRLA_7 DMAC.CRLA_7 -#define DMACDCTRL_0_7 DMAC.DCTRL_0_7 -#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7 -#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7 -#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7 -#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7 -#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7 -#define DMACN0SA_8 DMAC.N0SA_8 -#define DMACN0DA_8 DMAC.N0DA_8 -#define DMACN0TB_8 DMAC.N0TB_8 -#define DMACN1SA_8 DMAC.N1SA_8 -#define DMACN1DA_8 DMAC.N1DA_8 -#define DMACN1TB_8 DMAC.N1TB_8 -#define DMACCRSA_8 DMAC.CRSA_8 -#define DMACCRDA_8 DMAC.CRDA_8 -#define DMACCRTB_8 DMAC.CRTB_8 -#define DMACCHSTAT_8 DMAC.CHSTAT_8 -#define DMACCHCTRL_8 DMAC.CHCTRL_8 -#define DMACCHCFG_8 DMAC.CHCFG_8 -#define DMACCHITVL_8 DMAC.CHITVL_8 -#define DMACCHEXT_8 DMAC.CHEXT_8 -#define DMACNXLA_8 DMAC.NXLA_8 -#define DMACCRLA_8 DMAC.CRLA_8 -#define DMACN0SA_9 DMAC.N0SA_9 -#define DMACN0DA_9 DMAC.N0DA_9 -#define DMACN0TB_9 DMAC.N0TB_9 -#define DMACN1SA_9 DMAC.N1SA_9 -#define DMACN1DA_9 DMAC.N1DA_9 -#define DMACN1TB_9 DMAC.N1TB_9 -#define DMACCRSA_9 DMAC.CRSA_9 -#define DMACCRDA_9 DMAC.CRDA_9 -#define DMACCRTB_9 DMAC.CRTB_9 -#define DMACCHSTAT_9 DMAC.CHSTAT_9 -#define DMACCHCTRL_9 DMAC.CHCTRL_9 -#define DMACCHCFG_9 DMAC.CHCFG_9 -#define DMACCHITVL_9 DMAC.CHITVL_9 -#define DMACCHEXT_9 DMAC.CHEXT_9 -#define DMACNXLA_9 DMAC.NXLA_9 -#define DMACCRLA_9 DMAC.CRLA_9 -#define DMACN0SA_10 DMAC.N0SA_10 -#define DMACN0DA_10 DMAC.N0DA_10 -#define DMACN0TB_10 DMAC.N0TB_10 -#define DMACN1SA_10 DMAC.N1SA_10 -#define DMACN1DA_10 DMAC.N1DA_10 -#define DMACN1TB_10 DMAC.N1TB_10 -#define DMACCRSA_10 DMAC.CRSA_10 -#define DMACCRDA_10 DMAC.CRDA_10 -#define DMACCRTB_10 DMAC.CRTB_10 -#define DMACCHSTAT_10 DMAC.CHSTAT_10 -#define DMACCHCTRL_10 DMAC.CHCTRL_10 -#define DMACCHCFG_10 DMAC.CHCFG_10 -#define DMACCHITVL_10 DMAC.CHITVL_10 -#define DMACCHEXT_10 DMAC.CHEXT_10 -#define DMACNXLA_10 DMAC.NXLA_10 -#define DMACCRLA_10 DMAC.CRLA_10 -#define DMACN0SA_11 DMAC.N0SA_11 -#define DMACN0DA_11 DMAC.N0DA_11 -#define DMACN0TB_11 DMAC.N0TB_11 -#define DMACN1SA_11 DMAC.N1SA_11 -#define DMACN1DA_11 DMAC.N1DA_11 -#define DMACN1TB_11 DMAC.N1TB_11 -#define DMACCRSA_11 DMAC.CRSA_11 -#define DMACCRDA_11 DMAC.CRDA_11 -#define DMACCRTB_11 DMAC.CRTB_11 -#define DMACCHSTAT_11 DMAC.CHSTAT_11 -#define DMACCHCTRL_11 DMAC.CHCTRL_11 -#define DMACCHCFG_11 DMAC.CHCFG_11 -#define DMACCHITVL_11 DMAC.CHITVL_11 -#define DMACCHEXT_11 DMAC.CHEXT_11 -#define DMACNXLA_11 DMAC.NXLA_11 -#define DMACCRLA_11 DMAC.CRLA_11 -#define DMACN0SA_12 DMAC.N0SA_12 -#define DMACN0DA_12 DMAC.N0DA_12 -#define DMACN0TB_12 DMAC.N0TB_12 -#define DMACN1SA_12 DMAC.N1SA_12 -#define DMACN1DA_12 DMAC.N1DA_12 -#define DMACN1TB_12 DMAC.N1TB_12 -#define DMACCRSA_12 DMAC.CRSA_12 -#define DMACCRDA_12 DMAC.CRDA_12 -#define DMACCRTB_12 DMAC.CRTB_12 -#define DMACCHSTAT_12 DMAC.CHSTAT_12 -#define DMACCHCTRL_12 DMAC.CHCTRL_12 -#define DMACCHCFG_12 DMAC.CHCFG_12 -#define DMACCHITVL_12 DMAC.CHITVL_12 -#define DMACCHEXT_12 DMAC.CHEXT_12 -#define DMACNXLA_12 DMAC.NXLA_12 -#define DMACCRLA_12 DMAC.CRLA_12 -#define DMACN0SA_13 DMAC.N0SA_13 -#define DMACN0DA_13 DMAC.N0DA_13 -#define DMACN0TB_13 DMAC.N0TB_13 -#define DMACN1SA_13 DMAC.N1SA_13 -#define DMACN1DA_13 DMAC.N1DA_13 -#define DMACN1TB_13 DMAC.N1TB_13 -#define DMACCRSA_13 DMAC.CRSA_13 -#define DMACCRDA_13 DMAC.CRDA_13 -#define DMACCRTB_13 DMAC.CRTB_13 -#define DMACCHSTAT_13 DMAC.CHSTAT_13 -#define DMACCHCTRL_13 DMAC.CHCTRL_13 -#define DMACCHCFG_13 DMAC.CHCFG_13 -#define DMACCHITVL_13 DMAC.CHITVL_13 -#define DMACCHEXT_13 DMAC.CHEXT_13 -#define DMACNXLA_13 DMAC.NXLA_13 -#define DMACCRLA_13 DMAC.CRLA_13 -#define DMACN0SA_14 DMAC.N0SA_14 -#define DMACN0DA_14 DMAC.N0DA_14 -#define DMACN0TB_14 DMAC.N0TB_14 -#define DMACN1SA_14 DMAC.N1SA_14 -#define DMACN1DA_14 DMAC.N1DA_14 -#define DMACN1TB_14 DMAC.N1TB_14 -#define DMACCRSA_14 DMAC.CRSA_14 -#define DMACCRDA_14 DMAC.CRDA_14 -#define DMACCRTB_14 DMAC.CRTB_14 -#define DMACCHSTAT_14 DMAC.CHSTAT_14 -#define DMACCHCTRL_14 DMAC.CHCTRL_14 -#define DMACCHCFG_14 DMAC.CHCFG_14 -#define DMACCHITVL_14 DMAC.CHITVL_14 -#define DMACCHEXT_14 DMAC.CHEXT_14 -#define DMACNXLA_14 DMAC.NXLA_14 -#define DMACCRLA_14 DMAC.CRLA_14 -#define DMACN0SA_15 DMAC.N0SA_15 -#define DMACN0DA_15 DMAC.N0DA_15 -#define DMACN0TB_15 DMAC.N0TB_15 -#define DMACN1SA_15 DMAC.N1SA_15 -#define DMACN1DA_15 DMAC.N1DA_15 -#define DMACN1TB_15 DMAC.N1TB_15 -#define DMACCRSA_15 DMAC.CRSA_15 -#define DMACCRDA_15 DMAC.CRDA_15 -#define DMACCRTB_15 DMAC.CRTB_15 -#define DMACCHSTAT_15 DMAC.CHSTAT_15 -#define DMACCHCTRL_15 DMAC.CHCTRL_15 -#define DMACCHCFG_15 DMAC.CHCFG_15 -#define DMACCHITVL_15 DMAC.CHITVL_15 -#define DMACCHEXT_15 DMAC.CHEXT_15 -#define DMACNXLA_15 DMAC.NXLA_15 -#define DMACCRLA_15 DMAC.CRLA_15 -#define DMACDCTRL_8_15 DMAC.DCTRL_8_15 -#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15 -#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15 -#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15 -#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15 -#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15 -#define DMACDMARS0 DMAC.DMARS0 -#define DMACDMARS1 DMAC.DMARS1 -#define DMACDMARS2 DMAC.DMARS2 -#define DMACDMARS3 DMAC.DMARS3 -#define DMACDMARS4 DMAC.DMARS4 -#define DMACDMARS5 DMAC.DMARS5 -#define DMACDMARS6 DMAC.DMARS6 -#define DMACDMARS7 DMAC.DMARS7 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h index 6c28acb009..54bd656227 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h @@ -18,40 +18,289 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : dvdec_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef DVDEC_IODEFINE_H #define DVDEC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_dvdec -{ /* DVDEC */ +#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ +#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ + + +/* Start of channel array defines of DVDEC */ + +/* Channel array defines of DVDEC */ +/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ +#define DVDEC_COUNT (2) +#define DVDEC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &DVDEC0, &DVDEC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of DVDEC */ + + +#define ADCCR1_1 (DVDEC1.ADCCR1) +#define TGCR1_1 (DVDEC1.TGCR1) +#define TGCR2_1 (DVDEC1.TGCR2) +#define TGCR3_1 (DVDEC1.TGCR3) +#define SYNSCR1_1 (DVDEC1.SYNSCR1) +#define SYNSCR2_1 (DVDEC1.SYNSCR2) +#define SYNSCR3_1 (DVDEC1.SYNSCR3) +#define SYNSCR4_1 (DVDEC1.SYNSCR4) +#define SYNSCR5_1 (DVDEC1.SYNSCR5) +#define HAFCCR1_1 (DVDEC1.HAFCCR1) +#define HAFCCR2_1 (DVDEC1.HAFCCR2) +#define HAFCCR3_1 (DVDEC1.HAFCCR3) +#define VCDWCR1_1 (DVDEC1.VCDWCR1) +#define DCPCR1_1 (DVDEC1.DCPCR1) +#define DCPCR2_1 (DVDEC1.DCPCR2) +#define DCPCR3_1 (DVDEC1.DCPCR3) +#define DCPCR4_1 (DVDEC1.DCPCR4) +#define DCPCR5_1 (DVDEC1.DCPCR5) +#define DCPCR6_1 (DVDEC1.DCPCR6) +#define DCPCR7_1 (DVDEC1.DCPCR7) +#define DCPCR8_1 (DVDEC1.DCPCR8) +#define NSDCR_1 (DVDEC1.NSDCR) +#define BTLCR_1 (DVDEC1.BTLCR) +#define BTGPCR_1 (DVDEC1.BTGPCR) +#define ACCCR1_1 (DVDEC1.ACCCR1) +#define ACCCR2_1 (DVDEC1.ACCCR2) +#define ACCCR3_1 (DVDEC1.ACCCR3) +#define TINTCR_1 (DVDEC1.TINTCR) +#define YCDCR_1 (DVDEC1.YCDCR) +#define AGCCR1_1 (DVDEC1.AGCCR1) +#define AGCCR2_1 (DVDEC1.AGCCR2) +#define PKLIMITCR_1 (DVDEC1.PKLIMITCR) +#define RGORCR1_1 (DVDEC1.RGORCR1) +#define RGORCR2_1 (DVDEC1.RGORCR2) +#define RGORCR3_1 (DVDEC1.RGORCR3) +#define RGORCR4_1 (DVDEC1.RGORCR4) +#define RGORCR5_1 (DVDEC1.RGORCR5) +#define RGORCR6_1 (DVDEC1.RGORCR6) +#define RGORCR7_1 (DVDEC1.RGORCR7) +#define AFCPFCR_1 (DVDEC1.AFCPFCR) +#define RUPDCR_1 (DVDEC1.RUPDCR) +#define VSYNCSR_1 (DVDEC1.VSYNCSR) +#define HSYNCSR_1 (DVDEC1.HSYNCSR) +#define DCPSR1_1 (DVDEC1.DCPSR1) +#define DCPSR2_1 (DVDEC1.DCPSR2) +#define NSDSR_1 (DVDEC1.NSDSR) +#define CROMASR1_1 (DVDEC1.CROMASR1) +#define CROMASR2_1 (DVDEC1.CROMASR2) +#define SYNCSSR_1 (DVDEC1.SYNCSSR) +#define AGCCSR1_1 (DVDEC1.AGCCSR1) +#define AGCCSR2_1 (DVDEC1.AGCCSR2) +#define YCSCR3_1 (DVDEC1.YCSCR3) +#define YCSCR4_1 (DVDEC1.YCSCR4) +#define YCSCR5_1 (DVDEC1.YCSCR5) +#define YCSCR6_1 (DVDEC1.YCSCR6) +#define YCSCR7_1 (DVDEC1.YCSCR7) +#define YCSCR8_1 (DVDEC1.YCSCR8) +#define YCSCR9_1 (DVDEC1.YCSCR9) +#define YCSCR11_1 (DVDEC1.YCSCR11) +#define YCSCR12_1 (DVDEC1.YCSCR12) +#define DCPCR9_1 (DVDEC1.DCPCR9) +#define YCTWA_F0_1 (DVDEC1.YCTWA_F0) +#define YCTWA_F1_1 (DVDEC1.YCTWA_F1) +#define YCTWA_F2_1 (DVDEC1.YCTWA_F2) +#define YCTWA_F3_1 (DVDEC1.YCTWA_F3) +#define YCTWA_F4_1 (DVDEC1.YCTWA_F4) +#define YCTWA_F5_1 (DVDEC1.YCTWA_F5) +#define YCTWA_F6_1 (DVDEC1.YCTWA_F6) +#define YCTWA_F7_1 (DVDEC1.YCTWA_F7) +#define YCTWA_F8_1 (DVDEC1.YCTWA_F8) +#define YCTWB_F0_1 (DVDEC1.YCTWB_F0) +#define YCTWB_F1_1 (DVDEC1.YCTWB_F1) +#define YCTWB_F2_1 (DVDEC1.YCTWB_F2) +#define YCTWB_F3_1 (DVDEC1.YCTWB_F3) +#define YCTWB_F4_1 (DVDEC1.YCTWB_F4) +#define YCTWB_F5_1 (DVDEC1.YCTWB_F5) +#define YCTWB_F6_1 (DVDEC1.YCTWB_F6) +#define YCTWB_F7_1 (DVDEC1.YCTWB_F7) +#define YCTWB_F8_1 (DVDEC1.YCTWB_F8) +#define YCTNA_F0_1 (DVDEC1.YCTNA_F0) +#define YCTNA_F1_1 (DVDEC1.YCTNA_F1) +#define YCTNA_F2_1 (DVDEC1.YCTNA_F2) +#define YCTNA_F3_1 (DVDEC1.YCTNA_F3) +#define YCTNA_F4_1 (DVDEC1.YCTNA_F4) +#define YCTNA_F5_1 (DVDEC1.YCTNA_F5) +#define YCTNA_F6_1 (DVDEC1.YCTNA_F6) +#define YCTNA_F7_1 (DVDEC1.YCTNA_F7) +#define YCTNA_F8_1 (DVDEC1.YCTNA_F8) +#define YCTNB_F0_1 (DVDEC1.YCTNB_F0) +#define YCTNB_F1_1 (DVDEC1.YCTNB_F1) +#define YCTNB_F2_1 (DVDEC1.YCTNB_F2) +#define YCTNB_F3_1 (DVDEC1.YCTNB_F3) +#define YCTNB_F4_1 (DVDEC1.YCTNB_F4) +#define YCTNB_F5_1 (DVDEC1.YCTNB_F5) +#define YCTNB_F6_1 (DVDEC1.YCTNB_F6) +#define YCTNB_F7_1 (DVDEC1.YCTNB_F7) +#define YCTNB_F8_1 (DVDEC1.YCTNB_F8) +#define YGAINCR_1 (DVDEC1.YGAINCR) +#define CBGAINCR_1 (DVDEC1.CBGAINCR) +#define CRGAINCR_1 (DVDEC1.CRGAINCR) +#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE) +#define PGACR_1 (DVDEC1.PGACR) +#define ADCCR2_1 (DVDEC1.ADCCR2) +#define ADCCR1_0 (DVDEC0.ADCCR1) +#define TGCR1_0 (DVDEC0.TGCR1) +#define TGCR2_0 (DVDEC0.TGCR2) +#define TGCR3_0 (DVDEC0.TGCR3) +#define SYNSCR1_0 (DVDEC0.SYNSCR1) +#define SYNSCR2_0 (DVDEC0.SYNSCR2) +#define SYNSCR3_0 (DVDEC0.SYNSCR3) +#define SYNSCR4_0 (DVDEC0.SYNSCR4) +#define SYNSCR5_0 (DVDEC0.SYNSCR5) +#define HAFCCR1_0 (DVDEC0.HAFCCR1) +#define HAFCCR2_0 (DVDEC0.HAFCCR2) +#define HAFCCR3_0 (DVDEC0.HAFCCR3) +#define VCDWCR1_0 (DVDEC0.VCDWCR1) +#define DCPCR1_0 (DVDEC0.DCPCR1) +#define DCPCR2_0 (DVDEC0.DCPCR2) +#define DCPCR3_0 (DVDEC0.DCPCR3) +#define DCPCR4_0 (DVDEC0.DCPCR4) +#define DCPCR5_0 (DVDEC0.DCPCR5) +#define DCPCR6_0 (DVDEC0.DCPCR6) +#define DCPCR7_0 (DVDEC0.DCPCR7) +#define DCPCR8_0 (DVDEC0.DCPCR8) +#define NSDCR_0 (DVDEC0.NSDCR) +#define BTLCR_0 (DVDEC0.BTLCR) +#define BTGPCR_0 (DVDEC0.BTGPCR) +#define ACCCR1_0 (DVDEC0.ACCCR1) +#define ACCCR2_0 (DVDEC0.ACCCR2) +#define ACCCR3_0 (DVDEC0.ACCCR3) +#define TINTCR_0 (DVDEC0.TINTCR) +#define YCDCR_0 (DVDEC0.YCDCR) +#define AGCCR1_0 (DVDEC0.AGCCR1) +#define AGCCR2_0 (DVDEC0.AGCCR2) +#define PKLIMITCR_0 (DVDEC0.PKLIMITCR) +#define RGORCR1_0 (DVDEC0.RGORCR1) +#define RGORCR2_0 (DVDEC0.RGORCR2) +#define RGORCR3_0 (DVDEC0.RGORCR3) +#define RGORCR4_0 (DVDEC0.RGORCR4) +#define RGORCR5_0 (DVDEC0.RGORCR5) +#define RGORCR6_0 (DVDEC0.RGORCR6) +#define RGORCR7_0 (DVDEC0.RGORCR7) +#define AFCPFCR_0 (DVDEC0.AFCPFCR) +#define RUPDCR_0 (DVDEC0.RUPDCR) +#define VSYNCSR_0 (DVDEC0.VSYNCSR) +#define HSYNCSR_0 (DVDEC0.HSYNCSR) +#define DCPSR1_0 (DVDEC0.DCPSR1) +#define DCPSR2_0 (DVDEC0.DCPSR2) +#define NSDSR_0 (DVDEC0.NSDSR) +#define CROMASR1_0 (DVDEC0.CROMASR1) +#define CROMASR2_0 (DVDEC0.CROMASR2) +#define SYNCSSR_0 (DVDEC0.SYNCSSR) +#define AGCCSR1_0 (DVDEC0.AGCCSR1) +#define AGCCSR2_0 (DVDEC0.AGCCSR2) +#define YCSCR3_0 (DVDEC0.YCSCR3) +#define YCSCR4_0 (DVDEC0.YCSCR4) +#define YCSCR5_0 (DVDEC0.YCSCR5) +#define YCSCR6_0 (DVDEC0.YCSCR6) +#define YCSCR7_0 (DVDEC0.YCSCR7) +#define YCSCR8_0 (DVDEC0.YCSCR8) +#define YCSCR9_0 (DVDEC0.YCSCR9) +#define YCSCR11_0 (DVDEC0.YCSCR11) +#define YCSCR12_0 (DVDEC0.YCSCR12) +#define DCPCR9_0 (DVDEC0.DCPCR9) +#define YCTWA_F0_0 (DVDEC0.YCTWA_F0) +#define YCTWA_F1_0 (DVDEC0.YCTWA_F1) +#define YCTWA_F2_0 (DVDEC0.YCTWA_F2) +#define YCTWA_F3_0 (DVDEC0.YCTWA_F3) +#define YCTWA_F4_0 (DVDEC0.YCTWA_F4) +#define YCTWA_F5_0 (DVDEC0.YCTWA_F5) +#define YCTWA_F6_0 (DVDEC0.YCTWA_F6) +#define YCTWA_F7_0 (DVDEC0.YCTWA_F7) +#define YCTWA_F8_0 (DVDEC0.YCTWA_F8) +#define YCTWB_F0_0 (DVDEC0.YCTWB_F0) +#define YCTWB_F1_0 (DVDEC0.YCTWB_F1) +#define YCTWB_F2_0 (DVDEC0.YCTWB_F2) +#define YCTWB_F3_0 (DVDEC0.YCTWB_F3) +#define YCTWB_F4_0 (DVDEC0.YCTWB_F4) +#define YCTWB_F5_0 (DVDEC0.YCTWB_F5) +#define YCTWB_F6_0 (DVDEC0.YCTWB_F6) +#define YCTWB_F7_0 (DVDEC0.YCTWB_F7) +#define YCTWB_F8_0 (DVDEC0.YCTWB_F8) +#define YCTNA_F0_0 (DVDEC0.YCTNA_F0) +#define YCTNA_F1_0 (DVDEC0.YCTNA_F1) +#define YCTNA_F2_0 (DVDEC0.YCTNA_F2) +#define YCTNA_F3_0 (DVDEC0.YCTNA_F3) +#define YCTNA_F4_0 (DVDEC0.YCTNA_F4) +#define YCTNA_F5_0 (DVDEC0.YCTNA_F5) +#define YCTNA_F6_0 (DVDEC0.YCTNA_F6) +#define YCTNA_F7_0 (DVDEC0.YCTNA_F7) +#define YCTNA_F8_0 (DVDEC0.YCTNA_F8) +#define YCTNB_F0_0 (DVDEC0.YCTNB_F0) +#define YCTNB_F1_0 (DVDEC0.YCTNB_F1) +#define YCTNB_F2_0 (DVDEC0.YCTNB_F2) +#define YCTNB_F3_0 (DVDEC0.YCTNB_F3) +#define YCTNB_F4_0 (DVDEC0.YCTNB_F4) +#define YCTNB_F5_0 (DVDEC0.YCTNB_F5) +#define YCTNB_F6_0 (DVDEC0.YCTNB_F6) +#define YCTNB_F7_0 (DVDEC0.YCTNB_F7) +#define YCTNB_F8_0 (DVDEC0.YCTNB_F8) +#define YGAINCR_0 (DVDEC0.YGAINCR) +#define CBGAINCR_0 (DVDEC0.CBGAINCR) +#define CRGAINCR_0 (DVDEC0.CRGAINCR) +#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE) +#define PGACR_0 (DVDEC0.PGACR) +#define ADCCR2_0 (DVDEC0.ADCCR2) + +#define DVDEC_TGCRn_COUNT (3) +#define DVDEC_SYNSCRn_COUNT (5) +#define DVDEC_HAFCCRn_COUNT (3) +#define DVDEC_DCPCRn_COUNT (8) +#define DVDEC_ACCCRn_COUNT (3) +#define DVDEC_AGCCRn_COUNT (2) +#define DVDEC_RGORCRn_COUNT (7) +#define DVDEC_DCPSRn_COUNT (2) +#define DVDEC_CROMASRn_COUNT (2) +#define DVDEC_AGCCSRn_COUNT (2) +#define DVDEC_YCSCRn_COUNT (7) +#define DVDEC_YCTWA_Fn_COUNT (9) +#define DVDEC_YCTWB_Fn_COUNT (9) +#define DVDEC_YCTNA_Fn_COUNT (9) +#define DVDEC_YCTNB_Fn_COUNT (9) + + +typedef struct st_dvdec +{ + /* DVDEC */ volatile uint16_t ADCCR1; /* ADCCR1 */ volatile uint8_t dummy1[4]; /* */ -#define DVDEC_TGCRn_COUNT 3 + +/* #define DVDEC_TGCRn_COUNT (3) */ volatile uint16_t TGCR1; /* TGCR1 */ volatile uint16_t TGCR2; /* TGCR2 */ volatile uint16_t TGCR3; /* TGCR3 */ volatile uint8_t dummy2[6]; /* */ -#define DVDEC_SYNSCRn_COUNT 5 + +/* #define DVDEC_SYNSCRn_COUNT (5) */ volatile uint16_t SYNSCR1; /* SYNSCR1 */ volatile uint16_t SYNSCR2; /* SYNSCR2 */ volatile uint16_t SYNSCR3; /* SYNSCR3 */ volatile uint16_t SYNSCR4; /* SYNSCR4 */ volatile uint16_t SYNSCR5; /* SYNSCR5 */ -#define DVDEC_HAFCCRn_COUNT 3 + +/* #define DVDEC_HAFCCRn_COUNT (3) */ volatile uint16_t HAFCCR1; /* HAFCCR1 */ volatile uint16_t HAFCCR2; /* HAFCCR2 */ volatile uint16_t HAFCCR3; /* HAFCCR3 */ volatile uint16_t VCDWCR1; /* VCDWCR1 */ volatile uint8_t dummy3[4]; /* */ -#define DVDEC_DCPCRn_COUNT 8 + +/* #define DVDEC_DCPCRn_COUNT (8) */ volatile uint16_t DCPCR1; /* DCPCR1 */ volatile uint16_t DCPCR2; /* DCPCR2 */ volatile uint16_t DCPCR3; /* DCPCR3 */ @@ -63,17 +312,20 @@ struct st_dvdec volatile uint16_t NSDCR; /* NSDCR */ volatile uint16_t BTLCR; /* BTLCR */ volatile uint16_t BTGPCR; /* BTGPCR */ -#define DVDEC_ACCCRn_COUNT 3 + +/* #define DVDEC_ACCCRn_COUNT (3) */ volatile uint16_t ACCCR1; /* ACCCR1 */ volatile uint16_t ACCCR2; /* ACCCR2 */ volatile uint16_t ACCCR3; /* ACCCR3 */ volatile uint16_t TINTCR; /* TINTCR */ volatile uint16_t YCDCR; /* YCDCR */ -#define DVDEC_AGCCRn_COUNT 2 + +/* #define DVDEC_AGCCRn_COUNT (2) */ volatile uint16_t AGCCR1; /* AGCCR1 */ volatile uint16_t AGCCR2; /* AGCCR2 */ volatile uint16_t PKLIMITCR; /* PKLIMITCR */ -#define DVDEC_RGORCRn_COUNT 7 + +/* #define DVDEC_RGORCRn_COUNT (7) */ volatile uint16_t RGORCR1; /* RGORCR1 */ volatile uint16_t RGORCR2; /* RGORCR2 */ volatile uint16_t RGORCR3; /* RGORCR3 */ @@ -86,20 +338,24 @@ struct st_dvdec volatile uint16_t RUPDCR; /* RUPDCR */ volatile uint16_t VSYNCSR; /* VSYNCSR */ volatile uint16_t HSYNCSR; /* HSYNCSR */ -#define DVDEC_DCPSRn_COUNT 2 + +/* #define DVDEC_DCPSRn_COUNT (2) */ volatile uint16_t DCPSR1; /* DCPSR1 */ volatile uint16_t DCPSR2; /* DCPSR2 */ volatile uint8_t dummy5[4]; /* */ volatile uint16_t NSDSR; /* NSDSR */ -#define DVDEC_CROMASRn_COUNT 2 + +/* #define DVDEC_CROMASRn_COUNT (2) */ volatile uint16_t CROMASR1; /* CROMASR1 */ volatile uint16_t CROMASR2; /* CROMASR2 */ volatile uint16_t SYNCSSR; /* SYNCSSR */ -#define DVDEC_AGCCSRn_COUNT 2 + +/* #define DVDEC_AGCCSRn_COUNT (2) */ volatile uint16_t AGCCSR1; /* AGCCSR1 */ volatile uint16_t AGCCSR2; /* AGCCSR2 */ volatile uint8_t dummy6[108]; /* */ -#define DVDEC_YCSCRn_COUNT 7 + +/* #define DVDEC_YCSCRn_COUNT (7) */ volatile uint16_t YCSCR3; /* YCSCR3 */ volatile uint16_t YCSCR4; /* YCSCR4 */ volatile uint16_t YCSCR5; /* YCSCR5 */ @@ -113,7 +369,8 @@ struct st_dvdec volatile uint8_t dummy8[104]; /* */ volatile uint16_t DCPCR9; /* DCPCR9 */ volatile uint8_t dummy9[16]; /* */ -#define DVDEC_YCTWA_Fn_COUNT 9 + +/* #define DVDEC_YCTWA_Fn_COUNT (9) */ volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ @@ -123,7 +380,8 @@ struct st_dvdec volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ -#define DVDEC_YCTWB_Fn_COUNT 9 + +/* #define DVDEC_YCTWB_Fn_COUNT (9) */ volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ @@ -133,7 +391,8 @@ struct st_dvdec volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ -#define DVDEC_YCTNA_Fn_COUNT 9 + +/* #define DVDEC_YCTNA_Fn_COUNT (9) */ volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ @@ -143,7 +402,8 @@ struct st_dvdec volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ -#define DVDEC_YCTNB_Fn_COUNT 9 + +/* #define DVDEC_YCTNB_Fn_COUNT (9) */ volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ @@ -161,231 +421,21 @@ struct st_dvdec volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ volatile uint16_t PGACR; /* PGACR */ volatile uint16_t ADCCR2; /* ADCCR2 */ -}; +} r_io_dvdec_t; -#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ -#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ +/* Channel array defines of DVDEC (2)*/ +#ifdef DECLARE_DVDEC_CHANNELS +volatile struct st_dvdec* DVDEC[ DVDEC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + DVDEC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_DVDEC_CHANNELS */ +/* End of channel array defines of DVDEC (2)*/ -/* Start of channnel array defines of DVDEC */ - -/* Channnel array defines of DVDEC */ -/*(Sample) value = DVDEC[ channel ]->ADCCR1; */ -#define DVDEC_COUNT 2 -#define DVDEC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &DVDEC0, &DVDEC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of DVDEC */ - - -#define ADCCR1_1 DVDEC1.ADCCR1 -#define TGCR1_1 DVDEC1.TGCR1 -#define TGCR2_1 DVDEC1.TGCR2 -#define TGCR3_1 DVDEC1.TGCR3 -#define SYNSCR1_1 DVDEC1.SYNSCR1 -#define SYNSCR2_1 DVDEC1.SYNSCR2 -#define SYNSCR3_1 DVDEC1.SYNSCR3 -#define SYNSCR4_1 DVDEC1.SYNSCR4 -#define SYNSCR5_1 DVDEC1.SYNSCR5 -#define HAFCCR1_1 DVDEC1.HAFCCR1 -#define HAFCCR2_1 DVDEC1.HAFCCR2 -#define HAFCCR3_1 DVDEC1.HAFCCR3 -#define VCDWCR1_1 DVDEC1.VCDWCR1 -#define DCPCR1_1 DVDEC1.DCPCR1 -#define DCPCR2_1 DVDEC1.DCPCR2 -#define DCPCR3_1 DVDEC1.DCPCR3 -#define DCPCR4_1 DVDEC1.DCPCR4 -#define DCPCR5_1 DVDEC1.DCPCR5 -#define DCPCR6_1 DVDEC1.DCPCR6 -#define DCPCR7_1 DVDEC1.DCPCR7 -#define DCPCR8_1 DVDEC1.DCPCR8 -#define NSDCR_1 DVDEC1.NSDCR -#define BTLCR_1 DVDEC1.BTLCR -#define BTGPCR_1 DVDEC1.BTGPCR -#define ACCCR1_1 DVDEC1.ACCCR1 -#define ACCCR2_1 DVDEC1.ACCCR2 -#define ACCCR3_1 DVDEC1.ACCCR3 -#define TINTCR_1 DVDEC1.TINTCR -#define YCDCR_1 DVDEC1.YCDCR -#define AGCCR1_1 DVDEC1.AGCCR1 -#define AGCCR2_1 DVDEC1.AGCCR2 -#define PKLIMITCR_1 DVDEC1.PKLIMITCR -#define RGORCR1_1 DVDEC1.RGORCR1 -#define RGORCR2_1 DVDEC1.RGORCR2 -#define RGORCR3_1 DVDEC1.RGORCR3 -#define RGORCR4_1 DVDEC1.RGORCR4 -#define RGORCR5_1 DVDEC1.RGORCR5 -#define RGORCR6_1 DVDEC1.RGORCR6 -#define RGORCR7_1 DVDEC1.RGORCR7 -#define AFCPFCR_1 DVDEC1.AFCPFCR -#define RUPDCR_1 DVDEC1.RUPDCR -#define VSYNCSR_1 DVDEC1.VSYNCSR -#define HSYNCSR_1 DVDEC1.HSYNCSR -#define DCPSR1_1 DVDEC1.DCPSR1 -#define DCPSR2_1 DVDEC1.DCPSR2 -#define NSDSR_1 DVDEC1.NSDSR -#define CROMASR1_1 DVDEC1.CROMASR1 -#define CROMASR2_1 DVDEC1.CROMASR2 -#define SYNCSSR_1 DVDEC1.SYNCSSR -#define AGCCSR1_1 DVDEC1.AGCCSR1 -#define AGCCSR2_1 DVDEC1.AGCCSR2 -#define YCSCR3_1 DVDEC1.YCSCR3 -#define YCSCR4_1 DVDEC1.YCSCR4 -#define YCSCR5_1 DVDEC1.YCSCR5 -#define YCSCR6_1 DVDEC1.YCSCR6 -#define YCSCR7_1 DVDEC1.YCSCR7 -#define YCSCR8_1 DVDEC1.YCSCR8 -#define YCSCR9_1 DVDEC1.YCSCR9 -#define YCSCR11_1 DVDEC1.YCSCR11 -#define YCSCR12_1 DVDEC1.YCSCR12 -#define DCPCR9_1 DVDEC1.DCPCR9 -#define YCTWA_F0_1 DVDEC1.YCTWA_F0 -#define YCTWA_F1_1 DVDEC1.YCTWA_F1 -#define YCTWA_F2_1 DVDEC1.YCTWA_F2 -#define YCTWA_F3_1 DVDEC1.YCTWA_F3 -#define YCTWA_F4_1 DVDEC1.YCTWA_F4 -#define YCTWA_F5_1 DVDEC1.YCTWA_F5 -#define YCTWA_F6_1 DVDEC1.YCTWA_F6 -#define YCTWA_F7_1 DVDEC1.YCTWA_F7 -#define YCTWA_F8_1 DVDEC1.YCTWA_F8 -#define YCTWB_F0_1 DVDEC1.YCTWB_F0 -#define YCTWB_F1_1 DVDEC1.YCTWB_F1 -#define YCTWB_F2_1 DVDEC1.YCTWB_F2 -#define YCTWB_F3_1 DVDEC1.YCTWB_F3 -#define YCTWB_F4_1 DVDEC1.YCTWB_F4 -#define YCTWB_F5_1 DVDEC1.YCTWB_F5 -#define YCTWB_F6_1 DVDEC1.YCTWB_F6 -#define YCTWB_F7_1 DVDEC1.YCTWB_F7 -#define YCTWB_F8_1 DVDEC1.YCTWB_F8 -#define YCTNA_F0_1 DVDEC1.YCTNA_F0 -#define YCTNA_F1_1 DVDEC1.YCTNA_F1 -#define YCTNA_F2_1 DVDEC1.YCTNA_F2 -#define YCTNA_F3_1 DVDEC1.YCTNA_F3 -#define YCTNA_F4_1 DVDEC1.YCTNA_F4 -#define YCTNA_F5_1 DVDEC1.YCTNA_F5 -#define YCTNA_F6_1 DVDEC1.YCTNA_F6 -#define YCTNA_F7_1 DVDEC1.YCTNA_F7 -#define YCTNA_F8_1 DVDEC1.YCTNA_F8 -#define YCTNB_F0_1 DVDEC1.YCTNB_F0 -#define YCTNB_F1_1 DVDEC1.YCTNB_F1 -#define YCTNB_F2_1 DVDEC1.YCTNB_F2 -#define YCTNB_F3_1 DVDEC1.YCTNB_F3 -#define YCTNB_F4_1 DVDEC1.YCTNB_F4 -#define YCTNB_F5_1 DVDEC1.YCTNB_F5 -#define YCTNB_F6_1 DVDEC1.YCTNB_F6 -#define YCTNB_F7_1 DVDEC1.YCTNB_F7 -#define YCTNB_F8_1 DVDEC1.YCTNB_F8 -#define YGAINCR_1 DVDEC1.YGAINCR -#define CBGAINCR_1 DVDEC1.CBGAINCR -#define CRGAINCR_1 DVDEC1.CRGAINCR -#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE -#define PGACR_1 DVDEC1.PGACR -#define ADCCR2_1 DVDEC1.ADCCR2 -#define ADCCR1_0 DVDEC0.ADCCR1 -#define TGCR1_0 DVDEC0.TGCR1 -#define TGCR2_0 DVDEC0.TGCR2 -#define TGCR3_0 DVDEC0.TGCR3 -#define SYNSCR1_0 DVDEC0.SYNSCR1 -#define SYNSCR2_0 DVDEC0.SYNSCR2 -#define SYNSCR3_0 DVDEC0.SYNSCR3 -#define SYNSCR4_0 DVDEC0.SYNSCR4 -#define SYNSCR5_0 DVDEC0.SYNSCR5 -#define HAFCCR1_0 DVDEC0.HAFCCR1 -#define HAFCCR2_0 DVDEC0.HAFCCR2 -#define HAFCCR3_0 DVDEC0.HAFCCR3 -#define VCDWCR1_0 DVDEC0.VCDWCR1 -#define DCPCR1_0 DVDEC0.DCPCR1 -#define DCPCR2_0 DVDEC0.DCPCR2 -#define DCPCR3_0 DVDEC0.DCPCR3 -#define DCPCR4_0 DVDEC0.DCPCR4 -#define DCPCR5_0 DVDEC0.DCPCR5 -#define DCPCR6_0 DVDEC0.DCPCR6 -#define DCPCR7_0 DVDEC0.DCPCR7 -#define DCPCR8_0 DVDEC0.DCPCR8 -#define NSDCR_0 DVDEC0.NSDCR -#define BTLCR_0 DVDEC0.BTLCR -#define BTGPCR_0 DVDEC0.BTGPCR -#define ACCCR1_0 DVDEC0.ACCCR1 -#define ACCCR2_0 DVDEC0.ACCCR2 -#define ACCCR3_0 DVDEC0.ACCCR3 -#define TINTCR_0 DVDEC0.TINTCR -#define YCDCR_0 DVDEC0.YCDCR -#define AGCCR1_0 DVDEC0.AGCCR1 -#define AGCCR2_0 DVDEC0.AGCCR2 -#define PKLIMITCR_0 DVDEC0.PKLIMITCR -#define RGORCR1_0 DVDEC0.RGORCR1 -#define RGORCR2_0 DVDEC0.RGORCR2 -#define RGORCR3_0 DVDEC0.RGORCR3 -#define RGORCR4_0 DVDEC0.RGORCR4 -#define RGORCR5_0 DVDEC0.RGORCR5 -#define RGORCR6_0 DVDEC0.RGORCR6 -#define RGORCR7_0 DVDEC0.RGORCR7 -#define AFCPFCR_0 DVDEC0.AFCPFCR -#define RUPDCR_0 DVDEC0.RUPDCR -#define VSYNCSR_0 DVDEC0.VSYNCSR -#define HSYNCSR_0 DVDEC0.HSYNCSR -#define DCPSR1_0 DVDEC0.DCPSR1 -#define DCPSR2_0 DVDEC0.DCPSR2 -#define NSDSR_0 DVDEC0.NSDSR -#define CROMASR1_0 DVDEC0.CROMASR1 -#define CROMASR2_0 DVDEC0.CROMASR2 -#define SYNCSSR_0 DVDEC0.SYNCSSR -#define AGCCSR1_0 DVDEC0.AGCCSR1 -#define AGCCSR2_0 DVDEC0.AGCCSR2 -#define YCSCR3_0 DVDEC0.YCSCR3 -#define YCSCR4_0 DVDEC0.YCSCR4 -#define YCSCR5_0 DVDEC0.YCSCR5 -#define YCSCR6_0 DVDEC0.YCSCR6 -#define YCSCR7_0 DVDEC0.YCSCR7 -#define YCSCR8_0 DVDEC0.YCSCR8 -#define YCSCR9_0 DVDEC0.YCSCR9 -#define YCSCR11_0 DVDEC0.YCSCR11 -#define YCSCR12_0 DVDEC0.YCSCR12 -#define DCPCR9_0 DVDEC0.DCPCR9 -#define YCTWA_F0_0 DVDEC0.YCTWA_F0 -#define YCTWA_F1_0 DVDEC0.YCTWA_F1 -#define YCTWA_F2_0 DVDEC0.YCTWA_F2 -#define YCTWA_F3_0 DVDEC0.YCTWA_F3 -#define YCTWA_F4_0 DVDEC0.YCTWA_F4 -#define YCTWA_F5_0 DVDEC0.YCTWA_F5 -#define YCTWA_F6_0 DVDEC0.YCTWA_F6 -#define YCTWA_F7_0 DVDEC0.YCTWA_F7 -#define YCTWA_F8_0 DVDEC0.YCTWA_F8 -#define YCTWB_F0_0 DVDEC0.YCTWB_F0 -#define YCTWB_F1_0 DVDEC0.YCTWB_F1 -#define YCTWB_F2_0 DVDEC0.YCTWB_F2 -#define YCTWB_F3_0 DVDEC0.YCTWB_F3 -#define YCTWB_F4_0 DVDEC0.YCTWB_F4 -#define YCTWB_F5_0 DVDEC0.YCTWB_F5 -#define YCTWB_F6_0 DVDEC0.YCTWB_F6 -#define YCTWB_F7_0 DVDEC0.YCTWB_F7 -#define YCTWB_F8_0 DVDEC0.YCTWB_F8 -#define YCTNA_F0_0 DVDEC0.YCTNA_F0 -#define YCTNA_F1_0 DVDEC0.YCTNA_F1 -#define YCTNA_F2_0 DVDEC0.YCTNA_F2 -#define YCTNA_F3_0 DVDEC0.YCTNA_F3 -#define YCTNA_F4_0 DVDEC0.YCTNA_F4 -#define YCTNA_F5_0 DVDEC0.YCTNA_F5 -#define YCTNA_F6_0 DVDEC0.YCTNA_F6 -#define YCTNA_F7_0 DVDEC0.YCTNA_F7 -#define YCTNA_F8_0 DVDEC0.YCTNA_F8 -#define YCTNB_F0_0 DVDEC0.YCTNB_F0 -#define YCTNB_F1_0 DVDEC0.YCTNB_F1 -#define YCTNB_F2_0 DVDEC0.YCTNB_F2 -#define YCTNB_F3_0 DVDEC0.YCTNB_F3 -#define YCTNB_F4_0 DVDEC0.YCTNB_F4 -#define YCTNB_F5_0 DVDEC0.YCTNB_F5 -#define YCTNB_F6_0 DVDEC0.YCTNB_F6 -#define YCTNB_F7_0 DVDEC0.YCTNB_F7 -#define YCTNB_F8_0 DVDEC0.YCTNB_F8 -#define YGAINCR_0 DVDEC0.YGAINCR -#define CBGAINCR_0 DVDEC0.CBGAINCR -#define CRGAINCR_0 DVDEC0.CRGAINCR -#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE -#define PGACR_0 DVDEC0.PGACR -#define ADCCR2_0 DVDEC0.ADCCR2 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h index 88b268ec7d..fef3000ff9 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h @@ -18,21 +18,192 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ether_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ETHER_IODEFINE_H #define ETHER_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ether -{ /* ETHER */ +#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ + + +/* Start of channel array defines of ETHER */ + +/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ +/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ +#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32) +#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ + ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ + ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ + ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ +#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ +#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ +#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ +#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ +#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ +#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ +#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ +#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ +#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ +#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ +#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ +#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ +#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ +#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ +#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ +#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ +#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ +#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ +#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ +#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ +#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ +#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ +#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ +#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ +#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ +#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ +#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ +#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ +#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ +#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ +#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ + +/* End of channel array defines of ETHER */ + + +#define ETHEREDSR0 (ETHER.EDSR0) +#define ETHERTDLAR0 (ETHER.TDLAR0) +#define ETHERTDFAR0 (ETHER.TDFAR0) +#define ETHERTDFXR0 (ETHER.TDFXR0) +#define ETHERTDFFR0 (ETHER.TDFFR0) +#define ETHERRDLAR0 (ETHER.RDLAR0) +#define ETHERRDFAR0 (ETHER.RDFAR0) +#define ETHERRDFXR0 (ETHER.RDFXR0) +#define ETHERRDFFR0 (ETHER.RDFFR0) +#define ETHEREDMR0 (ETHER.EDMR0) +#define ETHEREDTRR0 (ETHER.EDTRR0) +#define ETHEREDRRR0 (ETHER.EDRRR0) +#define ETHEREESR0 (ETHER.EESR0) +#define ETHEREESIPR0 (ETHER.EESIPR0) +#define ETHERTRSCER0 (ETHER.TRSCER0) +#define ETHERRMFCR0 (ETHER.RMFCR0) +#define ETHERTFTR0 (ETHER.TFTR0) +#define ETHERFDR0 (ETHER.FDR0) +#define ETHERRMCR0 (ETHER.RMCR0) +#define ETHERRPADIR0 (ETHER.RPADIR0) +#define ETHERFCFTR0 (ETHER.FCFTR0) +#define ETHERCSMR (ETHER.CSMR) +#define ETHERCSSBM (ETHER.CSSBM) +#define ETHERCSSMR (ETHER.CSSMR) +#define ETHERECMR0 (ETHER.ECMR0) +#define ETHERRFLR0 (ETHER.RFLR0) +#define ETHERECSR0 (ETHER.ECSR0) +#define ETHERECSIPR0 (ETHER.ECSIPR0) +#define ETHERPIR0 (ETHER.PIR0) +#define ETHERAPR0 (ETHER.APR0) +#define ETHERMPR0 (ETHER.MPR0) +#define ETHERPFTCR0 (ETHER.PFTCR0) +#define ETHERPFRCR0 (ETHER.PFRCR0) +#define ETHERTPAUSER0 (ETHER.TPAUSER0) +#define ETHERMAHR0 (ETHER.MAHR0) +#define ETHERMALR0 (ETHER.MALR0) +#define ETHERCEFCR0 (ETHER.CEFCR0) +#define ETHERFRECR0 (ETHER.FRECR0) +#define ETHERTSFRCR0 (ETHER.TSFRCR0) +#define ETHERTLFRCR0 (ETHER.TLFRCR0) +#define ETHERRFCR0 (ETHER.RFCR0) +#define ETHERMAFCR0 (ETHER.MAFCR0) +#define ETHERARSTR (ETHER.ARSTR) +#define ETHERTSU_CTRST (ETHER.TSU_CTRST) +#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0) +#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY) +#define ETHERTSU_TEN (ETHER.TSU_TEN) +#define ETHERTXNLCR0 (ETHER.TXNLCR0) +#define ETHERTXALCR0 (ETHER.TXALCR0) +#define ETHERRXNLCR0 (ETHER.RXNLCR0) +#define ETHERRXALCR0 (ETHER.RXALCR0) +#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0) +#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0) +#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1) +#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1) +#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2) +#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2) +#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3) +#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3) +#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4) +#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4) +#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5) +#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5) +#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6) +#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6) +#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7) +#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7) +#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8) +#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8) +#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9) +#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9) +#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10) +#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10) +#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11) +#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11) +#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12) +#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12) +#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13) +#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13) +#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14) +#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14) +#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15) +#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15) +#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16) +#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16) +#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17) +#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17) +#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18) +#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18) +#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19) +#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19) +#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20) +#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20) +#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21) +#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21) +#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22) +#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22) +#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23) +#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23) +#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24) +#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24) +#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25) +#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25) +#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26) +#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26) +#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27) +#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27) +#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28) +#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28) +#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29) +#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29) +#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30) +#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30) +#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31) +#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31) + + +typedef struct st_ether +{ + /* ETHER */ volatile uint32_t EDSR0; /* EDSR0 */ volatile uint8_t dummy207[12]; /* */ volatile uint32_t TDLAR0; /* TDLAR0 */ @@ -118,310 +289,221 @@ struct st_ether volatile uint32_t RXNLCR0; /* RXNLCR0 */ volatile uint32_t RXALCR0; /* RXALCR0 */ volatile uint8_t dummy240[112]; /* */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */ volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */ volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */ volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */ volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */ volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */ volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */ volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */ volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */ volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */ volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */ volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */ volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */ volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */ volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */ volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */ volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */ volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */ volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */ volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */ volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */ volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */ volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */ volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */ volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */ volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */ volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */ volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */ volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */ volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */ volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */ + /* end of struct st_ether_from_tsu_adrh0 */ + /* start of struct st_ether_from_tsu_adrh0 */ volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */ volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */ + /* end of struct st_ether_from_tsu_adrh0 */ -}; +} r_io_ether_t; -struct st_ether_from_tsu_adrh0 +typedef struct st_ether_from_tsu_adrh0 { + volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */ volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */ -}; +} r_io_ether_from_tsu_adrh0_t; -#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */ +/* Channel array defines of ETHER (2)*/ +#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS +volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */ +/* End of channel array defines of ETHER (2)*/ -/* Start of channnel array defines of ETHER */ - -/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */ -/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */ -#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT 32 -#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - ÐER_FROM_TSU_ADRH0, ÐER_FROM_TSU_ADRH1, ÐER_FROM_TSU_ADRH2, ÐER_FROM_TSU_ADRH3, ÐER_FROM_TSU_ADRH4, ÐER_FROM_TSU_ADRH5, ÐER_FROM_TSU_ADRH6, ÐER_FROM_TSU_ADRH7, \ - ÐER_FROM_TSU_ADRH8, ÐER_FROM_TSU_ADRH9, ÐER_FROM_TSU_ADRH10, ÐER_FROM_TSU_ADRH11, ÐER_FROM_TSU_ADRH12, ÐER_FROM_TSU_ADRH13, ÐER_FROM_TSU_ADRH14, ÐER_FROM_TSU_ADRH15, \ - ÐER_FROM_TSU_ADRH16, ÐER_FROM_TSU_ADRH17, ÐER_FROM_TSU_ADRH18, ÐER_FROM_TSU_ADRH19, ÐER_FROM_TSU_ADRH20, ÐER_FROM_TSU_ADRH21, ÐER_FROM_TSU_ADRH22, ÐER_FROM_TSU_ADRH23, \ - ÐER_FROM_TSU_ADRH24, ÐER_FROM_TSU_ADRH25, ÐER_FROM_TSU_ADRH26, ÐER_FROM_TSU_ADRH27, ÐER_FROM_TSU_ADRH28, ÐER_FROM_TSU_ADRH29, ÐER_FROM_TSU_ADRH30, ÐER_FROM_TSU_ADRH31 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */ -#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */ -#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */ -#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */ -#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */ -#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */ -#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */ -#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */ -#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */ -#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */ -#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */ -#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */ -#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */ -#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */ -#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */ -#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */ -#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */ -#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */ -#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */ -#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */ -#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */ -#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */ -#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */ -#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */ -#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */ -#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */ -#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */ -#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */ -#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */ -#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */ -#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */ -#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)ÐER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */ - -/* End of channnel array defines of ETHER */ - - -#define ETHEREDSR0 ETHER.EDSR0 -#define ETHERTDLAR0 ETHER.TDLAR0 -#define ETHERTDFAR0 ETHER.TDFAR0 -#define ETHERTDFXR0 ETHER.TDFXR0 -#define ETHERTDFFR0 ETHER.TDFFR0 -#define ETHERRDLAR0 ETHER.RDLAR0 -#define ETHERRDFAR0 ETHER.RDFAR0 -#define ETHERRDFXR0 ETHER.RDFXR0 -#define ETHERRDFFR0 ETHER.RDFFR0 -#define ETHEREDMR0 ETHER.EDMR0 -#define ETHEREDTRR0 ETHER.EDTRR0 -#define ETHEREDRRR0 ETHER.EDRRR0 -#define ETHEREESR0 ETHER.EESR0 -#define ETHEREESIPR0 ETHER.EESIPR0 -#define ETHERTRSCER0 ETHER.TRSCER0 -#define ETHERRMFCR0 ETHER.RMFCR0 -#define ETHERTFTR0 ETHER.TFTR0 -#define ETHERFDR0 ETHER.FDR0 -#define ETHERRMCR0 ETHER.RMCR0 -#define ETHERRPADIR0 ETHER.RPADIR0 -#define ETHERFCFTR0 ETHER.FCFTR0 -#define ETHERCSMR ETHER.CSMR -#define ETHERCSSBM ETHER.CSSBM -#define ETHERCSSMR ETHER.CSSMR -#define ETHERECMR0 ETHER.ECMR0 -#define ETHERRFLR0 ETHER.RFLR0 -#define ETHERECSR0 ETHER.ECSR0 -#define ETHERECSIPR0 ETHER.ECSIPR0 -#define ETHERPIR0 ETHER.PIR0 -#define ETHERAPR0 ETHER.APR0 -#define ETHERMPR0 ETHER.MPR0 -#define ETHERPFTCR0 ETHER.PFTCR0 -#define ETHERPFRCR0 ETHER.PFRCR0 -#define ETHERTPAUSER0 ETHER.TPAUSER0 -#define ETHERMAHR0 ETHER.MAHR0 -#define ETHERMALR0 ETHER.MALR0 -#define ETHERCEFCR0 ETHER.CEFCR0 -#define ETHERFRECR0 ETHER.FRECR0 -#define ETHERTSFRCR0 ETHER.TSFRCR0 -#define ETHERTLFRCR0 ETHER.TLFRCR0 -#define ETHERRFCR0 ETHER.RFCR0 -#define ETHERMAFCR0 ETHER.MAFCR0 -#define ETHERARSTR ETHER.ARSTR -#define ETHERTSU_CTRST ETHER.TSU_CTRST -#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0 -#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY -#define ETHERTSU_TEN ETHER.TSU_TEN -#define ETHERTXNLCR0 ETHER.TXNLCR0 -#define ETHERTXALCR0 ETHER.TXALCR0 -#define ETHERRXNLCR0 ETHER.RXNLCR0 -#define ETHERRXALCR0 ETHER.RXALCR0 -#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0 -#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0 -#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1 -#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1 -#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2 -#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2 -#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3 -#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3 -#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4 -#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4 -#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5 -#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5 -#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6 -#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6 -#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7 -#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7 -#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8 -#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8 -#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9 -#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9 -#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10 -#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10 -#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11 -#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11 -#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12 -#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12 -#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13 -#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13 -#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14 -#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14 -#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15 -#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15 -#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16 -#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16 -#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17 -#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17 -#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18 -#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18 -#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19 -#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19 -#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20 -#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20 -#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21 -#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21 -#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22 -#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22 -#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23 -#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23 -#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24 -#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24 -#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25 -#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25 -#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26 -#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26 -#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27 -#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27 -#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28 -#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28 -#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29 -#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29 -#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30 -#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30 -#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31 -#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h index 3f8ec183c2..0e88e0cad2 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h @@ -18,20 +18,41 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : flctl_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef FLCTL_IODEFINE_H #define FLCTL_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_flctl -{ /* FLCTL */ +#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ + + +#define FLCTLFLCMNCR (FLCTL.FLCMNCR) +#define FLCTLFLCMDCR (FLCTL.FLCMDCR) +#define FLCTLFLCMCDR (FLCTL.FLCMCDR) +#define FLCTLFLADR (FLCTL.FLADR) +#define FLCTLFLDATAR (FLCTL.FLDATAR) +#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR) +#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR) +#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR) +#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT) +#define FLCTLFLTRCR (FLCTL.FLTRCR) +#define FLCTLFLADR2 (FLCTL.FLADR2) +#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO) + + +typedef struct st_flctl +{ + /* FLCTL */ volatile uint32_t FLCMNCR; /* FLCMNCR */ volatile uint32_t FLCMDCR; /* FLCMDCR */ volatile uint32_t FLCMCDR; /* FLCMCDR */ @@ -47,26 +68,11 @@ struct st_flctl volatile uint32_t FLADR2; /* FLADR2 */ volatile uint8_t dummy557[16]; /* */ volatile uint32_t FLDTFIFO; /* FLDTFIFO */ - volatile uint8_t dummy558[12]; /* */ - volatile uint32_t FLECFIFO; /* FLECFIFO */ -}; +} r_io_flctl_t; -#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */ - - -#define FLCTLFLCMNCR FLCTL.FLCMNCR -#define FLCTLFLCMDCR FLCTL.FLCMDCR -#define FLCTLFLCMCDR FLCTL.FLCMCDR -#define FLCTLFLADR FLCTL.FLADR -#define FLCTLFLDATAR FLCTL.FLDATAR -#define FLCTLFLDTCNTR FLCTL.FLDTCNTR -#define FLCTLFLINTDMACR FLCTL.FLINTDMACR -#define FLCTLFLBSYTMR FLCTL.FLBSYTMR -#define FLCTLFLBSYCNT FLCTL.FLBSYCNT -#define FLCTLFLTRCR FLCTL.FLTRCR -#define FLCTLFLADR2 FLCTL.FLADR2 -#define FLCTLFLDTFIFO FLCTL.FLDTFIFO -#define FLCTLFLECFIFO FLCTL.FLECFIFO /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h index 8bedb518ff..05c30ecdf5 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h @@ -18,662 +18,29 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : gpio_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef GPIO_IODEFINE_H #define GPIO_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_gpio -{ /* GPIO */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P1; /* P1 */ - volatile uint8_t dummy348[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P2; /* P2 */ - volatile uint8_t dummy349[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P3; /* P3 */ - volatile uint8_t dummy350[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P4; /* P4 */ - volatile uint8_t dummy351[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P5; /* P5 */ - volatile uint8_t dummy352[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P6; /* P6 */ - volatile uint8_t dummy353[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P7; /* P7 */ - volatile uint8_t dummy354[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P8; /* P8 */ - volatile uint8_t dummy355[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P9; /* P9 */ - volatile uint8_t dummy356[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P10; /* P10 */ - volatile uint8_t dummy357[2]; /* */ -/* end of struct st_gpio_from_p1 */ -/* start of struct st_gpio_from_p1 */ - volatile uint16_t P11; /* P11 */ - volatile uint8_t dummy3580[2]; /* */ -/* end of struct st_gpio_from_p1 */ - volatile uint8_t dummy3581[212]; /* */ -#define GPIO_PSRn_COUNT 11 - volatile uint32_t PSR1; /* PSR1 */ - volatile uint32_t PSR2; /* PSR2 */ - volatile uint32_t PSR3; /* PSR3 */ - volatile uint32_t PSR4; /* PSR4 */ - volatile uint32_t PSR5; /* PSR5 */ - volatile uint32_t PSR6; /* PSR6 */ - volatile uint32_t PSR7; /* PSR7 */ - volatile uint32_t PSR8; /* PSR8 */ - volatile uint32_t PSR9; /* PSR9 */ - volatile uint32_t PSR10; /* PSR10 */ - volatile uint32_t PSR11; /* PSR11 */ - volatile uint8_t dummy359[208]; /* */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR0; /* PPR0 */ - volatile uint8_t dummy360[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR1; /* PPR1 */ - volatile uint8_t dummy361[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR2; /* PPR2 */ - volatile uint8_t dummy362[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR3; /* PPR3 */ - volatile uint8_t dummy363[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR4; /* PPR4 */ - volatile uint8_t dummy364[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR5; /* PPR5 */ - volatile uint8_t dummy365[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR6; /* PPR6 */ - volatile uint8_t dummy366[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR7; /* PPR7 */ - volatile uint8_t dummy367[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR8; /* PPR8 */ - volatile uint8_t dummy368[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR9; /* PPR9 */ - volatile uint8_t dummy369[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR10; /* PPR10 */ - volatile uint8_t dummy370[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ -/* start of struct st_gpio_from_ppr0 */ - volatile uint16_t PPR11; /* PPR11 */ - volatile uint8_t dummy3710[2]; /* */ -/* end of struct st_gpio_from_ppr0 */ - volatile uint8_t dummy3711[212]; /* */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM1; /* PM1 */ - volatile uint8_t dummy372[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM2; /* PM2 */ - volatile uint8_t dummy373[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM3; /* PM3 */ - volatile uint8_t dummy374[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM4; /* PM4 */ - volatile uint8_t dummy375[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM5; /* PM5 */ - volatile uint8_t dummy376[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM6; /* PM6 */ - volatile uint8_t dummy377[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM7; /* PM7 */ - volatile uint8_t dummy378[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM8; /* PM8 */ - volatile uint8_t dummy379[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM9; /* PM9 */ - volatile uint8_t dummy380[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM10; /* PM10 */ - volatile uint8_t dummy381[2]; /* */ -/* end of struct st_gpio_from_pm1 */ -/* start of struct st_gpio_from_pm1 */ - volatile uint16_t PM11; /* PM11 */ - volatile uint8_t dummy3820[2]; /* */ -/* end of struct st_gpio_from_pm1 */ - volatile uint8_t dummy3821[208]; /* */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC0; /* PMC0 */ - volatile uint8_t dummy383[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC1; /* PMC1 */ - volatile uint8_t dummy384[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC2; /* PMC2 */ - volatile uint8_t dummy385[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC3; /* PMC3 */ - volatile uint8_t dummy386[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC4; /* PMC4 */ - volatile uint8_t dummy387[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC5; /* PMC5 */ - volatile uint8_t dummy388[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC6; /* PMC6 */ - volatile uint8_t dummy389[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC7; /* PMC7 */ - volatile uint8_t dummy390[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC8; /* PMC8 */ - volatile uint8_t dummy391[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC9; /* PMC9 */ - volatile uint8_t dummy392[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC10; /* PMC10 */ - volatile uint8_t dummy393[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ -/* start of struct st_gpio_from_pmc0 */ - volatile uint16_t PMC11; /* PMC11 */ - volatile uint8_t dummy3940[2]; /* */ -/* end of struct st_gpio_from_pmc0 */ - volatile uint8_t dummy3941[212]; /* */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC1; /* PFC1 */ - volatile uint8_t dummy395[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC2; /* PFC2 */ - volatile uint8_t dummy396[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC3; /* PFC3 */ - volatile uint8_t dummy397[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC4; /* PFC4 */ - volatile uint8_t dummy398[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC5; /* PFC5 */ - volatile uint8_t dummy399[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC6; /* PFC6 */ - volatile uint8_t dummy400[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC7; /* PFC7 */ - volatile uint8_t dummy401[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC8; /* PFC8 */ - volatile uint8_t dummy402[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC9; /* PFC9 */ - volatile uint8_t dummy403[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC10; /* PFC10 */ - volatile uint8_t dummy404[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ -/* start of struct st_gpio_from_pfc1 */ - volatile uint16_t PFC11; /* PFC11 */ - volatile uint8_t dummy4050[2]; /* */ -/* end of struct st_gpio_from_pfc1 */ - volatile uint8_t dummy4051[212]; /* */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE1; /* PFCE1 */ - volatile uint8_t dummy406[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE2; /* PFCE2 */ - volatile uint8_t dummy407[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE3; /* PFCE3 */ - volatile uint8_t dummy408[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE4; /* PFCE4 */ - volatile uint8_t dummy409[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE5; /* PFCE5 */ - volatile uint8_t dummy410[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE6; /* PFCE6 */ - volatile uint8_t dummy411[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE7; /* PFCE7 */ - volatile uint8_t dummy412[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE8; /* PFCE8 */ - volatile uint8_t dummy413[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE9; /* PFCE9 */ - volatile uint8_t dummy414[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE10; /* PFCE10 */ - volatile uint8_t dummy415[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ -/* start of struct st_gpio_from_pfce1 */ - volatile uint16_t PFCE11; /* PFCE11 */ - volatile uint8_t dummy4160[2]; /* */ -/* end of struct st_gpio_from_pfce1 */ - volatile uint8_t dummy4161[212]; /* */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT1; /* PNOT1 */ - volatile uint8_t dummy417[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT2; /* PNOT2 */ - volatile uint8_t dummy418[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT3; /* PNOT3 */ - volatile uint8_t dummy419[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT4; /* PNOT4 */ - volatile uint8_t dummy420[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT5; /* PNOT5 */ - volatile uint8_t dummy421[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT6; /* PNOT6 */ - volatile uint8_t dummy422[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT7; /* PNOT7 */ - volatile uint8_t dummy423[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT8; /* PNOT8 */ - volatile uint8_t dummy424[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT9; /* PNOT9 */ - volatile uint8_t dummy425[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT10; /* PNOT10 */ - volatile uint8_t dummy426[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ -/* start of struct st_gpio_from_pnot1 */ - volatile uint16_t PNOT11; /* PNOT11 */ - volatile uint8_t dummy4270[2]; /* */ -/* end of struct st_gpio_from_pnot1 */ - volatile uint8_t dummy4271[212]; /* */ -#define GPIO_PMSRn_COUNT 11 - volatile uint32_t PMSR1; /* PMSR1 */ - volatile uint32_t PMSR2; /* PMSR2 */ - volatile uint32_t PMSR3; /* PMSR3 */ - volatile uint32_t PMSR4; /* PMSR4 */ - volatile uint32_t PMSR5; /* PMSR5 */ - volatile uint32_t PMSR6; /* PMSR6 */ - volatile uint32_t PMSR7; /* PMSR7 */ - volatile uint32_t PMSR8; /* PMSR8 */ - volatile uint32_t PMSR9; /* PMSR9 */ - volatile uint32_t PMSR10; /* PMSR10 */ - volatile uint32_t PMSR11; /* PMSR11 */ - volatile uint8_t dummy428[208]; /* */ -#define GPIO_PMCSRn_COUNT 12 - volatile uint32_t PMCSR0; /* PMCSR0 */ - volatile uint32_t PMCSR1; /* PMCSR1 */ - volatile uint32_t PMCSR2; /* PMCSR2 */ - volatile uint32_t PMCSR3; /* PMCSR3 */ - volatile uint32_t PMCSR4; /* PMCSR4 */ - volatile uint32_t PMCSR5; /* PMCSR5 */ - volatile uint32_t PMCSR6; /* PMCSR6 */ - volatile uint32_t PMCSR7; /* PMCSR7 */ - volatile uint32_t PMCSR8; /* PMCSR8 */ - volatile uint32_t PMCSR9; /* PMCSR9 */ - volatile uint32_t PMCSR10; /* PMCSR10 */ - volatile uint32_t PMCSR11; /* PMCSR11 */ - volatile uint8_t dummy429[212]; /* */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE1; /* PFCAE1 */ - volatile uint8_t dummy430[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE2; /* PFCAE2 */ - volatile uint8_t dummy431[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE3; /* PFCAE3 */ - volatile uint8_t dummy432[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE4; /* PFCAE4 */ - volatile uint8_t dummy433[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE5; /* PFCAE5 */ - volatile uint8_t dummy434[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE6; /* PFCAE6 */ - volatile uint8_t dummy435[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE7; /* PFCAE7 */ - volatile uint8_t dummy436[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE8; /* PFCAE8 */ - volatile uint8_t dummy437[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE9; /* PFCAE9 */ - volatile uint8_t dummy438[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE10; /* PFCAE10 */ - volatile uint8_t dummy439[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ -/* start of struct st_gpio_from_pfcae1 */ - volatile uint16_t PFCAE11; /* PFCAE11 */ - volatile uint8_t dummy4400[2]; /* */ -/* end of struct st_gpio_from_pfcae1 */ - volatile uint8_t dummy4401[464]; /* */ - volatile uint32_t SNCR; /* SNCR */ - volatile uint8_t dummy441[13308]; /* */ - volatile uint16_t PIBC0; /* PIBC0 */ - volatile uint8_t dummy442[2]; /* */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC1; /* PIBC1 */ - volatile uint8_t dummy443[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC2; /* PIBC2 */ - volatile uint8_t dummy444[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC3; /* PIBC3 */ - volatile uint8_t dummy445[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC4; /* PIBC4 */ - volatile uint8_t dummy446[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC5; /* PIBC5 */ - volatile uint8_t dummy447[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC6; /* PIBC6 */ - volatile uint8_t dummy448[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC7; /* PIBC7 */ - volatile uint8_t dummy449[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC8; /* PIBC8 */ - volatile uint8_t dummy450[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC9; /* PIBC9 */ - volatile uint8_t dummy451[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC10; /* PIBC10 */ - volatile uint8_t dummy452[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ -/* start of struct st_gpio_from_pibc1 */ - volatile uint16_t PIBC11; /* PIBC11 */ - volatile uint8_t dummy4530[2]; /* */ -/* end of struct st_gpio_from_pibc1 */ - volatile uint8_t dummy4531[212]; /* */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC1; /* PBDC1 */ - volatile uint8_t dummy454[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC2; /* PBDC2 */ - volatile uint8_t dummy455[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC3; /* PBDC3 */ - volatile uint8_t dummy456[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC4; /* PBDC4 */ - volatile uint8_t dummy457[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC5; /* PBDC5 */ - volatile uint8_t dummy458[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC6; /* PBDC6 */ - volatile uint8_t dummy459[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC7; /* PBDC7 */ - volatile uint8_t dummy460[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC8; /* PBDC8 */ - volatile uint8_t dummy461[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC9; /* PBDC9 */ - volatile uint8_t dummy462[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC10; /* PBDC10 */ - volatile uint8_t dummy463[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ -/* start of struct st_gpio_from_pbdc1 */ - volatile uint16_t PBDC11; /* PBDC11 */ - volatile uint8_t dummy4640[2]; /* */ -/* end of struct st_gpio_from_pbdc1 */ - volatile uint8_t dummy4641[212]; /* */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC1; /* PIPC1 */ - volatile uint8_t dummy465[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC2; /* PIPC2 */ - volatile uint8_t dummy466[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC3; /* PIPC3 */ - volatile uint8_t dummy467[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC4; /* PIPC4 */ - volatile uint8_t dummy468[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC5; /* PIPC5 */ - volatile uint8_t dummy469[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC6; /* PIPC6 */ - volatile uint8_t dummy470[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC7; /* PIPC7 */ - volatile uint8_t dummy471[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC8; /* PIPC8 */ - volatile uint8_t dummy472[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC9; /* PIPC9 */ - volatile uint8_t dummy473[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC10; /* PIPC10 */ - volatile uint8_t dummy474[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ -/* start of struct st_gpio_from_pipc1 */ - volatile uint16_t PIPC11; /* PIPC11 */ - volatile uint8_t dummy4750[2]; /* */ -/* end of struct st_gpio_from_pipc1 */ - volatile uint8_t dummy4751[2288]; /* */ - volatile uint16_t JPPR0; /* JPPR0 */ - volatile uint8_t dummy476[30]; /* */ - volatile uint16_t JPMC0; /* JPMC0 */ - volatile uint8_t dummy477[78]; /* */ - volatile uint32_t JPMCSR0; /* JPMCSR0 */ - volatile uint8_t dummy478[876]; /* */ - volatile uint16_t JPIBC0; /* JPIBC0 */ -}; - - -struct st_gpio_from_p1 -{ - volatile uint16_t P1; /* P1 */ - volatile uint8_t dummy1[3]; /* */ -}; - - -struct st_gpio_from_ppr0 -{ - volatile uint16_t PPR0; /* PPR0 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pm1 -{ - volatile uint16_t PM1; /* PM1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pmc0 -{ - volatile uint16_t PMC0; /* PMC0 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pfc1 -{ - volatile uint16_t PFC1; /* PFC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pfce1 -{ - volatile uint16_t PFCE1; /* PFCE1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pnot1 -{ - volatile uint16_t PNOT1; /* PNOT1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pfcae1 -{ - volatile uint16_t PFCAE1; /* PFCAE1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pibc1 -{ - volatile uint16_t PIBC1; /* PIBC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pbdc1 -{ - volatile uint16_t PBDC1; /* PBDC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - -struct st_gpio_from_pipc1 -{ - volatile uint16_t PIPC1; /* PIPC1 */ - volatile uint8_t dummy1[2]; /* */ -}; - - #define GPIO (*(struct st_gpio *)0xFCFE3004uL) /* GPIO */ -/* Start of channnel array defines of GPIO */ -/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */ +/* Start of channel array defines of GPIO */ + +/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */ /*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */ -#define GPIO_FROM_PIPC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIPC1_ARRAY_COUNT (11) #define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \ @@ -692,9 +59,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */ -/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */ +/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */ /*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */ -#define GPIO_FROM_PBDC1_ARRAY_COUNT 11 +#define GPIO_FROM_PBDC1_ARRAY_COUNT (11) #define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \ @@ -713,14 +80,15 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */ -/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */ +/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */ /*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */ -#define GPIO_FROM_PIBC1_ARRAY_COUNT 11 +#define GPIO_FROM_PIBC1_ARRAY_COUNT (12) #define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \ - &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ + &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \ + &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */ #define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */ #define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */ #define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */ @@ -734,9 +102,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */ -/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */ +/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */ /*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */ -#define GPIO_FROM_PFCAE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCAE1_ARRAY_COUNT (11) #define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \ @@ -755,9 +123,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */ -/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */ +/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */ /*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */ -#define GPIO_FROM_PNOT1_ARRAY_COUNT 11 +#define GPIO_FROM_PNOT1_ARRAY_COUNT (11) #define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \ @@ -776,9 +144,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */ -/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */ +/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */ /*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */ -#define GPIO_FROM_PFCE1_ARRAY_COUNT 11 +#define GPIO_FROM_PFCE1_ARRAY_COUNT (11) #define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \ @@ -797,9 +165,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */ -/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */ +/* Channel array defines of GPIO_FROM_PFC1_ARRAY */ /*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */ -#define GPIO_FROM_PFC1_ARRAY_COUNT 11 +#define GPIO_FROM_PFC1_ARRAY_COUNT (11) #define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \ @@ -818,9 +186,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */ -/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */ +/* Channel array defines of GPIO_FROM_PMC0_ARRAY */ /*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */ -#define GPIO_FROM_PMC0_ARRAY_COUNT 12 +#define GPIO_FROM_PMC0_ARRAY_COUNT (12) #define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \ @@ -840,9 +208,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */ -/* Channnel array defines of GPIO_FROM_PM1_ARRAY */ +/* Channel array defines of GPIO_FROM_PM1_ARRAY */ /*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */ -#define GPIO_FROM_PM1_ARRAY_COUNT 11 +#define GPIO_FROM_PM1_ARRAY_COUNT (11) #define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \ @@ -861,9 +229,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11) /* GPIO_FROM_PM11 */ -/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */ +/* Channel array defines of GPIO_FROM_PPR0_ARRAY */ /*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */ -#define GPIO_FROM_PPR0_ARRAY_COUNT 12 +#define GPIO_FROM_PPR0_ARRAY_COUNT (12) #define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \ @@ -883,9 +251,9 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */ -/* Channnel array defines of GPIO_FROM_P1_ARRAY */ +/* Channel array defines of GPIO_FROM_P1_ARRAY */ /*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */ -#define GPIO_FROM_P1_ARRAY_COUNT 11 +#define GPIO_FROM_P1_ARRAY_COUNT (11) #define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \ @@ -903,172 +271,1161 @@ struct st_gpio_from_pipc1 #define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10) /* GPIO_FROM_P10 */ #define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11) /* GPIO_FROM_P11 */ -/* End of channnel array defines of GPIO */ +/* End of channel array defines of GPIO */ + + +#define GPIOP1 (GPIO.P1) +#define GPIOP2 (GPIO.P2) +#define GPIOP3 (GPIO.P3) +#define GPIOP4 (GPIO.P4) +#define GPIOP5 (GPIO.P5) +#define GPIOP6 (GPIO.P6) +#define GPIOP7 (GPIO.P7) +#define GPIOP8 (GPIO.P8) +#define GPIOP9 (GPIO.P9) +#define GPIOP10 (GPIO.P10) +#define GPIOP11 (GPIO.P11) +#define GPIOPSR1 (GPIO.PSR1) +#define GPIOPSR2 (GPIO.PSR2) +#define GPIOPSR3 (GPIO.PSR3) +#define GPIOPSR4 (GPIO.PSR4) +#define GPIOPSR5 (GPIO.PSR5) +#define GPIOPSR6 (GPIO.PSR6) +#define GPIOPSR7 (GPIO.PSR7) +#define GPIOPSR8 (GPIO.PSR8) +#define GPIOPSR9 (GPIO.PSR9) +#define GPIOPSR10 (GPIO.PSR10) +#define GPIOPSR11 (GPIO.PSR11) +#define GPIOPPR0 (GPIO.PPR0) +#define GPIOPPR1 (GPIO.PPR1) +#define GPIOPPR2 (GPIO.PPR2) +#define GPIOPPR3 (GPIO.PPR3) +#define GPIOPPR4 (GPIO.PPR4) +#define GPIOPPR5 (GPIO.PPR5) +#define GPIOPPR6 (GPIO.PPR6) +#define GPIOPPR7 (GPIO.PPR7) +#define GPIOPPR8 (GPIO.PPR8) +#define GPIOPPR9 (GPIO.PPR9) +#define GPIOPPR10 (GPIO.PPR10) +#define GPIOPPR11 (GPIO.PPR11) +#define GPIOPM1 (GPIO.PM1) +#define GPIOPM2 (GPIO.PM2) +#define GPIOPM3 (GPIO.PM3) +#define GPIOPM4 (GPIO.PM4) +#define GPIOPM5 (GPIO.PM5) +#define GPIOPM6 (GPIO.PM6) +#define GPIOPM7 (GPIO.PM7) +#define GPIOPM8 (GPIO.PM8) +#define GPIOPM9 (GPIO.PM9) +#define GPIOPM10 (GPIO.PM10) +#define GPIOPM11 (GPIO.PM11) +#define GPIOPMC0 (GPIO.PMC0) +#define GPIOPMC1 (GPIO.PMC1) +#define GPIOPMC2 (GPIO.PMC2) +#define GPIOPMC3 (GPIO.PMC3) +#define GPIOPMC4 (GPIO.PMC4) +#define GPIOPMC5 (GPIO.PMC5) +#define GPIOPMC6 (GPIO.PMC6) +#define GPIOPMC7 (GPIO.PMC7) +#define GPIOPMC8 (GPIO.PMC8) +#define GPIOPMC9 (GPIO.PMC9) +#define GPIOPMC10 (GPIO.PMC10) +#define GPIOPMC11 (GPIO.PMC11) +#define GPIOPFC1 (GPIO.PFC1) +#define GPIOPFC2 (GPIO.PFC2) +#define GPIOPFC3 (GPIO.PFC3) +#define GPIOPFC4 (GPIO.PFC4) +#define GPIOPFC5 (GPIO.PFC5) +#define GPIOPFC6 (GPIO.PFC6) +#define GPIOPFC7 (GPIO.PFC7) +#define GPIOPFC8 (GPIO.PFC8) +#define GPIOPFC9 (GPIO.PFC9) +#define GPIOPFC10 (GPIO.PFC10) +#define GPIOPFC11 (GPIO.PFC11) +#define GPIOPFCE1 (GPIO.PFCE1) +#define GPIOPFCE2 (GPIO.PFCE2) +#define GPIOPFCE3 (GPIO.PFCE3) +#define GPIOPFCE4 (GPIO.PFCE4) +#define GPIOPFCE5 (GPIO.PFCE5) +#define GPIOPFCE6 (GPIO.PFCE6) +#define GPIOPFCE7 (GPIO.PFCE7) +#define GPIOPFCE8 (GPIO.PFCE8) +#define GPIOPFCE9 (GPIO.PFCE9) +#define GPIOPFCE10 (GPIO.PFCE10) +#define GPIOPFCE11 (GPIO.PFCE11) +#define GPIOPNOT1 (GPIO.PNOT1) +#define GPIOPNOT2 (GPIO.PNOT2) +#define GPIOPNOT3 (GPIO.PNOT3) +#define GPIOPNOT4 (GPIO.PNOT4) +#define GPIOPNOT5 (GPIO.PNOT5) +#define GPIOPNOT6 (GPIO.PNOT6) +#define GPIOPNOT7 (GPIO.PNOT7) +#define GPIOPNOT8 (GPIO.PNOT8) +#define GPIOPNOT9 (GPIO.PNOT9) +#define GPIOPNOT10 (GPIO.PNOT10) +#define GPIOPNOT11 (GPIO.PNOT11) +#define GPIOPMSR1 (GPIO.PMSR1) +#define GPIOPMSR2 (GPIO.PMSR2) +#define GPIOPMSR3 (GPIO.PMSR3) +#define GPIOPMSR4 (GPIO.PMSR4) +#define GPIOPMSR5 (GPIO.PMSR5) +#define GPIOPMSR6 (GPIO.PMSR6) +#define GPIOPMSR7 (GPIO.PMSR7) +#define GPIOPMSR8 (GPIO.PMSR8) +#define GPIOPMSR9 (GPIO.PMSR9) +#define GPIOPMSR10 (GPIO.PMSR10) +#define GPIOPMSR11 (GPIO.PMSR11) +#define GPIOPMCSR0 (GPIO.PMCSR0) +#define GPIOPMCSR1 (GPIO.PMCSR1) +#define GPIOPMCSR2 (GPIO.PMCSR2) +#define GPIOPMCSR3 (GPIO.PMCSR3) +#define GPIOPMCSR4 (GPIO.PMCSR4) +#define GPIOPMCSR5 (GPIO.PMCSR5) +#define GPIOPMCSR6 (GPIO.PMCSR6) +#define GPIOPMCSR7 (GPIO.PMCSR7) +#define GPIOPMCSR8 (GPIO.PMCSR8) +#define GPIOPMCSR9 (GPIO.PMCSR9) +#define GPIOPMCSR10 (GPIO.PMCSR10) +#define GPIOPMCSR11 (GPIO.PMCSR11) +#define GPIOPFCAE1 (GPIO.PFCAE1) +#define GPIOPFCAE2 (GPIO.PFCAE2) +#define GPIOPFCAE3 (GPIO.PFCAE3) +#define GPIOPFCAE4 (GPIO.PFCAE4) +#define GPIOPFCAE5 (GPIO.PFCAE5) +#define GPIOPFCAE6 (GPIO.PFCAE6) +#define GPIOPFCAE7 (GPIO.PFCAE7) +#define GPIOPFCAE8 (GPIO.PFCAE8) +#define GPIOPFCAE9 (GPIO.PFCAE9) +#define GPIOPFCAE10 (GPIO.PFCAE10) +#define GPIOPFCAE11 (GPIO.PFCAE11) +#define GPIOSNCR (GPIO.SNCR) +#define GPIOPIBC0 (GPIO.PIBC0) +#define GPIOPIBC1 (GPIO.PIBC1) +#define GPIOPIBC2 (GPIO.PIBC2) +#define GPIOPIBC3 (GPIO.PIBC3) +#define GPIOPIBC4 (GPIO.PIBC4) +#define GPIOPIBC5 (GPIO.PIBC5) +#define GPIOPIBC6 (GPIO.PIBC6) +#define GPIOPIBC7 (GPIO.PIBC7) +#define GPIOPIBC8 (GPIO.PIBC8) +#define GPIOPIBC9 (GPIO.PIBC9) +#define GPIOPIBC10 (GPIO.PIBC10) +#define GPIOPIBC11 (GPIO.PIBC11) +#define GPIOPBDC1 (GPIO.PBDC1) +#define GPIOPBDC2 (GPIO.PBDC2) +#define GPIOPBDC3 (GPIO.PBDC3) +#define GPIOPBDC4 (GPIO.PBDC4) +#define GPIOPBDC5 (GPIO.PBDC5) +#define GPIOPBDC6 (GPIO.PBDC6) +#define GPIOPBDC7 (GPIO.PBDC7) +#define GPIOPBDC8 (GPIO.PBDC8) +#define GPIOPBDC9 (GPIO.PBDC9) +#define GPIOPBDC10 (GPIO.PBDC10) +#define GPIOPBDC11 (GPIO.PBDC11) +#define GPIOPIPC1 (GPIO.PIPC1) +#define GPIOPIPC2 (GPIO.PIPC2) +#define GPIOPIPC3 (GPIO.PIPC3) +#define GPIOPIPC4 (GPIO.PIPC4) +#define GPIOPIPC5 (GPIO.PIPC5) +#define GPIOPIPC6 (GPIO.PIPC6) +#define GPIOPIPC7 (GPIO.PIPC7) +#define GPIOPIPC8 (GPIO.PIPC8) +#define GPIOPIPC9 (GPIO.PIPC9) +#define GPIOPIPC10 (GPIO.PIPC10) +#define GPIOPIPC11 (GPIO.PIPC11) +#define GPIOJPPR0 (GPIO.JPPR0) +#define GPIOJPMC0 (GPIO.JPMC0) +#define GPIOJPMCSR0 (GPIO.JPMCSR0) +#define GPIOJPIBC0 (GPIO.JPIBC0) + +#define GPIO_PSRn_COUNT (11) +#define GPIO_PMSRn_COUNT (11) +#define GPIO_PMCSRn_COUNT (12) + + +typedef struct st_gpio +{ + /* GPIO */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy348[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P2; /* P2 */ + volatile uint8_t dummy349[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P3; /* P3 */ + volatile uint8_t dummy350[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P4; /* P4 */ + volatile uint8_t dummy351[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P5; /* P5 */ + volatile uint8_t dummy352[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P6; /* P6 */ + volatile uint8_t dummy353[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P7; /* P7 */ + volatile uint8_t dummy354[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P8; /* P8 */ + volatile uint8_t dummy355[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P9; /* P9 */ + volatile uint8_t dummy356[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P10; /* P10 */ + volatile uint8_t dummy357[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + +/* start of struct st_gpio_from_p1 */ + volatile uint16_t P11; /* P11 */ + volatile uint8_t dummy3580[2]; /* */ + +/* end of struct st_gpio_from_p1 */ + volatile uint8_t dummy3581[212]; /* */ + +/* #define GPIO_PSRn_COUNT (11) */ + volatile uint32_t PSR1; /* PSR1 */ + volatile uint32_t PSR2; /* PSR2 */ + volatile uint32_t PSR3; /* PSR3 */ + volatile uint32_t PSR4; /* PSR4 */ + volatile uint32_t PSR5; /* PSR5 */ + volatile uint32_t PSR6; /* PSR6 */ + volatile uint32_t PSR7; /* PSR7 */ + volatile uint32_t PSR8; /* PSR8 */ + volatile uint32_t PSR9; /* PSR9 */ + volatile uint32_t PSR10; /* PSR10 */ + volatile uint32_t PSR11; /* PSR11 */ + volatile uint8_t dummy359[208]; /* */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy360[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR1; /* PPR1 */ + volatile uint8_t dummy361[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR2; /* PPR2 */ + volatile uint8_t dummy362[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR3; /* PPR3 */ + volatile uint8_t dummy363[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR4; /* PPR4 */ + volatile uint8_t dummy364[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR5; /* PPR5 */ + volatile uint8_t dummy365[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR6; /* PPR6 */ + volatile uint8_t dummy366[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR7; /* PPR7 */ + volatile uint8_t dummy367[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR8; /* PPR8 */ + volatile uint8_t dummy368[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR9; /* PPR9 */ + volatile uint8_t dummy369[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR10; /* PPR10 */ + volatile uint8_t dummy370[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + +/* start of struct st_gpio_from_ppr0 */ + volatile uint16_t PPR11; /* PPR11 */ + volatile uint8_t dummy3710[2]; /* */ + +/* end of struct st_gpio_from_ppr0 */ + volatile uint8_t dummy3711[212]; /* */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy372[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM2; /* PM2 */ + volatile uint8_t dummy373[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM3; /* PM3 */ + volatile uint8_t dummy374[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM4; /* PM4 */ + volatile uint8_t dummy375[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM5; /* PM5 */ + volatile uint8_t dummy376[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM6; /* PM6 */ + volatile uint8_t dummy377[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM7; /* PM7 */ + volatile uint8_t dummy378[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM8; /* PM8 */ + volatile uint8_t dummy379[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM9; /* PM9 */ + volatile uint8_t dummy380[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM10; /* PM10 */ + volatile uint8_t dummy381[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + +/* start of struct st_gpio_from_pm1 */ + volatile uint16_t PM11; /* PM11 */ + volatile uint8_t dummy3820[2]; /* */ + +/* end of struct st_gpio_from_pm1 */ + volatile uint8_t dummy3821[208]; /* */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy383[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC1; /* PMC1 */ + volatile uint8_t dummy384[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC2; /* PMC2 */ + volatile uint8_t dummy385[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC3; /* PMC3 */ + volatile uint8_t dummy386[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC4; /* PMC4 */ + volatile uint8_t dummy387[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC5; /* PMC5 */ + volatile uint8_t dummy388[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC6; /* PMC6 */ + volatile uint8_t dummy389[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC7; /* PMC7 */ + volatile uint8_t dummy390[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC8; /* PMC8 */ + volatile uint8_t dummy391[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC9; /* PMC9 */ + volatile uint8_t dummy392[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC10; /* PMC10 */ + volatile uint8_t dummy393[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + +/* start of struct st_gpio_from_pmc0 */ + volatile uint16_t PMC11; /* PMC11 */ + volatile uint8_t dummy3940[2]; /* */ + +/* end of struct st_gpio_from_pmc0 */ + volatile uint8_t dummy3941[212]; /* */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy395[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC2; /* PFC2 */ + volatile uint8_t dummy396[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC3; /* PFC3 */ + volatile uint8_t dummy397[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC4; /* PFC4 */ + volatile uint8_t dummy398[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC5; /* PFC5 */ + volatile uint8_t dummy399[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC6; /* PFC6 */ + volatile uint8_t dummy400[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC7; /* PFC7 */ + volatile uint8_t dummy401[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC8; /* PFC8 */ + volatile uint8_t dummy402[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC9; /* PFC9 */ + volatile uint8_t dummy403[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC10; /* PFC10 */ + volatile uint8_t dummy404[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + +/* start of struct st_gpio_from_pfc1 */ + volatile uint16_t PFC11; /* PFC11 */ + volatile uint8_t dummy4050[2]; /* */ + +/* end of struct st_gpio_from_pfc1 */ + volatile uint8_t dummy4051[212]; /* */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy406[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE2; /* PFCE2 */ + volatile uint8_t dummy407[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE3; /* PFCE3 */ + volatile uint8_t dummy408[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE4; /* PFCE4 */ + volatile uint8_t dummy409[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE5; /* PFCE5 */ + volatile uint8_t dummy410[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE6; /* PFCE6 */ + volatile uint8_t dummy411[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE7; /* PFCE7 */ + volatile uint8_t dummy412[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE8; /* PFCE8 */ + volatile uint8_t dummy413[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE9; /* PFCE9 */ + volatile uint8_t dummy414[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE10; /* PFCE10 */ + volatile uint8_t dummy415[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + +/* start of struct st_gpio_from_pfce1 */ + volatile uint16_t PFCE11; /* PFCE11 */ + volatile uint8_t dummy4160[2]; /* */ + +/* end of struct st_gpio_from_pfce1 */ + volatile uint8_t dummy4161[212]; /* */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy417[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT2; /* PNOT2 */ + volatile uint8_t dummy418[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT3; /* PNOT3 */ + volatile uint8_t dummy419[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT4; /* PNOT4 */ + volatile uint8_t dummy420[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT5; /* PNOT5 */ + volatile uint8_t dummy421[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT6; /* PNOT6 */ + volatile uint8_t dummy422[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT7; /* PNOT7 */ + volatile uint8_t dummy423[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT8; /* PNOT8 */ + volatile uint8_t dummy424[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT9; /* PNOT9 */ + volatile uint8_t dummy425[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT10; /* PNOT10 */ + volatile uint8_t dummy426[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + +/* start of struct st_gpio_from_pnot1 */ + volatile uint16_t PNOT11; /* PNOT11 */ + volatile uint8_t dummy4270[2]; /* */ + +/* end of struct st_gpio_from_pnot1 */ + volatile uint8_t dummy4271[212]; /* */ + +/* #define GPIO_PMSRn_COUNT (11) */ + volatile uint32_t PMSR1; /* PMSR1 */ + volatile uint32_t PMSR2; /* PMSR2 */ + volatile uint32_t PMSR3; /* PMSR3 */ + volatile uint32_t PMSR4; /* PMSR4 */ + volatile uint32_t PMSR5; /* PMSR5 */ + volatile uint32_t PMSR6; /* PMSR6 */ + volatile uint32_t PMSR7; /* PMSR7 */ + volatile uint32_t PMSR8; /* PMSR8 */ + volatile uint32_t PMSR9; /* PMSR9 */ + volatile uint32_t PMSR10; /* PMSR10 */ + volatile uint32_t PMSR11; /* PMSR11 */ + volatile uint8_t dummy428[208]; /* */ + +/* #define GPIO_PMCSRn_COUNT (12) */ + volatile uint32_t PMCSR0; /* PMCSR0 */ + volatile uint32_t PMCSR1; /* PMCSR1 */ + volatile uint32_t PMCSR2; /* PMCSR2 */ + volatile uint32_t PMCSR3; /* PMCSR3 */ + volatile uint32_t PMCSR4; /* PMCSR4 */ + volatile uint32_t PMCSR5; /* PMCSR5 */ + volatile uint32_t PMCSR6; /* PMCSR6 */ + volatile uint32_t PMCSR7; /* PMCSR7 */ + volatile uint32_t PMCSR8; /* PMCSR8 */ + volatile uint32_t PMCSR9; /* PMCSR9 */ + volatile uint32_t PMCSR10; /* PMCSR10 */ + volatile uint32_t PMCSR11; /* PMCSR11 */ + volatile uint8_t dummy429[212]; /* */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy430[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE2; /* PFCAE2 */ + volatile uint8_t dummy431[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE3; /* PFCAE3 */ + volatile uint8_t dummy432[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE4; /* PFCAE4 */ + volatile uint8_t dummy433[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE5; /* PFCAE5 */ + volatile uint8_t dummy434[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE6; /* PFCAE6 */ + volatile uint8_t dummy435[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE7; /* PFCAE7 */ + volatile uint8_t dummy436[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE8; /* PFCAE8 */ + volatile uint8_t dummy437[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE9; /* PFCAE9 */ + volatile uint8_t dummy438[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE10; /* PFCAE10 */ + volatile uint8_t dummy439[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + +/* start of struct st_gpio_from_pfcae1 */ + volatile uint16_t PFCAE11; /* PFCAE11 */ + volatile uint8_t dummy4400[2]; /* */ + +/* end of struct st_gpio_from_pfcae1 */ + volatile uint8_t dummy4401[464]; /* */ + volatile uint32_t SNCR; /* SNCR */ + volatile uint8_t dummy441[13308]; /* */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC0; /* PIBC0 */ + volatile uint8_t dummy442[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy443[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC2; /* PIBC2 */ + volatile uint8_t dummy444[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC3; /* PIBC3 */ + volatile uint8_t dummy445[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC4; /* PIBC4 */ + volatile uint8_t dummy446[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC5; /* PIBC5 */ + volatile uint8_t dummy447[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC6; /* PIBC6 */ + volatile uint8_t dummy448[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC7; /* PIBC7 */ + volatile uint8_t dummy449[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC8; /* PIBC8 */ + volatile uint8_t dummy450[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC9; /* PIBC9 */ + volatile uint8_t dummy451[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC10; /* PIBC10 */ + volatile uint8_t dummy452[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + +/* start of struct st_gpio_from_pibc1 */ + volatile uint16_t PIBC11; /* PIBC11 */ + volatile uint8_t dummy4530[2]; /* */ + +/* end of struct st_gpio_from_pibc1 */ + volatile uint8_t dummy4531[212]; /* */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy454[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC2; /* PBDC2 */ + volatile uint8_t dummy455[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC3; /* PBDC3 */ + volatile uint8_t dummy456[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC4; /* PBDC4 */ + volatile uint8_t dummy457[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC5; /* PBDC5 */ + volatile uint8_t dummy458[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC6; /* PBDC6 */ + volatile uint8_t dummy459[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC7; /* PBDC7 */ + volatile uint8_t dummy460[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC8; /* PBDC8 */ + volatile uint8_t dummy461[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC9; /* PBDC9 */ + volatile uint8_t dummy462[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC10; /* PBDC10 */ + volatile uint8_t dummy463[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + +/* start of struct st_gpio_from_pbdc1 */ + volatile uint16_t PBDC11; /* PBDC11 */ + volatile uint8_t dummy4640[2]; /* */ + +/* end of struct st_gpio_from_pbdc1 */ + volatile uint8_t dummy4641[212]; /* */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy465[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC2; /* PIPC2 */ + volatile uint8_t dummy466[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC3; /* PIPC3 */ + volatile uint8_t dummy467[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC4; /* PIPC4 */ + volatile uint8_t dummy468[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC5; /* PIPC5 */ + volatile uint8_t dummy469[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC6; /* PIPC6 */ + volatile uint8_t dummy470[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC7; /* PIPC7 */ + volatile uint8_t dummy471[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC8; /* PIPC8 */ + volatile uint8_t dummy472[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC9; /* PIPC9 */ + volatile uint8_t dummy473[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC10; /* PIPC10 */ + volatile uint8_t dummy474[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + +/* start of struct st_gpio_from_pipc1 */ + volatile uint16_t PIPC11; /* PIPC11 */ + volatile uint8_t dummy4750[2]; /* */ + +/* end of struct st_gpio_from_pipc1 */ + volatile uint8_t dummy4751[2288]; /* */ + volatile uint16_t JPPR0; /* JPPR0 */ + volatile uint8_t dummy476[30]; /* */ + volatile uint16_t JPMC0; /* JPMC0 */ + volatile uint8_t dummy477[78]; /* */ + volatile uint32_t JPMCSR0; /* JPMCSR0 */ + volatile uint8_t dummy478[876]; /* */ + volatile uint16_t JPIBC0; /* JPIBC0 */ +} r_io_gpio_t; + + +typedef struct st_gpio_from_p1 +{ + + volatile uint16_t P1; /* P1 */ + volatile uint8_t dummy1[3]; /* */ +} r_io_gpio_from_p1_t; + + +typedef struct st_gpio_from_ppr0 +{ + + volatile uint16_t PPR0; /* PPR0 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_ppr0_t; + + +typedef struct st_gpio_from_pm1 +{ + + volatile uint16_t PM1; /* PM1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pm1_t; + + +typedef struct st_gpio_from_pmc0 +{ + + volatile uint16_t PMC0; /* PMC0 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pmc0_t; + + +typedef struct st_gpio_from_pfc1 +{ + + volatile uint16_t PFC1; /* PFC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfc1_t; + + +typedef struct st_gpio_from_pfce1 +{ + + volatile uint16_t PFCE1; /* PFCE1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfce1_t; + + +typedef struct st_gpio_from_pnot1 +{ + + volatile uint16_t PNOT1; /* PNOT1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pnot1_t; + + +typedef struct st_gpio_from_pfcae1 +{ + + volatile uint16_t PFCAE1; /* PFCAE1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pfcae1_t; + + +typedef struct st_gpio_from_pibc1 +{ + + volatile uint16_t PIBC1; /* PIBC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pibc1_t; + + +typedef struct st_gpio_from_pbdc1 +{ + + volatile uint16_t PBDC1; /* PBDC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pbdc1_t; + + +typedef struct st_gpio_from_pipc1 +{ + + volatile uint16_t PIPC1; /* PIPC1 */ + volatile uint8_t dummy1[2]; /* */ +} r_io_gpio_from_pipc1_t; + + +/* Channel array defines of GPIO (2)*/ +#ifdef DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pipc1* GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pbdc1* GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pibc1* GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfcae1* GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS +volatile struct st_gpio_from_pnot1* GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfce1* GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS +volatile struct st_gpio_from_pfc1* GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS +volatile struct st_gpio_from_pmc0* GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS +volatile struct st_gpio_from_pm1* GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PM1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS +volatile struct st_gpio_from_ppr0* GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */ + +#ifdef DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS +volatile struct st_gpio_from_p1* GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + GPIO_FROM_P1_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */ +/* End of channel array defines of GPIO (2)*/ -#define GPIOP1 GPIO.P1 -#define GPIOP2 GPIO.P2 -#define GPIOP3 GPIO.P3 -#define GPIOP4 GPIO.P4 -#define GPIOP5 GPIO.P5 -#define GPIOP6 GPIO.P6 -#define GPIOP7 GPIO.P7 -#define GPIOP8 GPIO.P8 -#define GPIOP9 GPIO.P9 -#define GPIOP10 GPIO.P10 -#define GPIOP11 GPIO.P11 -#define GPIOPSR1 GPIO.PSR1 -#define GPIOPSR2 GPIO.PSR2 -#define GPIOPSR3 GPIO.PSR3 -#define GPIOPSR4 GPIO.PSR4 -#define GPIOPSR5 GPIO.PSR5 -#define GPIOPSR6 GPIO.PSR6 -#define GPIOPSR7 GPIO.PSR7 -#define GPIOPSR8 GPIO.PSR8 -#define GPIOPSR9 GPIO.PSR9 -#define GPIOPSR10 GPIO.PSR10 -#define GPIOPSR11 GPIO.PSR11 -#define GPIOPPR0 GPIO.PPR0 -#define GPIOPPR1 GPIO.PPR1 -#define GPIOPPR2 GPIO.PPR2 -#define GPIOPPR3 GPIO.PPR3 -#define GPIOPPR4 GPIO.PPR4 -#define GPIOPPR5 GPIO.PPR5 -#define GPIOPPR6 GPIO.PPR6 -#define GPIOPPR7 GPIO.PPR7 -#define GPIOPPR8 GPIO.PPR8 -#define GPIOPPR9 GPIO.PPR9 -#define GPIOPPR10 GPIO.PPR10 -#define GPIOPPR11 GPIO.PPR11 -#define GPIOPM1 GPIO.PM1 -#define GPIOPM2 GPIO.PM2 -#define GPIOPM3 GPIO.PM3 -#define GPIOPM4 GPIO.PM4 -#define GPIOPM5 GPIO.PM5 -#define GPIOPM6 GPIO.PM6 -#define GPIOPM7 GPIO.PM7 -#define GPIOPM8 GPIO.PM8 -#define GPIOPM9 GPIO.PM9 -#define GPIOPM10 GPIO.PM10 -#define GPIOPM11 GPIO.PM11 -#define GPIOPMC0 GPIO.PMC0 -#define GPIOPMC1 GPIO.PMC1 -#define GPIOPMC2 GPIO.PMC2 -#define GPIOPMC3 GPIO.PMC3 -#define GPIOPMC4 GPIO.PMC4 -#define GPIOPMC5 GPIO.PMC5 -#define GPIOPMC6 GPIO.PMC6 -#define GPIOPMC7 GPIO.PMC7 -#define GPIOPMC8 GPIO.PMC8 -#define GPIOPMC9 GPIO.PMC9 -#define GPIOPMC10 GPIO.PMC10 -#define GPIOPMC11 GPIO.PMC11 -#define GPIOPFC1 GPIO.PFC1 -#define GPIOPFC2 GPIO.PFC2 -#define GPIOPFC3 GPIO.PFC3 -#define GPIOPFC4 GPIO.PFC4 -#define GPIOPFC5 GPIO.PFC5 -#define GPIOPFC6 GPIO.PFC6 -#define GPIOPFC7 GPIO.PFC7 -#define GPIOPFC8 GPIO.PFC8 -#define GPIOPFC9 GPIO.PFC9 -#define GPIOPFC10 GPIO.PFC10 -#define GPIOPFC11 GPIO.PFC11 -#define GPIOPFCE1 GPIO.PFCE1 -#define GPIOPFCE2 GPIO.PFCE2 -#define GPIOPFCE3 GPIO.PFCE3 -#define GPIOPFCE4 GPIO.PFCE4 -#define GPIOPFCE5 GPIO.PFCE5 -#define GPIOPFCE6 GPIO.PFCE6 -#define GPIOPFCE7 GPIO.PFCE7 -#define GPIOPFCE8 GPIO.PFCE8 -#define GPIOPFCE9 GPIO.PFCE9 -#define GPIOPFCE10 GPIO.PFCE10 -#define GPIOPFCE11 GPIO.PFCE11 -#define GPIOPNOT1 GPIO.PNOT1 -#define GPIOPNOT2 GPIO.PNOT2 -#define GPIOPNOT3 GPIO.PNOT3 -#define GPIOPNOT4 GPIO.PNOT4 -#define GPIOPNOT5 GPIO.PNOT5 -#define GPIOPNOT6 GPIO.PNOT6 -#define GPIOPNOT7 GPIO.PNOT7 -#define GPIOPNOT8 GPIO.PNOT8 -#define GPIOPNOT9 GPIO.PNOT9 -#define GPIOPNOT10 GPIO.PNOT10 -#define GPIOPNOT11 GPIO.PNOT11 -#define GPIOPMSR1 GPIO.PMSR1 -#define GPIOPMSR2 GPIO.PMSR2 -#define GPIOPMSR3 GPIO.PMSR3 -#define GPIOPMSR4 GPIO.PMSR4 -#define GPIOPMSR5 GPIO.PMSR5 -#define GPIOPMSR6 GPIO.PMSR6 -#define GPIOPMSR7 GPIO.PMSR7 -#define GPIOPMSR8 GPIO.PMSR8 -#define GPIOPMSR9 GPIO.PMSR9 -#define GPIOPMSR10 GPIO.PMSR10 -#define GPIOPMSR11 GPIO.PMSR11 -#define GPIOPMCSR0 GPIO.PMCSR0 -#define GPIOPMCSR1 GPIO.PMCSR1 -#define GPIOPMCSR2 GPIO.PMCSR2 -#define GPIOPMCSR3 GPIO.PMCSR3 -#define GPIOPMCSR4 GPIO.PMCSR4 -#define GPIOPMCSR5 GPIO.PMCSR5 -#define GPIOPMCSR6 GPIO.PMCSR6 -#define GPIOPMCSR7 GPIO.PMCSR7 -#define GPIOPMCSR8 GPIO.PMCSR8 -#define GPIOPMCSR9 GPIO.PMCSR9 -#define GPIOPMCSR10 GPIO.PMCSR10 -#define GPIOPMCSR11 GPIO.PMCSR11 -#define GPIOPFCAE1 GPIO.PFCAE1 -#define GPIOPFCAE2 GPIO.PFCAE2 -#define GPIOPFCAE3 GPIO.PFCAE3 -#define GPIOPFCAE4 GPIO.PFCAE4 -#define GPIOPFCAE5 GPIO.PFCAE5 -#define GPIOPFCAE6 GPIO.PFCAE6 -#define GPIOPFCAE7 GPIO.PFCAE7 -#define GPIOPFCAE8 GPIO.PFCAE8 -#define GPIOPFCAE9 GPIO.PFCAE9 -#define GPIOPFCAE10 GPIO.PFCAE10 -#define GPIOPFCAE11 GPIO.PFCAE11 -#define GPIOSNCR GPIO.SNCR -#define GPIOPIBC0 GPIO.PIBC0 -#define GPIOPIBC1 GPIO.PIBC1 -#define GPIOPIBC2 GPIO.PIBC2 -#define GPIOPIBC3 GPIO.PIBC3 -#define GPIOPIBC4 GPIO.PIBC4 -#define GPIOPIBC5 GPIO.PIBC5 -#define GPIOPIBC6 GPIO.PIBC6 -#define GPIOPIBC7 GPIO.PIBC7 -#define GPIOPIBC8 GPIO.PIBC8 -#define GPIOPIBC9 GPIO.PIBC9 -#define GPIOPIBC10 GPIO.PIBC10 -#define GPIOPIBC11 GPIO.PIBC11 -#define GPIOPBDC1 GPIO.PBDC1 -#define GPIOPBDC2 GPIO.PBDC2 -#define GPIOPBDC3 GPIO.PBDC3 -#define GPIOPBDC4 GPIO.PBDC4 -#define GPIOPBDC5 GPIO.PBDC5 -#define GPIOPBDC6 GPIO.PBDC6 -#define GPIOPBDC7 GPIO.PBDC7 -#define GPIOPBDC8 GPIO.PBDC8 -#define GPIOPBDC9 GPIO.PBDC9 -#define GPIOPBDC10 GPIO.PBDC10 -#define GPIOPBDC11 GPIO.PBDC11 -#define GPIOPIPC1 GPIO.PIPC1 -#define GPIOPIPC2 GPIO.PIPC2 -#define GPIOPIPC3 GPIO.PIPC3 -#define GPIOPIPC4 GPIO.PIPC4 -#define GPIOPIPC5 GPIO.PIPC5 -#define GPIOPIPC6 GPIO.PIPC6 -#define GPIOPIPC7 GPIO.PIPC7 -#define GPIOPIPC8 GPIO.PIPC8 -#define GPIOPIPC9 GPIO.PIPC9 -#define GPIOPIPC10 GPIO.PIPC10 -#define GPIOPIPC11 GPIO.PIPC11 -#define GPIOJPPR0 GPIO.JPPR0 -#define GPIOJPMC0 GPIO.JPMC0 -#define GPIOJPMCSR0 GPIO.JPMCSR0 -#define GPIOJPIBC0 GPIO.JPIBC0 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h index 8b76e23c6f..5dee5fab31 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h @@ -18,20 +18,55 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ieb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef IEB_IODEFINE_H #define IEB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ieb -{ /* IEB */ +#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ + + +#define IEBB0BCR (IEB.B0BCR) +#define IEBB0PSR (IEB.B0PSR) +#define IEBB0UAR (IEB.B0UAR) +#define IEBB0SAR (IEB.B0SAR) +#define IEBB0PAR (IEB.B0PAR) +#define IEBB0RSA (IEB.B0RSA) +#define IEBB0CDR (IEB.B0CDR) +#define IEBB0TCD (IEB.B0TCD) +#define IEBB0RCD (IEB.B0RCD) +#define IEBB0DLR (IEB.B0DLR) +#define IEBB0TDL (IEB.B0TDL) +#define IEBB0RDL (IEB.B0RDL) +#define IEBB0CKS (IEB.B0CKS) +#define IEBB0TMS (IEB.B0TMS) +#define IEBB0PCR (IEB.B0PCR) +#define IEBB0BSR (IEB.B0BSR) +#define IEBB0SSR (IEB.B0SSR) +#define IEBB0USR (IEB.B0USR) +#define IEBB0ISR (IEB.B0ISR) +#define IEBB0ESR (IEB.B0ESR) +#define IEBB0FSR (IEB.B0FSR) +#define IEBB0SCR (IEB.B0SCR) +#define IEBB0CCR (IEB.B0CCR) +#define IEBB0STC0 (IEB.B0STC0) +#define IEBB0STC1 (IEB.B0STC1) +#define IEBB0DR (IEB.B0DR) + + +typedef struct st_ieb +{ + /* IEB */ volatile uint8_t B0BCR; /* B0BCR */ volatile uint8_t dummy495[3]; /* */ volatile uint8_t B0PSR; /* B0PSR */ @@ -83,37 +118,11 @@ struct st_ieb volatile uint8_t B0STC1; /* B0STC1 */ volatile uint8_t dummy519[3]; /* */ volatile uint8_t B0DR; /* B0DR */ -}; +} r_io_ieb_t; -#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */ - - -#define IEBB0BCR IEB.B0BCR -#define IEBB0PSR IEB.B0PSR -#define IEBB0UAR IEB.B0UAR -#define IEBB0SAR IEB.B0SAR -#define IEBB0PAR IEB.B0PAR -#define IEBB0RSA IEB.B0RSA -#define IEBB0CDR IEB.B0CDR -#define IEBB0TCD IEB.B0TCD -#define IEBB0RCD IEB.B0RCD -#define IEBB0DLR IEB.B0DLR -#define IEBB0TDL IEB.B0TDL -#define IEBB0RDL IEB.B0RDL -#define IEBB0CKS IEB.B0CKS -#define IEBB0TMS IEB.B0TMS -#define IEBB0PCR IEB.B0PCR -#define IEBB0BSR IEB.B0BSR -#define IEBB0SSR IEB.B0SSR -#define IEBB0USR IEB.B0USR -#define IEBB0ISR IEB.B0ISR -#define IEBB0ESR IEB.B0ESR -#define IEBB0FSR IEB.B0FSR -#define IEBB0SCR IEB.B0SCR -#define IEBB0CCR IEB.B0CCR -#define IEBB0STC0 IEB.B0STC0 -#define IEBB0STC1 IEB.B0STC1 -#define IEBB0DR IEB.B0DR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h index f8175a6978..ea148b05d4 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h @@ -18,21 +18,61 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : inb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef INB_IODEFINE_H #define INB_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_inb -{ /* INB */ +#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ + + +#define INBRMPR (INB.RMPR) +#define INBAXIBUSCTL0 (INB.AXIBUSCTL0) +#define INBAXIBUSCTL1 (INB.AXIBUSCTL1) +#define INBAXIBUSCTL2 (INB.AXIBUSCTL2) +#define INBAXIBUSCTL3 (INB.AXIBUSCTL3) +#define INBAXIBUSCTL4 (INB.AXIBUSCTL4) +#define INBAXIBUSCTL5 (INB.AXIBUSCTL5) +#define INBAXIBUSCTL6 (INB.AXIBUSCTL6) +#define INBAXIBUSCTL7 (INB.AXIBUSCTL7) +#define INBAXIBUSCTL8 (INB.AXIBUSCTL8) +#define INBAXIBUSCTL9 (INB.AXIBUSCTL9) +#define INBAXIBUSCTL10 (INB.AXIBUSCTL10) +#define INBAXIRERRCTL0 (INB.AXIRERRCTL0) +#define INBAXIRERRCTL1 (INB.AXIRERRCTL1) +#define INBAXIRERRCTL2 (INB.AXIRERRCTL2) +#define INBAXIRERRCTL3 (INB.AXIRERRCTL3) +#define INBAXIRERRST0 (INB.AXIRERRST0) +#define INBAXIRERRST1 (INB.AXIRERRST1) +#define INBAXIRERRST2 (INB.AXIRERRST2) +#define INBAXIRERRST3 (INB.AXIRERRST3) +#define INBAXIRERRCLR0 (INB.AXIRERRCLR0) +#define INBAXIRERRCLR1 (INB.AXIRERRCLR1) +#define INBAXIRERRCLR2 (INB.AXIRERRCLR2) +#define INBAXIRERRCLR3 (INB.AXIRERRCLR3) + +#define INB_AXIBUSCTLn_COUNT (11) +#define INB_AXIRERRCTLn_COUNT (4) +#define INB_AXIRERRSTn_COUNT (4) +#define INB_AXIRERRCLRn_COUNT (4) + + +typedef struct st_inb +{ + /* INB */ volatile uint32_t RMPR; /* RMPR */ -#define INB_AXIBUSCTLn_COUNT 11 + +/* #define INB_AXIBUSCTLn_COUNT (11) */ volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */ volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */ volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */ @@ -44,49 +84,29 @@ struct st_inb volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */ volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */ volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */ -#define INB_AXIRERRCTLn_COUNT 4 + +/* #define INB_AXIRERRCTLn_COUNT (4) */ volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */ volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */ volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */ volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */ -#define INB_AXIRERRSTn_COUNT 4 + +/* #define INB_AXIRERRSTn_COUNT (4) */ volatile uint32_t AXIRERRST0; /* AXIRERRST0 */ volatile uint32_t AXIRERRST1; /* AXIRERRST1 */ volatile uint32_t AXIRERRST2; /* AXIRERRST2 */ volatile uint32_t AXIRERRST3; /* AXIRERRST3 */ -#define INB_AXIRERRCLRn_COUNT 4 + +/* #define INB_AXIRERRCLRn_COUNT (4) */ volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */ volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */ volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */ volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */ -}; +} r_io_inb_t; -#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */ - - -#define INBRMPR INB.RMPR -#define INBAXIBUSCTL0 INB.AXIBUSCTL0 -#define INBAXIBUSCTL1 INB.AXIBUSCTL1 -#define INBAXIBUSCTL2 INB.AXIBUSCTL2 -#define INBAXIBUSCTL3 INB.AXIBUSCTL3 -#define INBAXIBUSCTL4 INB.AXIBUSCTL4 -#define INBAXIBUSCTL5 INB.AXIBUSCTL5 -#define INBAXIBUSCTL6 INB.AXIBUSCTL6 -#define INBAXIBUSCTL7 INB.AXIBUSCTL7 -#define INBAXIBUSCTL8 INB.AXIBUSCTL8 -#define INBAXIBUSCTL9 INB.AXIBUSCTL9 -#define INBAXIBUSCTL10 INB.AXIBUSCTL10 -#define INBAXIRERRCTL0 INB.AXIRERRCTL0 -#define INBAXIRERRCTL1 INB.AXIRERRCTL1 -#define INBAXIRERRCTL2 INB.AXIRERRCTL2 -#define INBAXIRERRCTL3 INB.AXIRERRCTL3 -#define INBAXIRERRST0 INB.AXIRERRST0 -#define INBAXIRERRST1 INB.AXIRERRST1 -#define INBAXIRERRST2 INB.AXIRERRST2 -#define INBAXIRERRST3 INB.AXIRERRST3 -#define INBAXIRERRCLR0 INB.AXIRERRCLR0 -#define INBAXIRERRCLR1 INB.AXIRERRCLR1 -#define INBAXIRERRCLR2 INB.AXIRERRCLR2 -#define INBAXIRERRCLR3 INB.AXIRERRCLR3 +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h index 253d4b9399..6ee9ea1bab 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h @@ -18,26 +18,525 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : intc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef INTC_IODEFINE_H #define INTC_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_intc -{ /* INTC */ +#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ + + +#define INTCICDDCR (INTC.ICDDCR) +#define INTCICDICTR (INTC.ICDICTR) +#define INTCICDIIDR (INTC.ICDIIDR) +#define INTCICDISR0 (INTC.ICDISR0) +#define INTCICDISR1 (INTC.ICDISR1) +#define INTCICDISR2 (INTC.ICDISR2) +#define INTCICDISR3 (INTC.ICDISR3) +#define INTCICDISR4 (INTC.ICDISR4) +#define INTCICDISR5 (INTC.ICDISR5) +#define INTCICDISR6 (INTC.ICDISR6) +#define INTCICDISR7 (INTC.ICDISR7) +#define INTCICDISR8 (INTC.ICDISR8) +#define INTCICDISR9 (INTC.ICDISR9) +#define INTCICDISR10 (INTC.ICDISR10) +#define INTCICDISR11 (INTC.ICDISR11) +#define INTCICDISR12 (INTC.ICDISR12) +#define INTCICDISR13 (INTC.ICDISR13) +#define INTCICDISR14 (INTC.ICDISR14) +#define INTCICDISR15 (INTC.ICDISR15) +#define INTCICDISR16 (INTC.ICDISR16) +#define INTCICDISR17 (INTC.ICDISR17) +#define INTCICDISR18 (INTC.ICDISR18) +#define INTCICDISER0 (INTC.ICDISER0) +#define INTCICDISER1 (INTC.ICDISER1) +#define INTCICDISER2 (INTC.ICDISER2) +#define INTCICDISER3 (INTC.ICDISER3) +#define INTCICDISER4 (INTC.ICDISER4) +#define INTCICDISER5 (INTC.ICDISER5) +#define INTCICDISER6 (INTC.ICDISER6) +#define INTCICDISER7 (INTC.ICDISER7) +#define INTCICDISER8 (INTC.ICDISER8) +#define INTCICDISER9 (INTC.ICDISER9) +#define INTCICDISER10 (INTC.ICDISER10) +#define INTCICDISER11 (INTC.ICDISER11) +#define INTCICDISER12 (INTC.ICDISER12) +#define INTCICDISER13 (INTC.ICDISER13) +#define INTCICDISER14 (INTC.ICDISER14) +#define INTCICDISER15 (INTC.ICDISER15) +#define INTCICDISER16 (INTC.ICDISER16) +#define INTCICDISER17 (INTC.ICDISER17) +#define INTCICDISER18 (INTC.ICDISER18) +#define INTCICDICER0 (INTC.ICDICER0) +#define INTCICDICER1 (INTC.ICDICER1) +#define INTCICDICER2 (INTC.ICDICER2) +#define INTCICDICER3 (INTC.ICDICER3) +#define INTCICDICER4 (INTC.ICDICER4) +#define INTCICDICER5 (INTC.ICDICER5) +#define INTCICDICER6 (INTC.ICDICER6) +#define INTCICDICER7 (INTC.ICDICER7) +#define INTCICDICER8 (INTC.ICDICER8) +#define INTCICDICER9 (INTC.ICDICER9) +#define INTCICDICER10 (INTC.ICDICER10) +#define INTCICDICER11 (INTC.ICDICER11) +#define INTCICDICER12 (INTC.ICDICER12) +#define INTCICDICER13 (INTC.ICDICER13) +#define INTCICDICER14 (INTC.ICDICER14) +#define INTCICDICER15 (INTC.ICDICER15) +#define INTCICDICER16 (INTC.ICDICER16) +#define INTCICDICER17 (INTC.ICDICER17) +#define INTCICDICER18 (INTC.ICDICER18) +#define INTCICDISPR0 (INTC.ICDISPR0) +#define INTCICDISPR1 (INTC.ICDISPR1) +#define INTCICDISPR2 (INTC.ICDISPR2) +#define INTCICDISPR3 (INTC.ICDISPR3) +#define INTCICDISPR4 (INTC.ICDISPR4) +#define INTCICDISPR5 (INTC.ICDISPR5) +#define INTCICDISPR6 (INTC.ICDISPR6) +#define INTCICDISPR7 (INTC.ICDISPR7) +#define INTCICDISPR8 (INTC.ICDISPR8) +#define INTCICDISPR9 (INTC.ICDISPR9) +#define INTCICDISPR10 (INTC.ICDISPR10) +#define INTCICDISPR11 (INTC.ICDISPR11) +#define INTCICDISPR12 (INTC.ICDISPR12) +#define INTCICDISPR13 (INTC.ICDISPR13) +#define INTCICDISPR14 (INTC.ICDISPR14) +#define INTCICDISPR15 (INTC.ICDISPR15) +#define INTCICDISPR16 (INTC.ICDISPR16) +#define INTCICDISPR17 (INTC.ICDISPR17) +#define INTCICDISPR18 (INTC.ICDISPR18) +#define INTCICDICPR0 (INTC.ICDICPR0) +#define INTCICDICPR1 (INTC.ICDICPR1) +#define INTCICDICPR2 (INTC.ICDICPR2) +#define INTCICDICPR3 (INTC.ICDICPR3) +#define INTCICDICPR4 (INTC.ICDICPR4) +#define INTCICDICPR5 (INTC.ICDICPR5) +#define INTCICDICPR6 (INTC.ICDICPR6) +#define INTCICDICPR7 (INTC.ICDICPR7) +#define INTCICDICPR8 (INTC.ICDICPR8) +#define INTCICDICPR9 (INTC.ICDICPR9) +#define INTCICDICPR10 (INTC.ICDICPR10) +#define INTCICDICPR11 (INTC.ICDICPR11) +#define INTCICDICPR12 (INTC.ICDICPR12) +#define INTCICDICPR13 (INTC.ICDICPR13) +#define INTCICDICPR14 (INTC.ICDICPR14) +#define INTCICDICPR15 (INTC.ICDICPR15) +#define INTCICDICPR16 (INTC.ICDICPR16) +#define INTCICDICPR17 (INTC.ICDICPR17) +#define INTCICDICPR18 (INTC.ICDICPR18) +#define INTCICDABR0 (INTC.ICDABR0) +#define INTCICDABR1 (INTC.ICDABR1) +#define INTCICDABR2 (INTC.ICDABR2) +#define INTCICDABR3 (INTC.ICDABR3) +#define INTCICDABR4 (INTC.ICDABR4) +#define INTCICDABR5 (INTC.ICDABR5) +#define INTCICDABR6 (INTC.ICDABR6) +#define INTCICDABR7 (INTC.ICDABR7) +#define INTCICDABR8 (INTC.ICDABR8) +#define INTCICDABR9 (INTC.ICDABR9) +#define INTCICDABR10 (INTC.ICDABR10) +#define INTCICDABR11 (INTC.ICDABR11) +#define INTCICDABR12 (INTC.ICDABR12) +#define INTCICDABR13 (INTC.ICDABR13) +#define INTCICDABR14 (INTC.ICDABR14) +#define INTCICDABR15 (INTC.ICDABR15) +#define INTCICDABR16 (INTC.ICDABR16) +#define INTCICDABR17 (INTC.ICDABR17) +#define INTCICDABR18 (INTC.ICDABR18) +#define INTCICDIPR0 (INTC.ICDIPR0) +#define INTCICDIPR1 (INTC.ICDIPR1) +#define INTCICDIPR2 (INTC.ICDIPR2) +#define INTCICDIPR3 (INTC.ICDIPR3) +#define INTCICDIPR4 (INTC.ICDIPR4) +#define INTCICDIPR5 (INTC.ICDIPR5) +#define INTCICDIPR6 (INTC.ICDIPR6) +#define INTCICDIPR7 (INTC.ICDIPR7) +#define INTCICDIPR8 (INTC.ICDIPR8) +#define INTCICDIPR9 (INTC.ICDIPR9) +#define INTCICDIPR10 (INTC.ICDIPR10) +#define INTCICDIPR11 (INTC.ICDIPR11) +#define INTCICDIPR12 (INTC.ICDIPR12) +#define INTCICDIPR13 (INTC.ICDIPR13) +#define INTCICDIPR14 (INTC.ICDIPR14) +#define INTCICDIPR15 (INTC.ICDIPR15) +#define INTCICDIPR16 (INTC.ICDIPR16) +#define INTCICDIPR17 (INTC.ICDIPR17) +#define INTCICDIPR18 (INTC.ICDIPR18) +#define INTCICDIPR19 (INTC.ICDIPR19) +#define INTCICDIPR20 (INTC.ICDIPR20) +#define INTCICDIPR21 (INTC.ICDIPR21) +#define INTCICDIPR22 (INTC.ICDIPR22) +#define INTCICDIPR23 (INTC.ICDIPR23) +#define INTCICDIPR24 (INTC.ICDIPR24) +#define INTCICDIPR25 (INTC.ICDIPR25) +#define INTCICDIPR26 (INTC.ICDIPR26) +#define INTCICDIPR27 (INTC.ICDIPR27) +#define INTCICDIPR28 (INTC.ICDIPR28) +#define INTCICDIPR29 (INTC.ICDIPR29) +#define INTCICDIPR30 (INTC.ICDIPR30) +#define INTCICDIPR31 (INTC.ICDIPR31) +#define INTCICDIPR32 (INTC.ICDIPR32) +#define INTCICDIPR33 (INTC.ICDIPR33) +#define INTCICDIPR34 (INTC.ICDIPR34) +#define INTCICDIPR35 (INTC.ICDIPR35) +#define INTCICDIPR36 (INTC.ICDIPR36) +#define INTCICDIPR37 (INTC.ICDIPR37) +#define INTCICDIPR38 (INTC.ICDIPR38) +#define INTCICDIPR39 (INTC.ICDIPR39) +#define INTCICDIPR40 (INTC.ICDIPR40) +#define INTCICDIPR41 (INTC.ICDIPR41) +#define INTCICDIPR42 (INTC.ICDIPR42) +#define INTCICDIPR43 (INTC.ICDIPR43) +#define INTCICDIPR44 (INTC.ICDIPR44) +#define INTCICDIPR45 (INTC.ICDIPR45) +#define INTCICDIPR46 (INTC.ICDIPR46) +#define INTCICDIPR47 (INTC.ICDIPR47) +#define INTCICDIPR48 (INTC.ICDIPR48) +#define INTCICDIPR49 (INTC.ICDIPR49) +#define INTCICDIPR50 (INTC.ICDIPR50) +#define INTCICDIPR51 (INTC.ICDIPR51) +#define INTCICDIPR52 (INTC.ICDIPR52) +#define INTCICDIPR53 (INTC.ICDIPR53) +#define INTCICDIPR54 (INTC.ICDIPR54) +#define INTCICDIPR55 (INTC.ICDIPR55) +#define INTCICDIPR56 (INTC.ICDIPR56) +#define INTCICDIPR57 (INTC.ICDIPR57) +#define INTCICDIPR58 (INTC.ICDIPR58) +#define INTCICDIPR59 (INTC.ICDIPR59) +#define INTCICDIPR60 (INTC.ICDIPR60) +#define INTCICDIPR61 (INTC.ICDIPR61) +#define INTCICDIPR62 (INTC.ICDIPR62) +#define INTCICDIPR63 (INTC.ICDIPR63) +#define INTCICDIPR64 (INTC.ICDIPR64) +#define INTCICDIPR65 (INTC.ICDIPR65) +#define INTCICDIPR66 (INTC.ICDIPR66) +#define INTCICDIPR67 (INTC.ICDIPR67) +#define INTCICDIPR68 (INTC.ICDIPR68) +#define INTCICDIPR69 (INTC.ICDIPR69) +#define INTCICDIPR70 (INTC.ICDIPR70) +#define INTCICDIPR71 (INTC.ICDIPR71) +#define INTCICDIPR72 (INTC.ICDIPR72) +#define INTCICDIPR73 (INTC.ICDIPR73) +#define INTCICDIPR74 (INTC.ICDIPR74) +#define INTCICDIPR75 (INTC.ICDIPR75) +#define INTCICDIPR76 (INTC.ICDIPR76) +#define INTCICDIPR77 (INTC.ICDIPR77) +#define INTCICDIPR78 (INTC.ICDIPR78) +#define INTCICDIPR79 (INTC.ICDIPR79) +#define INTCICDIPR80 (INTC.ICDIPR80) +#define INTCICDIPR81 (INTC.ICDIPR81) +#define INTCICDIPR82 (INTC.ICDIPR82) +#define INTCICDIPR83 (INTC.ICDIPR83) +#define INTCICDIPR84 (INTC.ICDIPR84) +#define INTCICDIPR85 (INTC.ICDIPR85) +#define INTCICDIPR86 (INTC.ICDIPR86) +#define INTCICDIPR87 (INTC.ICDIPR87) +#define INTCICDIPR88 (INTC.ICDIPR88) +#define INTCICDIPR89 (INTC.ICDIPR89) +#define INTCICDIPR90 (INTC.ICDIPR90) +#define INTCICDIPR91 (INTC.ICDIPR91) +#define INTCICDIPR92 (INTC.ICDIPR92) +#define INTCICDIPR93 (INTC.ICDIPR93) +#define INTCICDIPR94 (INTC.ICDIPR94) +#define INTCICDIPR95 (INTC.ICDIPR95) +#define INTCICDIPR96 (INTC.ICDIPR96) +#define INTCICDIPR97 (INTC.ICDIPR97) +#define INTCICDIPR98 (INTC.ICDIPR98) +#define INTCICDIPR99 (INTC.ICDIPR99) +#define INTCICDIPR100 (INTC.ICDIPR100) +#define INTCICDIPR101 (INTC.ICDIPR101) +#define INTCICDIPR102 (INTC.ICDIPR102) +#define INTCICDIPR103 (INTC.ICDIPR103) +#define INTCICDIPR104 (INTC.ICDIPR104) +#define INTCICDIPR105 (INTC.ICDIPR105) +#define INTCICDIPR106 (INTC.ICDIPR106) +#define INTCICDIPR107 (INTC.ICDIPR107) +#define INTCICDIPR108 (INTC.ICDIPR108) +#define INTCICDIPR109 (INTC.ICDIPR109) +#define INTCICDIPR110 (INTC.ICDIPR110) +#define INTCICDIPR111 (INTC.ICDIPR111) +#define INTCICDIPR112 (INTC.ICDIPR112) +#define INTCICDIPR113 (INTC.ICDIPR113) +#define INTCICDIPR114 (INTC.ICDIPR114) +#define INTCICDIPR115 (INTC.ICDIPR115) +#define INTCICDIPR116 (INTC.ICDIPR116) +#define INTCICDIPR117 (INTC.ICDIPR117) +#define INTCICDIPR118 (INTC.ICDIPR118) +#define INTCICDIPR119 (INTC.ICDIPR119) +#define INTCICDIPR120 (INTC.ICDIPR120) +#define INTCICDIPR121 (INTC.ICDIPR121) +#define INTCICDIPR122 (INTC.ICDIPR122) +#define INTCICDIPR123 (INTC.ICDIPR123) +#define INTCICDIPR124 (INTC.ICDIPR124) +#define INTCICDIPR125 (INTC.ICDIPR125) +#define INTCICDIPR126 (INTC.ICDIPR126) +#define INTCICDIPR127 (INTC.ICDIPR127) +#define INTCICDIPR128 (INTC.ICDIPR128) +#define INTCICDIPR129 (INTC.ICDIPR129) +#define INTCICDIPR130 (INTC.ICDIPR130) +#define INTCICDIPR131 (INTC.ICDIPR131) +#define INTCICDIPR132 (INTC.ICDIPR132) +#define INTCICDIPR133 (INTC.ICDIPR133) +#define INTCICDIPR134 (INTC.ICDIPR134) +#define INTCICDIPR135 (INTC.ICDIPR135) +#define INTCICDIPR136 (INTC.ICDIPR136) +#define INTCICDIPR137 (INTC.ICDIPR137) +#define INTCICDIPR138 (INTC.ICDIPR138) +#define INTCICDIPR139 (INTC.ICDIPR139) +#define INTCICDIPR140 (INTC.ICDIPR140) +#define INTCICDIPR141 (INTC.ICDIPR141) +#define INTCICDIPR142 (INTC.ICDIPR142) +#define INTCICDIPR143 (INTC.ICDIPR143) +#define INTCICDIPR144 (INTC.ICDIPR144) +#define INTCICDIPR145 (INTC.ICDIPR145) +#define INTCICDIPR146 (INTC.ICDIPR146) +#define INTCICDIPTR0 (INTC.ICDIPTR0) +#define INTCICDIPTR1 (INTC.ICDIPTR1) +#define INTCICDIPTR2 (INTC.ICDIPTR2) +#define INTCICDIPTR3 (INTC.ICDIPTR3) +#define INTCICDIPTR4 (INTC.ICDIPTR4) +#define INTCICDIPTR5 (INTC.ICDIPTR5) +#define INTCICDIPTR6 (INTC.ICDIPTR6) +#define INTCICDIPTR7 (INTC.ICDIPTR7) +#define INTCICDIPTR8 (INTC.ICDIPTR8) +#define INTCICDIPTR9 (INTC.ICDIPTR9) +#define INTCICDIPTR10 (INTC.ICDIPTR10) +#define INTCICDIPTR11 (INTC.ICDIPTR11) +#define INTCICDIPTR12 (INTC.ICDIPTR12) +#define INTCICDIPTR13 (INTC.ICDIPTR13) +#define INTCICDIPTR14 (INTC.ICDIPTR14) +#define INTCICDIPTR15 (INTC.ICDIPTR15) +#define INTCICDIPTR16 (INTC.ICDIPTR16) +#define INTCICDIPTR17 (INTC.ICDIPTR17) +#define INTCICDIPTR18 (INTC.ICDIPTR18) +#define INTCICDIPTR19 (INTC.ICDIPTR19) +#define INTCICDIPTR20 (INTC.ICDIPTR20) +#define INTCICDIPTR21 (INTC.ICDIPTR21) +#define INTCICDIPTR22 (INTC.ICDIPTR22) +#define INTCICDIPTR23 (INTC.ICDIPTR23) +#define INTCICDIPTR24 (INTC.ICDIPTR24) +#define INTCICDIPTR25 (INTC.ICDIPTR25) +#define INTCICDIPTR26 (INTC.ICDIPTR26) +#define INTCICDIPTR27 (INTC.ICDIPTR27) +#define INTCICDIPTR28 (INTC.ICDIPTR28) +#define INTCICDIPTR29 (INTC.ICDIPTR29) +#define INTCICDIPTR30 (INTC.ICDIPTR30) +#define INTCICDIPTR31 (INTC.ICDIPTR31) +#define INTCICDIPTR32 (INTC.ICDIPTR32) +#define INTCICDIPTR33 (INTC.ICDIPTR33) +#define INTCICDIPTR34 (INTC.ICDIPTR34) +#define INTCICDIPTR35 (INTC.ICDIPTR35) +#define INTCICDIPTR36 (INTC.ICDIPTR36) +#define INTCICDIPTR37 (INTC.ICDIPTR37) +#define INTCICDIPTR38 (INTC.ICDIPTR38) +#define INTCICDIPTR39 (INTC.ICDIPTR39) +#define INTCICDIPTR40 (INTC.ICDIPTR40) +#define INTCICDIPTR41 (INTC.ICDIPTR41) +#define INTCICDIPTR42 (INTC.ICDIPTR42) +#define INTCICDIPTR43 (INTC.ICDIPTR43) +#define INTCICDIPTR44 (INTC.ICDIPTR44) +#define INTCICDIPTR45 (INTC.ICDIPTR45) +#define INTCICDIPTR46 (INTC.ICDIPTR46) +#define INTCICDIPTR47 (INTC.ICDIPTR47) +#define INTCICDIPTR48 (INTC.ICDIPTR48) +#define INTCICDIPTR49 (INTC.ICDIPTR49) +#define INTCICDIPTR50 (INTC.ICDIPTR50) +#define INTCICDIPTR51 (INTC.ICDIPTR51) +#define INTCICDIPTR52 (INTC.ICDIPTR52) +#define INTCICDIPTR53 (INTC.ICDIPTR53) +#define INTCICDIPTR54 (INTC.ICDIPTR54) +#define INTCICDIPTR55 (INTC.ICDIPTR55) +#define INTCICDIPTR56 (INTC.ICDIPTR56) +#define INTCICDIPTR57 (INTC.ICDIPTR57) +#define INTCICDIPTR58 (INTC.ICDIPTR58) +#define INTCICDIPTR59 (INTC.ICDIPTR59) +#define INTCICDIPTR60 (INTC.ICDIPTR60) +#define INTCICDIPTR61 (INTC.ICDIPTR61) +#define INTCICDIPTR62 (INTC.ICDIPTR62) +#define INTCICDIPTR63 (INTC.ICDIPTR63) +#define INTCICDIPTR64 (INTC.ICDIPTR64) +#define INTCICDIPTR65 (INTC.ICDIPTR65) +#define INTCICDIPTR66 (INTC.ICDIPTR66) +#define INTCICDIPTR67 (INTC.ICDIPTR67) +#define INTCICDIPTR68 (INTC.ICDIPTR68) +#define INTCICDIPTR69 (INTC.ICDIPTR69) +#define INTCICDIPTR70 (INTC.ICDIPTR70) +#define INTCICDIPTR71 (INTC.ICDIPTR71) +#define INTCICDIPTR72 (INTC.ICDIPTR72) +#define INTCICDIPTR73 (INTC.ICDIPTR73) +#define INTCICDIPTR74 (INTC.ICDIPTR74) +#define INTCICDIPTR75 (INTC.ICDIPTR75) +#define INTCICDIPTR76 (INTC.ICDIPTR76) +#define INTCICDIPTR77 (INTC.ICDIPTR77) +#define INTCICDIPTR78 (INTC.ICDIPTR78) +#define INTCICDIPTR79 (INTC.ICDIPTR79) +#define INTCICDIPTR80 (INTC.ICDIPTR80) +#define INTCICDIPTR81 (INTC.ICDIPTR81) +#define INTCICDIPTR82 (INTC.ICDIPTR82) +#define INTCICDIPTR83 (INTC.ICDIPTR83) +#define INTCICDIPTR84 (INTC.ICDIPTR84) +#define INTCICDIPTR85 (INTC.ICDIPTR85) +#define INTCICDIPTR86 (INTC.ICDIPTR86) +#define INTCICDIPTR87 (INTC.ICDIPTR87) +#define INTCICDIPTR88 (INTC.ICDIPTR88) +#define INTCICDIPTR89 (INTC.ICDIPTR89) +#define INTCICDIPTR90 (INTC.ICDIPTR90) +#define INTCICDIPTR91 (INTC.ICDIPTR91) +#define INTCICDIPTR92 (INTC.ICDIPTR92) +#define INTCICDIPTR93 (INTC.ICDIPTR93) +#define INTCICDIPTR94 (INTC.ICDIPTR94) +#define INTCICDIPTR95 (INTC.ICDIPTR95) +#define INTCICDIPTR96 (INTC.ICDIPTR96) +#define INTCICDIPTR97 (INTC.ICDIPTR97) +#define INTCICDIPTR98 (INTC.ICDIPTR98) +#define INTCICDIPTR99 (INTC.ICDIPTR99) +#define INTCICDIPTR100 (INTC.ICDIPTR100) +#define INTCICDIPTR101 (INTC.ICDIPTR101) +#define INTCICDIPTR102 (INTC.ICDIPTR102) +#define INTCICDIPTR103 (INTC.ICDIPTR103) +#define INTCICDIPTR104 (INTC.ICDIPTR104) +#define INTCICDIPTR105 (INTC.ICDIPTR105) +#define INTCICDIPTR106 (INTC.ICDIPTR106) +#define INTCICDIPTR107 (INTC.ICDIPTR107) +#define INTCICDIPTR108 (INTC.ICDIPTR108) +#define INTCICDIPTR109 (INTC.ICDIPTR109) +#define INTCICDIPTR110 (INTC.ICDIPTR110) +#define INTCICDIPTR111 (INTC.ICDIPTR111) +#define INTCICDIPTR112 (INTC.ICDIPTR112) +#define INTCICDIPTR113 (INTC.ICDIPTR113) +#define INTCICDIPTR114 (INTC.ICDIPTR114) +#define INTCICDIPTR115 (INTC.ICDIPTR115) +#define INTCICDIPTR116 (INTC.ICDIPTR116) +#define INTCICDIPTR117 (INTC.ICDIPTR117) +#define INTCICDIPTR118 (INTC.ICDIPTR118) +#define INTCICDIPTR119 (INTC.ICDIPTR119) +#define INTCICDIPTR120 (INTC.ICDIPTR120) +#define INTCICDIPTR121 (INTC.ICDIPTR121) +#define INTCICDIPTR122 (INTC.ICDIPTR122) +#define INTCICDIPTR123 (INTC.ICDIPTR123) +#define INTCICDIPTR124 (INTC.ICDIPTR124) +#define INTCICDIPTR125 (INTC.ICDIPTR125) +#define INTCICDIPTR126 (INTC.ICDIPTR126) +#define INTCICDIPTR127 (INTC.ICDIPTR127) +#define INTCICDIPTR128 (INTC.ICDIPTR128) +#define INTCICDIPTR129 (INTC.ICDIPTR129) +#define INTCICDIPTR130 (INTC.ICDIPTR130) +#define INTCICDIPTR131 (INTC.ICDIPTR131) +#define INTCICDIPTR132 (INTC.ICDIPTR132) +#define INTCICDIPTR133 (INTC.ICDIPTR133) +#define INTCICDIPTR134 (INTC.ICDIPTR134) +#define INTCICDIPTR135 (INTC.ICDIPTR135) +#define INTCICDIPTR136 (INTC.ICDIPTR136) +#define INTCICDIPTR137 (INTC.ICDIPTR137) +#define INTCICDIPTR138 (INTC.ICDIPTR138) +#define INTCICDIPTR139 (INTC.ICDIPTR139) +#define INTCICDIPTR140 (INTC.ICDIPTR140) +#define INTCICDIPTR141 (INTC.ICDIPTR141) +#define INTCICDIPTR142 (INTC.ICDIPTR142) +#define INTCICDIPTR143 (INTC.ICDIPTR143) +#define INTCICDIPTR144 (INTC.ICDIPTR144) +#define INTCICDIPTR145 (INTC.ICDIPTR145) +#define INTCICDIPTR146 (INTC.ICDIPTR146) +#define INTCICDICFR0 (INTC.ICDICFR0) +#define INTCICDICFR1 (INTC.ICDICFR1) +#define INTCICDICFR2 (INTC.ICDICFR2) +#define INTCICDICFR3 (INTC.ICDICFR3) +#define INTCICDICFR4 (INTC.ICDICFR4) +#define INTCICDICFR5 (INTC.ICDICFR5) +#define INTCICDICFR6 (INTC.ICDICFR6) +#define INTCICDICFR7 (INTC.ICDICFR7) +#define INTCICDICFR8 (INTC.ICDICFR8) +#define INTCICDICFR9 (INTC.ICDICFR9) +#define INTCICDICFR10 (INTC.ICDICFR10) +#define INTCICDICFR11 (INTC.ICDICFR11) +#define INTCICDICFR12 (INTC.ICDICFR12) +#define INTCICDICFR13 (INTC.ICDICFR13) +#define INTCICDICFR14 (INTC.ICDICFR14) +#define INTCICDICFR15 (INTC.ICDICFR15) +#define INTCICDICFR16 (INTC.ICDICFR16) +#define INTCICDICFR17 (INTC.ICDICFR17) +#define INTCICDICFR18 (INTC.ICDICFR18) +#define INTCICDICFR19 (INTC.ICDICFR19) +#define INTCICDICFR20 (INTC.ICDICFR20) +#define INTCICDICFR21 (INTC.ICDICFR21) +#define INTCICDICFR22 (INTC.ICDICFR22) +#define INTCICDICFR23 (INTC.ICDICFR23) +#define INTCICDICFR24 (INTC.ICDICFR24) +#define INTCICDICFR25 (INTC.ICDICFR25) +#define INTCICDICFR26 (INTC.ICDICFR26) +#define INTCICDICFR27 (INTC.ICDICFR27) +#define INTCICDICFR28 (INTC.ICDICFR28) +#define INTCICDICFR29 (INTC.ICDICFR29) +#define INTCICDICFR30 (INTC.ICDICFR30) +#define INTCICDICFR31 (INTC.ICDICFR31) +#define INTCICDICFR32 (INTC.ICDICFR32) +#define INTCICDICFR33 (INTC.ICDICFR33) +#define INTCICDICFR34 (INTC.ICDICFR34) +#define INTCICDICFR35 (INTC.ICDICFR35) +#define INTCICDICFR36 (INTC.ICDICFR36) +#define INTCPPI_STATUS (INTC.PPI_STATUS) +#define INTCSPI_STATUS0 (INTC.SPI_STATUS0) +#define INTCSPI_STATUS1 (INTC.SPI_STATUS1) +#define INTCSPI_STATUS2 (INTC.SPI_STATUS2) +#define INTCSPI_STATUS3 (INTC.SPI_STATUS3) +#define INTCSPI_STATUS4 (INTC.SPI_STATUS4) +#define INTCSPI_STATUS5 (INTC.SPI_STATUS5) +#define INTCSPI_STATUS6 (INTC.SPI_STATUS6) +#define INTCSPI_STATUS7 (INTC.SPI_STATUS7) +#define INTCSPI_STATUS8 (INTC.SPI_STATUS8) +#define INTCSPI_STATUS9 (INTC.SPI_STATUS9) +#define INTCSPI_STATUS10 (INTC.SPI_STATUS10) +#define INTCSPI_STATUS11 (INTC.SPI_STATUS11) +#define INTCSPI_STATUS12 (INTC.SPI_STATUS12) +#define INTCSPI_STATUS13 (INTC.SPI_STATUS13) +#define INTCSPI_STATUS14 (INTC.SPI_STATUS14) +#define INTCSPI_STATUS15 (INTC.SPI_STATUS15) +#define INTCSPI_STATUS16 (INTC.SPI_STATUS16) +#define INTCICDSGIR (INTC.ICDSGIR) +#define INTCICCICR (INTC.ICCICR) +#define INTCICCPMR (INTC.ICCPMR) +#define INTCICCBPR (INTC.ICCBPR) +#define INTCICCIAR (INTC.ICCIAR) +#define INTCICCEOIR (INTC.ICCEOIR) +#define INTCICCRPR (INTC.ICCRPR) +#define INTCICCHPIR (INTC.ICCHPIR) +#define INTCICCABPR (INTC.ICCABPR) +#define INTCICCIIDR (INTC.ICCIIDR) +#define INTCICR0 (INTC.ICR0) +#define INTCICR1 (INTC.ICR1) +#define INTCIRQRR (INTC.IRQRR) + +#define INTC_ICDISR0_COUNT (19) +#define INTC_ICDISER0_COUNT (19) +#define INTC_ICDICER0_COUNT (19) +#define INTC_ICDISPR0_COUNT (19) +#define INTC_ICDICPR0_COUNT (19) +#define INTC_ICDABR0_COUNT (19) +#define INTC_ICDIPR0_COUNT (147) +#define INTC_ICDIPTR0_COUNT (147) +#define INTC_ICDICFR0_COUNT (37) +#define INTC_SPI_STATUS0_COUNT (17) + + +typedef struct st_intc +{ + /* INTC */ volatile uint32_t ICDDCR; /* ICDDCR */ volatile uint32_t ICDICTR; /* ICDICTR */ volatile uint32_t ICDIIDR; /* ICDIIDR */ volatile uint8_t dummy193[116]; /* */ -#define INTC_ICDISR0_COUNT 19 + +/* #define INTC_ICDISR0_COUNT (19) */ volatile uint32_t ICDISR0; /* ICDISR0 */ volatile uint32_t ICDISR1; /* ICDISR1 */ volatile uint32_t ICDISR2; /* ICDISR2 */ @@ -58,7 +557,8 @@ struct st_intc volatile uint32_t ICDISR17; /* ICDISR17 */ volatile uint32_t ICDISR18; /* ICDISR18 */ volatile uint8_t dummy194[52]; /* */ -#define INTC_ICDISER0_COUNT 19 + +/* #define INTC_ICDISER0_COUNT (19) */ volatile uint32_t ICDISER0; /* ICDISER0 */ volatile uint32_t ICDISER1; /* ICDISER1 */ volatile uint32_t ICDISER2; /* ICDISER2 */ @@ -79,7 +579,8 @@ struct st_intc volatile uint32_t ICDISER17; /* ICDISER17 */ volatile uint32_t ICDISER18; /* ICDISER18 */ volatile uint8_t dummy195[52]; /* */ -#define INTC_ICDICER0_COUNT 19 + +/* #define INTC_ICDICER0_COUNT (19) */ volatile uint32_t ICDICER0; /* ICDICER0 */ volatile uint32_t ICDICER1; /* ICDICER1 */ volatile uint32_t ICDICER2; /* ICDICER2 */ @@ -100,7 +601,8 @@ struct st_intc volatile uint32_t ICDICER17; /* ICDICER17 */ volatile uint32_t ICDICER18; /* ICDICER18 */ volatile uint8_t dummy196[52]; /* */ -#define INTC_ICDISPR0_COUNT 19 + +/* #define INTC_ICDISPR0_COUNT (19) */ volatile uint32_t ICDISPR0; /* ICDISPR0 */ volatile uint32_t ICDISPR1; /* ICDISPR1 */ volatile uint32_t ICDISPR2; /* ICDISPR2 */ @@ -121,7 +623,8 @@ struct st_intc volatile uint32_t ICDISPR17; /* ICDISPR17 */ volatile uint32_t ICDISPR18; /* ICDISPR18 */ volatile uint8_t dummy197[52]; /* */ -#define INTC_ICDICPR0_COUNT 19 + +/* #define INTC_ICDICPR0_COUNT (19) */ volatile uint32_t ICDICPR0; /* ICDICPR0 */ volatile uint32_t ICDICPR1; /* ICDICPR1 */ volatile uint32_t ICDICPR2; /* ICDICPR2 */ @@ -142,7 +645,8 @@ struct st_intc volatile uint32_t ICDICPR17; /* ICDICPR17 */ volatile uint32_t ICDICPR18; /* ICDICPR18 */ volatile uint8_t dummy198[52]; /* */ -#define INTC_ICDABR0_COUNT 19 + +/* #define INTC_ICDABR0_COUNT (19) */ volatile uint32_t ICDABR0; /* ICDABR0 */ volatile uint32_t ICDABR1; /* ICDABR1 */ volatile uint32_t ICDABR2; /* ICDABR2 */ @@ -163,7 +667,8 @@ struct st_intc volatile uint32_t ICDABR17; /* ICDABR17 */ volatile uint32_t ICDABR18; /* ICDABR18 */ volatile uint8_t dummy199[180]; /* */ -#define INTC_ICDIPR0_COUNT 147 + +/* #define INTC_ICDIPR0_COUNT (147) */ volatile uint32_t ICDIPR0; /* ICDIPR0 */ volatile uint32_t ICDIPR1; /* ICDIPR1 */ volatile uint32_t ICDIPR2; /* ICDIPR2 */ @@ -312,7 +817,8 @@ struct st_intc volatile uint32_t ICDIPR145; /* ICDIPR145 */ volatile uint32_t ICDIPR146; /* ICDIPR146 */ volatile uint8_t dummy200[436]; /* */ -#define INTC_ICDIPTR0_COUNT 147 + +/* #define INTC_ICDIPTR0_COUNT (147) */ volatile uint32_t ICDIPTR0; /* ICDIPTR0 */ volatile uint32_t ICDIPTR1; /* ICDIPTR1 */ volatile uint32_t ICDIPTR2; /* ICDIPTR2 */ @@ -461,7 +967,8 @@ struct st_intc volatile uint32_t ICDIPTR145; /* ICDIPTR145 */ volatile uint32_t ICDIPTR146; /* ICDIPTR146 */ volatile uint8_t dummy201[436]; /* */ -#define INTC_ICDICFR0_COUNT 37 + +/* #define INTC_ICDICFR0_COUNT (37) */ volatile uint32_t ICDICFR0; /* ICDICFR0 */ volatile uint32_t ICDICFR1; /* ICDICFR1 */ volatile uint32_t ICDICFR2; /* ICDICFR2 */ @@ -501,7 +1008,8 @@ struct st_intc volatile uint32_t ICDICFR36; /* ICDICFR36 */ volatile uint8_t dummy202[108]; /* */ volatile uint32_t PPI_STATUS; /* PPI_STATUS */ -#define INTC_SPI_STATUS0_COUNT 17 + +/* #define INTC_SPI_STATUS0_COUNT (17) */ volatile uint32_t SPI_STATUS0; /* SPI_STATUS0 */ volatile uint32_t SPI_STATUS1; /* SPI_STATUS1 */ volatile uint32_t SPI_STATUS2; /* SPI_STATUS2 */ @@ -536,491 +1044,11 @@ struct st_intc volatile uint16_t ICR0; /* ICR0 */ volatile uint16_t ICR1; /* ICR1 */ volatile uint16_t IRQRR; /* IRQRR */ -}; +} r_io_intc_t; -#define INTC (*(struct st_intc *)0xE8201000uL) /* INTC */ - - -#define INTCICDDCR INTC.ICDDCR -#define INTCICDICTR INTC.ICDICTR -#define INTCICDIIDR INTC.ICDIIDR -#define INTCICDISR0 INTC.ICDISR0 -#define INTCICDISR1 INTC.ICDISR1 -#define INTCICDISR2 INTC.ICDISR2 -#define INTCICDISR3 INTC.ICDISR3 -#define INTCICDISR4 INTC.ICDISR4 -#define INTCICDISR5 INTC.ICDISR5 -#define INTCICDISR6 INTC.ICDISR6 -#define INTCICDISR7 INTC.ICDISR7 -#define INTCICDISR8 INTC.ICDISR8 -#define INTCICDISR9 INTC.ICDISR9 -#define INTCICDISR10 INTC.ICDISR10 -#define INTCICDISR11 INTC.ICDISR11 -#define INTCICDISR12 INTC.ICDISR12 -#define INTCICDISR13 INTC.ICDISR13 -#define INTCICDISR14 INTC.ICDISR14 -#define INTCICDISR15 INTC.ICDISR15 -#define INTCICDISR16 INTC.ICDISR16 -#define INTCICDISR17 INTC.ICDISR17 -#define INTCICDISR18 INTC.ICDISR18 -#define INTCICDISER0 INTC.ICDISER0 -#define INTCICDISER1 INTC.ICDISER1 -#define INTCICDISER2 INTC.ICDISER2 -#define INTCICDISER3 INTC.ICDISER3 -#define INTCICDISER4 INTC.ICDISER4 -#define INTCICDISER5 INTC.ICDISER5 -#define INTCICDISER6 INTC.ICDISER6 -#define INTCICDISER7 INTC.ICDISER7 -#define INTCICDISER8 INTC.ICDISER8 -#define INTCICDISER9 INTC.ICDISER9 -#define INTCICDISER10 INTC.ICDISER10 -#define INTCICDISER11 INTC.ICDISER11 -#define INTCICDISER12 INTC.ICDISER12 -#define INTCICDISER13 INTC.ICDISER13 -#define INTCICDISER14 INTC.ICDISER14 -#define INTCICDISER15 INTC.ICDISER15 -#define INTCICDISER16 INTC.ICDISER16 -#define INTCICDISER17 INTC.ICDISER17 -#define INTCICDISER18 INTC.ICDISER18 -#define INTCICDICER0 INTC.ICDICER0 -#define INTCICDICER1 INTC.ICDICER1 -#define INTCICDICER2 INTC.ICDICER2 -#define INTCICDICER3 INTC.ICDICER3 -#define INTCICDICER4 INTC.ICDICER4 -#define INTCICDICER5 INTC.ICDICER5 -#define INTCICDICER6 INTC.ICDICER6 -#define INTCICDICER7 INTC.ICDICER7 -#define INTCICDICER8 INTC.ICDICER8 -#define INTCICDICER9 INTC.ICDICER9 -#define INTCICDICER10 INTC.ICDICER10 -#define INTCICDICER11 INTC.ICDICER11 -#define INTCICDICER12 INTC.ICDICER12 -#define INTCICDICER13 INTC.ICDICER13 -#define INTCICDICER14 INTC.ICDICER14 -#define INTCICDICER15 INTC.ICDICER15 -#define INTCICDICER16 INTC.ICDICER16 -#define INTCICDICER17 INTC.ICDICER17 -#define INTCICDICER18 INTC.ICDICER18 -#define INTCICDISPR0 INTC.ICDISPR0 -#define INTCICDISPR1 INTC.ICDISPR1 -#define INTCICDISPR2 INTC.ICDISPR2 -#define INTCICDISPR3 INTC.ICDISPR3 -#define INTCICDISPR4 INTC.ICDISPR4 -#define INTCICDISPR5 INTC.ICDISPR5 -#define INTCICDISPR6 INTC.ICDISPR6 -#define INTCICDISPR7 INTC.ICDISPR7 -#define INTCICDISPR8 INTC.ICDISPR8 -#define INTCICDISPR9 INTC.ICDISPR9 -#define INTCICDISPR10 INTC.ICDISPR10 -#define INTCICDISPR11 INTC.ICDISPR11 -#define INTCICDISPR12 INTC.ICDISPR12 -#define INTCICDISPR13 INTC.ICDISPR13 -#define INTCICDISPR14 INTC.ICDISPR14 -#define INTCICDISPR15 INTC.ICDISPR15 -#define INTCICDISPR16 INTC.ICDISPR16 -#define INTCICDISPR17 INTC.ICDISPR17 -#define INTCICDISPR18 INTC.ICDISPR18 -#define INTCICDICPR0 INTC.ICDICPR0 -#define INTCICDICPR1 INTC.ICDICPR1 -#define INTCICDICPR2 INTC.ICDICPR2 -#define INTCICDICPR3 INTC.ICDICPR3 -#define INTCICDICPR4 INTC.ICDICPR4 -#define INTCICDICPR5 INTC.ICDICPR5 -#define INTCICDICPR6 INTC.ICDICPR6 -#define INTCICDICPR7 INTC.ICDICPR7 -#define INTCICDICPR8 INTC.ICDICPR8 -#define INTCICDICPR9 INTC.ICDICPR9 -#define INTCICDICPR10 INTC.ICDICPR10 -#define INTCICDICPR11 INTC.ICDICPR11 -#define INTCICDICPR12 INTC.ICDICPR12 -#define INTCICDICPR13 INTC.ICDICPR13 -#define INTCICDICPR14 INTC.ICDICPR14 -#define INTCICDICPR15 INTC.ICDICPR15 -#define INTCICDICPR16 INTC.ICDICPR16 -#define INTCICDICPR17 INTC.ICDICPR17 -#define INTCICDICPR18 INTC.ICDICPR18 -#define INTCICDABR0 INTC.ICDABR0 -#define INTCICDABR1 INTC.ICDABR1 -#define INTCICDABR2 INTC.ICDABR2 -#define INTCICDABR3 INTC.ICDABR3 -#define INTCICDABR4 INTC.ICDABR4 -#define INTCICDABR5 INTC.ICDABR5 -#define INTCICDABR6 INTC.ICDABR6 -#define INTCICDABR7 INTC.ICDABR7 -#define INTCICDABR8 INTC.ICDABR8 -#define INTCICDABR9 INTC.ICDABR9 -#define INTCICDABR10 INTC.ICDABR10 -#define INTCICDABR11 INTC.ICDABR11 -#define INTCICDABR12 INTC.ICDABR12 -#define INTCICDABR13 INTC.ICDABR13 -#define INTCICDABR14 INTC.ICDABR14 -#define INTCICDABR15 INTC.ICDABR15 -#define INTCICDABR16 INTC.ICDABR16 -#define INTCICDABR17 INTC.ICDABR17 -#define INTCICDABR18 INTC.ICDABR18 -#define INTCICDIPR0 INTC.ICDIPR0 -#define INTCICDIPR1 INTC.ICDIPR1 -#define INTCICDIPR2 INTC.ICDIPR2 -#define INTCICDIPR3 INTC.ICDIPR3 -#define INTCICDIPR4 INTC.ICDIPR4 -#define INTCICDIPR5 INTC.ICDIPR5 -#define INTCICDIPR6 INTC.ICDIPR6 -#define INTCICDIPR7 INTC.ICDIPR7 -#define INTCICDIPR8 INTC.ICDIPR8 -#define INTCICDIPR9 INTC.ICDIPR9 -#define INTCICDIPR10 INTC.ICDIPR10 -#define INTCICDIPR11 INTC.ICDIPR11 -#define INTCICDIPR12 INTC.ICDIPR12 -#define INTCICDIPR13 INTC.ICDIPR13 -#define INTCICDIPR14 INTC.ICDIPR14 -#define INTCICDIPR15 INTC.ICDIPR15 -#define INTCICDIPR16 INTC.ICDIPR16 -#define INTCICDIPR17 INTC.ICDIPR17 -#define INTCICDIPR18 INTC.ICDIPR18 -#define INTCICDIPR19 INTC.ICDIPR19 -#define INTCICDIPR20 INTC.ICDIPR20 -#define INTCICDIPR21 INTC.ICDIPR21 -#define INTCICDIPR22 INTC.ICDIPR22 -#define INTCICDIPR23 INTC.ICDIPR23 -#define INTCICDIPR24 INTC.ICDIPR24 -#define INTCICDIPR25 INTC.ICDIPR25 -#define INTCICDIPR26 INTC.ICDIPR26 -#define INTCICDIPR27 INTC.ICDIPR27 -#define INTCICDIPR28 INTC.ICDIPR28 -#define INTCICDIPR29 INTC.ICDIPR29 -#define INTCICDIPR30 INTC.ICDIPR30 -#define INTCICDIPR31 INTC.ICDIPR31 -#define INTCICDIPR32 INTC.ICDIPR32 -#define INTCICDIPR33 INTC.ICDIPR33 -#define INTCICDIPR34 INTC.ICDIPR34 -#define INTCICDIPR35 INTC.ICDIPR35 -#define INTCICDIPR36 INTC.ICDIPR36 -#define INTCICDIPR37 INTC.ICDIPR37 -#define INTCICDIPR38 INTC.ICDIPR38 -#define INTCICDIPR39 INTC.ICDIPR39 -#define INTCICDIPR40 INTC.ICDIPR40 -#define INTCICDIPR41 INTC.ICDIPR41 -#define INTCICDIPR42 INTC.ICDIPR42 -#define INTCICDIPR43 INTC.ICDIPR43 -#define INTCICDIPR44 INTC.ICDIPR44 -#define INTCICDIPR45 INTC.ICDIPR45 -#define INTCICDIPR46 INTC.ICDIPR46 -#define INTCICDIPR47 INTC.ICDIPR47 -#define INTCICDIPR48 INTC.ICDIPR48 -#define INTCICDIPR49 INTC.ICDIPR49 -#define INTCICDIPR50 INTC.ICDIPR50 -#define INTCICDIPR51 INTC.ICDIPR51 -#define INTCICDIPR52 INTC.ICDIPR52 -#define INTCICDIPR53 INTC.ICDIPR53 -#define INTCICDIPR54 INTC.ICDIPR54 -#define INTCICDIPR55 INTC.ICDIPR55 -#define INTCICDIPR56 INTC.ICDIPR56 -#define INTCICDIPR57 INTC.ICDIPR57 -#define INTCICDIPR58 INTC.ICDIPR58 -#define INTCICDIPR59 INTC.ICDIPR59 -#define INTCICDIPR60 INTC.ICDIPR60 -#define INTCICDIPR61 INTC.ICDIPR61 -#define INTCICDIPR62 INTC.ICDIPR62 -#define INTCICDIPR63 INTC.ICDIPR63 -#define INTCICDIPR64 INTC.ICDIPR64 -#define INTCICDIPR65 INTC.ICDIPR65 -#define INTCICDIPR66 INTC.ICDIPR66 -#define INTCICDIPR67 INTC.ICDIPR67 -#define INTCICDIPR68 INTC.ICDIPR68 -#define INTCICDIPR69 INTC.ICDIPR69 -#define INTCICDIPR70 INTC.ICDIPR70 -#define INTCICDIPR71 INTC.ICDIPR71 -#define INTCICDIPR72 INTC.ICDIPR72 -#define INTCICDIPR73 INTC.ICDIPR73 -#define INTCICDIPR74 INTC.ICDIPR74 -#define INTCICDIPR75 INTC.ICDIPR75 -#define INTCICDIPR76 INTC.ICDIPR76 -#define INTCICDIPR77 INTC.ICDIPR77 -#define INTCICDIPR78 INTC.ICDIPR78 -#define INTCICDIPR79 INTC.ICDIPR79 -#define INTCICDIPR80 INTC.ICDIPR80 -#define INTCICDIPR81 INTC.ICDIPR81 -#define INTCICDIPR82 INTC.ICDIPR82 -#define INTCICDIPR83 INTC.ICDIPR83 -#define INTCICDIPR84 INTC.ICDIPR84 -#define INTCICDIPR85 INTC.ICDIPR85 -#define INTCICDIPR86 INTC.ICDIPR86 -#define INTCICDIPR87 INTC.ICDIPR87 -#define INTCICDIPR88 INTC.ICDIPR88 -#define INTCICDIPR89 INTC.ICDIPR89 -#define INTCICDIPR90 INTC.ICDIPR90 -#define INTCICDIPR91 INTC.ICDIPR91 -#define INTCICDIPR92 INTC.ICDIPR92 -#define INTCICDIPR93 INTC.ICDIPR93 -#define INTCICDIPR94 INTC.ICDIPR94 -#define INTCICDIPR95 INTC.ICDIPR95 -#define INTCICDIPR96 INTC.ICDIPR96 -#define INTCICDIPR97 INTC.ICDIPR97 -#define INTCICDIPR98 INTC.ICDIPR98 -#define INTCICDIPR99 INTC.ICDIPR99 -#define INTCICDIPR100 INTC.ICDIPR100 -#define INTCICDIPR101 INTC.ICDIPR101 -#define INTCICDIPR102 INTC.ICDIPR102 -#define INTCICDIPR103 INTC.ICDIPR103 -#define INTCICDIPR104 INTC.ICDIPR104 -#define INTCICDIPR105 INTC.ICDIPR105 -#define INTCICDIPR106 INTC.ICDIPR106 -#define INTCICDIPR107 INTC.ICDIPR107 -#define INTCICDIPR108 INTC.ICDIPR108 -#define INTCICDIPR109 INTC.ICDIPR109 -#define INTCICDIPR110 INTC.ICDIPR110 -#define INTCICDIPR111 INTC.ICDIPR111 -#define INTCICDIPR112 INTC.ICDIPR112 -#define INTCICDIPR113 INTC.ICDIPR113 -#define INTCICDIPR114 INTC.ICDIPR114 -#define INTCICDIPR115 INTC.ICDIPR115 -#define INTCICDIPR116 INTC.ICDIPR116 -#define INTCICDIPR117 INTC.ICDIPR117 -#define INTCICDIPR118 INTC.ICDIPR118 -#define INTCICDIPR119 INTC.ICDIPR119 -#define INTCICDIPR120 INTC.ICDIPR120 -#define INTCICDIPR121 INTC.ICDIPR121 -#define INTCICDIPR122 INTC.ICDIPR122 -#define INTCICDIPR123 INTC.ICDIPR123 -#define INTCICDIPR124 INTC.ICDIPR124 -#define INTCICDIPR125 INTC.ICDIPR125 -#define INTCICDIPR126 INTC.ICDIPR126 -#define INTCICDIPR127 INTC.ICDIPR127 -#define INTCICDIPR128 INTC.ICDIPR128 -#define INTCICDIPR129 INTC.ICDIPR129 -#define INTCICDIPR130 INTC.ICDIPR130 -#define INTCICDIPR131 INTC.ICDIPR131 -#define INTCICDIPR132 INTC.ICDIPR132 -#define INTCICDIPR133 INTC.ICDIPR133 -#define INTCICDIPR134 INTC.ICDIPR134 -#define INTCICDIPR135 INTC.ICDIPR135 -#define INTCICDIPR136 INTC.ICDIPR136 -#define INTCICDIPR137 INTC.ICDIPR137 -#define INTCICDIPR138 INTC.ICDIPR138 -#define INTCICDIPR139 INTC.ICDIPR139 -#define INTCICDIPR140 INTC.ICDIPR140 -#define INTCICDIPR141 INTC.ICDIPR141 -#define INTCICDIPR142 INTC.ICDIPR142 -#define INTCICDIPR143 INTC.ICDIPR143 -#define INTCICDIPR144 INTC.ICDIPR144 -#define INTCICDIPR145 INTC.ICDIPR145 -#define INTCICDIPR146 INTC.ICDIPR146 -#define INTCICDIPTR0 INTC.ICDIPTR0 -#define INTCICDIPTR1 INTC.ICDIPTR1 -#define INTCICDIPTR2 INTC.ICDIPTR2 -#define INTCICDIPTR3 INTC.ICDIPTR3 -#define INTCICDIPTR4 INTC.ICDIPTR4 -#define INTCICDIPTR5 INTC.ICDIPTR5 -#define INTCICDIPTR6 INTC.ICDIPTR6 -#define INTCICDIPTR7 INTC.ICDIPTR7 -#define INTCICDIPTR8 INTC.ICDIPTR8 -#define INTCICDIPTR9 INTC.ICDIPTR9 -#define INTCICDIPTR10 INTC.ICDIPTR10 -#define INTCICDIPTR11 INTC.ICDIPTR11 -#define INTCICDIPTR12 INTC.ICDIPTR12 -#define INTCICDIPTR13 INTC.ICDIPTR13 -#define INTCICDIPTR14 INTC.ICDIPTR14 -#define INTCICDIPTR15 INTC.ICDIPTR15 -#define INTCICDIPTR16 INTC.ICDIPTR16 -#define INTCICDIPTR17 INTC.ICDIPTR17 -#define INTCICDIPTR18 INTC.ICDIPTR18 -#define INTCICDIPTR19 INTC.ICDIPTR19 -#define INTCICDIPTR20 INTC.ICDIPTR20 -#define INTCICDIPTR21 INTC.ICDIPTR21 -#define INTCICDIPTR22 INTC.ICDIPTR22 -#define INTCICDIPTR23 INTC.ICDIPTR23 -#define INTCICDIPTR24 INTC.ICDIPTR24 -#define INTCICDIPTR25 INTC.ICDIPTR25 -#define INTCICDIPTR26 INTC.ICDIPTR26 -#define INTCICDIPTR27 INTC.ICDIPTR27 -#define INTCICDIPTR28 INTC.ICDIPTR28 -#define INTCICDIPTR29 INTC.ICDIPTR29 -#define INTCICDIPTR30 INTC.ICDIPTR30 -#define INTCICDIPTR31 INTC.ICDIPTR31 -#define INTCICDIPTR32 INTC.ICDIPTR32 -#define INTCICDIPTR33 INTC.ICDIPTR33 -#define INTCICDIPTR34 INTC.ICDIPTR34 -#define INTCICDIPTR35 INTC.ICDIPTR35 -#define INTCICDIPTR36 INTC.ICDIPTR36 -#define INTCICDIPTR37 INTC.ICDIPTR37 -#define INTCICDIPTR38 INTC.ICDIPTR38 -#define INTCICDIPTR39 INTC.ICDIPTR39 -#define INTCICDIPTR40 INTC.ICDIPTR40 -#define INTCICDIPTR41 INTC.ICDIPTR41 -#define INTCICDIPTR42 INTC.ICDIPTR42 -#define INTCICDIPTR43 INTC.ICDIPTR43 -#define INTCICDIPTR44 INTC.ICDIPTR44 -#define INTCICDIPTR45 INTC.ICDIPTR45 -#define INTCICDIPTR46 INTC.ICDIPTR46 -#define INTCICDIPTR47 INTC.ICDIPTR47 -#define INTCICDIPTR48 INTC.ICDIPTR48 -#define INTCICDIPTR49 INTC.ICDIPTR49 -#define INTCICDIPTR50 INTC.ICDIPTR50 -#define INTCICDIPTR51 INTC.ICDIPTR51 -#define INTCICDIPTR52 INTC.ICDIPTR52 -#define INTCICDIPTR53 INTC.ICDIPTR53 -#define INTCICDIPTR54 INTC.ICDIPTR54 -#define INTCICDIPTR55 INTC.ICDIPTR55 -#define INTCICDIPTR56 INTC.ICDIPTR56 -#define INTCICDIPTR57 INTC.ICDIPTR57 -#define INTCICDIPTR58 INTC.ICDIPTR58 -#define INTCICDIPTR59 INTC.ICDIPTR59 -#define INTCICDIPTR60 INTC.ICDIPTR60 -#define INTCICDIPTR61 INTC.ICDIPTR61 -#define INTCICDIPTR62 INTC.ICDIPTR62 -#define INTCICDIPTR63 INTC.ICDIPTR63 -#define INTCICDIPTR64 INTC.ICDIPTR64 -#define INTCICDIPTR65 INTC.ICDIPTR65 -#define INTCICDIPTR66 INTC.ICDIPTR66 -#define INTCICDIPTR67 INTC.ICDIPTR67 -#define INTCICDIPTR68 INTC.ICDIPTR68 -#define INTCICDIPTR69 INTC.ICDIPTR69 -#define INTCICDIPTR70 INTC.ICDIPTR70 -#define INTCICDIPTR71 INTC.ICDIPTR71 -#define INTCICDIPTR72 INTC.ICDIPTR72 -#define INTCICDIPTR73 INTC.ICDIPTR73 -#define INTCICDIPTR74 INTC.ICDIPTR74 -#define INTCICDIPTR75 INTC.ICDIPTR75 -#define INTCICDIPTR76 INTC.ICDIPTR76 -#define INTCICDIPTR77 INTC.ICDIPTR77 -#define INTCICDIPTR78 INTC.ICDIPTR78 -#define INTCICDIPTR79 INTC.ICDIPTR79 -#define INTCICDIPTR80 INTC.ICDIPTR80 -#define INTCICDIPTR81 INTC.ICDIPTR81 -#define INTCICDIPTR82 INTC.ICDIPTR82 -#define INTCICDIPTR83 INTC.ICDIPTR83 -#define INTCICDIPTR84 INTC.ICDIPTR84 -#define INTCICDIPTR85 INTC.ICDIPTR85 -#define INTCICDIPTR86 INTC.ICDIPTR86 -#define INTCICDIPTR87 INTC.ICDIPTR87 -#define INTCICDIPTR88 INTC.ICDIPTR88 -#define INTCICDIPTR89 INTC.ICDIPTR89 -#define INTCICDIPTR90 INTC.ICDIPTR90 -#define INTCICDIPTR91 INTC.ICDIPTR91 -#define INTCICDIPTR92 INTC.ICDIPTR92 -#define INTCICDIPTR93 INTC.ICDIPTR93 -#define INTCICDIPTR94 INTC.ICDIPTR94 -#define INTCICDIPTR95 INTC.ICDIPTR95 -#define INTCICDIPTR96 INTC.ICDIPTR96 -#define INTCICDIPTR97 INTC.ICDIPTR97 -#define INTCICDIPTR98 INTC.ICDIPTR98 -#define INTCICDIPTR99 INTC.ICDIPTR99 -#define INTCICDIPTR100 INTC.ICDIPTR100 -#define INTCICDIPTR101 INTC.ICDIPTR101 -#define INTCICDIPTR102 INTC.ICDIPTR102 -#define INTCICDIPTR103 INTC.ICDIPTR103 -#define INTCICDIPTR104 INTC.ICDIPTR104 -#define INTCICDIPTR105 INTC.ICDIPTR105 -#define INTCICDIPTR106 INTC.ICDIPTR106 -#define INTCICDIPTR107 INTC.ICDIPTR107 -#define INTCICDIPTR108 INTC.ICDIPTR108 -#define INTCICDIPTR109 INTC.ICDIPTR109 -#define INTCICDIPTR110 INTC.ICDIPTR110 -#define INTCICDIPTR111 INTC.ICDIPTR111 -#define INTCICDIPTR112 INTC.ICDIPTR112 -#define INTCICDIPTR113 INTC.ICDIPTR113 -#define INTCICDIPTR114 INTC.ICDIPTR114 -#define INTCICDIPTR115 INTC.ICDIPTR115 -#define INTCICDIPTR116 INTC.ICDIPTR116 -#define INTCICDIPTR117 INTC.ICDIPTR117 -#define INTCICDIPTR118 INTC.ICDIPTR118 -#define INTCICDIPTR119 INTC.ICDIPTR119 -#define INTCICDIPTR120 INTC.ICDIPTR120 -#define INTCICDIPTR121 INTC.ICDIPTR121 -#define INTCICDIPTR122 INTC.ICDIPTR122 -#define INTCICDIPTR123 INTC.ICDIPTR123 -#define INTCICDIPTR124 INTC.ICDIPTR124 -#define INTCICDIPTR125 INTC.ICDIPTR125 -#define INTCICDIPTR126 INTC.ICDIPTR126 -#define INTCICDIPTR127 INTC.ICDIPTR127 -#define INTCICDIPTR128 INTC.ICDIPTR128 -#define INTCICDIPTR129 INTC.ICDIPTR129 -#define INTCICDIPTR130 INTC.ICDIPTR130 -#define INTCICDIPTR131 INTC.ICDIPTR131 -#define INTCICDIPTR132 INTC.ICDIPTR132 -#define INTCICDIPTR133 INTC.ICDIPTR133 -#define INTCICDIPTR134 INTC.ICDIPTR134 -#define INTCICDIPTR135 INTC.ICDIPTR135 -#define INTCICDIPTR136 INTC.ICDIPTR136 -#define INTCICDIPTR137 INTC.ICDIPTR137 -#define INTCICDIPTR138 INTC.ICDIPTR138 -#define INTCICDIPTR139 INTC.ICDIPTR139 -#define INTCICDIPTR140 INTC.ICDIPTR140 -#define INTCICDIPTR141 INTC.ICDIPTR141 -#define INTCICDIPTR142 INTC.ICDIPTR142 -#define INTCICDIPTR143 INTC.ICDIPTR143 -#define INTCICDIPTR144 INTC.ICDIPTR144 -#define INTCICDIPTR145 INTC.ICDIPTR145 -#define INTCICDIPTR146 INTC.ICDIPTR146 -#define INTCICDICFR0 INTC.ICDICFR0 -#define INTCICDICFR1 INTC.ICDICFR1 -#define INTCICDICFR2 INTC.ICDICFR2 -#define INTCICDICFR3 INTC.ICDICFR3 -#define INTCICDICFR4 INTC.ICDICFR4 -#define INTCICDICFR5 INTC.ICDICFR5 -#define INTCICDICFR6 INTC.ICDICFR6 -#define INTCICDICFR7 INTC.ICDICFR7 -#define INTCICDICFR8 INTC.ICDICFR8 -#define INTCICDICFR9 INTC.ICDICFR9 -#define INTCICDICFR10 INTC.ICDICFR10 -#define INTCICDICFR11 INTC.ICDICFR11 -#define INTCICDICFR12 INTC.ICDICFR12 -#define INTCICDICFR13 INTC.ICDICFR13 -#define INTCICDICFR14 INTC.ICDICFR14 -#define INTCICDICFR15 INTC.ICDICFR15 -#define INTCICDICFR16 INTC.ICDICFR16 -#define INTCICDICFR17 INTC.ICDICFR17 -#define INTCICDICFR18 INTC.ICDICFR18 -#define INTCICDICFR19 INTC.ICDICFR19 -#define INTCICDICFR20 INTC.ICDICFR20 -#define INTCICDICFR21 INTC.ICDICFR21 -#define INTCICDICFR22 INTC.ICDICFR22 -#define INTCICDICFR23 INTC.ICDICFR23 -#define INTCICDICFR24 INTC.ICDICFR24 -#define INTCICDICFR25 INTC.ICDICFR25 -#define INTCICDICFR26 INTC.ICDICFR26 -#define INTCICDICFR27 INTC.ICDICFR27 -#define INTCICDICFR28 INTC.ICDICFR28 -#define INTCICDICFR29 INTC.ICDICFR29 -#define INTCICDICFR30 INTC.ICDICFR30 -#define INTCICDICFR31 INTC.ICDICFR31 -#define INTCICDICFR32 INTC.ICDICFR32 -#define INTCICDICFR33 INTC.ICDICFR33 -#define INTCICDICFR34 INTC.ICDICFR34 -#define INTCICDICFR35 INTC.ICDICFR35 -#define INTCICDICFR36 INTC.ICDICFR36 -#define INTCPPI_STATUS INTC.PPI_STATUS -#define INTCSPI_STATUS0 INTC.SPI_STATUS0 -#define INTCSPI_STATUS1 INTC.SPI_STATUS1 -#define INTCSPI_STATUS2 INTC.SPI_STATUS2 -#define INTCSPI_STATUS3 INTC.SPI_STATUS3 -#define INTCSPI_STATUS4 INTC.SPI_STATUS4 -#define INTCSPI_STATUS5 INTC.SPI_STATUS5 -#define INTCSPI_STATUS6 INTC.SPI_STATUS6 -#define INTCSPI_STATUS7 INTC.SPI_STATUS7 -#define INTCSPI_STATUS8 INTC.SPI_STATUS8 -#define INTCSPI_STATUS9 INTC.SPI_STATUS9 -#define INTCSPI_STATUS10 INTC.SPI_STATUS10 -#define INTCSPI_STATUS11 INTC.SPI_STATUS11 -#define INTCSPI_STATUS12 INTC.SPI_STATUS12 -#define INTCSPI_STATUS13 INTC.SPI_STATUS13 -#define INTCSPI_STATUS14 INTC.SPI_STATUS14 -#define INTCSPI_STATUS15 INTC.SPI_STATUS15 -#define INTCSPI_STATUS16 INTC.SPI_STATUS16 -#define INTCICDSGIR INTC.ICDSGIR -#define INTCICCICR INTC.ICCICR -#define INTCICCPMR INTC.ICCPMR -#define INTCICCBPR INTC.ICCBPR -#define INTCICCIAR INTC.ICCIAR -#define INTCICCEOIR INTC.ICCEOIR -#define INTCICCRPR INTC.ICCRPR -#define INTCICCHPIR INTC.ICCHPIR -#define INTCICCABPR INTC.ICCABPR -#define INTCICCIIDR INTC.ICCIIDR -#define INTCICR0 INTC.ICR0 -#define INTCICR1 INTC.ICR1 -#define INTCIRQRR INTC.IRQRR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h new file mode 100644 index 0000000000..434b931933 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h @@ -0,0 +1,118 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer* +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. +*******************************************************************************/ +/******************************************************************************* +* File Name : iodefine_typedef.h +* $Rev: $ +* $Date:: $ +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) +******************************************************************************/ +#ifndef IODEFINE_TYPEDEF_H +#define IODEFINE_TYPEDEF_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ + +/* Shared types and macros for iodefine.h */ + +/*********************************************************************** +* Macro: IODEFINE_H_VERSION +************************************************************************/ +#define IODEFINE_H_VERSION (200) + + +/*********************************************************************** +* Enum: iodefine_byte_select_t +* +* R_IO_L - Low 16bit or Low 8 bit +* R_IO_H - High 16bit or Low 8 bit +* R_IO_LL - Low 8 bit +* R_IO_LH - Middle Low 8 bit +* R_IO_HL - Middle High 8 bit +* R_IO_HH - High 8 bit +************************************************************************/ +typedef enum iodefine_byte_select_t +{ + R_IO_L = 0, R_IO_H = 1, + R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3, + L = 0, H = 1, + LL= 0, LH = 1, HL = 2, HH = 3 +} iodefine_byte_select_t; + + +/*********************************************************************** +* Type: iodefine_reg32_t +* 32/16/8 bit access register +* +* - Padding : sizeof(iodefine_reg32_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ + volatile uint8_t UINT8[4]; /* 8-bit Access */ +} iodefine_reg32_t; + + +/*********************************************************************** +* Type: iodefine_reg32_16_t +* 32/16 bit access register +* +* - Padding : sizeof(iodefine_reg32_16_t) == 4 +* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg32_16_t +{ + volatile uint32_t UINT32; /* 32-bit Access */ + volatile uint16_t UINT16[2]; /* 16-bit Access */ +} iodefine_reg32_16_t; + + +/*********************************************************************** +* Type: iodefine_reg16_8_t +* 16/8 bit access register +* +* - Padding : sizeof(iodefine_reg16_8_t) == 2 +* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1 +* - Endian : Independent (Same as CPU endian as register endian) +* - Bit-Order : Independent +************************************************************************/ +typedef union iodefine_reg16_8_t +{ + volatile uint16_t UINT16; /* 16-bit Access */ + volatile uint8_t UINT8[2]; /* 8-bit Access */ +} iodefine_reg16_8_t; + + +/* End of shared types and macros for iodefine.h */ +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ +#endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h index 14665ef2d6..eb5d842138 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h @@ -18,25 +18,36 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : irda_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef IRDA_IODEFINE_H #define IRDA_IODEFINE_H - -struct st_irda -{ /* IRDA */ - volatile uint8_t IRCR; /* IRCR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */ -#define IRDAIRCR IRDA.IRCR +#define IRDAIRCR (IRDA.IRCR) + + +typedef struct st_irda +{ + /* IRDA */ + volatile uint8_t IRCR; /* IRCR */ +} r_io_irda_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h index fa34ce2150..de1db5846a 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h @@ -18,20 +18,88 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : jcu_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef JCU_IODEFINE_H #define JCU_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_jcu -{ /* JCU */ +#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ + + +/* Start of channel array defines of JCU */ + +/* Channel array defines of JCU_JCQTBL0 */ +/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ +#define JCU_JCQTBL0_COUNT (4) +#define JCU_JCQTBL0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ +#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ +#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ +#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ + +/* End of channel array defines of JCU */ + + +#define JCUJCMOD (JCU.JCMOD) +#define JCUJCCMD (JCU.JCCMD) +#define JCUJCQTN (JCU.JCQTN) +#define JCUJCHTN (JCU.JCHTN) +#define JCUJCDRIU (JCU.JCDRIU) +#define JCUJCDRID (JCU.JCDRID) +#define JCUJCVSZU (JCU.JCVSZU) +#define JCUJCVSZD (JCU.JCVSZD) +#define JCUJCHSZU (JCU.JCHSZU) +#define JCUJCHSZD (JCU.JCHSZD) +#define JCUJCDTCU (JCU.JCDTCU) +#define JCUJCDTCM (JCU.JCDTCM) +#define JCUJCDTCD (JCU.JCDTCD) +#define JCUJINTE0 (JCU.JINTE0) +#define JCUJINTS0 (JCU.JINTS0) +#define JCUJCDERR (JCU.JCDERR) +#define JCUJCRST (JCU.JCRST) +#define JCUJIFECNT (JCU.JIFECNT) +#define JCUJIFESA (JCU.JIFESA) +#define JCUJIFESOFST (JCU.JIFESOFST) +#define JCUJIFEDA (JCU.JIFEDA) +#define JCUJIFESLC (JCU.JIFESLC) +#define JCUJIFEDDC (JCU.JIFEDDC) +#define JCUJIFDCNT (JCU.JIFDCNT) +#define JCUJIFDSA (JCU.JIFDSA) +#define JCUJIFDDOFST (JCU.JIFDDOFST) +#define JCUJIFDDA (JCU.JIFDDA) +#define JCUJIFDSDC (JCU.JIFDSDC) +#define JCUJIFDDLC (JCU.JIFDDLC) +#define JCUJIFDADT (JCU.JIFDADT) +#define JCUJINTE1 (JCU.JINTE1) +#define JCUJINTS1 (JCU.JINTS1) +#define JCUJIFESVSZ (JCU.JIFESVSZ) +#define JCUJIFESHSZ (JCU.JIFESHSZ) +#define JCUJCQTBL0 (JCU.JCQTBL0) +#define JCUJCQTBL1 (JCU.JCQTBL1) +#define JCUJCQTBL2 (JCU.JCQTBL2) +#define JCUJCQTBL3 (JCU.JCQTBL3) +#define JCUJCHTBD0 (JCU.JCHTBD0) +#define JCUJCHTBA0 (JCU.JCHTBA0) +#define JCUJCHTBD1 (JCU.JCHTBD1) +#define JCUJCHTBA1 (JCU.JCHTBA1) + + +typedef struct st_jcu +{ + /* JCU */ volatile uint8_t JCMOD; /* JCMOD */ volatile uint8_t JCCMD; /* JCCMD */ volatile uint8_t dummy145[1]; /* */ @@ -70,21 +138,29 @@ struct st_jcu volatile uint32_t JIFESVSZ; /* JIFESVSZ */ volatile uint32_t JIFESHSZ; /* JIFESHSZ */ volatile uint8_t dummy148[100]; /* */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL0; /* JCQTBL0 */ volatile uint8_t dummy149[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL1; /* JCQTBL1 */ volatile uint8_t dummy150[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL2; /* JCQTBL2 */ volatile uint8_t dummy151[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ + /* start of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCQTBL3; /* JCQTBL3 */ volatile uint8_t dummy152[63]; /* */ + /* end of struct st_jcu_from_jcqtbl0 */ volatile uint8_t JCHTBD0; /* JCHTBD0 */ volatile uint8_t dummy153[31]; /* */ @@ -93,77 +169,29 @@ struct st_jcu volatile uint8_t JCHTBD1; /* JCHTBD1 */ volatile uint8_t dummy155[31]; /* */ volatile uint8_t JCHTBA1; /* JCHTBA1 */ -}; +} r_io_jcu_t; -struct st_jcu_from_jcqtbl0 +typedef struct st_jcu_from_jcqtbl0 { + volatile uint8_t JCQTBL0; /* JCQTBL0 */ volatile uint8_t dummy1[63]; /* */ -}; +} r_io_jcu_from_jcqtbl0_t; -#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */ +/* Channel array defines of JCU (2)*/ +#ifdef DECLARE_JCU_JCQTBL0_CHANNELS +volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + JCU_JCQTBL0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */ +/* End of channel array defines of JCU (2)*/ -/* Start of channnel array defines of JCU */ - -/* Channnel array defines of JCU_JCQTBL0 */ -/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */ -#define JCU_JCQTBL0_COUNT 4 -#define JCU_JCQTBL0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */ -#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */ -#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */ -#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */ - -/* End of channnel array defines of JCU */ - - -#define JCUJCMOD JCU.JCMOD -#define JCUJCCMD JCU.JCCMD -#define JCUJCQTN JCU.JCQTN -#define JCUJCHTN JCU.JCHTN -#define JCUJCDRIU JCU.JCDRIU -#define JCUJCDRID JCU.JCDRID -#define JCUJCVSZU JCU.JCVSZU -#define JCUJCVSZD JCU.JCVSZD -#define JCUJCHSZU JCU.JCHSZU -#define JCUJCHSZD JCU.JCHSZD -#define JCUJCDTCU JCU.JCDTCU -#define JCUJCDTCM JCU.JCDTCM -#define JCUJCDTCD JCU.JCDTCD -#define JCUJINTE0 JCU.JINTE0 -#define JCUJINTS0 JCU.JINTS0 -#define JCUJCDERR JCU.JCDERR -#define JCUJCRST JCU.JCRST -#define JCUJIFECNT JCU.JIFECNT -#define JCUJIFESA JCU.JIFESA -#define JCUJIFESOFST JCU.JIFESOFST -#define JCUJIFEDA JCU.JIFEDA -#define JCUJIFESLC JCU.JIFESLC -#define JCUJIFEDDC JCU.JIFEDDC -#define JCUJIFDCNT JCU.JIFDCNT -#define JCUJIFDSA JCU.JIFDSA -#define JCUJIFDDOFST JCU.JIFDDOFST -#define JCUJIFDDA JCU.JIFDDA -#define JCUJIFDSDC JCU.JIFDSDC -#define JCUJIFDDLC JCU.JIFDDLC -#define JCUJIFDADT JCU.JIFDADT -#define JCUJINTE1 JCU.JINTE1 -#define JCUJINTS1 JCU.JINTS1 -#define JCUJIFESVSZ JCU.JIFESVSZ -#define JCUJIFESHSZ JCU.JIFESHSZ -#define JCUJCQTBL0 JCU.JCQTBL0 -#define JCUJCQTBL1 JCU.JCQTBL1 -#define JCUJCQTBL2 JCU.JCQTBL2 -#define JCUJCQTBL3 JCU.JCQTBL3 -#define JCUJCHTBD0 JCU.JCHTBD0 -#define JCUJCHTBA0 JCU.JCHTBA0 -#define JCUJCHTBD1 JCU.JCHTBD1 -#define JCUJCHTBA1 JCU.JCHTBA1 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h index ba6cb180bf..76604a953f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h @@ -18,20 +18,97 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : l2c_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef L2C_IODEFINE_H #define L2C_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_l2c -{ /* L2C */ +#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ + + +/* Start of channel array defines of L2C */ + +/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ +/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8) +#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ +#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ +#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ +#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ +#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ +#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ +#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ +#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ + +/* End of channel array defines of L2C */ + + +#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID) +#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE) +#define L2CREG1_CONTROL (L2C.REG1_CONTROL) +#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL) +#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL) +#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL) +#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL) +#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG) +#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG) +#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1) +#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0) +#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK) +#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS) +#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS) +#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR) +#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC) +#define L2CREG7_INV_PA (L2C.REG7_INV_PA) +#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY) +#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA) +#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX) +#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY) +#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA) +#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX) +#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY) +#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0) +#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0) +#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1) +#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1) +#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2) +#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2) +#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3) +#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3) +#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4) +#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4) +#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5) +#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5) +#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6) +#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6) +#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7) +#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7) +#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN) +#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY) +#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START) +#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END) +#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL) +#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL) +#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL) + + +typedef struct st_l2c +{ + /* L2C */ volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */ volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */ volatile uint8_t dummy8[248]; /* */ @@ -66,37 +143,53 @@ struct st_l2c volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */ volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */ volatile uint8_t dummy17[256]; /* */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */ volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */ volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */ volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */ volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */ volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */ volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ + /* start of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */ volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */ + /* end of struct st_l2c_from_reg9_d_lockdown0 */ volatile uint8_t dummy18[16]; /* */ volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */ @@ -110,86 +203,29 @@ struct st_l2c volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */ volatile uint8_t dummy22[28]; /* */ volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */ -}; +} r_io_l2c_t; -struct st_l2c_from_reg9_d_lockdown0 +typedef struct st_l2c_from_reg9_d_lockdown0 { + volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */ volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */ -}; +} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */; -#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */ +/* Channel array defines of L2C (2)*/ +#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS +volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */ +/* End of channel array defines of L2C (2)*/ -/* Start of channnel array defines of L2C */ - -/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */ -/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */ -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT 8 -#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */ -#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */ -#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */ -#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */ -#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */ -#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */ -#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */ -#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */ - -/* End of channnel array defines of L2C */ - - -#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID -#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE -#define L2CREG1_CONTROL L2C.REG1_CONTROL -#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL -#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL -#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL -#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL -#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG -#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG -#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1 -#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0 -#define L2CREG2_INT_MASK L2C.REG2_INT_MASK -#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS -#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS -#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR -#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC -#define L2CREG7_INV_PA L2C.REG7_INV_PA -#define L2CREG7_INV_WAY L2C.REG7_INV_WAY -#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA -#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX -#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY -#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA -#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX -#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY -#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0 -#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0 -#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1 -#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1 -#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2 -#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2 -#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3 -#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3 -#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4 -#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4 -#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5 -#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5 -#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6 -#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6 -#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7 -#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7 -#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN -#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY -#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START -#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END -#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL -#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL -#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h index d46e7770b3..6c0fcc0877 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h @@ -18,25 +18,101 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : lin_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef LIN_IODEFINE_H #define LIN_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_lin -{ /* LIN */ +#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ +#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ + + +/* Start of channel array defines of LIN */ + +/* Channel array defines of LIN */ +/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ +#define LIN_COUNT (2) +#define LIN_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &LIN0, &LIN1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of LIN */ + + +#define LIN0RLN30LWBR (LIN0.RLN3nLWBR) +#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0) +#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1) +#define LIN0RLN30LSTC (LIN0.RLN3nLSTC) +#define LIN0RLN30LMD (LIN0.RLN3nLMD) +#define LIN0RLN30LBFC (LIN0.RLN3nLBFC) +#define LIN0RLN30LSC (LIN0.RLN3nLSC) +#define LIN0RLN30LWUP (LIN0.RLN3nLWUP) +#define LIN0RLN30LIE (LIN0.RLN3nLIE) +#define LIN0RLN30LEDE (LIN0.RLN3nLEDE) +#define LIN0RLN30LCUC (LIN0.RLN3nLCUC) +#define LIN0RLN30LTRC (LIN0.RLN3nLTRC) +#define LIN0RLN30LMST (LIN0.RLN3nLMST) +#define LIN0RLN30LST (LIN0.RLN3nLST) +#define LIN0RLN30LEST (LIN0.RLN3nLEST) +#define LIN0RLN30LDFC (LIN0.RLN3nLDFC) +#define LIN0RLN30LIDB (LIN0.RLN3nLIDB) +#define LIN0RLN30LCBR (LIN0.RLN3nLCBR) +#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1) +#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2) +#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3) +#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4) +#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5) +#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6) +#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7) +#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8) +#define LIN1RLN31LWBR (LIN1.RLN3nLWBR) +#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0) +#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1) +#define LIN1RLN31LSTC (LIN1.RLN3nLSTC) +#define LIN1RLN31LMD (LIN1.RLN3nLMD) +#define LIN1RLN31LBFC (LIN1.RLN3nLBFC) +#define LIN1RLN31LSC (LIN1.RLN3nLSC) +#define LIN1RLN31LWUP (LIN1.RLN3nLWUP) +#define LIN1RLN31LIE (LIN1.RLN3nLIE) +#define LIN1RLN31LEDE (LIN1.RLN3nLEDE) +#define LIN1RLN31LCUC (LIN1.RLN3nLCUC) +#define LIN1RLN31LTRC (LIN1.RLN3nLTRC) +#define LIN1RLN31LMST (LIN1.RLN3nLMST) +#define LIN1RLN31LST (LIN1.RLN3nLST) +#define LIN1RLN31LEST (LIN1.RLN3nLEST) +#define LIN1RLN31LDFC (LIN1.RLN3nLDFC) +#define LIN1RLN31LIDB (LIN1.RLN3nLIDB) +#define LIN1RLN31LCBR (LIN1.RLN3nLCBR) +#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1) +#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2) +#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3) +#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4) +#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5) +#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6) +#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7) +#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8) + +#define LIN_LDBn_COUNT (8) + + +typedef struct st_lin +{ + /* LIN */ volatile uint8_t dummy1[1]; /* */ volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */ - union iodefine_reg16_8_t RLN3nLBRP01; /* RLN3nLBRP01 */ - + volatile uint8_t RLN3nLBRP0; /* RLN3nLBRP0 */ + volatile uint8_t RLN3nLBRP1; /* RLN3nLBRP1 */ volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */ volatile uint8_t dummy2[3]; /* */ volatile uint8_t RLN3nLMD; /* RLN3nLMD */ @@ -54,8 +130,9 @@ struct st_lin volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */ volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */ volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */ - volatile uint8_t RLN3nLUDB0; /* RLN3nLUDB0 */ -#define LIN_LDBn_COUNT 8 + volatile uint8_t dummy4[1]; /* */ + +/* #define LIN_LDBn_COUNT (8) */ volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */ volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */ volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */ @@ -64,111 +141,21 @@ struct st_lin volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */ volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */ volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */ - volatile uint8_t RLN3nLUOER; /* RLN3nLUOER */ - volatile uint8_t RLN3nLUOR1; /* RLN3nLUOR1 */ - volatile uint8_t dummy4[2]; /* */ - union iodefine_reg16_8_t RLN3nLUTDR; /* RLN3nLUTDR */ - union iodefine_reg16_8_t RLN3nLURDR; /* RLN3nLURDR */ - union iodefine_reg16_8_t RLN3nLUWTDR; /* RLN3nLUWTDR */ - -}; +} r_io_lin_t; -#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */ -#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */ +/* Channel array defines of LIN (2)*/ +#ifdef DECLARE_LIN_CHANNELS +volatile struct st_lin* LIN[ LIN_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + LIN_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_LIN_CHANNELS */ +/* End of channel array defines of LIN (2)*/ -/* Start of channnel array defines of LIN */ - -/* Channnel array defines of LIN */ -/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */ -#define LIN_COUNT 2 -#define LIN_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &LIN0, &LIN1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of LIN */ - - -#define LIN0RLN30LWBR LIN0.RLN3nLWBR -#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16 -#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L] -#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H] -#define LIN0RLN30LSTC LIN0.RLN3nLSTC -#define LIN0RLN30LMD LIN0.RLN3nLMD -#define LIN0RLN30LBFC LIN0.RLN3nLBFC -#define LIN0RLN30LSC LIN0.RLN3nLSC -#define LIN0RLN30LWUP LIN0.RLN3nLWUP -#define LIN0RLN30LIE LIN0.RLN3nLIE -#define LIN0RLN30LEDE LIN0.RLN3nLEDE -#define LIN0RLN30LCUC LIN0.RLN3nLCUC -#define LIN0RLN30LTRC LIN0.RLN3nLTRC -#define LIN0RLN30LMST LIN0.RLN3nLMST -#define LIN0RLN30LST LIN0.RLN3nLST -#define LIN0RLN30LEST LIN0.RLN3nLEST -#define LIN0RLN30LDFC LIN0.RLN3nLDFC -#define LIN0RLN30LIDB LIN0.RLN3nLIDB -#define LIN0RLN30LCBR LIN0.RLN3nLCBR -#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0 -#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1 -#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2 -#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3 -#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4 -#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5 -#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6 -#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7 -#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8 -#define LIN0RLN30LUOER LIN0.RLN3nLUOER -#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1 -#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16 -#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L] -#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H] -#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16 -#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L] -#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H] -#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16 -#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L] -#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H] -#define LIN1RLN31LWBR LIN1.RLN3nLWBR -#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16 -#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L] -#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H] -#define LIN1RLN31LSTC LIN1.RLN3nLSTC -#define LIN1RLN31LMD LIN1.RLN3nLMD -#define LIN1RLN31LBFC LIN1.RLN3nLBFC -#define LIN1RLN31LSC LIN1.RLN3nLSC -#define LIN1RLN31LWUP LIN1.RLN3nLWUP -#define LIN1RLN31LIE LIN1.RLN3nLIE -#define LIN1RLN31LEDE LIN1.RLN3nLEDE -#define LIN1RLN31LCUC LIN1.RLN3nLCUC -#define LIN1RLN31LTRC LIN1.RLN3nLTRC -#define LIN1RLN31LMST LIN1.RLN3nLMST -#define LIN1RLN31LST LIN1.RLN3nLST -#define LIN1RLN31LEST LIN1.RLN3nLEST -#define LIN1RLN31LDFC LIN1.RLN3nLDFC -#define LIN1RLN31LIDB LIN1.RLN3nLIDB -#define LIN1RLN31LCBR LIN1.RLN3nLCBR -#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0 -#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1 -#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2 -#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3 -#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4 -#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5 -#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6 -#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7 -#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8 -#define LIN1RLN31LUOER LIN1.RLN3nLUOER -#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1 -#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16 -#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L] -#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H] -#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16 -#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L] -#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H] -#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16 -#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L] -#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H] /* <-SEC M1.10.1 */ /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h index 64d52eef01..c32caa6952 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h @@ -18,20 +18,34 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : lvds_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.01a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef LVDS_IODEFINE_H #define LVDS_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_lvds -{ /* LVDS */ +#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ + + +#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE) +#define LVDSLVDSFCL (LVDS.LVDSFCL) +#define LVDSLCLKSELR (LVDS.LCLKSELR) +#define LVDSLPLLSETR (LVDS.LPLLSETR) +#define LVDSLPHYACC (LVDS.LPHYACC) + + +typedef struct st_lvds +{ + /* LVDS */ volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */ volatile uint32_t LVDSFCL; /* LVDSFCL */ volatile uint8_t dummy608[24]; /* */ @@ -39,16 +53,11 @@ struct st_lvds volatile uint32_t LPLLSETR; /* LPLLSETR */ volatile uint8_t dummy609[4]; /* */ volatile uint32_t LPHYACC; /* LPHYACC */ -}; +} r_io_lvds_t; -#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */ - - -#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE -#define LVDSLVDSFCL LVDS.LVDSFCL -#define LVDSLCLKSELR LVDS.LCLKSELR -#define LVDSLPLLSETR LVDS.LPLLSETR -#define LVDSLPHYACC LVDS.LPHYACC /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h index ae97365872..d06c767089 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h @@ -18,273 +18,29 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mlb_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MLB_IODEFINE_H #define MLB_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mlb -{ /* MLB */ - volatile uint32_t DCCR; /* DCCR */ - volatile uint32_t SSCR; /* SSCR */ - volatile uint32_t SDCR; /* SDCR */ - volatile uint32_t SMCR; /* SMCR */ - volatile uint8_t dummy156[12]; /* */ - volatile uint32_t VCCR; /* VCCR */ - volatile uint32_t SBCR; /* SBCR */ - volatile uint32_t ABCR; /* ABCR */ - volatile uint32_t CBCR; /* CBCR */ - volatile uint32_t IBCR; /* IBCR */ - volatile uint32_t CICR; /* CICR */ - volatile uint8_t dummy157[12]; /* */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR0; /* CECR0 */ - volatile uint32_t CSCR0; /* CSCR0 */ - volatile uint32_t CCBCR0; /* CCBCR0 */ - volatile uint32_t CNBCR0; /* CNBCR0 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR1; /* CECR1 */ - volatile uint32_t CSCR1; /* CSCR1 */ - volatile uint32_t CCBCR1; /* CCBCR1 */ - volatile uint32_t CNBCR1; /* CNBCR1 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR2; /* CECR2 */ - volatile uint32_t CSCR2; /* CSCR2 */ - volatile uint32_t CCBCR2; /* CCBCR2 */ - volatile uint32_t CNBCR2; /* CNBCR2 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR3; /* CECR3 */ - volatile uint32_t CSCR3; /* CSCR3 */ - volatile uint32_t CCBCR3; /* CCBCR3 */ - volatile uint32_t CNBCR3; /* CNBCR3 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR4; /* CECR4 */ - volatile uint32_t CSCR4; /* CSCR4 */ - volatile uint32_t CCBCR4; /* CCBCR4 */ - volatile uint32_t CNBCR4; /* CNBCR4 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR5; /* CECR5 */ - volatile uint32_t CSCR5; /* CSCR5 */ - volatile uint32_t CCBCR5; /* CCBCR5 */ - volatile uint32_t CNBCR5; /* CNBCR5 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR6; /* CECR6 */ - volatile uint32_t CSCR6; /* CSCR6 */ - volatile uint32_t CCBCR6; /* CCBCR6 */ - volatile uint32_t CNBCR6; /* CNBCR6 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR7; /* CECR7 */ - volatile uint32_t CSCR7; /* CSCR7 */ - volatile uint32_t CCBCR7; /* CCBCR7 */ - volatile uint32_t CNBCR7; /* CNBCR7 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR8; /* CECR8 */ - volatile uint32_t CSCR8; /* CSCR8 */ - volatile uint32_t CCBCR8; /* CCBCR8 */ - volatile uint32_t CNBCR8; /* CNBCR8 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR9; /* CECR9 */ - volatile uint32_t CSCR9; /* CSCR9 */ - volatile uint32_t CCBCR9; /* CCBCR9 */ - volatile uint32_t CNBCR9; /* CNBCR9 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR10; /* CECR10 */ - volatile uint32_t CSCR10; /* CSCR10 */ - volatile uint32_t CCBCR10; /* CCBCR10 */ - volatile uint32_t CNBCR10; /* CNBCR10 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR11; /* CECR11 */ - volatile uint32_t CSCR11; /* CSCR11 */ - volatile uint32_t CCBCR11; /* CCBCR11 */ - volatile uint32_t CNBCR11; /* CNBCR11 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR12; /* CECR12 */ - volatile uint32_t CSCR12; /* CSCR12 */ - volatile uint32_t CCBCR12; /* CCBCR12 */ - volatile uint32_t CNBCR12; /* CNBCR12 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR13; /* CECR13 */ - volatile uint32_t CSCR13; /* CSCR13 */ - volatile uint32_t CCBCR13; /* CCBCR13 */ - volatile uint32_t CNBCR13; /* CNBCR13 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR14; /* CECR14 */ - volatile uint32_t CSCR14; /* CSCR14 */ - volatile uint32_t CCBCR14; /* CCBCR14 */ - volatile uint32_t CNBCR14; /* CNBCR14 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR15; /* CECR15 */ - volatile uint32_t CSCR15; /* CSCR15 */ - volatile uint32_t CCBCR15; /* CCBCR15 */ - volatile uint32_t CNBCR15; /* CNBCR15 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR16; /* CECR16 */ - volatile uint32_t CSCR16; /* CSCR16 */ - volatile uint32_t CCBCR16; /* CCBCR16 */ - volatile uint32_t CNBCR16; /* CNBCR16 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR17; /* CECR17 */ - volatile uint32_t CSCR17; /* CSCR17 */ - volatile uint32_t CCBCR17; /* CCBCR17 */ - volatile uint32_t CNBCR17; /* CNBCR17 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR18; /* CECR18 */ - volatile uint32_t CSCR18; /* CSCR18 */ - volatile uint32_t CCBCR18; /* CCBCR18 */ - volatile uint32_t CNBCR18; /* CNBCR18 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR19; /* CECR19 */ - volatile uint32_t CSCR19; /* CSCR19 */ - volatile uint32_t CCBCR19; /* CCBCR19 */ - volatile uint32_t CNBCR19; /* CNBCR19 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR20; /* CECR20 */ - volatile uint32_t CSCR20; /* CSCR20 */ - volatile uint32_t CCBCR20; /* CCBCR20 */ - volatile uint32_t CNBCR20; /* CNBCR20 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR21; /* CECR21 */ - volatile uint32_t CSCR21; /* CSCR21 */ - volatile uint32_t CCBCR21; /* CCBCR21 */ - volatile uint32_t CNBCR21; /* CNBCR21 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR22; /* CECR22 */ - volatile uint32_t CSCR22; /* CSCR22 */ - volatile uint32_t CCBCR22; /* CCBCR22 */ - volatile uint32_t CNBCR22; /* CNBCR22 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR23; /* CECR23 */ - volatile uint32_t CSCR23; /* CSCR23 */ - volatile uint32_t CCBCR23; /* CCBCR23 */ - volatile uint32_t CNBCR23; /* CNBCR23 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR24; /* CECR24 */ - volatile uint32_t CSCR24; /* CSCR24 */ - volatile uint32_t CCBCR24; /* CCBCR24 */ - volatile uint32_t CNBCR24; /* CNBCR24 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR25; /* CECR25 */ - volatile uint32_t CSCR25; /* CSCR25 */ - volatile uint32_t CCBCR25; /* CCBCR25 */ - volatile uint32_t CNBCR25; /* CNBCR25 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR26; /* CECR26 */ - volatile uint32_t CSCR26; /* CSCR26 */ - volatile uint32_t CCBCR26; /* CCBCR26 */ - volatile uint32_t CNBCR26; /* CNBCR26 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR27; /* CECR27 */ - volatile uint32_t CSCR27; /* CSCR27 */ - volatile uint32_t CCBCR27; /* CCBCR27 */ - volatile uint32_t CNBCR27; /* CNBCR27 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR28; /* CECR28 */ - volatile uint32_t CSCR28; /* CSCR28 */ - volatile uint32_t CCBCR28; /* CCBCR28 */ - volatile uint32_t CNBCR28; /* CNBCR28 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR29; /* CECR29 */ - volatile uint32_t CSCR29; /* CSCR29 */ - volatile uint32_t CCBCR29; /* CCBCR29 */ - volatile uint32_t CNBCR29; /* CNBCR29 */ -/* end of struct st_mlb_from_cecr0 */ -/* start of struct st_mlb_from_cecr0 */ - volatile uint32_t CECR30; /* CECR30 */ - volatile uint32_t CSCR30; /* CSCR30 */ - volatile uint32_t CCBCR30; /* CCBCR30 */ - volatile uint32_t CNBCR30; /* CNBCR30 */ -/* end of struct st_mlb_from_cecr0 */ - volatile uint8_t dummy158[80]; /* */ -#define MLB_LCBCR0_COUNT 31 - volatile uint32_t LCBCR0; /* LCBCR0 */ - volatile uint32_t LCBCR1; /* LCBCR1 */ - volatile uint32_t LCBCR2; /* LCBCR2 */ - volatile uint32_t LCBCR3; /* LCBCR3 */ - volatile uint32_t LCBCR4; /* LCBCR4 */ - volatile uint32_t LCBCR5; /* LCBCR5 */ - volatile uint32_t LCBCR6; /* LCBCR6 */ - volatile uint32_t LCBCR7; /* LCBCR7 */ - volatile uint32_t LCBCR8; /* LCBCR8 */ - volatile uint32_t LCBCR9; /* LCBCR9 */ - volatile uint32_t LCBCR10; /* LCBCR10 */ - volatile uint32_t LCBCR11; /* LCBCR11 */ - volatile uint32_t LCBCR12; /* LCBCR12 */ - volatile uint32_t LCBCR13; /* LCBCR13 */ - volatile uint32_t LCBCR14; /* LCBCR14 */ - volatile uint32_t LCBCR15; /* LCBCR15 */ - volatile uint32_t LCBCR16; /* LCBCR16 */ - volatile uint32_t LCBCR17; /* LCBCR17 */ - volatile uint32_t LCBCR18; /* LCBCR18 */ - volatile uint32_t LCBCR19; /* LCBCR19 */ - volatile uint32_t LCBCR20; /* LCBCR20 */ - volatile uint32_t LCBCR21; /* LCBCR21 */ - volatile uint32_t LCBCR22; /* LCBCR22 */ - volatile uint32_t LCBCR23; /* LCBCR23 */ - volatile uint32_t LCBCR24; /* LCBCR24 */ - volatile uint32_t LCBCR25; /* LCBCR25 */ - volatile uint32_t LCBCR26; /* LCBCR26 */ - volatile uint32_t LCBCR27; /* LCBCR27 */ - volatile uint32_t LCBCR28; /* LCBCR28 */ - volatile uint32_t LCBCR29; /* LCBCR29 */ - volatile uint32_t LCBCR30; /* LCBCR30 */ -}; - - -struct st_mlb_from_cecr0 -{ - volatile uint32_t CECR0; /* CECR0 */ - volatile uint32_t CSCR0; /* CSCR0 */ - volatile uint32_t CCBCR0; /* CCBCR0 */ - volatile uint32_t CNBCR0; /* CNBCR0 */ -}; - - #define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */ -/* Start of channnel array defines of MLB */ +/* Start of channel array defines of MLB */ -/* Channnel array defines of MLB_FROM_CECR0_ARRAY */ +/* Channel array defines of MLB_FROM_CECR0_ARRAY */ /*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */ -#define MLB_FROM_CECR0_ARRAY_COUNT 31 +#define MLB_FROM_CECR0_ARRAY_COUNT (31) #define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \ @@ -324,175 +80,500 @@ struct st_mlb_from_cecr0 #define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */ #define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */ -/* End of channnel array defines of MLB */ +/* End of channel array defines of MLB */ + + +#define MLBDCCR (MLB.DCCR) +#define MLBSSCR (MLB.SSCR) +#define MLBSDCR (MLB.SDCR) +#define MLBSMCR (MLB.SMCR) +#define MLBVCCR (MLB.VCCR) +#define MLBSBCR (MLB.SBCR) +#define MLBABCR (MLB.ABCR) +#define MLBCBCR (MLB.CBCR) +#define MLBIBCR (MLB.IBCR) +#define MLBCICR (MLB.CICR) +#define MLBCECR0 (MLB.CECR0) +#define MLBCSCR0 (MLB.CSCR0) +#define MLBCCBCR0 (MLB.CCBCR0) +#define MLBCNBCR0 (MLB.CNBCR0) +#define MLBCECR1 (MLB.CECR1) +#define MLBCSCR1 (MLB.CSCR1) +#define MLBCCBCR1 (MLB.CCBCR1) +#define MLBCNBCR1 (MLB.CNBCR1) +#define MLBCECR2 (MLB.CECR2) +#define MLBCSCR2 (MLB.CSCR2) +#define MLBCCBCR2 (MLB.CCBCR2) +#define MLBCNBCR2 (MLB.CNBCR2) +#define MLBCECR3 (MLB.CECR3) +#define MLBCSCR3 (MLB.CSCR3) +#define MLBCCBCR3 (MLB.CCBCR3) +#define MLBCNBCR3 (MLB.CNBCR3) +#define MLBCECR4 (MLB.CECR4) +#define MLBCSCR4 (MLB.CSCR4) +#define MLBCCBCR4 (MLB.CCBCR4) +#define MLBCNBCR4 (MLB.CNBCR4) +#define MLBCECR5 (MLB.CECR5) +#define MLBCSCR5 (MLB.CSCR5) +#define MLBCCBCR5 (MLB.CCBCR5) +#define MLBCNBCR5 (MLB.CNBCR5) +#define MLBCECR6 (MLB.CECR6) +#define MLBCSCR6 (MLB.CSCR6) +#define MLBCCBCR6 (MLB.CCBCR6) +#define MLBCNBCR6 (MLB.CNBCR6) +#define MLBCECR7 (MLB.CECR7) +#define MLBCSCR7 (MLB.CSCR7) +#define MLBCCBCR7 (MLB.CCBCR7) +#define MLBCNBCR7 (MLB.CNBCR7) +#define MLBCECR8 (MLB.CECR8) +#define MLBCSCR8 (MLB.CSCR8) +#define MLBCCBCR8 (MLB.CCBCR8) +#define MLBCNBCR8 (MLB.CNBCR8) +#define MLBCECR9 (MLB.CECR9) +#define MLBCSCR9 (MLB.CSCR9) +#define MLBCCBCR9 (MLB.CCBCR9) +#define MLBCNBCR9 (MLB.CNBCR9) +#define MLBCECR10 (MLB.CECR10) +#define MLBCSCR10 (MLB.CSCR10) +#define MLBCCBCR10 (MLB.CCBCR10) +#define MLBCNBCR10 (MLB.CNBCR10) +#define MLBCECR11 (MLB.CECR11) +#define MLBCSCR11 (MLB.CSCR11) +#define MLBCCBCR11 (MLB.CCBCR11) +#define MLBCNBCR11 (MLB.CNBCR11) +#define MLBCECR12 (MLB.CECR12) +#define MLBCSCR12 (MLB.CSCR12) +#define MLBCCBCR12 (MLB.CCBCR12) +#define MLBCNBCR12 (MLB.CNBCR12) +#define MLBCECR13 (MLB.CECR13) +#define MLBCSCR13 (MLB.CSCR13) +#define MLBCCBCR13 (MLB.CCBCR13) +#define MLBCNBCR13 (MLB.CNBCR13) +#define MLBCECR14 (MLB.CECR14) +#define MLBCSCR14 (MLB.CSCR14) +#define MLBCCBCR14 (MLB.CCBCR14) +#define MLBCNBCR14 (MLB.CNBCR14) +#define MLBCECR15 (MLB.CECR15) +#define MLBCSCR15 (MLB.CSCR15) +#define MLBCCBCR15 (MLB.CCBCR15) +#define MLBCNBCR15 (MLB.CNBCR15) +#define MLBCECR16 (MLB.CECR16) +#define MLBCSCR16 (MLB.CSCR16) +#define MLBCCBCR16 (MLB.CCBCR16) +#define MLBCNBCR16 (MLB.CNBCR16) +#define MLBCECR17 (MLB.CECR17) +#define MLBCSCR17 (MLB.CSCR17) +#define MLBCCBCR17 (MLB.CCBCR17) +#define MLBCNBCR17 (MLB.CNBCR17) +#define MLBCECR18 (MLB.CECR18) +#define MLBCSCR18 (MLB.CSCR18) +#define MLBCCBCR18 (MLB.CCBCR18) +#define MLBCNBCR18 (MLB.CNBCR18) +#define MLBCECR19 (MLB.CECR19) +#define MLBCSCR19 (MLB.CSCR19) +#define MLBCCBCR19 (MLB.CCBCR19) +#define MLBCNBCR19 (MLB.CNBCR19) +#define MLBCECR20 (MLB.CECR20) +#define MLBCSCR20 (MLB.CSCR20) +#define MLBCCBCR20 (MLB.CCBCR20) +#define MLBCNBCR20 (MLB.CNBCR20) +#define MLBCECR21 (MLB.CECR21) +#define MLBCSCR21 (MLB.CSCR21) +#define MLBCCBCR21 (MLB.CCBCR21) +#define MLBCNBCR21 (MLB.CNBCR21) +#define MLBCECR22 (MLB.CECR22) +#define MLBCSCR22 (MLB.CSCR22) +#define MLBCCBCR22 (MLB.CCBCR22) +#define MLBCNBCR22 (MLB.CNBCR22) +#define MLBCECR23 (MLB.CECR23) +#define MLBCSCR23 (MLB.CSCR23) +#define MLBCCBCR23 (MLB.CCBCR23) +#define MLBCNBCR23 (MLB.CNBCR23) +#define MLBCECR24 (MLB.CECR24) +#define MLBCSCR24 (MLB.CSCR24) +#define MLBCCBCR24 (MLB.CCBCR24) +#define MLBCNBCR24 (MLB.CNBCR24) +#define MLBCECR25 (MLB.CECR25) +#define MLBCSCR25 (MLB.CSCR25) +#define MLBCCBCR25 (MLB.CCBCR25) +#define MLBCNBCR25 (MLB.CNBCR25) +#define MLBCECR26 (MLB.CECR26) +#define MLBCSCR26 (MLB.CSCR26) +#define MLBCCBCR26 (MLB.CCBCR26) +#define MLBCNBCR26 (MLB.CNBCR26) +#define MLBCECR27 (MLB.CECR27) +#define MLBCSCR27 (MLB.CSCR27) +#define MLBCCBCR27 (MLB.CCBCR27) +#define MLBCNBCR27 (MLB.CNBCR27) +#define MLBCECR28 (MLB.CECR28) +#define MLBCSCR28 (MLB.CSCR28) +#define MLBCCBCR28 (MLB.CCBCR28) +#define MLBCNBCR28 (MLB.CNBCR28) +#define MLBCECR29 (MLB.CECR29) +#define MLBCSCR29 (MLB.CSCR29) +#define MLBCCBCR29 (MLB.CCBCR29) +#define MLBCNBCR29 (MLB.CNBCR29) +#define MLBCECR30 (MLB.CECR30) +#define MLBCSCR30 (MLB.CSCR30) +#define MLBCCBCR30 (MLB.CCBCR30) +#define MLBCNBCR30 (MLB.CNBCR30) +#define MLBLCBCR0 (MLB.LCBCR0) +#define MLBLCBCR1 (MLB.LCBCR1) +#define MLBLCBCR2 (MLB.LCBCR2) +#define MLBLCBCR3 (MLB.LCBCR3) +#define MLBLCBCR4 (MLB.LCBCR4) +#define MLBLCBCR5 (MLB.LCBCR5) +#define MLBLCBCR6 (MLB.LCBCR6) +#define MLBLCBCR7 (MLB.LCBCR7) +#define MLBLCBCR8 (MLB.LCBCR8) +#define MLBLCBCR9 (MLB.LCBCR9) +#define MLBLCBCR10 (MLB.LCBCR10) +#define MLBLCBCR11 (MLB.LCBCR11) +#define MLBLCBCR12 (MLB.LCBCR12) +#define MLBLCBCR13 (MLB.LCBCR13) +#define MLBLCBCR14 (MLB.LCBCR14) +#define MLBLCBCR15 (MLB.LCBCR15) +#define MLBLCBCR16 (MLB.LCBCR16) +#define MLBLCBCR17 (MLB.LCBCR17) +#define MLBLCBCR18 (MLB.LCBCR18) +#define MLBLCBCR19 (MLB.LCBCR19) +#define MLBLCBCR20 (MLB.LCBCR20) +#define MLBLCBCR21 (MLB.LCBCR21) +#define MLBLCBCR22 (MLB.LCBCR22) +#define MLBLCBCR23 (MLB.LCBCR23) +#define MLBLCBCR24 (MLB.LCBCR24) +#define MLBLCBCR25 (MLB.LCBCR25) +#define MLBLCBCR26 (MLB.LCBCR26) +#define MLBLCBCR27 (MLB.LCBCR27) +#define MLBLCBCR28 (MLB.LCBCR28) +#define MLBLCBCR29 (MLB.LCBCR29) +#define MLBLCBCR30 (MLB.LCBCR30) + +#define MLB_LCBCR0_COUNT (31) + + +typedef struct st_mlb +{ + /* MLB */ + volatile uint32_t DCCR; /* DCCR */ + volatile uint32_t SSCR; /* SSCR */ + volatile uint32_t SDCR; /* SDCR */ + volatile uint32_t SMCR; /* SMCR */ + volatile uint8_t dummy156[12]; /* */ + volatile uint32_t VCCR; /* VCCR */ + volatile uint32_t SBCR; /* SBCR */ + volatile uint32_t ABCR; /* ABCR */ + volatile uint32_t CBCR; /* CBCR */ + volatile uint32_t IBCR; /* IBCR */ + volatile uint32_t CICR; /* CICR */ + volatile uint8_t dummy157[12]; /* */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR1; /* CECR1 */ + volatile uint32_t CSCR1; /* CSCR1 */ + volatile uint32_t CCBCR1; /* CCBCR1 */ + volatile uint32_t CNBCR1; /* CNBCR1 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR2; /* CECR2 */ + volatile uint32_t CSCR2; /* CSCR2 */ + volatile uint32_t CCBCR2; /* CCBCR2 */ + volatile uint32_t CNBCR2; /* CNBCR2 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR3; /* CECR3 */ + volatile uint32_t CSCR3; /* CSCR3 */ + volatile uint32_t CCBCR3; /* CCBCR3 */ + volatile uint32_t CNBCR3; /* CNBCR3 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR4; /* CECR4 */ + volatile uint32_t CSCR4; /* CSCR4 */ + volatile uint32_t CCBCR4; /* CCBCR4 */ + volatile uint32_t CNBCR4; /* CNBCR4 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR5; /* CECR5 */ + volatile uint32_t CSCR5; /* CSCR5 */ + volatile uint32_t CCBCR5; /* CCBCR5 */ + volatile uint32_t CNBCR5; /* CNBCR5 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR6; /* CECR6 */ + volatile uint32_t CSCR6; /* CSCR6 */ + volatile uint32_t CCBCR6; /* CCBCR6 */ + volatile uint32_t CNBCR6; /* CNBCR6 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR7; /* CECR7 */ + volatile uint32_t CSCR7; /* CSCR7 */ + volatile uint32_t CCBCR7; /* CCBCR7 */ + volatile uint32_t CNBCR7; /* CNBCR7 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR8; /* CECR8 */ + volatile uint32_t CSCR8; /* CSCR8 */ + volatile uint32_t CCBCR8; /* CCBCR8 */ + volatile uint32_t CNBCR8; /* CNBCR8 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR9; /* CECR9 */ + volatile uint32_t CSCR9; /* CSCR9 */ + volatile uint32_t CCBCR9; /* CCBCR9 */ + volatile uint32_t CNBCR9; /* CNBCR9 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR10; /* CECR10 */ + volatile uint32_t CSCR10; /* CSCR10 */ + volatile uint32_t CCBCR10; /* CCBCR10 */ + volatile uint32_t CNBCR10; /* CNBCR10 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR11; /* CECR11 */ + volatile uint32_t CSCR11; /* CSCR11 */ + volatile uint32_t CCBCR11; /* CCBCR11 */ + volatile uint32_t CNBCR11; /* CNBCR11 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR12; /* CECR12 */ + volatile uint32_t CSCR12; /* CSCR12 */ + volatile uint32_t CCBCR12; /* CCBCR12 */ + volatile uint32_t CNBCR12; /* CNBCR12 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR13; /* CECR13 */ + volatile uint32_t CSCR13; /* CSCR13 */ + volatile uint32_t CCBCR13; /* CCBCR13 */ + volatile uint32_t CNBCR13; /* CNBCR13 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR14; /* CECR14 */ + volatile uint32_t CSCR14; /* CSCR14 */ + volatile uint32_t CCBCR14; /* CCBCR14 */ + volatile uint32_t CNBCR14; /* CNBCR14 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR15; /* CECR15 */ + volatile uint32_t CSCR15; /* CSCR15 */ + volatile uint32_t CCBCR15; /* CCBCR15 */ + volatile uint32_t CNBCR15; /* CNBCR15 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR16; /* CECR16 */ + volatile uint32_t CSCR16; /* CSCR16 */ + volatile uint32_t CCBCR16; /* CCBCR16 */ + volatile uint32_t CNBCR16; /* CNBCR16 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR17; /* CECR17 */ + volatile uint32_t CSCR17; /* CSCR17 */ + volatile uint32_t CCBCR17; /* CCBCR17 */ + volatile uint32_t CNBCR17; /* CNBCR17 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR18; /* CECR18 */ + volatile uint32_t CSCR18; /* CSCR18 */ + volatile uint32_t CCBCR18; /* CCBCR18 */ + volatile uint32_t CNBCR18; /* CNBCR18 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR19; /* CECR19 */ + volatile uint32_t CSCR19; /* CSCR19 */ + volatile uint32_t CCBCR19; /* CCBCR19 */ + volatile uint32_t CNBCR19; /* CNBCR19 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR20; /* CECR20 */ + volatile uint32_t CSCR20; /* CSCR20 */ + volatile uint32_t CCBCR20; /* CCBCR20 */ + volatile uint32_t CNBCR20; /* CNBCR20 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR21; /* CECR21 */ + volatile uint32_t CSCR21; /* CSCR21 */ + volatile uint32_t CCBCR21; /* CCBCR21 */ + volatile uint32_t CNBCR21; /* CNBCR21 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR22; /* CECR22 */ + volatile uint32_t CSCR22; /* CSCR22 */ + volatile uint32_t CCBCR22; /* CCBCR22 */ + volatile uint32_t CNBCR22; /* CNBCR22 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR23; /* CECR23 */ + volatile uint32_t CSCR23; /* CSCR23 */ + volatile uint32_t CCBCR23; /* CCBCR23 */ + volatile uint32_t CNBCR23; /* CNBCR23 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR24; /* CECR24 */ + volatile uint32_t CSCR24; /* CSCR24 */ + volatile uint32_t CCBCR24; /* CCBCR24 */ + volatile uint32_t CNBCR24; /* CNBCR24 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR25; /* CECR25 */ + volatile uint32_t CSCR25; /* CSCR25 */ + volatile uint32_t CCBCR25; /* CCBCR25 */ + volatile uint32_t CNBCR25; /* CNBCR25 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR26; /* CECR26 */ + volatile uint32_t CSCR26; /* CSCR26 */ + volatile uint32_t CCBCR26; /* CCBCR26 */ + volatile uint32_t CNBCR26; /* CNBCR26 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR27; /* CECR27 */ + volatile uint32_t CSCR27; /* CSCR27 */ + volatile uint32_t CCBCR27; /* CCBCR27 */ + volatile uint32_t CNBCR27; /* CNBCR27 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR28; /* CECR28 */ + volatile uint32_t CSCR28; /* CSCR28 */ + volatile uint32_t CCBCR28; /* CCBCR28 */ + volatile uint32_t CNBCR28; /* CNBCR28 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR29; /* CECR29 */ + volatile uint32_t CSCR29; /* CSCR29 */ + volatile uint32_t CCBCR29; /* CCBCR29 */ + volatile uint32_t CNBCR29; /* CNBCR29 */ + +/* end of struct st_mlb_from_cecr0 */ + +/* start of struct st_mlb_from_cecr0 */ + volatile uint32_t CECR30; /* CECR30 */ + volatile uint32_t CSCR30; /* CSCR30 */ + volatile uint32_t CCBCR30; /* CCBCR30 */ + volatile uint32_t CNBCR30; /* CNBCR30 */ + +/* end of struct st_mlb_from_cecr0 */ + volatile uint8_t dummy158[80]; /* */ + +/* #define MLB_LCBCR0_COUNT (31) */ + volatile uint32_t LCBCR0; /* LCBCR0 */ + volatile uint32_t LCBCR1; /* LCBCR1 */ + volatile uint32_t LCBCR2; /* LCBCR2 */ + volatile uint32_t LCBCR3; /* LCBCR3 */ + volatile uint32_t LCBCR4; /* LCBCR4 */ + volatile uint32_t LCBCR5; /* LCBCR5 */ + volatile uint32_t LCBCR6; /* LCBCR6 */ + volatile uint32_t LCBCR7; /* LCBCR7 */ + volatile uint32_t LCBCR8; /* LCBCR8 */ + volatile uint32_t LCBCR9; /* LCBCR9 */ + volatile uint32_t LCBCR10; /* LCBCR10 */ + volatile uint32_t LCBCR11; /* LCBCR11 */ + volatile uint32_t LCBCR12; /* LCBCR12 */ + volatile uint32_t LCBCR13; /* LCBCR13 */ + volatile uint32_t LCBCR14; /* LCBCR14 */ + volatile uint32_t LCBCR15; /* LCBCR15 */ + volatile uint32_t LCBCR16; /* LCBCR16 */ + volatile uint32_t LCBCR17; /* LCBCR17 */ + volatile uint32_t LCBCR18; /* LCBCR18 */ + volatile uint32_t LCBCR19; /* LCBCR19 */ + volatile uint32_t LCBCR20; /* LCBCR20 */ + volatile uint32_t LCBCR21; /* LCBCR21 */ + volatile uint32_t LCBCR22; /* LCBCR22 */ + volatile uint32_t LCBCR23; /* LCBCR23 */ + volatile uint32_t LCBCR24; /* LCBCR24 */ + volatile uint32_t LCBCR25; /* LCBCR25 */ + volatile uint32_t LCBCR26; /* LCBCR26 */ + volatile uint32_t LCBCR27; /* LCBCR27 */ + volatile uint32_t LCBCR28; /* LCBCR28 */ + volatile uint32_t LCBCR29; /* LCBCR29 */ + volatile uint32_t LCBCR30; /* LCBCR30 */ +} r_io_mlb_t; + + +typedef struct st_mlb_from_cecr0 +{ + + volatile uint32_t CECR0; /* CECR0 */ + volatile uint32_t CSCR0; /* CSCR0 */ + volatile uint32_t CCBCR0; /* CCBCR0 */ + volatile uint32_t CNBCR0; /* CNBCR0 */ +} r_io_mlb_from_cecr0_t; + + +/* Channel array defines of MLB (2)*/ +#ifdef DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS +volatile struct st_mlb_from_cecr0* MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + MLB_FROM_CECR0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */ +/* End of channel array defines of MLB (2)*/ -#define MLBDCCR MLB.DCCR -#define MLBSSCR MLB.SSCR -#define MLBSDCR MLB.SDCR -#define MLBSMCR MLB.SMCR -#define MLBVCCR MLB.VCCR -#define MLBSBCR MLB.SBCR -#define MLBABCR MLB.ABCR -#define MLBCBCR MLB.CBCR -#define MLBIBCR MLB.IBCR -#define MLBCICR MLB.CICR -#define MLBCECR0 MLB.CECR0 -#define MLBCSCR0 MLB.CSCR0 -#define MLBCCBCR0 MLB.CCBCR0 -#define MLBCNBCR0 MLB.CNBCR0 -#define MLBCECR1 MLB.CECR1 -#define MLBCSCR1 MLB.CSCR1 -#define MLBCCBCR1 MLB.CCBCR1 -#define MLBCNBCR1 MLB.CNBCR1 -#define MLBCECR2 MLB.CECR2 -#define MLBCSCR2 MLB.CSCR2 -#define MLBCCBCR2 MLB.CCBCR2 -#define MLBCNBCR2 MLB.CNBCR2 -#define MLBCECR3 MLB.CECR3 -#define MLBCSCR3 MLB.CSCR3 -#define MLBCCBCR3 MLB.CCBCR3 -#define MLBCNBCR3 MLB.CNBCR3 -#define MLBCECR4 MLB.CECR4 -#define MLBCSCR4 MLB.CSCR4 -#define MLBCCBCR4 MLB.CCBCR4 -#define MLBCNBCR4 MLB.CNBCR4 -#define MLBCECR5 MLB.CECR5 -#define MLBCSCR5 MLB.CSCR5 -#define MLBCCBCR5 MLB.CCBCR5 -#define MLBCNBCR5 MLB.CNBCR5 -#define MLBCECR6 MLB.CECR6 -#define MLBCSCR6 MLB.CSCR6 -#define MLBCCBCR6 MLB.CCBCR6 -#define MLBCNBCR6 MLB.CNBCR6 -#define MLBCECR7 MLB.CECR7 -#define MLBCSCR7 MLB.CSCR7 -#define MLBCCBCR7 MLB.CCBCR7 -#define MLBCNBCR7 MLB.CNBCR7 -#define MLBCECR8 MLB.CECR8 -#define MLBCSCR8 MLB.CSCR8 -#define MLBCCBCR8 MLB.CCBCR8 -#define MLBCNBCR8 MLB.CNBCR8 -#define MLBCECR9 MLB.CECR9 -#define MLBCSCR9 MLB.CSCR9 -#define MLBCCBCR9 MLB.CCBCR9 -#define MLBCNBCR9 MLB.CNBCR9 -#define MLBCECR10 MLB.CECR10 -#define MLBCSCR10 MLB.CSCR10 -#define MLBCCBCR10 MLB.CCBCR10 -#define MLBCNBCR10 MLB.CNBCR10 -#define MLBCECR11 MLB.CECR11 -#define MLBCSCR11 MLB.CSCR11 -#define MLBCCBCR11 MLB.CCBCR11 -#define MLBCNBCR11 MLB.CNBCR11 -#define MLBCECR12 MLB.CECR12 -#define MLBCSCR12 MLB.CSCR12 -#define MLBCCBCR12 MLB.CCBCR12 -#define MLBCNBCR12 MLB.CNBCR12 -#define MLBCECR13 MLB.CECR13 -#define MLBCSCR13 MLB.CSCR13 -#define MLBCCBCR13 MLB.CCBCR13 -#define MLBCNBCR13 MLB.CNBCR13 -#define MLBCECR14 MLB.CECR14 -#define MLBCSCR14 MLB.CSCR14 -#define MLBCCBCR14 MLB.CCBCR14 -#define MLBCNBCR14 MLB.CNBCR14 -#define MLBCECR15 MLB.CECR15 -#define MLBCSCR15 MLB.CSCR15 -#define MLBCCBCR15 MLB.CCBCR15 -#define MLBCNBCR15 MLB.CNBCR15 -#define MLBCECR16 MLB.CECR16 -#define MLBCSCR16 MLB.CSCR16 -#define MLBCCBCR16 MLB.CCBCR16 -#define MLBCNBCR16 MLB.CNBCR16 -#define MLBCECR17 MLB.CECR17 -#define MLBCSCR17 MLB.CSCR17 -#define MLBCCBCR17 MLB.CCBCR17 -#define MLBCNBCR17 MLB.CNBCR17 -#define MLBCECR18 MLB.CECR18 -#define MLBCSCR18 MLB.CSCR18 -#define MLBCCBCR18 MLB.CCBCR18 -#define MLBCNBCR18 MLB.CNBCR18 -#define MLBCECR19 MLB.CECR19 -#define MLBCSCR19 MLB.CSCR19 -#define MLBCCBCR19 MLB.CCBCR19 -#define MLBCNBCR19 MLB.CNBCR19 -#define MLBCECR20 MLB.CECR20 -#define MLBCSCR20 MLB.CSCR20 -#define MLBCCBCR20 MLB.CCBCR20 -#define MLBCNBCR20 MLB.CNBCR20 -#define MLBCECR21 MLB.CECR21 -#define MLBCSCR21 MLB.CSCR21 -#define MLBCCBCR21 MLB.CCBCR21 -#define MLBCNBCR21 MLB.CNBCR21 -#define MLBCECR22 MLB.CECR22 -#define MLBCSCR22 MLB.CSCR22 -#define MLBCCBCR22 MLB.CCBCR22 -#define MLBCNBCR22 MLB.CNBCR22 -#define MLBCECR23 MLB.CECR23 -#define MLBCSCR23 MLB.CSCR23 -#define MLBCCBCR23 MLB.CCBCR23 -#define MLBCNBCR23 MLB.CNBCR23 -#define MLBCECR24 MLB.CECR24 -#define MLBCSCR24 MLB.CSCR24 -#define MLBCCBCR24 MLB.CCBCR24 -#define MLBCNBCR24 MLB.CNBCR24 -#define MLBCECR25 MLB.CECR25 -#define MLBCSCR25 MLB.CSCR25 -#define MLBCCBCR25 MLB.CCBCR25 -#define MLBCNBCR25 MLB.CNBCR25 -#define MLBCECR26 MLB.CECR26 -#define MLBCSCR26 MLB.CSCR26 -#define MLBCCBCR26 MLB.CCBCR26 -#define MLBCNBCR26 MLB.CNBCR26 -#define MLBCECR27 MLB.CECR27 -#define MLBCSCR27 MLB.CSCR27 -#define MLBCCBCR27 MLB.CCBCR27 -#define MLBCNBCR27 MLB.CNBCR27 -#define MLBCECR28 MLB.CECR28 -#define MLBCSCR28 MLB.CSCR28 -#define MLBCCBCR28 MLB.CCBCR28 -#define MLBCNBCR28 MLB.CNBCR28 -#define MLBCECR29 MLB.CECR29 -#define MLBCSCR29 MLB.CSCR29 -#define MLBCCBCR29 MLB.CCBCR29 -#define MLBCNBCR29 MLB.CNBCR29 -#define MLBCECR30 MLB.CECR30 -#define MLBCSCR30 MLB.CSCR30 -#define MLBCCBCR30 MLB.CCBCR30 -#define MLBCNBCR30 MLB.CNBCR30 -#define MLBLCBCR0 MLB.LCBCR0 -#define MLBLCBCR1 MLB.LCBCR1 -#define MLBLCBCR2 MLB.LCBCR2 -#define MLBLCBCR3 MLB.LCBCR3 -#define MLBLCBCR4 MLB.LCBCR4 -#define MLBLCBCR5 MLB.LCBCR5 -#define MLBLCBCR6 MLB.LCBCR6 -#define MLBLCBCR7 MLB.LCBCR7 -#define MLBLCBCR8 MLB.LCBCR8 -#define MLBLCBCR9 MLB.LCBCR9 -#define MLBLCBCR10 MLB.LCBCR10 -#define MLBLCBCR11 MLB.LCBCR11 -#define MLBLCBCR12 MLB.LCBCR12 -#define MLBLCBCR13 MLB.LCBCR13 -#define MLBLCBCR14 MLB.LCBCR14 -#define MLBLCBCR15 MLB.LCBCR15 -#define MLBLCBCR16 MLB.LCBCR16 -#define MLBLCBCR17 MLB.LCBCR17 -#define MLBLCBCR18 MLB.LCBCR18 -#define MLBLCBCR19 MLB.LCBCR19 -#define MLBLCBCR20 MLB.LCBCR20 -#define MLBLCBCR21 MLB.LCBCR21 -#define MLBLCBCR22 MLB.LCBCR22 -#define MLBLCBCR23 MLB.LCBCR23 -#define MLBLCBCR24 MLB.LCBCR24 -#define MLBLCBCR25 MLB.LCBCR25 -#define MLBLCBCR26 MLB.LCBCR26 -#define MLBLCBCR27 MLB.LCBCR27 -#define MLBLCBCR28 MLB.LCBCR28 -#define MLBLCBCR29 MLB.LCBCR29 -#define MLBLCBCR30 MLB.LCBCR30 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h index 43a23670d0..cccfd79f66 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h @@ -18,20 +18,53 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mmc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MMC_IODEFINE_H #define MMC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mmc -{ /* MMC */ +#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ + + +#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH) +#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL) +#define MMCCE_ARG (MMC.CE_ARG) +#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12) +#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL) +#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET) +#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL) +#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC) +#define MMCCE_RESP3 (MMC.CE_RESP3) +#define MMCCE_RESP2 (MMC.CE_RESP2) +#define MMCCE_RESP1 (MMC.CE_RESP1) +#define MMCCE_RESP0 (MMC.CE_RESP0) +#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12) +#define MMCCE_DATA (MMC.CE_DATA) +#define MMCCE_INT (MMC.CE_INT) +#define MMCCE_INT_EN (MMC.CE_INT_EN) +#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1) +#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2) +#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE) +#define MMCCE_DETECT (MMC.CE_DETECT) +#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE) +#define MMCCE_VERSION (MMC.CE_VERSION) + +#define MMC_CE_RESPn_COUNT (4) + + +typedef struct st_mmc +{ + /* MMC */ volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */ volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */ volatile uint8_t dummy182[4]; /* */ @@ -41,7 +74,8 @@ struct st_mmc volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */ volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */ volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */ -#define MMC_CE_RESPn_COUNT 4 + +/* #define MMC_CE_RESPn_COUNT (4) */ volatile uint32_t CE_RESP3; /* CE_RESP3 */ volatile uint32_t CE_RESP2; /* CE_RESP2 */ volatile uint32_t CE_RESP1; /* CE_RESP1 */ @@ -60,33 +94,11 @@ struct st_mmc volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */ volatile uint8_t dummy186[4]; /* */ volatile uint32_t CE_VERSION; /* CE_VERSION */ -}; +} r_io_mmc_t; -#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */ - - -#define MMCCE_CMD_SETH MMC.CE_CMD_SETH -#define MMCCE_CMD_SETL MMC.CE_CMD_SETL -#define MMCCE_ARG MMC.CE_ARG -#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12 -#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL -#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET -#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL -#define MMCCE_BUF_ACC MMC.CE_BUF_ACC -#define MMCCE_RESP3 MMC.CE_RESP3 -#define MMCCE_RESP2 MMC.CE_RESP2 -#define MMCCE_RESP1 MMC.CE_RESP1 -#define MMCCE_RESP0 MMC.CE_RESP0 -#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12 -#define MMCCE_DATA MMC.CE_DATA -#define MMCCE_INT MMC.CE_INT -#define MMCCE_INT_EN MMC.CE_INT_EN -#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1 -#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2 -#define MMCCE_DMA_MODE MMC.CE_DMA_MODE -#define MMCCE_DETECT MMC.CE_DETECT -#define MMCCE_ADD_MODE MMC.CE_ADD_MODE -#define MMCCE_VERSION MMC.CE_VERSION /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h index c2d0aeec84..9e3248029f 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h @@ -18,20 +18,108 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : mtu2_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef MTU2_IODEFINE_H #define MTU2_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_mtu2 -{ /* MTU2 */ +#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ + + +#define MTU2TCR_2 (MTU2.TCR_2) +#define MTU2TMDR_2 (MTU2.TMDR_2) +#define MTU2TIOR_2 (MTU2.TIOR_2) +#define MTU2TIER_2 (MTU2.TIER_2) +#define MTU2TSR_2 (MTU2.TSR_2) +#define MTU2TCNT_2 (MTU2.TCNT_2) +#define MTU2TGRA_2 (MTU2.TGRA_2) +#define MTU2TGRB_2 (MTU2.TGRB_2) +#define MTU2TCR_3 (MTU2.TCR_3) +#define MTU2TCR_4 (MTU2.TCR_4) +#define MTU2TMDR_3 (MTU2.TMDR_3) +#define MTU2TMDR_4 (MTU2.TMDR_4) +#define MTU2TIORH_3 (MTU2.TIORH_3) +#define MTU2TIORL_3 (MTU2.TIORL_3) +#define MTU2TIORH_4 (MTU2.TIORH_4) +#define MTU2TIORL_4 (MTU2.TIORL_4) +#define MTU2TIER_3 (MTU2.TIER_3) +#define MTU2TIER_4 (MTU2.TIER_4) +#define MTU2TOER (MTU2.TOER) +#define MTU2TGCR (MTU2.TGCR) +#define MTU2TOCR1 (MTU2.TOCR1) +#define MTU2TOCR2 (MTU2.TOCR2) +#define MTU2TCNT_3 (MTU2.TCNT_3) +#define MTU2TCNT_4 (MTU2.TCNT_4) +#define MTU2TCDR (MTU2.TCDR) +#define MTU2TDDR (MTU2.TDDR) +#define MTU2TGRA_3 (MTU2.TGRA_3) +#define MTU2TGRB_3 (MTU2.TGRB_3) +#define MTU2TGRA_4 (MTU2.TGRA_4) +#define MTU2TGRB_4 (MTU2.TGRB_4) +#define MTU2TCNTS (MTU2.TCNTS) +#define MTU2TCBR (MTU2.TCBR) +#define MTU2TGRC_3 (MTU2.TGRC_3) +#define MTU2TGRD_3 (MTU2.TGRD_3) +#define MTU2TGRC_4 (MTU2.TGRC_4) +#define MTU2TGRD_4 (MTU2.TGRD_4) +#define MTU2TSR_3 (MTU2.TSR_3) +#define MTU2TSR_4 (MTU2.TSR_4) +#define MTU2TITCR (MTU2.TITCR) +#define MTU2TITCNT (MTU2.TITCNT) +#define MTU2TBTER (MTU2.TBTER) +#define MTU2TDER (MTU2.TDER) +#define MTU2TOLBR (MTU2.TOLBR) +#define MTU2TBTM_3 (MTU2.TBTM_3) +#define MTU2TBTM_4 (MTU2.TBTM_4) +#define MTU2TADCR (MTU2.TADCR) +#define MTU2TADCORA_4 (MTU2.TADCORA_4) +#define MTU2TADCORB_4 (MTU2.TADCORB_4) +#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4) +#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4) +#define MTU2TWCR (MTU2.TWCR) +#define MTU2TSTR (MTU2.TSTR) +#define MTU2TSYR (MTU2.TSYR) +#define MTU2TRWER (MTU2.TRWER) +#define MTU2TCR_0 (MTU2.TCR_0) +#define MTU2TMDR_0 (MTU2.TMDR_0) +#define MTU2TIORH_0 (MTU2.TIORH_0) +#define MTU2TIORL_0 (MTU2.TIORL_0) +#define MTU2TIER_0 (MTU2.TIER_0) +#define MTU2TSR_0 (MTU2.TSR_0) +#define MTU2TCNT_0 (MTU2.TCNT_0) +#define MTU2TGRA_0 (MTU2.TGRA_0) +#define MTU2TGRB_0 (MTU2.TGRB_0) +#define MTU2TGRC_0 (MTU2.TGRC_0) +#define MTU2TGRD_0 (MTU2.TGRD_0) +#define MTU2TGRE_0 (MTU2.TGRE_0) +#define MTU2TGRF_0 (MTU2.TGRF_0) +#define MTU2TIER2_0 (MTU2.TIER2_0) +#define MTU2TSR2_0 (MTU2.TSR2_0) +#define MTU2TBTM_0 (MTU2.TBTM_0) +#define MTU2TCR_1 (MTU2.TCR_1) +#define MTU2TMDR_1 (MTU2.TMDR_1) +#define MTU2TIOR_1 (MTU2.TIOR_1) +#define MTU2TIER_1 (MTU2.TIER_1) +#define MTU2TSR_1 (MTU2.TSR_1) +#define MTU2TCNT_1 (MTU2.TCNT_1) +#define MTU2TGRA_1 (MTU2.TGRA_1) +#define MTU2TGRB_1 (MTU2.TGRB_1) +#define MTU2TICCR (MTU2.TICCR) + + +typedef struct st_mtu2 +{ + /* MTU2 */ volatile uint8_t TCR_2; /* TCR_2 */ volatile uint8_t TMDR_2; /* TMDR_2 */ volatile uint8_t TIOR_2; /* TIOR_2 */ @@ -128,90 +216,11 @@ struct st_mtu2 volatile uint16_t TGRB_1; /* TGRB_1 */ volatile uint8_t dummy536[4]; /* */ volatile uint8_t TICCR; /* TICCR */ -}; +} r_io_mtu2_t; -#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */ - - -#define MTU2TCR_2 MTU2.TCR_2 -#define MTU2TMDR_2 MTU2.TMDR_2 -#define MTU2TIOR_2 MTU2.TIOR_2 -#define MTU2TIER_2 MTU2.TIER_2 -#define MTU2TSR_2 MTU2.TSR_2 -#define MTU2TCNT_2 MTU2.TCNT_2 -#define MTU2TGRA_2 MTU2.TGRA_2 -#define MTU2TGRB_2 MTU2.TGRB_2 -#define MTU2TCR_3 MTU2.TCR_3 -#define MTU2TCR_4 MTU2.TCR_4 -#define MTU2TMDR_3 MTU2.TMDR_3 -#define MTU2TMDR_4 MTU2.TMDR_4 -#define MTU2TIORH_3 MTU2.TIORH_3 -#define MTU2TIORL_3 MTU2.TIORL_3 -#define MTU2TIORH_4 MTU2.TIORH_4 -#define MTU2TIORL_4 MTU2.TIORL_4 -#define MTU2TIER_3 MTU2.TIER_3 -#define MTU2TIER_4 MTU2.TIER_4 -#define MTU2TOER MTU2.TOER -#define MTU2TGCR MTU2.TGCR -#define MTU2TOCR1 MTU2.TOCR1 -#define MTU2TOCR2 MTU2.TOCR2 -#define MTU2TCNT_3 MTU2.TCNT_3 -#define MTU2TCNT_4 MTU2.TCNT_4 -#define MTU2TCDR MTU2.TCDR -#define MTU2TDDR MTU2.TDDR -#define MTU2TGRA_3 MTU2.TGRA_3 -#define MTU2TGRB_3 MTU2.TGRB_3 -#define MTU2TGRA_4 MTU2.TGRA_4 -#define MTU2TGRB_4 MTU2.TGRB_4 -#define MTU2TCNTS MTU2.TCNTS -#define MTU2TCBR MTU2.TCBR -#define MTU2TGRC_3 MTU2.TGRC_3 -#define MTU2TGRD_3 MTU2.TGRD_3 -#define MTU2TGRC_4 MTU2.TGRC_4 -#define MTU2TGRD_4 MTU2.TGRD_4 -#define MTU2TSR_3 MTU2.TSR_3 -#define MTU2TSR_4 MTU2.TSR_4 -#define MTU2TITCR MTU2.TITCR -#define MTU2TITCNT MTU2.TITCNT -#define MTU2TBTER MTU2.TBTER -#define MTU2TDER MTU2.TDER -#define MTU2TOLBR MTU2.TOLBR -#define MTU2TBTM_3 MTU2.TBTM_3 -#define MTU2TBTM_4 MTU2.TBTM_4 -#define MTU2TADCR MTU2.TADCR -#define MTU2TADCORA_4 MTU2.TADCORA_4 -#define MTU2TADCORB_4 MTU2.TADCORB_4 -#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4 -#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4 -#define MTU2TWCR MTU2.TWCR -#define MTU2TSTR MTU2.TSTR -#define MTU2TSYR MTU2.TSYR -#define MTU2TRWER MTU2.TRWER -#define MTU2TCR_0 MTU2.TCR_0 -#define MTU2TMDR_0 MTU2.TMDR_0 -#define MTU2TIORH_0 MTU2.TIORH_0 -#define MTU2TIORL_0 MTU2.TIORL_0 -#define MTU2TIER_0 MTU2.TIER_0 -#define MTU2TSR_0 MTU2.TSR_0 -#define MTU2TCNT_0 MTU2.TCNT_0 -#define MTU2TGRA_0 MTU2.TGRA_0 -#define MTU2TGRB_0 MTU2.TGRB_0 -#define MTU2TGRC_0 MTU2.TGRC_0 -#define MTU2TGRD_0 MTU2.TGRD_0 -#define MTU2TGRE_0 MTU2.TGRE_0 -#define MTU2TGRF_0 MTU2.TGRF_0 -#define MTU2TIER2_0 MTU2.TIER2_0 -#define MTU2TSR2_0 MTU2.TSR2_0 -#define MTU2TBTM_0 MTU2.TBTM_0 -#define MTU2TCR_1 MTU2.TCR_1 -#define MTU2TMDR_1 MTU2.TMDR_1 -#define MTU2TIOR_1 MTU2.TIOR_1 -#define MTU2TIER_1 MTU2.TIER_1 -#define MTU2TSR_1 MTU2.TSR_1 -#define MTU2TCNT_1 MTU2.TCNT_1 -#define MTU2TGRA_1 MTU2.TGRA_1 -#define MTU2TGRB_1 MTU2.TGRB_1 -#define MTU2TICCR MTU2.TICCR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h index b0aa5587db..f246dd3773 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h @@ -18,20 +18,55 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ostm_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef OSTM_IODEFINE_H #define OSTM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ostm -{ /* OSTM */ +#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ +#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ + + +/* Start of channel array defines of OSTM */ + +/* Channel array defines of OSTM */ +/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ +#define OSTM_COUNT (2) +#define OSTM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &OSTM0, &OSTM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of OSTM */ + + +#define OSTM0CMP (OSTM0.OSTMnCMP) +#define OSTM0CNT (OSTM0.OSTMnCNT) +#define OSTM0TE (OSTM0.OSTMnTE) +#define OSTM0TS (OSTM0.OSTMnTS) +#define OSTM0TT (OSTM0.OSTMnTT) +#define OSTM0CTL (OSTM0.OSTMnCTL) +#define OSTM1CMP (OSTM1.OSTMnCMP) +#define OSTM1CNT (OSTM1.OSTMnCNT) +#define OSTM1TE (OSTM1.OSTMnTE) +#define OSTM1TS (OSTM1.OSTMnTS) +#define OSTM1TT (OSTM1.OSTMnTT) +#define OSTM1CTL (OSTM1.OSTMnCTL) + + +typedef struct st_ostm +{ + /* OSTM */ volatile uint32_t OSTMnCMP; /* OSTMnCMP */ volatile uint32_t OSTMnCNT; /* OSTMnCNT */ volatile uint8_t dummy1[8]; /* */ @@ -42,37 +77,21 @@ struct st_ostm volatile uint8_t OSTMnTT; /* OSTMnTT */ volatile uint8_t dummy4[7]; /* */ volatile uint8_t OSTMnCTL; /* OSTMnCTL */ -}; +} r_io_ostm_t; -#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */ -#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */ +/* Channel array defines of OSTM (2)*/ +#ifdef DECLARE_OSTM_CHANNELS +volatile struct st_ostm* OSTM[ OSTM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + OSTM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_OSTM_CHANNELS */ +/* End of channel array defines of OSTM (2)*/ -/* Start of channnel array defines of OSTM */ - -/* Channnel array defines of OSTM */ -/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */ -#define OSTM_COUNT 2 -#define OSTM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &OSTM0, &OSTM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of OSTM */ - - -#define OSTM0CMP OSTM0.OSTMnCMP -#define OSTM0CNT OSTM0.OSTMnCNT -#define OSTM0TE OSTM0.OSTMnTE -#define OSTM0TS OSTM0.OSTMnTS -#define OSTM0TT OSTM0.OSTMnTT -#define OSTM0CTL OSTM0.OSTMnCTL -#define OSTM1CMP OSTM1.OSTMnCMP -#define OSTM1CNT OSTM1.OSTMnCNT -#define OSTM1TE OSTM1.OSTMnTE -#define OSTM1TS OSTM1.OSTMnTS -#define OSTM1TT OSTM1.OSTMnTT -#define OSTM1CTL OSTM1.OSTMnCTL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h index 230dd62947..e62a51cca3 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h @@ -18,25 +18,112 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : pfv_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef PFV_IODEFINE_H #define PFV_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_pfv -{ /* PFV */ +#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ +#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ + + +/* Start of channel array defines of PFV */ + +/* Channel array defines of PFV */ +/*(Sample) value = PFV[ channel ]->PFVCR; */ +#define PFV_COUNT (2) +#define PFV_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &PFV0, &PFV1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of PFV */ + + +#define PFV0PFVCR (PFV0.PFVCR) +#define PFV0PFVICR (PFV0.PFVICR) +#define PFV0PFVISR (PFV0.PFVISR) +#define PFV0PFVID0 (PFV0.PFVID0) +#define PFV0PFVID1 (PFV0.PFVID1) +#define PFV0PFVID2 (PFV0.PFVID2) +#define PFV0PFVID3 (PFV0.PFVID3) +#define PFV0PFVID4 (PFV0.PFVID4) +#define PFV0PFVID5 (PFV0.PFVID5) +#define PFV0PFVID6 (PFV0.PFVID6) +#define PFV0PFVID7 (PFV0.PFVID7) +#define PFV0PFVOD0 (PFV0.PFVOD0) +#define PFV0PFVOD1 (PFV0.PFVOD1) +#define PFV0PFVOD2 (PFV0.PFVOD2) +#define PFV0PFVOD3 (PFV0.PFVOD3) +#define PFV0PFVOD4 (PFV0.PFVOD4) +#define PFV0PFVOD5 (PFV0.PFVOD5) +#define PFV0PFVOD6 (PFV0.PFVOD6) +#define PFV0PFVOD7 (PFV0.PFVOD7) +#define PFV0PFVIFSR (PFV0.PFVIFSR) +#define PFV0PFVOFSR (PFV0.PFVOFSR) +#define PFV0PFVACR (PFV0.PFVACR) +#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE) +#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0) +#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1) +#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0) +#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1) +#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0) +#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1) +#define PFV0PFVSZR (PFV0.PFVSZR) +#define PFV1PFVCR (PFV1.PFVCR) +#define PFV1PFVICR (PFV1.PFVICR) +#define PFV1PFVISR (PFV1.PFVISR) +#define PFV1PFVID0 (PFV1.PFVID0) +#define PFV1PFVID1 (PFV1.PFVID1) +#define PFV1PFVID2 (PFV1.PFVID2) +#define PFV1PFVID3 (PFV1.PFVID3) +#define PFV1PFVID4 (PFV1.PFVID4) +#define PFV1PFVID5 (PFV1.PFVID5) +#define PFV1PFVID6 (PFV1.PFVID6) +#define PFV1PFVID7 (PFV1.PFVID7) +#define PFV1PFVOD0 (PFV1.PFVOD0) +#define PFV1PFVOD1 (PFV1.PFVOD1) +#define PFV1PFVOD2 (PFV1.PFVOD2) +#define PFV1PFVOD3 (PFV1.PFVOD3) +#define PFV1PFVOD4 (PFV1.PFVOD4) +#define PFV1PFVOD5 (PFV1.PFVOD5) +#define PFV1PFVOD6 (PFV1.PFVOD6) +#define PFV1PFVOD7 (PFV1.PFVOD7) +#define PFV1PFVIFSR (PFV1.PFVIFSR) +#define PFV1PFVOFSR (PFV1.PFVOFSR) +#define PFV1PFVACR (PFV1.PFVACR) +#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE) +#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0) +#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1) +#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0) +#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1) +#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0) +#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1) +#define PFV1PFVSZR (PFV1.PFVSZR) + +#define PFVID_COUNT (8) +#define PFVOD_COUNT (8) + + +typedef struct st_pfv +{ + /* PFV */ volatile uint32_t PFVCR; /* PFVCR */ volatile uint32_t PFVICR; /* PFVICR */ volatile uint32_t PFVISR; /* PFVISR */ volatile uint8_t dummy1[20]; /* */ -#define PFVID_COUNT 8 + +/* #define PFVID_COUNT (8) */ volatile uint32_t PFVID0; /* PFVID0 */ volatile uint32_t PFVID1; /* PFVID1 */ volatile uint32_t PFVID2; /* PFVID2 */ @@ -45,7 +132,8 @@ struct st_pfv volatile uint32_t PFVID5; /* PFVID5 */ volatile uint32_t PFVID6; /* PFVID6 */ volatile uint32_t PFVID7; /* PFVID7 */ -#define PFVOD_COUNT 8 + +/* #define PFVOD_COUNT (8) */ volatile uint32_t PFVOD0; /* PFVOD0 */ volatile uint32_t PFVOD1; /* PFVOD1 */ volatile uint32_t PFVOD2; /* PFVOD2 */ @@ -66,85 +154,21 @@ struct st_pfv volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */ volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */ volatile uint32_t PFVSZR; /* PFVSZR */ -}; +} r_io_pfv_t; -#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */ -#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */ +/* Channel array defines of PFV (2)*/ +#ifdef DECLARE_PFV_CHANNELS +volatile struct st_pfv* PFV[ PFV_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + PFV_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_PFV_CHANNELS */ +/* End of channel array defines of PFV (2)*/ -/* Start of channnel array defines of PFV */ - -/* Channnel array defines of PFV */ -/*(Sample) value = PFV[ channel ]->PFVCR; */ -#define PFV_COUNT 2 -#define PFV_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &PFV0, &PFV1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of PFV */ - - -#define PFV0PFVCR PFV0.PFVCR -#define PFV0PFVICR PFV0.PFVICR -#define PFV0PFVISR PFV0.PFVISR -#define PFV0PFVID0 PFV0.PFVID0 -#define PFV0PFVID1 PFV0.PFVID1 -#define PFV0PFVID2 PFV0.PFVID2 -#define PFV0PFVID3 PFV0.PFVID3 -#define PFV0PFVID4 PFV0.PFVID4 -#define PFV0PFVID5 PFV0.PFVID5 -#define PFV0PFVID6 PFV0.PFVID6 -#define PFV0PFVID7 PFV0.PFVID7 -#define PFV0PFVOD0 PFV0.PFVOD0 -#define PFV0PFVOD1 PFV0.PFVOD1 -#define PFV0PFVOD2 PFV0.PFVOD2 -#define PFV0PFVOD3 PFV0.PFVOD3 -#define PFV0PFVOD4 PFV0.PFVOD4 -#define PFV0PFVOD5 PFV0.PFVOD5 -#define PFV0PFVOD6 PFV0.PFVOD6 -#define PFV0PFVOD7 PFV0.PFVOD7 -#define PFV0PFVIFSR PFV0.PFVIFSR -#define PFV0PFVOFSR PFV0.PFVOFSR -#define PFV0PFVACR PFV0.PFVACR -#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE -#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0 -#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1 -#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0 -#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1 -#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0 -#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1 -#define PFV0PFVSZR PFV0.PFVSZR -#define PFV1PFVCR PFV1.PFVCR -#define PFV1PFVICR PFV1.PFVICR -#define PFV1PFVISR PFV1.PFVISR -#define PFV1PFVID0 PFV1.PFVID0 -#define PFV1PFVID1 PFV1.PFVID1 -#define PFV1PFVID2 PFV1.PFVID2 -#define PFV1PFVID3 PFV1.PFVID3 -#define PFV1PFVID4 PFV1.PFVID4 -#define PFV1PFVID5 PFV1.PFVID5 -#define PFV1PFVID6 PFV1.PFVID6 -#define PFV1PFVID7 PFV1.PFVID7 -#define PFV1PFVOD0 PFV1.PFVOD0 -#define PFV1PFVOD1 PFV1.PFVOD1 -#define PFV1PFVOD2 PFV1.PFVOD2 -#define PFV1PFVOD3 PFV1.PFVOD3 -#define PFV1PFVOD4 PFV1.PFVOD4 -#define PFV1PFVOD5 PFV1.PFVOD5 -#define PFV1PFVOD6 PFV1.PFVOD6 -#define PFV1PFVOD7 PFV1.PFVOD7 -#define PFV1PFVIFSR PFV1.PFVIFSR -#define PFV1PFVOFSR PFV1.PFVOFSR -#define PFV1PFVACR PFV1.PFVACR -#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE -#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0 -#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1 -#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0 -#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1 -#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0 -#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1 -#define PFV1PFVSZR PFV1.PFVSZR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h index a7143d481d..128b1099d8 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h @@ -18,83 +18,29 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : pwm_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef PWM_IODEFINE_H #define PWM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -union reg16_8_t -{ - volatile uint16_t UINT16; /* 16-bit Access */ - volatile uint8_t UINT8[2]; /* 8-bit Access */ -}; - -struct st_pwm -{ /* PWM */ - volatile uint8_t dummy559[2]; /* */ - union reg16_8_t PWBTCR; /* PWBTCR */ - - volatile uint8_t dummy560[216]; /* */ - -/* start of struct st_pwm_common */ - union reg16_8_t PWCR_1; /* PWCR_1 */ - - volatile uint8_t dummy561[2]; /* */ - union reg16_8_t PWPR_1; /* PWPR_1 */ - - volatile uint16_t PWCYR_1; /* PWCYR_1 */ - volatile uint16_t PWBFR_1A; /* PWBFR_1A */ - volatile uint16_t PWBFR_1C; /* PWBFR_1C */ - volatile uint16_t PWBFR_1E; /* PWBFR_1E */ - volatile uint16_t PWBFR_1G; /* PWBFR_1G */ -/* end of struct st_pwm_common */ - -/* start of struct st_pwm_common */ - union reg16_8_t PWCR_2; /* PWCR_2 */ - - volatile uint8_t dummy562[2]; /* */ - union reg16_8_t PWPR_2; /* PWPR_2 */ - - volatile uint16_t PWCYR_2; /* PWCYR_2 */ - volatile uint16_t PWBFR_2A; /* PWBFR_2A */ - volatile uint16_t PWBFR_2C; /* PWBFR_2C */ - volatile uint16_t PWBFR_2E; /* PWBFR_2E */ - volatile uint16_t PWBFR_2G; /* PWBFR_2G */ -/* end of struct st_pwm_common */ -}; - - -struct st_pwm_common -{ - union reg16_8_t PWCR_1; /* PWCR_1 */ - - volatile uint8_t dummy572[2]; /* */ - union reg16_8_t PWPR_1; /* PWPR_1 */ - - volatile uint16_t PWCYR_1; /* PWCYR_1 */ - volatile uint16_t PWBFR_1A; /* PWBFR_1A */ - volatile uint16_t PWBFR_1C; /* PWBFR_1C */ - volatile uint16_t PWBFR_1E; /* PWBFR_1E */ - volatile uint16_t PWBFR_1G; /* PWBFR_1G */ -}; - - #define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */ -/* Start of channnel array defines of PWM */ +/* Start of channel array defines of PWM */ -/* Channnel array defines of PWMn */ -/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */ -#define PWMn_COUNT 2 +/* Channel array defines of PWMn */ +/*(Sample) value = PWMn[ channel ]->PWCR_1; */ +#define PWMn_COUNT (2) #define PWMn_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &PWM1, &PWM2 \ @@ -102,34 +48,88 @@ struct st_pwm_common #define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */ #define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */ -/* End of channnel array defines of PWM */ +/* End of channel array defines of PWM */ + + +#define PWMPWBTCR (PWM.PWBTCR) +#define PWMPWCR_1 (PWM.PWCR_1) +#define PWMPWPR_1 (PWM.PWPR_1) +#define PWMPWCYR_1 (PWM.PWCYR_1) +#define PWMPWBFR_1A (PWM.PWBFR_1A) +#define PWMPWBFR_1C (PWM.PWBFR_1C) +#define PWMPWBFR_1E (PWM.PWBFR_1E) +#define PWMPWBFR_1G (PWM.PWBFR_1G) +#define PWMPWCR_2 (PWM.PWCR_2) +#define PWMPWPR_2 (PWM.PWPR_2) +#define PWMPWCYR_2 (PWM.PWCYR_2) +#define PWMPWBFR_2A (PWM.PWBFR_2A) +#define PWMPWBFR_2C (PWM.PWBFR_2C) +#define PWMPWBFR_2E (PWM.PWBFR_2E) +#define PWMPWBFR_2G (PWM.PWBFR_2G) + + +typedef struct st_pwm +{ + /* PWM */ + volatile uint8_t dummy559[2]; /* */ + volatile uint8_t PWBTCR; /* PWBTCR */ + volatile uint8_t dummy560[217]; /* */ + +/* start of struct st_pwm_common */ + volatile uint8_t PWCR_1; /* PWCR_1 */ + volatile uint8_t dummy561[3]; /* */ + volatile uint8_t PWPR_1; /* PWPR_1 */ + volatile uint8_t dummy562[1]; /* */ + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ + +/* end of struct st_pwm_common */ + +/* start of struct st_pwm_common */ + volatile uint8_t PWCR_2; /* PWCR_2 */ + volatile uint8_t dummy563[3]; /* */ + volatile uint8_t PWPR_2; /* PWPR_2 */ + volatile uint8_t dummy564[1]; /* */ + volatile uint16_t PWCYR_2; /* PWCYR_2 */ + volatile uint16_t PWBFR_2A; /* PWBFR_2A */ + volatile uint16_t PWBFR_2C; /* PWBFR_2C */ + volatile uint16_t PWBFR_2E; /* PWBFR_2E */ + volatile uint16_t PWBFR_2G; /* PWBFR_2G */ + +/* end of struct st_pwm_common */ +} r_io_pwm_t; + + +typedef struct st_pwm_common +{ + + volatile uint8_t PWCR_1; /* PWCR_1 */ + volatile uint8_t dummy562[3]; /* */ + volatile uint8_t PWPR_1; /* PWPR_1 */ + volatile uint8_t dummy563[1]; /* */ + volatile uint16_t PWCYR_1; /* PWCYR_1 */ + volatile uint16_t PWBFR_1A; /* PWBFR_1A */ + volatile uint16_t PWBFR_1C; /* PWBFR_1C */ + volatile uint16_t PWBFR_1E; /* PWBFR_1E */ + volatile uint16_t PWBFR_1G; /* PWBFR_1G */ +} r_io_pwm_common_t; + + +/* Channel array defines of PWMn (2)*/ +#ifdef DECLARE_PWMn_CHANNELS +volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + PWMn_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_PWMn_CHANNELS */ +/* End of channel array defines of PWMn (2)*/ -#define PWMPWBTCR PWM.PWBTCR.UINT16 -#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0] -#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1] -#define PWMPWCR_1 PWM.PWCR_1.UINT16 -#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0] -#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1] -#define PWMPWPR_1 PWM.PWPR_1.UINT16 -#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0] -#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1] -#define PWMPWCYR_1 PWM.PWCYR_1 -#define PWMPWBFR_1A PWM.PWBFR_1A -#define PWMPWBFR_1C PWM.PWBFR_1C -#define PWMPWBFR_1E PWM.PWBFR_1E -#define PWMPWBFR_1G PWM.PWBFR_1G -#define PWMPWCR_2 PWM.PWCR_2.UINT16 -#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0] -#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1] -#define PWMPWPR_2 PWM.PWPR_2.UINT16 -#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0] -#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1] -#define PWMPWCYR_2 PWM.PWCYR_2 -#define PWMPWBFR_2A PWM.PWBFR_2A -#define PWMPWBFR_2C PWM.PWBFR_2C -#define PWMPWBFR_2E PWM.PWBFR_2E -#define PWMPWBFR_2G PWM.PWBFR_2G /* <-SEC M1.10.1 */ /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h index 9daefe447a..8fd2be68db 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h @@ -18,45 +18,20 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : riic_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RIIC_IODEFINE_H #define RIIC_IODEFINE_H - -#include "reg32_t.h" - -struct st_riic -{ /* RIIC */ -#define RIICnCRm_COUNT 2 - union reg32_t RIICnCR1; /* RIICnCR1 */ - union reg32_t RIICnCR2; /* RIICnCR2 */ -#define RIICnMRm_COUNT 3 - union reg32_t RIICnMR1; /* RIICnMR1 */ - union reg32_t RIICnMR2; /* RIICnMR2 */ - union reg32_t RIICnMR3; /* RIICnMR3 */ - union reg32_t RIICnFER; /* RIICnFER */ - union reg32_t RIICnSER; /* RIICnSER */ - union reg32_t RIICnIER; /* RIICnIER */ -#define RIICnSRm_COUNT 2 - union reg32_t RIICnSR1; /* RIICnSR1 */ - union reg32_t RIICnSR2; /* RIICnSR2 */ -#define RIICnSARm_COUNT 3 - union reg32_t RIICnSAR0; /* RIICnSAR0 */ - union reg32_t RIICnSAR1; /* RIICnSAR1 */ - union reg32_t RIICnSAR2; /* RIICnSAR2 */ - union reg32_t RIICnBRL; /* RIICnBRL */ - union reg32_t RIICnBRH; /* RIICnBRH */ - union reg32_t RIICnDRT; /* RIICnDRT */ - union reg32_t RIICnDRR; /* RIICnDRR */ - -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */ #define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */ @@ -64,493 +39,546 @@ struct st_riic #define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */ -/* Start of channnel array defines of RIIC */ +/* Start of channel array defines of RIIC */ -/* Channnel array defines of RIIC */ +/* Channel array defines of RIIC */ /*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */ -#define RIIC_COUNT 4 +#define RIIC_COUNT (4) #define RIIC_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RIIC0, &RIIC1, &RIIC2, &RIIC3 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of RIIC */ +/* End of channel array defines of RIIC */ -#define RIIC0CR1 RIIC0.RIICnCR1.UINT32 -#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L] -#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL] -#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH] -#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H] -#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL] -#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH] -#define RIIC0CR2 RIIC0.RIICnCR2.UINT32 -#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L] -#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL] -#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH] -#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H] -#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL] -#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH] -#define RIIC0MR1 RIIC0.RIICnMR1.UINT32 -#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L] -#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL] -#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH] -#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H] -#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL] -#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH] -#define RIIC0MR2 RIIC0.RIICnMR2.UINT32 -#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L] -#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL] -#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH] -#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H] -#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL] -#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH] -#define RIIC0MR3 RIIC0.RIICnMR3.UINT32 -#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L] -#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL] -#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH] -#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H] -#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL] -#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH] -#define RIIC0FER RIIC0.RIICnFER.UINT32 -#define RIIC0FERL RIIC0.RIICnFER.UINT16[L] -#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL] -#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH] -#define RIIC0FERH RIIC0.RIICnFER.UINT16[H] -#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL] -#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH] -#define RIIC0SER RIIC0.RIICnSER.UINT32 -#define RIIC0SERL RIIC0.RIICnSER.UINT16[L] -#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL] -#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH] -#define RIIC0SERH RIIC0.RIICnSER.UINT16[H] -#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL] -#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH] -#define RIIC0IER RIIC0.RIICnIER.UINT32 -#define RIIC0IERL RIIC0.RIICnIER.UINT16[L] -#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL] -#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH] -#define RIIC0IERH RIIC0.RIICnIER.UINT16[H] -#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL] -#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH] -#define RIIC0SR1 RIIC0.RIICnSR1.UINT32 -#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L] -#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL] -#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH] -#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H] -#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL] -#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH] -#define RIIC0SR2 RIIC0.RIICnSR2.UINT32 -#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L] -#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL] -#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH] -#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H] -#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL] -#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH] -#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32 -#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L] -#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL] -#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH] -#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H] -#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL] -#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH] -#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32 -#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L] -#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL] -#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH] -#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H] -#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL] -#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH] -#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32 -#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L] -#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL] -#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH] -#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H] -#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL] -#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH] -#define RIIC0BRL RIIC0.RIICnBRL.UINT32 -#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L] -#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL] -#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH] -#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H] -#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL] -#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH] -#define RIIC0BRH RIIC0.RIICnBRH.UINT32 -#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L] -#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL] -#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH] -#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H] -#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL] -#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH] -#define RIIC0DRT RIIC0.RIICnDRT.UINT32 -#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L] -#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL] -#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH] -#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H] -#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL] -#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH] -#define RIIC0DRR RIIC0.RIICnDRR.UINT32 -#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L] -#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL] -#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH] -#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H] -#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL] -#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH] -#define RIIC1CR1 RIIC1.RIICnCR1.UINT32 -#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L] -#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL] -#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH] -#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H] -#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL] -#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH] -#define RIIC1CR2 RIIC1.RIICnCR2.UINT32 -#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L] -#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL] -#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH] -#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H] -#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL] -#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH] -#define RIIC1MR1 RIIC1.RIICnMR1.UINT32 -#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L] -#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL] -#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH] -#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H] -#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL] -#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH] -#define RIIC1MR2 RIIC1.RIICnMR2.UINT32 -#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L] -#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL] -#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH] -#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H] -#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL] -#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH] -#define RIIC1MR3 RIIC1.RIICnMR3.UINT32 -#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L] -#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL] -#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH] -#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H] -#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL] -#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH] -#define RIIC1FER RIIC1.RIICnFER.UINT32 -#define RIIC1FERL RIIC1.RIICnFER.UINT16[L] -#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL] -#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH] -#define RIIC1FERH RIIC1.RIICnFER.UINT16[H] -#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL] -#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH] -#define RIIC1SER RIIC1.RIICnSER.UINT32 -#define RIIC1SERL RIIC1.RIICnSER.UINT16[L] -#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL] -#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH] -#define RIIC1SERH RIIC1.RIICnSER.UINT16[H] -#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL] -#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH] -#define RIIC1IER RIIC1.RIICnIER.UINT32 -#define RIIC1IERL RIIC1.RIICnIER.UINT16[L] -#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL] -#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH] -#define RIIC1IERH RIIC1.RIICnIER.UINT16[H] -#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL] -#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH] -#define RIIC1SR1 RIIC1.RIICnSR1.UINT32 -#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L] -#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL] -#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH] -#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H] -#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL] -#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH] -#define RIIC1SR2 RIIC1.RIICnSR2.UINT32 -#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L] -#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL] -#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH] -#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H] -#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL] -#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH] -#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32 -#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L] -#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL] -#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH] -#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H] -#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL] -#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH] -#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32 -#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L] -#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL] -#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH] -#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H] -#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL] -#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH] -#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32 -#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L] -#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL] -#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH] -#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H] -#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL] -#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH] -#define RIIC1BRL RIIC1.RIICnBRL.UINT32 -#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L] -#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL] -#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH] -#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H] -#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL] -#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH] -#define RIIC1BRH RIIC1.RIICnBRH.UINT32 -#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L] -#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL] -#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH] -#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H] -#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL] -#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH] -#define RIIC1DRT RIIC1.RIICnDRT.UINT32 -#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L] -#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL] -#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH] -#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H] -#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL] -#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH] -#define RIIC1DRR RIIC1.RIICnDRR.UINT32 -#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L] -#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL] -#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH] -#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H] -#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL] -#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH] -#define RIIC2CR1 RIIC2.RIICnCR1.UINT32 -#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L] -#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL] -#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH] -#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H] -#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL] -#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH] -#define RIIC2CR2 RIIC2.RIICnCR2.UINT32 -#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L] -#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL] -#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH] -#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H] -#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL] -#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH] -#define RIIC2MR1 RIIC2.RIICnMR1.UINT32 -#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L] -#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL] -#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH] -#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H] -#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL] -#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH] -#define RIIC2MR2 RIIC2.RIICnMR2.UINT32 -#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L] -#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL] -#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH] -#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H] -#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL] -#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH] -#define RIIC2MR3 RIIC2.RIICnMR3.UINT32 -#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L] -#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL] -#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH] -#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H] -#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL] -#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH] -#define RIIC2FER RIIC2.RIICnFER.UINT32 -#define RIIC2FERL RIIC2.RIICnFER.UINT16[L] -#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL] -#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH] -#define RIIC2FERH RIIC2.RIICnFER.UINT16[H] -#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL] -#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH] -#define RIIC2SER RIIC2.RIICnSER.UINT32 -#define RIIC2SERL RIIC2.RIICnSER.UINT16[L] -#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL] -#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH] -#define RIIC2SERH RIIC2.RIICnSER.UINT16[H] -#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL] -#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH] -#define RIIC2IER RIIC2.RIICnIER.UINT32 -#define RIIC2IERL RIIC2.RIICnIER.UINT16[L] -#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL] -#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH] -#define RIIC2IERH RIIC2.RIICnIER.UINT16[H] -#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL] -#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH] -#define RIIC2SR1 RIIC2.RIICnSR1.UINT32 -#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L] -#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL] -#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH] -#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H] -#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL] -#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH] -#define RIIC2SR2 RIIC2.RIICnSR2.UINT32 -#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L] -#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL] -#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH] -#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H] -#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL] -#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH] -#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32 -#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L] -#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL] -#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH] -#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H] -#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL] -#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH] -#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32 -#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L] -#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL] -#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH] -#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H] -#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL] -#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH] -#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32 -#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L] -#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL] -#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH] -#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H] -#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL] -#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH] -#define RIIC2BRL RIIC2.RIICnBRL.UINT32 -#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L] -#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL] -#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH] -#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H] -#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL] -#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH] -#define RIIC2BRH RIIC2.RIICnBRH.UINT32 -#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L] -#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL] -#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH] -#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H] -#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL] -#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH] -#define RIIC2DRT RIIC2.RIICnDRT.UINT32 -#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L] -#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL] -#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH] -#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H] -#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL] -#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH] -#define RIIC2DRR RIIC2.RIICnDRR.UINT32 -#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L] -#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL] -#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH] -#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H] -#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL] -#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH] -#define RIIC3CR1 RIIC3.RIICnCR1.UINT32 -#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L] -#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL] -#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH] -#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H] -#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL] -#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH] -#define RIIC3CR2 RIIC3.RIICnCR2.UINT32 -#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L] -#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL] -#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH] -#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H] -#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL] -#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH] -#define RIIC3MR1 RIIC3.RIICnMR1.UINT32 -#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L] -#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL] -#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH] -#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H] -#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL] -#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH] -#define RIIC3MR2 RIIC3.RIICnMR2.UINT32 -#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L] -#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL] -#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH] -#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H] -#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL] -#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH] -#define RIIC3MR3 RIIC3.RIICnMR3.UINT32 -#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L] -#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL] -#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH] -#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H] -#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL] -#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH] -#define RIIC3FER RIIC3.RIICnFER.UINT32 -#define RIIC3FERL RIIC3.RIICnFER.UINT16[L] -#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL] -#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH] -#define RIIC3FERH RIIC3.RIICnFER.UINT16[H] -#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL] -#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH] -#define RIIC3SER RIIC3.RIICnSER.UINT32 -#define RIIC3SERL RIIC3.RIICnSER.UINT16[L] -#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL] -#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH] -#define RIIC3SERH RIIC3.RIICnSER.UINT16[H] -#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL] -#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH] -#define RIIC3IER RIIC3.RIICnIER.UINT32 -#define RIIC3IERL RIIC3.RIICnIER.UINT16[L] -#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL] -#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH] -#define RIIC3IERH RIIC3.RIICnIER.UINT16[H] -#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL] -#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH] -#define RIIC3SR1 RIIC3.RIICnSR1.UINT32 -#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L] -#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL] -#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH] -#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H] -#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL] -#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH] -#define RIIC3SR2 RIIC3.RIICnSR2.UINT32 -#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L] -#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL] -#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH] -#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H] -#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL] -#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH] -#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32 -#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L] -#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL] -#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH] -#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H] -#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL] -#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH] -#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32 -#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L] -#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL] -#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH] -#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H] -#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL] -#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH] -#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32 -#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L] -#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL] -#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH] -#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H] -#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL] -#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH] -#define RIIC3BRL RIIC3.RIICnBRL.UINT32 -#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L] -#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL] -#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH] -#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H] -#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL] -#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH] -#define RIIC3BRH RIIC3.RIICnBRH.UINT32 -#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L] -#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL] -#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH] -#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H] -#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL] -#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH] -#define RIIC3DRT RIIC3.RIICnDRT.UINT32 -#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L] -#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL] -#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH] -#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H] -#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL] -#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH] -#define RIIC3DRR RIIC3.RIICnDRR.UINT32 -#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L] -#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL] -#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH] -#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H] -#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL] -#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH] +#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32) +#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L]) +#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H]) +#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32) +#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L]) +#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H]) +#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32) +#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L]) +#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H]) +#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32) +#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L]) +#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H]) +#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32) +#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L]) +#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H]) +#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC0FER (RIIC0.RIICnFER.UINT32) +#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L]) +#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL]) +#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH]) +#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H]) +#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL]) +#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH]) +#define RIIC0SER (RIIC0.RIICnSER.UINT32) +#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L]) +#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL]) +#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH]) +#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H]) +#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL]) +#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH]) +#define RIIC0IER (RIIC0.RIICnIER.UINT32) +#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L]) +#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL]) +#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH]) +#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H]) +#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL]) +#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH]) +#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32) +#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L]) +#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H]) +#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32) +#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L]) +#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H]) +#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32) +#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32) +#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32) +#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC0BRL (RIIC0.RIICnBRL.UINT32) +#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L]) +#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H]) +#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC0BRH (RIIC0.RIICnBRH.UINT32) +#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L]) +#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H]) +#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC0DRT (RIIC0.RIICnDRT.UINT32) +#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L]) +#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H]) +#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC0DRR (RIIC0.RIICnDRR.UINT32) +#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L]) +#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H]) +#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32) +#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L]) +#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H]) +#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32) +#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L]) +#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H]) +#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32) +#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L]) +#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H]) +#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32) +#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L]) +#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H]) +#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32) +#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L]) +#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H]) +#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC1FER (RIIC1.RIICnFER.UINT32) +#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L]) +#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL]) +#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH]) +#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H]) +#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL]) +#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH]) +#define RIIC1SER (RIIC1.RIICnSER.UINT32) +#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L]) +#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL]) +#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH]) +#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H]) +#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL]) +#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH]) +#define RIIC1IER (RIIC1.RIICnIER.UINT32) +#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L]) +#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL]) +#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH]) +#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H]) +#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL]) +#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH]) +#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32) +#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L]) +#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H]) +#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32) +#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L]) +#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H]) +#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32) +#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32) +#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32) +#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC1BRL (RIIC1.RIICnBRL.UINT32) +#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L]) +#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H]) +#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC1BRH (RIIC1.RIICnBRH.UINT32) +#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L]) +#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H]) +#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC1DRT (RIIC1.RIICnDRT.UINT32) +#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L]) +#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H]) +#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC1DRR (RIIC1.RIICnDRR.UINT32) +#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L]) +#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H]) +#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32) +#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L]) +#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H]) +#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32) +#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L]) +#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H]) +#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32) +#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L]) +#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H]) +#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32) +#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L]) +#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H]) +#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32) +#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L]) +#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H]) +#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC2FER (RIIC2.RIICnFER.UINT32) +#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L]) +#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL]) +#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH]) +#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H]) +#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL]) +#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH]) +#define RIIC2SER (RIIC2.RIICnSER.UINT32) +#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L]) +#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL]) +#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH]) +#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H]) +#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL]) +#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH]) +#define RIIC2IER (RIIC2.RIICnIER.UINT32) +#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L]) +#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL]) +#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH]) +#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H]) +#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL]) +#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH]) +#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32) +#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L]) +#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H]) +#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32) +#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L]) +#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H]) +#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32) +#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32) +#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32) +#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC2BRL (RIIC2.RIICnBRL.UINT32) +#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L]) +#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H]) +#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC2BRH (RIIC2.RIICnBRH.UINT32) +#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L]) +#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H]) +#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC2DRT (RIIC2.RIICnDRT.UINT32) +#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L]) +#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H]) +#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC2DRR (RIIC2.RIICnDRR.UINT32) +#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L]) +#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H]) +#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH]) +#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32) +#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L]) +#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL]) +#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH]) +#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H]) +#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL]) +#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH]) +#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32) +#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L]) +#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL]) +#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH]) +#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H]) +#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL]) +#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH]) +#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32) +#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L]) +#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL]) +#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH]) +#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H]) +#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL]) +#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH]) +#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32) +#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L]) +#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL]) +#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH]) +#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H]) +#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL]) +#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH]) +#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32) +#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L]) +#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL]) +#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH]) +#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H]) +#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL]) +#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH]) +#define RIIC3FER (RIIC3.RIICnFER.UINT32) +#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L]) +#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL]) +#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH]) +#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H]) +#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL]) +#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH]) +#define RIIC3SER (RIIC3.RIICnSER.UINT32) +#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L]) +#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL]) +#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH]) +#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H]) +#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL]) +#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH]) +#define RIIC3IER (RIIC3.RIICnIER.UINT32) +#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L]) +#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL]) +#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH]) +#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H]) +#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL]) +#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH]) +#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32) +#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L]) +#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL]) +#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH]) +#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H]) +#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL]) +#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH]) +#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32) +#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L]) +#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL]) +#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH]) +#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H]) +#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL]) +#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH]) +#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32) +#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L]) +#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL]) +#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH]) +#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H]) +#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL]) +#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH]) +#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32) +#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L]) +#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL]) +#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH]) +#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H]) +#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL]) +#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH]) +#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32) +#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L]) +#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL]) +#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH]) +#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H]) +#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL]) +#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH]) +#define RIIC3BRL (RIIC3.RIICnBRL.UINT32) +#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L]) +#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL]) +#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH]) +#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H]) +#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL]) +#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH]) +#define RIIC3BRH (RIIC3.RIICnBRH.UINT32) +#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L]) +#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL]) +#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH]) +#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H]) +#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL]) +#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH]) +#define RIIC3DRT (RIIC3.RIICnDRT.UINT32) +#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L]) +#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL]) +#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH]) +#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H]) +#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL]) +#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH]) +#define RIIC3DRR (RIIC3.RIICnDRR.UINT32) +#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L]) +#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL]) +#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH]) +#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H]) +#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL]) +#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH]) + +#define RIICnCRm_COUNT (2) +#define RIICnMRm_COUNT (3) +#define RIICnSRm_COUNT (2) +#define RIICnSARm_COUNT (3) + + +typedef struct st_riic +{ + /* RIIC */ + +/* #define RIICnCRm_COUNT (2) */ + union iodefine_reg32_t RIICnCR1; /* RIICnCR1 */ + union iodefine_reg32_t RIICnCR2; /* RIICnCR2 */ + +/* #define RIICnMRm_COUNT (3) */ + union iodefine_reg32_t RIICnMR1; /* RIICnMR1 */ + union iodefine_reg32_t RIICnMR2; /* RIICnMR2 */ + union iodefine_reg32_t RIICnMR3; /* RIICnMR3 */ + union iodefine_reg32_t RIICnFER; /* RIICnFER */ + union iodefine_reg32_t RIICnSER; /* RIICnSER */ + union iodefine_reg32_t RIICnIER; /* RIICnIER */ + +/* #define RIICnSRm_COUNT (2) */ + union iodefine_reg32_t RIICnSR1; /* RIICnSR1 */ + union iodefine_reg32_t RIICnSR2; /* RIICnSR2 */ + +/* #define RIICnSARm_COUNT (3) */ + union iodefine_reg32_t RIICnSAR0; /* RIICnSAR0 */ + union iodefine_reg32_t RIICnSAR1; /* RIICnSAR1 */ + union iodefine_reg32_t RIICnSAR2; /* RIICnSAR2 */ + union iodefine_reg32_t RIICnBRL; /* RIICnBRL */ + union iodefine_reg32_t RIICnBRH; /* RIICnBRH */ + union iodefine_reg32_t RIICnDRT; /* RIICnDRT */ + union iodefine_reg32_t RIICnDRR; /* RIICnDRR */ + +} r_io_riic_t; + + +/* Channel array defines of RIIC (2)*/ +#ifdef DECLARE_RIIC_CHANNELS +volatile struct st_riic* RIIC[ RIIC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RIIC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RIIC_CHANNELS */ +/* End of channel array defines of RIIC (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h index cfcfda568d..7d6a207693 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h @@ -18,30 +18,104 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : romdec_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef ROMDEC_IODEFINE_H #define ROMDEC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_romdec -{ /* ROMDEC */ +#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ + + +#define ROMDECCROMEN (ROMDEC.CROMEN) +#define ROMDECCROMSY0 (ROMDEC.CROMSY0) +#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0) +#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1) +#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3) +#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4) +#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5) +#define ROMDECCROMST0 (ROMDEC.CROMST0) +#define ROMDECCROMST1 (ROMDEC.CROMST1) +#define ROMDECCROMST3 (ROMDEC.CROMST3) +#define ROMDECCROMST4 (ROMDEC.CROMST4) +#define ROMDECCROMST5 (ROMDEC.CROMST5) +#define ROMDECCROMST6 (ROMDEC.CROMST6) +#define ROMDECCBUFST0 (ROMDEC.CBUFST0) +#define ROMDECCBUFST1 (ROMDEC.CBUFST1) +#define ROMDECCBUFST2 (ROMDEC.CBUFST2) +#define ROMDECHEAD00 (ROMDEC.HEAD00) +#define ROMDECHEAD01 (ROMDEC.HEAD01) +#define ROMDECHEAD02 (ROMDEC.HEAD02) +#define ROMDECHEAD03 (ROMDEC.HEAD03) +#define ROMDECSHEAD00 (ROMDEC.SHEAD00) +#define ROMDECSHEAD01 (ROMDEC.SHEAD01) +#define ROMDECSHEAD02 (ROMDEC.SHEAD02) +#define ROMDECSHEAD03 (ROMDEC.SHEAD03) +#define ROMDECSHEAD04 (ROMDEC.SHEAD04) +#define ROMDECSHEAD05 (ROMDEC.SHEAD05) +#define ROMDECSHEAD06 (ROMDEC.SHEAD06) +#define ROMDECSHEAD07 (ROMDEC.SHEAD07) +#define ROMDECHEAD20 (ROMDEC.HEAD20) +#define ROMDECHEAD21 (ROMDEC.HEAD21) +#define ROMDECHEAD22 (ROMDEC.HEAD22) +#define ROMDECHEAD23 (ROMDEC.HEAD23) +#define ROMDECSHEAD20 (ROMDEC.SHEAD20) +#define ROMDECSHEAD21 (ROMDEC.SHEAD21) +#define ROMDECSHEAD22 (ROMDEC.SHEAD22) +#define ROMDECSHEAD23 (ROMDEC.SHEAD23) +#define ROMDECSHEAD24 (ROMDEC.SHEAD24) +#define ROMDECSHEAD25 (ROMDEC.SHEAD25) +#define ROMDECSHEAD26 (ROMDEC.SHEAD26) +#define ROMDECSHEAD27 (ROMDEC.SHEAD27) +#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0) +#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1) +#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2) +#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3) +#define ROMDECCROMST0M (ROMDEC.CROMST0M) +#define ROMDECROMDECRST (ROMDEC.ROMDECRST) +#define ROMDECRSTSTAT (ROMDEC.RSTSTAT) +#define ROMDECSSI (ROMDEC.SSI) +#define ROMDECINTHOLD (ROMDEC.INTHOLD) +#define ROMDECINHINT (ROMDEC.INHINT) +#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0) +#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2) +#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0) + +#define ROMDEC_CROMCTL0_COUNT (2) +#define ROMDEC_CROMST0_COUNT (2) +#define ROMDEC_CBUFST0_COUNT (3) +#define ROMDEC_HEAD00_COUNT (4) +#define ROMDEC_SHEAD00_COUNT (8) +#define ROMDEC_HEAD20_COUNT (4) +#define ROMDEC_SHEAD20_COUNT (8) +#define ROMDEC_CBUFCTL0_COUNT (4) +#define ROMDEC_STRMDIN0_COUNT (2) + + +typedef struct st_romdec +{ + /* ROMDEC */ volatile uint8_t CROMEN; /* CROMEN */ volatile uint8_t CROMSY0; /* CROMSY0 */ -#define ROMDEC_CROMCTL0_COUNT 2 + +/* #define ROMDEC_CROMCTL0_COUNT (2) */ volatile uint8_t CROMCTL0; /* CROMCTL0 */ volatile uint8_t CROMCTL1; /* CROMCTL1 */ volatile uint8_t dummy23[1]; /* */ volatile uint8_t CROMCTL3; /* CROMCTL3 */ volatile uint8_t CROMCTL4; /* CROMCTL4 */ volatile uint8_t CROMCTL5; /* CROMCTL5 */ -#define ROMDEC_CROMST0_COUNT 2 + +/* #define ROMDEC_CROMST0_COUNT (2) */ volatile uint8_t CROMST0; /* CROMST0 */ volatile uint8_t CROMST1; /* CROMST1 */ volatile uint8_t dummy24[1]; /* */ @@ -50,17 +124,20 @@ struct st_romdec volatile uint8_t CROMST5; /* CROMST5 */ volatile uint8_t CROMST6; /* CROMST6 */ volatile uint8_t dummy25[5]; /* */ -#define ROMDEC_CBUFST0_COUNT 3 + +/* #define ROMDEC_CBUFST0_COUNT (3) */ volatile uint8_t CBUFST0; /* CBUFST0 */ volatile uint8_t CBUFST1; /* CBUFST1 */ volatile uint8_t CBUFST2; /* CBUFST2 */ volatile uint8_t dummy26[1]; /* */ -#define ROMDEC_HEAD00_COUNT 4 + +/* #define ROMDEC_HEAD00_COUNT (4) */ volatile uint8_t HEAD00; /* HEAD00 */ volatile uint8_t HEAD01; /* HEAD01 */ volatile uint8_t HEAD02; /* HEAD02 */ volatile uint8_t HEAD03; /* HEAD03 */ -#define ROMDEC_SHEAD00_COUNT 8 + +/* #define ROMDEC_SHEAD00_COUNT (8) */ volatile uint8_t SHEAD00; /* SHEAD00 */ volatile uint8_t SHEAD01; /* SHEAD01 */ volatile uint8_t SHEAD02; /* SHEAD02 */ @@ -69,12 +146,14 @@ struct st_romdec volatile uint8_t SHEAD05; /* SHEAD05 */ volatile uint8_t SHEAD06; /* SHEAD06 */ volatile uint8_t SHEAD07; /* SHEAD07 */ -#define ROMDEC_HEAD20_COUNT 4 + +/* #define ROMDEC_HEAD20_COUNT (4) */ volatile uint8_t HEAD20; /* HEAD20 */ volatile uint8_t HEAD21; /* HEAD21 */ volatile uint8_t HEAD22; /* HEAD22 */ volatile uint8_t HEAD23; /* HEAD23 */ -#define ROMDEC_SHEAD20_COUNT 8 + +/* #define ROMDEC_SHEAD20_COUNT (8) */ volatile uint8_t SHEAD20; /* SHEAD20 */ volatile uint8_t SHEAD21; /* SHEAD21 */ volatile uint8_t SHEAD22; /* SHEAD22 */ @@ -84,7 +163,8 @@ struct st_romdec volatile uint8_t SHEAD26; /* SHEAD26 */ volatile uint8_t SHEAD27; /* SHEAD27 */ volatile uint8_t dummy27[16]; /* */ -#define ROMDEC_CBUFCTL0_COUNT 4 + +/* #define ROMDEC_CBUFCTL0_COUNT (4) */ volatile uint8_t CBUFCTL0; /* CBUFCTL0 */ volatile uint8_t CBUFCTL1; /* CBUFCTL1 */ volatile uint8_t CBUFCTL2; /* CBUFCTL2 */ @@ -99,68 +179,16 @@ struct st_romdec volatile uint8_t INTHOLD; /* INTHOLD */ volatile uint8_t INHINT; /* INHINT */ volatile uint8_t dummy31[246]; /* */ -#define ROMDEC_STRMDIN0_COUNT 2 + +/* #define ROMDEC_STRMDIN0_COUNT (2) */ volatile uint16_t STRMDIN0; /* STRMDIN0 */ volatile uint16_t STRMDIN2; /* STRMDIN2 */ volatile uint16_t STRMDOUT0; /* STRMDOUT0 */ -}; +} r_io_romdec_t; -#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */ - - -#define ROMDECCROMEN ROMDEC.CROMEN -#define ROMDECCROMSY0 ROMDEC.CROMSY0 -#define ROMDECCROMCTL0 ROMDEC.CROMCTL0 -#define ROMDECCROMCTL1 ROMDEC.CROMCTL1 -#define ROMDECCROMCTL3 ROMDEC.CROMCTL3 -#define ROMDECCROMCTL4 ROMDEC.CROMCTL4 -#define ROMDECCROMCTL5 ROMDEC.CROMCTL5 -#define ROMDECCROMST0 ROMDEC.CROMST0 -#define ROMDECCROMST1 ROMDEC.CROMST1 -#define ROMDECCROMST3 ROMDEC.CROMST3 -#define ROMDECCROMST4 ROMDEC.CROMST4 -#define ROMDECCROMST5 ROMDEC.CROMST5 -#define ROMDECCROMST6 ROMDEC.CROMST6 -#define ROMDECCBUFST0 ROMDEC.CBUFST0 -#define ROMDECCBUFST1 ROMDEC.CBUFST1 -#define ROMDECCBUFST2 ROMDEC.CBUFST2 -#define ROMDECHEAD00 ROMDEC.HEAD00 -#define ROMDECHEAD01 ROMDEC.HEAD01 -#define ROMDECHEAD02 ROMDEC.HEAD02 -#define ROMDECHEAD03 ROMDEC.HEAD03 -#define ROMDECSHEAD00 ROMDEC.SHEAD00 -#define ROMDECSHEAD01 ROMDEC.SHEAD01 -#define ROMDECSHEAD02 ROMDEC.SHEAD02 -#define ROMDECSHEAD03 ROMDEC.SHEAD03 -#define ROMDECSHEAD04 ROMDEC.SHEAD04 -#define ROMDECSHEAD05 ROMDEC.SHEAD05 -#define ROMDECSHEAD06 ROMDEC.SHEAD06 -#define ROMDECSHEAD07 ROMDEC.SHEAD07 -#define ROMDECHEAD20 ROMDEC.HEAD20 -#define ROMDECHEAD21 ROMDEC.HEAD21 -#define ROMDECHEAD22 ROMDEC.HEAD22 -#define ROMDECHEAD23 ROMDEC.HEAD23 -#define ROMDECSHEAD20 ROMDEC.SHEAD20 -#define ROMDECSHEAD21 ROMDEC.SHEAD21 -#define ROMDECSHEAD22 ROMDEC.SHEAD22 -#define ROMDECSHEAD23 ROMDEC.SHEAD23 -#define ROMDECSHEAD24 ROMDEC.SHEAD24 -#define ROMDECSHEAD25 ROMDEC.SHEAD25 -#define ROMDECSHEAD26 ROMDEC.SHEAD26 -#define ROMDECSHEAD27 ROMDEC.SHEAD27 -#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0 -#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1 -#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2 -#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3 -#define ROMDECCROMST0M ROMDEC.CROMST0M -#define ROMDECROMDECRST ROMDEC.ROMDECRST -#define ROMDECRSTSTAT ROMDEC.RSTSTAT -#define ROMDECSSI ROMDEC.SSI -#define ROMDECINTHOLD ROMDEC.INTHOLD -#define ROMDECINHINT ROMDEC.INHINT -#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0 -#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2 -#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h index 1698f027cc..38bc282098 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h @@ -18,1886 +18,30 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rscan0_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RSCAN0_IODEFINE_H #define RSCAN0_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_rscan0 -{ /* RSCAN0 */ -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C0CFG; /* C0CFG */ - union iodefine_reg32_t C0CTR; /* C0CTR */ - union iodefine_reg32_t C0STS; /* C0STS */ - union iodefine_reg32_t C0ERFL; /* C0ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C1CFG; /* C1CFG */ - union iodefine_reg32_t C1CTR; /* C1CTR */ - union iodefine_reg32_t C1STS; /* C1STS */ - union iodefine_reg32_t C1ERFL; /* C1ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C2CFG; /* C2CFG */ - union iodefine_reg32_t C2CTR; /* C2CTR */ - union iodefine_reg32_t C2STS; /* C2STS */ - union iodefine_reg32_t C2ERFL; /* C2ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C3CFG; /* C3CFG */ - union iodefine_reg32_t C3CTR; /* C3CTR */ - union iodefine_reg32_t C3STS; /* C3STS */ - union iodefine_reg32_t C3ERFL; /* C3ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - -/* start of struct st_rscan_from_rscan0cncfg */ - union iodefine_reg32_t C4CFG; /* C4CFG */ - union iodefine_reg32_t C4CTR; /* C4CTR */ - union iodefine_reg32_t C4STS; /* C4STS */ - union iodefine_reg32_t C4ERFL; /* C4ERFL */ -/* end of struct st_rscan_from_rscan0cncfg */ - - volatile uint8_t dummy159[52]; /* */ - union iodefine_reg32_t GCFG; /* GCFG */ - union iodefine_reg32_t GCTR; /* GCTR */ - union iodefine_reg32_t GSTS; /* GSTS */ - union iodefine_reg32_t GERFL; /* GERFL */ - union iodefine_reg32_16_t GTSC; /* GTSC */ - union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ -#define RSCAN0_GAFLCFG0_COUNT 2 - union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ - union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ - union iodefine_reg32_t RMNB; /* RMNB */ -#define RSCAN0_RMND0_COUNT 3 - union iodefine_reg32_t RMND0; /* RMND0 */ - union iodefine_reg32_t RMND1; /* RMND1 */ - union iodefine_reg32_t RMND2; /* RMND2 */ - - volatile uint8_t dummy160[4]; /* */ -#define RSCAN0_RFCC0_COUNT 8 - union iodefine_reg32_t RFCC0; /* RFCC0 */ - union iodefine_reg32_t RFCC1; /* RFCC1 */ - union iodefine_reg32_t RFCC2; /* RFCC2 */ - union iodefine_reg32_t RFCC3; /* RFCC3 */ - union iodefine_reg32_t RFCC4; /* RFCC4 */ - union iodefine_reg32_t RFCC5; /* RFCC5 */ - union iodefine_reg32_t RFCC6; /* RFCC6 */ - union iodefine_reg32_t RFCC7; /* RFCC7 */ -#define RSCAN0_RFSTS0_COUNT 8 - union iodefine_reg32_t RFSTS0; /* RFSTS0 */ - union iodefine_reg32_t RFSTS1; /* RFSTS1 */ - union iodefine_reg32_t RFSTS2; /* RFSTS2 */ - union iodefine_reg32_t RFSTS3; /* RFSTS3 */ - union iodefine_reg32_t RFSTS4; /* RFSTS4 */ - union iodefine_reg32_t RFSTS5; /* RFSTS5 */ - union iodefine_reg32_t RFSTS6; /* RFSTS6 */ - union iodefine_reg32_t RFSTS7; /* RFSTS7 */ -#define RSCAN0_RFPCTR0_COUNT 8 - union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ - union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ - union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ - union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ - union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ - union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ - union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ - union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ -#define RSCAN0_CFCC0_COUNT 15 - union iodefine_reg32_t CFCC0; /* CFCC0 */ - union iodefine_reg32_t CFCC1; /* CFCC1 */ - union iodefine_reg32_t CFCC2; /* CFCC2 */ - union iodefine_reg32_t CFCC3; /* CFCC3 */ - union iodefine_reg32_t CFCC4; /* CFCC4 */ - union iodefine_reg32_t CFCC5; /* CFCC5 */ - union iodefine_reg32_t CFCC6; /* CFCC6 */ - union iodefine_reg32_t CFCC7; /* CFCC7 */ - union iodefine_reg32_t CFCC8; /* CFCC8 */ - union iodefine_reg32_t CFCC9; /* CFCC9 */ - union iodefine_reg32_t CFCC10; /* CFCC10 */ - union iodefine_reg32_t CFCC11; /* CFCC11 */ - union iodefine_reg32_t CFCC12; /* CFCC12 */ - union iodefine_reg32_t CFCC13; /* CFCC13 */ - union iodefine_reg32_t CFCC14; /* CFCC14 */ - - volatile uint8_t dummy161[36]; /* */ -#define RSCAN0_CFSTS0_COUNT 15 - union iodefine_reg32_t CFSTS0; /* CFSTS0 */ - union iodefine_reg32_t CFSTS1; /* CFSTS1 */ - union iodefine_reg32_t CFSTS2; /* CFSTS2 */ - union iodefine_reg32_t CFSTS3; /* CFSTS3 */ - union iodefine_reg32_t CFSTS4; /* CFSTS4 */ - union iodefine_reg32_t CFSTS5; /* CFSTS5 */ - union iodefine_reg32_t CFSTS6; /* CFSTS6 */ - union iodefine_reg32_t CFSTS7; /* CFSTS7 */ - union iodefine_reg32_t CFSTS8; /* CFSTS8 */ - union iodefine_reg32_t CFSTS9; /* CFSTS9 */ - union iodefine_reg32_t CFSTS10; /* CFSTS10 */ - union iodefine_reg32_t CFSTS11; /* CFSTS11 */ - union iodefine_reg32_t CFSTS12; /* CFSTS12 */ - union iodefine_reg32_t CFSTS13; /* CFSTS13 */ - union iodefine_reg32_t CFSTS14; /* CFSTS14 */ - - volatile uint8_t dummy162[36]; /* */ -#define RSCAN0_CFPCTR0_COUNT 15 - union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ - union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ - union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ - union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ - union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ - union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ - union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ - union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ - union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ - union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ - union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ - union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ - union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ - union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ - union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ - - volatile uint8_t dummy163[36]; /* */ - union iodefine_reg32_t FESTS; /* FESTS */ - union iodefine_reg32_t FFSTS; /* FFSTS */ - union iodefine_reg32_t FMSTS; /* FMSTS */ - union iodefine_reg32_t RFISTS; /* RFISTS */ - union iodefine_reg32_t CFRISTS; /* CFRISTS */ - union iodefine_reg32_t CFTISTS; /* CFTISTS */ - -#define RSCAN0_TMC0_COUNT 80 - volatile uint8_t TMC0; /* TMC0 */ - volatile uint8_t TMC1; /* TMC1 */ - volatile uint8_t TMC2; /* TMC2 */ - volatile uint8_t TMC3; /* TMC3 */ - volatile uint8_t TMC4; /* TMC4 */ - volatile uint8_t TMC5; /* TMC5 */ - volatile uint8_t TMC6; /* TMC6 */ - volatile uint8_t TMC7; /* TMC7 */ - volatile uint8_t TMC8; /* TMC8 */ - volatile uint8_t TMC9; /* TMC9 */ - volatile uint8_t TMC10; /* TMC10 */ - volatile uint8_t TMC11; /* TMC11 */ - volatile uint8_t TMC12; /* TMC12 */ - volatile uint8_t TMC13; /* TMC13 */ - volatile uint8_t TMC14; /* TMC14 */ - volatile uint8_t TMC15; /* TMC15 */ - volatile uint8_t TMC16; /* TMC16 */ - volatile uint8_t TMC17; /* TMC17 */ - volatile uint8_t TMC18; /* TMC18 */ - volatile uint8_t TMC19; /* TMC19 */ - volatile uint8_t TMC20; /* TMC20 */ - volatile uint8_t TMC21; /* TMC21 */ - volatile uint8_t TMC22; /* TMC22 */ - volatile uint8_t TMC23; /* TMC23 */ - volatile uint8_t TMC24; /* TMC24 */ - volatile uint8_t TMC25; /* TMC25 */ - volatile uint8_t TMC26; /* TMC26 */ - volatile uint8_t TMC27; /* TMC27 */ - volatile uint8_t TMC28; /* TMC28 */ - volatile uint8_t TMC29; /* TMC29 */ - volatile uint8_t TMC30; /* TMC30 */ - volatile uint8_t TMC31; /* TMC31 */ - volatile uint8_t TMC32; /* TMC32 */ - volatile uint8_t TMC33; /* TMC33 */ - volatile uint8_t TMC34; /* TMC34 */ - volatile uint8_t TMC35; /* TMC35 */ - volatile uint8_t TMC36; /* TMC36 */ - volatile uint8_t TMC37; /* TMC37 */ - volatile uint8_t TMC38; /* TMC38 */ - volatile uint8_t TMC39; /* TMC39 */ - volatile uint8_t TMC40; /* TMC40 */ - volatile uint8_t TMC41; /* TMC41 */ - volatile uint8_t TMC42; /* TMC42 */ - volatile uint8_t TMC43; /* TMC43 */ - volatile uint8_t TMC44; /* TMC44 */ - volatile uint8_t TMC45; /* TMC45 */ - volatile uint8_t TMC46; /* TMC46 */ - volatile uint8_t TMC47; /* TMC47 */ - volatile uint8_t TMC48; /* TMC48 */ - volatile uint8_t TMC49; /* TMC49 */ - volatile uint8_t TMC50; /* TMC50 */ - volatile uint8_t TMC51; /* TMC51 */ - volatile uint8_t TMC52; /* TMC52 */ - volatile uint8_t TMC53; /* TMC53 */ - volatile uint8_t TMC54; /* TMC54 */ - volatile uint8_t TMC55; /* TMC55 */ - volatile uint8_t TMC56; /* TMC56 */ - volatile uint8_t TMC57; /* TMC57 */ - volatile uint8_t TMC58; /* TMC58 */ - volatile uint8_t TMC59; /* TMC59 */ - volatile uint8_t TMC60; /* TMC60 */ - volatile uint8_t TMC61; /* TMC61 */ - volatile uint8_t TMC62; /* TMC62 */ - volatile uint8_t TMC63; /* TMC63 */ - volatile uint8_t TMC64; /* TMC64 */ - volatile uint8_t TMC65; /* TMC65 */ - volatile uint8_t TMC66; /* TMC66 */ - volatile uint8_t TMC67; /* TMC67 */ - volatile uint8_t TMC68; /* TMC68 */ - volatile uint8_t TMC69; /* TMC69 */ - volatile uint8_t TMC70; /* TMC70 */ - volatile uint8_t TMC71; /* TMC71 */ - volatile uint8_t TMC72; /* TMC72 */ - volatile uint8_t TMC73; /* TMC73 */ - volatile uint8_t TMC74; /* TMC74 */ - volatile uint8_t TMC75; /* TMC75 */ - volatile uint8_t TMC76; /* TMC76 */ - volatile uint8_t TMC77; /* TMC77 */ - volatile uint8_t TMC78; /* TMC78 */ - volatile uint8_t TMC79; /* TMC79 */ - volatile uint8_t dummy164[48]; /* */ -#define RSCAN0_TMSTS0_COUNT 80 - volatile uint8_t TMSTS0; /* TMSTS0 */ - volatile uint8_t TMSTS1; /* TMSTS1 */ - volatile uint8_t TMSTS2; /* TMSTS2 */ - volatile uint8_t TMSTS3; /* TMSTS3 */ - volatile uint8_t TMSTS4; /* TMSTS4 */ - volatile uint8_t TMSTS5; /* TMSTS5 */ - volatile uint8_t TMSTS6; /* TMSTS6 */ - volatile uint8_t TMSTS7; /* TMSTS7 */ - volatile uint8_t TMSTS8; /* TMSTS8 */ - volatile uint8_t TMSTS9; /* TMSTS9 */ - volatile uint8_t TMSTS10; /* TMSTS10 */ - volatile uint8_t TMSTS11; /* TMSTS11 */ - volatile uint8_t TMSTS12; /* TMSTS12 */ - volatile uint8_t TMSTS13; /* TMSTS13 */ - volatile uint8_t TMSTS14; /* TMSTS14 */ - volatile uint8_t TMSTS15; /* TMSTS15 */ - volatile uint8_t TMSTS16; /* TMSTS16 */ - volatile uint8_t TMSTS17; /* TMSTS17 */ - volatile uint8_t TMSTS18; /* TMSTS18 */ - volatile uint8_t TMSTS19; /* TMSTS19 */ - volatile uint8_t TMSTS20; /* TMSTS20 */ - volatile uint8_t TMSTS21; /* TMSTS21 */ - volatile uint8_t TMSTS22; /* TMSTS22 */ - volatile uint8_t TMSTS23; /* TMSTS23 */ - volatile uint8_t TMSTS24; /* TMSTS24 */ - volatile uint8_t TMSTS25; /* TMSTS25 */ - volatile uint8_t TMSTS26; /* TMSTS26 */ - volatile uint8_t TMSTS27; /* TMSTS27 */ - volatile uint8_t TMSTS28; /* TMSTS28 */ - volatile uint8_t TMSTS29; /* TMSTS29 */ - volatile uint8_t TMSTS30; /* TMSTS30 */ - volatile uint8_t TMSTS31; /* TMSTS31 */ - volatile uint8_t TMSTS32; /* TMSTS32 */ - volatile uint8_t TMSTS33; /* TMSTS33 */ - volatile uint8_t TMSTS34; /* TMSTS34 */ - volatile uint8_t TMSTS35; /* TMSTS35 */ - volatile uint8_t TMSTS36; /* TMSTS36 */ - volatile uint8_t TMSTS37; /* TMSTS37 */ - volatile uint8_t TMSTS38; /* TMSTS38 */ - volatile uint8_t TMSTS39; /* TMSTS39 */ - volatile uint8_t TMSTS40; /* TMSTS40 */ - volatile uint8_t TMSTS41; /* TMSTS41 */ - volatile uint8_t TMSTS42; /* TMSTS42 */ - volatile uint8_t TMSTS43; /* TMSTS43 */ - volatile uint8_t TMSTS44; /* TMSTS44 */ - volatile uint8_t TMSTS45; /* TMSTS45 */ - volatile uint8_t TMSTS46; /* TMSTS46 */ - volatile uint8_t TMSTS47; /* TMSTS47 */ - volatile uint8_t TMSTS48; /* TMSTS48 */ - volatile uint8_t TMSTS49; /* TMSTS49 */ - volatile uint8_t TMSTS50; /* TMSTS50 */ - volatile uint8_t TMSTS51; /* TMSTS51 */ - volatile uint8_t TMSTS52; /* TMSTS52 */ - volatile uint8_t TMSTS53; /* TMSTS53 */ - volatile uint8_t TMSTS54; /* TMSTS54 */ - volatile uint8_t TMSTS55; /* TMSTS55 */ - volatile uint8_t TMSTS56; /* TMSTS56 */ - volatile uint8_t TMSTS57; /* TMSTS57 */ - volatile uint8_t TMSTS58; /* TMSTS58 */ - volatile uint8_t TMSTS59; /* TMSTS59 */ - volatile uint8_t TMSTS60; /* TMSTS60 */ - volatile uint8_t TMSTS61; /* TMSTS61 */ - volatile uint8_t TMSTS62; /* TMSTS62 */ - volatile uint8_t TMSTS63; /* TMSTS63 */ - volatile uint8_t TMSTS64; /* TMSTS64 */ - volatile uint8_t TMSTS65; /* TMSTS65 */ - volatile uint8_t TMSTS66; /* TMSTS66 */ - volatile uint8_t TMSTS67; /* TMSTS67 */ - volatile uint8_t TMSTS68; /* TMSTS68 */ - volatile uint8_t TMSTS69; /* TMSTS69 */ - volatile uint8_t TMSTS70; /* TMSTS70 */ - volatile uint8_t TMSTS71; /* TMSTS71 */ - volatile uint8_t TMSTS72; /* TMSTS72 */ - volatile uint8_t TMSTS73; /* TMSTS73 */ - volatile uint8_t TMSTS74; /* TMSTS74 */ - volatile uint8_t TMSTS75; /* TMSTS75 */ - volatile uint8_t TMSTS76; /* TMSTS76 */ - volatile uint8_t TMSTS77; /* TMSTS77 */ - volatile uint8_t TMSTS78; /* TMSTS78 */ - volatile uint8_t TMSTS79; /* TMSTS79 */ - volatile uint8_t dummy165[48]; /* */ -#define RSCAN0_TMTRSTS0_COUNT 3 - union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ - union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ - union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ - - volatile uint8_t dummy166[4]; /* */ -#define RSCAN0_TMTARSTS0_COUNT 3 - union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ - union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ - union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ - - volatile uint8_t dummy167[4]; /* */ -#define RSCAN0_TMTCSTS0_COUNT 3 - union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ - union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ - union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ - - volatile uint8_t dummy168[4]; /* */ -#define RSCAN0_TMTASTS0_COUNT 3 - union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ - union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ - union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ - - volatile uint8_t dummy169[4]; /* */ -#define RSCAN0_TMIEC0_COUNT 3 - union iodefine_reg32_t TMIEC0; /* TMIEC0 */ - union iodefine_reg32_t TMIEC1; /* TMIEC1 */ - union iodefine_reg32_t TMIEC2; /* TMIEC2 */ - - volatile uint8_t dummy170[4]; /* */ -#define RSCAN0_TXQCC0_COUNT 5 - union iodefine_reg32_t TXQCC0; /* TXQCC0 */ - union iodefine_reg32_t TXQCC1; /* TXQCC1 */ - union iodefine_reg32_t TXQCC2; /* TXQCC2 */ - union iodefine_reg32_t TXQCC3; /* TXQCC3 */ - union iodefine_reg32_t TXQCC4; /* TXQCC4 */ - - volatile uint8_t dummy171[12]; /* */ -#define RSCAN0_TXQSTS0_COUNT 5 - union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ - union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ - union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ - union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ - union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ - - volatile uint8_t dummy172[12]; /* */ -#define RSCAN0_TXQPCTR0_COUNT 5 - union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ - union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ - union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ - union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ - union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ - - volatile uint8_t dummy173[12]; /* */ -#define RSCAN0_THLCC0_COUNT 5 - union iodefine_reg32_t THLCC0; /* THLCC0 */ - union iodefine_reg32_t THLCC1; /* THLCC1 */ - union iodefine_reg32_t THLCC2; /* THLCC2 */ - union iodefine_reg32_t THLCC3; /* THLCC3 */ - union iodefine_reg32_t THLCC4; /* THLCC4 */ - - volatile uint8_t dummy174[12]; /* */ -#define RSCAN0_THLSTS0_COUNT 5 - union iodefine_reg32_t THLSTS0; /* THLSTS0 */ - union iodefine_reg32_t THLSTS1; /* THLSTS1 */ - union iodefine_reg32_t THLSTS2; /* THLSTS2 */ - union iodefine_reg32_t THLSTS3; /* THLSTS3 */ - union iodefine_reg32_t THLSTS4; /* THLSTS4 */ - - volatile uint8_t dummy175[12]; /* */ -#define RSCAN0_THLPCTR0_COUNT 5 - union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ - union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ - union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ - union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ - union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ - - volatile uint8_t dummy176[12]; /* */ -#define RSCAN0_GTINTSTS0_COUNT 2 - union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ - union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ - union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ - union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ - - volatile uint8_t dummy177[12]; /* */ - union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ - - volatile uint8_t dummy178[128]; /* */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID0; /* GAFLID0 */ - union iodefine_reg32_t GAFLM0; /* GAFLM0 */ - union iodefine_reg32_t GAFLP00; /* GAFLP00 */ - union iodefine_reg32_t GAFLP10; /* GAFLP10 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID1; /* GAFLID1 */ - union iodefine_reg32_t GAFLM1; /* GAFLM1 */ - union iodefine_reg32_t GAFLP01; /* GAFLP01 */ - union iodefine_reg32_t GAFLP11; /* GAFLP11 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID2; /* GAFLID2 */ - union iodefine_reg32_t GAFLM2; /* GAFLM2 */ - union iodefine_reg32_t GAFLP02; /* GAFLP02 */ - union iodefine_reg32_t GAFLP12; /* GAFLP12 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID3; /* GAFLID3 */ - union iodefine_reg32_t GAFLM3; /* GAFLM3 */ - union iodefine_reg32_t GAFLP03; /* GAFLP03 */ - union iodefine_reg32_t GAFLP13; /* GAFLP13 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID4; /* GAFLID4 */ - union iodefine_reg32_t GAFLM4; /* GAFLM4 */ - union iodefine_reg32_t GAFLP04; /* GAFLP04 */ - union iodefine_reg32_t GAFLP14; /* GAFLP14 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID5; /* GAFLID5 */ - union iodefine_reg32_t GAFLM5; /* GAFLM5 */ - union iodefine_reg32_t GAFLP05; /* GAFLP05 */ - union iodefine_reg32_t GAFLP15; /* GAFLP15 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID6; /* GAFLID6 */ - union iodefine_reg32_t GAFLM6; /* GAFLM6 */ - union iodefine_reg32_t GAFLP06; /* GAFLP06 */ - union iodefine_reg32_t GAFLP16; /* GAFLP16 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID7; /* GAFLID7 */ - union iodefine_reg32_t GAFLM7; /* GAFLM7 */ - union iodefine_reg32_t GAFLP07; /* GAFLP07 */ - union iodefine_reg32_t GAFLP17; /* GAFLP17 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID8; /* GAFLID8 */ - union iodefine_reg32_t GAFLM8; /* GAFLM8 */ - union iodefine_reg32_t GAFLP08; /* GAFLP08 */ - union iodefine_reg32_t GAFLP18; /* GAFLP18 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID9; /* GAFLID9 */ - union iodefine_reg32_t GAFLM9; /* GAFLM9 */ - union iodefine_reg32_t GAFLP09; /* GAFLP09 */ - union iodefine_reg32_t GAFLP19; /* GAFLP19 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID10; /* GAFLID10 */ - union iodefine_reg32_t GAFLM10; /* GAFLM10 */ - union iodefine_reg32_t GAFLP010; /* GAFLP010 */ - union iodefine_reg32_t GAFLP110; /* GAFLP110 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID11; /* GAFLID11 */ - union iodefine_reg32_t GAFLM11; /* GAFLM11 */ - union iodefine_reg32_t GAFLP011; /* GAFLP011 */ - union iodefine_reg32_t GAFLP111; /* GAFLP111 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID12; /* GAFLID12 */ - union iodefine_reg32_t GAFLM12; /* GAFLM12 */ - union iodefine_reg32_t GAFLP012; /* GAFLP012 */ - union iodefine_reg32_t GAFLP112; /* GAFLP112 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID13; /* GAFLID13 */ - union iodefine_reg32_t GAFLM13; /* GAFLM13 */ - union iodefine_reg32_t GAFLP013; /* GAFLP013 */ - union iodefine_reg32_t GAFLP113; /* GAFLP113 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID14; /* GAFLID14 */ - union iodefine_reg32_t GAFLM14; /* GAFLM14 */ - union iodefine_reg32_t GAFLP014; /* GAFLP014 */ - union iodefine_reg32_t GAFLP114; /* GAFLP114 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0gaflidj */ - union iodefine_reg32_t GAFLID15; /* GAFLID15 */ - union iodefine_reg32_t GAFLM15; /* GAFLM15 */ - union iodefine_reg32_t GAFLP015; /* GAFLP015 */ - union iodefine_reg32_t GAFLP115; /* GAFLP115 */ -/* end of struct st_rscan_from_rscan0gaflidj */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID0; /* RMID0 */ - union iodefine_reg32_t RMPTR0; /* RMPTR0 */ - union iodefine_reg32_t RMDF00; /* RMDF00 */ - union iodefine_reg32_t RMDF10; /* RMDF10 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID1; /* RMID1 */ - union iodefine_reg32_t RMPTR1; /* RMPTR1 */ - union iodefine_reg32_t RMDF01; /* RMDF01 */ - union iodefine_reg32_t RMDF11; /* RMDF11 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID2; /* RMID2 */ - union iodefine_reg32_t RMPTR2; /* RMPTR2 */ - union iodefine_reg32_t RMDF02; /* RMDF02 */ - union iodefine_reg32_t RMDF12; /* RMDF12 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID3; /* RMID3 */ - union iodefine_reg32_t RMPTR3; /* RMPTR3 */ - union iodefine_reg32_t RMDF03; /* RMDF03 */ - union iodefine_reg32_t RMDF13; /* RMDF13 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID4; /* RMID4 */ - union iodefine_reg32_t RMPTR4; /* RMPTR4 */ - union iodefine_reg32_t RMDF04; /* RMDF04 */ - union iodefine_reg32_t RMDF14; /* RMDF14 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID5; /* RMID5 */ - union iodefine_reg32_t RMPTR5; /* RMPTR5 */ - union iodefine_reg32_t RMDF05; /* RMDF05 */ - union iodefine_reg32_t RMDF15; /* RMDF15 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID6; /* RMID6 */ - union iodefine_reg32_t RMPTR6; /* RMPTR6 */ - union iodefine_reg32_t RMDF06; /* RMDF06 */ - union iodefine_reg32_t RMDF16; /* RMDF16 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID7; /* RMID7 */ - union iodefine_reg32_t RMPTR7; /* RMPTR7 */ - union iodefine_reg32_t RMDF07; /* RMDF07 */ - union iodefine_reg32_t RMDF17; /* RMDF17 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID8; /* RMID8 */ - union iodefine_reg32_t RMPTR8; /* RMPTR8 */ - union iodefine_reg32_t RMDF08; /* RMDF08 */ - union iodefine_reg32_t RMDF18; /* RMDF18 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID9; /* RMID9 */ - union iodefine_reg32_t RMPTR9; /* RMPTR9 */ - union iodefine_reg32_t RMDF09; /* RMDF09 */ - union iodefine_reg32_t RMDF19; /* RMDF19 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID10; /* RMID10 */ - union iodefine_reg32_t RMPTR10; /* RMPTR10 */ - union iodefine_reg32_t RMDF010; /* RMDF010 */ - union iodefine_reg32_t RMDF110; /* RMDF110 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID11; /* RMID11 */ - union iodefine_reg32_t RMPTR11; /* RMPTR11 */ - union iodefine_reg32_t RMDF011; /* RMDF011 */ - union iodefine_reg32_t RMDF111; /* RMDF111 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID12; /* RMID12 */ - union iodefine_reg32_t RMPTR12; /* RMPTR12 */ - union iodefine_reg32_t RMDF012; /* RMDF012 */ - union iodefine_reg32_t RMDF112; /* RMDF112 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID13; /* RMID13 */ - union iodefine_reg32_t RMPTR13; /* RMPTR13 */ - union iodefine_reg32_t RMDF013; /* RMDF013 */ - union iodefine_reg32_t RMDF113; /* RMDF113 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID14; /* RMID14 */ - union iodefine_reg32_t RMPTR14; /* RMPTR14 */ - union iodefine_reg32_t RMDF014; /* RMDF014 */ - union iodefine_reg32_t RMDF114; /* RMDF114 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID15; /* RMID15 */ - union iodefine_reg32_t RMPTR15; /* RMPTR15 */ - union iodefine_reg32_t RMDF015; /* RMDF015 */ - union iodefine_reg32_t RMDF115; /* RMDF115 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID16; /* RMID16 */ - union iodefine_reg32_t RMPTR16; /* RMPTR16 */ - union iodefine_reg32_t RMDF016; /* RMDF016 */ - union iodefine_reg32_t RMDF116; /* RMDF116 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID17; /* RMID17 */ - union iodefine_reg32_t RMPTR17; /* RMPTR17 */ - union iodefine_reg32_t RMDF017; /* RMDF017 */ - union iodefine_reg32_t RMDF117; /* RMDF117 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID18; /* RMID18 */ - union iodefine_reg32_t RMPTR18; /* RMPTR18 */ - union iodefine_reg32_t RMDF018; /* RMDF018 */ - union iodefine_reg32_t RMDF118; /* RMDF118 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID19; /* RMID19 */ - union iodefine_reg32_t RMPTR19; /* RMPTR19 */ - union iodefine_reg32_t RMDF019; /* RMDF019 */ - union iodefine_reg32_t RMDF119; /* RMDF119 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID20; /* RMID20 */ - union iodefine_reg32_t RMPTR20; /* RMPTR20 */ - union iodefine_reg32_t RMDF020; /* RMDF020 */ - union iodefine_reg32_t RMDF120; /* RMDF120 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID21; /* RMID21 */ - union iodefine_reg32_t RMPTR21; /* RMPTR21 */ - union iodefine_reg32_t RMDF021; /* RMDF021 */ - union iodefine_reg32_t RMDF121; /* RMDF121 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID22; /* RMID22 */ - union iodefine_reg32_t RMPTR22; /* RMPTR22 */ - union iodefine_reg32_t RMDF022; /* RMDF022 */ - union iodefine_reg32_t RMDF122; /* RMDF122 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID23; /* RMID23 */ - union iodefine_reg32_t RMPTR23; /* RMPTR23 */ - union iodefine_reg32_t RMDF023; /* RMDF023 */ - union iodefine_reg32_t RMDF123; /* RMDF123 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID24; /* RMID24 */ - union iodefine_reg32_t RMPTR24; /* RMPTR24 */ - union iodefine_reg32_t RMDF024; /* RMDF024 */ - union iodefine_reg32_t RMDF124; /* RMDF124 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID25; /* RMID25 */ - union iodefine_reg32_t RMPTR25; /* RMPTR25 */ - union iodefine_reg32_t RMDF025; /* RMDF025 */ - union iodefine_reg32_t RMDF125; /* RMDF125 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID26; /* RMID26 */ - union iodefine_reg32_t RMPTR26; /* RMPTR26 */ - union iodefine_reg32_t RMDF026; /* RMDF026 */ - union iodefine_reg32_t RMDF126; /* RMDF126 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID27; /* RMID27 */ - union iodefine_reg32_t RMPTR27; /* RMPTR27 */ - union iodefine_reg32_t RMDF027; /* RMDF027 */ - union iodefine_reg32_t RMDF127; /* RMDF127 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID28; /* RMID28 */ - union iodefine_reg32_t RMPTR28; /* RMPTR28 */ - union iodefine_reg32_t RMDF028; /* RMDF028 */ - union iodefine_reg32_t RMDF128; /* RMDF128 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID29; /* RMID29 */ - union iodefine_reg32_t RMPTR29; /* RMPTR29 */ - union iodefine_reg32_t RMDF029; /* RMDF029 */ - union iodefine_reg32_t RMDF129; /* RMDF129 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID30; /* RMID30 */ - union iodefine_reg32_t RMPTR30; /* RMPTR30 */ - union iodefine_reg32_t RMDF030; /* RMDF030 */ - union iodefine_reg32_t RMDF130; /* RMDF130 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID31; /* RMID31 */ - union iodefine_reg32_t RMPTR31; /* RMPTR31 */ - union iodefine_reg32_t RMDF031; /* RMDF031 */ - union iodefine_reg32_t RMDF131; /* RMDF131 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID32; /* RMID32 */ - union iodefine_reg32_t RMPTR32; /* RMPTR32 */ - union iodefine_reg32_t RMDF032; /* RMDF032 */ - union iodefine_reg32_t RMDF132; /* RMDF132 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID33; /* RMID33 */ - union iodefine_reg32_t RMPTR33; /* RMPTR33 */ - union iodefine_reg32_t RMDF033; /* RMDF033 */ - union iodefine_reg32_t RMDF133; /* RMDF133 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID34; /* RMID34 */ - union iodefine_reg32_t RMPTR34; /* RMPTR34 */ - union iodefine_reg32_t RMDF034; /* RMDF034 */ - union iodefine_reg32_t RMDF134; /* RMDF134 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID35; /* RMID35 */ - union iodefine_reg32_t RMPTR35; /* RMPTR35 */ - union iodefine_reg32_t RMDF035; /* RMDF035 */ - union iodefine_reg32_t RMDF135; /* RMDF135 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID36; /* RMID36 */ - union iodefine_reg32_t RMPTR36; /* RMPTR36 */ - union iodefine_reg32_t RMDF036; /* RMDF036 */ - union iodefine_reg32_t RMDF136; /* RMDF136 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID37; /* RMID37 */ - union iodefine_reg32_t RMPTR37; /* RMPTR37 */ - union iodefine_reg32_t RMDF037; /* RMDF037 */ - union iodefine_reg32_t RMDF137; /* RMDF137 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID38; /* RMID38 */ - union iodefine_reg32_t RMPTR38; /* RMPTR38 */ - union iodefine_reg32_t RMDF038; /* RMDF038 */ - union iodefine_reg32_t RMDF138; /* RMDF138 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID39; /* RMID39 */ - union iodefine_reg32_t RMPTR39; /* RMPTR39 */ - union iodefine_reg32_t RMDF039; /* RMDF039 */ - union iodefine_reg32_t RMDF139; /* RMDF139 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID40; /* RMID40 */ - union iodefine_reg32_t RMPTR40; /* RMPTR40 */ - union iodefine_reg32_t RMDF040; /* RMDF040 */ - union iodefine_reg32_t RMDF140; /* RMDF140 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID41; /* RMID41 */ - union iodefine_reg32_t RMPTR41; /* RMPTR41 */ - union iodefine_reg32_t RMDF041; /* RMDF041 */ - union iodefine_reg32_t RMDF141; /* RMDF141 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID42; /* RMID42 */ - union iodefine_reg32_t RMPTR42; /* RMPTR42 */ - union iodefine_reg32_t RMDF042; /* RMDF042 */ - union iodefine_reg32_t RMDF142; /* RMDF142 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID43; /* RMID43 */ - union iodefine_reg32_t RMPTR43; /* RMPTR43 */ - union iodefine_reg32_t RMDF043; /* RMDF043 */ - union iodefine_reg32_t RMDF143; /* RMDF143 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID44; /* RMID44 */ - union iodefine_reg32_t RMPTR44; /* RMPTR44 */ - union iodefine_reg32_t RMDF044; /* RMDF044 */ - union iodefine_reg32_t RMDF144; /* RMDF144 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID45; /* RMID45 */ - union iodefine_reg32_t RMPTR45; /* RMPTR45 */ - union iodefine_reg32_t RMDF045; /* RMDF045 */ - union iodefine_reg32_t RMDF145; /* RMDF145 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID46; /* RMID46 */ - union iodefine_reg32_t RMPTR46; /* RMPTR46 */ - union iodefine_reg32_t RMDF046; /* RMDF046 */ - union iodefine_reg32_t RMDF146; /* RMDF146 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID47; /* RMID47 */ - union iodefine_reg32_t RMPTR47; /* RMPTR47 */ - union iodefine_reg32_t RMDF047; /* RMDF047 */ - union iodefine_reg32_t RMDF147; /* RMDF147 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID48; /* RMID48 */ - union iodefine_reg32_t RMPTR48; /* RMPTR48 */ - union iodefine_reg32_t RMDF048; /* RMDF048 */ - union iodefine_reg32_t RMDF148; /* RMDF148 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID49; /* RMID49 */ - union iodefine_reg32_t RMPTR49; /* RMPTR49 */ - union iodefine_reg32_t RMDF049; /* RMDF049 */ - union iodefine_reg32_t RMDF149; /* RMDF149 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID50; /* RMID50 */ - union iodefine_reg32_t RMPTR50; /* RMPTR50 */ - union iodefine_reg32_t RMDF050; /* RMDF050 */ - union iodefine_reg32_t RMDF150; /* RMDF150 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID51; /* RMID51 */ - union iodefine_reg32_t RMPTR51; /* RMPTR51 */ - union iodefine_reg32_t RMDF051; /* RMDF051 */ - union iodefine_reg32_t RMDF151; /* RMDF151 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID52; /* RMID52 */ - union iodefine_reg32_t RMPTR52; /* RMPTR52 */ - union iodefine_reg32_t RMDF052; /* RMDF052 */ - union iodefine_reg32_t RMDF152; /* RMDF152 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID53; /* RMID53 */ - union iodefine_reg32_t RMPTR53; /* RMPTR53 */ - union iodefine_reg32_t RMDF053; /* RMDF053 */ - union iodefine_reg32_t RMDF153; /* RMDF153 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID54; /* RMID54 */ - union iodefine_reg32_t RMPTR54; /* RMPTR54 */ - union iodefine_reg32_t RMDF054; /* RMDF054 */ - union iodefine_reg32_t RMDF154; /* RMDF154 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID55; /* RMID55 */ - union iodefine_reg32_t RMPTR55; /* RMPTR55 */ - union iodefine_reg32_t RMDF055; /* RMDF055 */ - union iodefine_reg32_t RMDF155; /* RMDF155 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID56; /* RMID56 */ - union iodefine_reg32_t RMPTR56; /* RMPTR56 */ - union iodefine_reg32_t RMDF056; /* RMDF056 */ - union iodefine_reg32_t RMDF156; /* RMDF156 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID57; /* RMID57 */ - union iodefine_reg32_t RMPTR57; /* RMPTR57 */ - union iodefine_reg32_t RMDF057; /* RMDF057 */ - union iodefine_reg32_t RMDF157; /* RMDF157 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID58; /* RMID58 */ - union iodefine_reg32_t RMPTR58; /* RMPTR58 */ - union iodefine_reg32_t RMDF058; /* RMDF058 */ - union iodefine_reg32_t RMDF158; /* RMDF158 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID59; /* RMID59 */ - union iodefine_reg32_t RMPTR59; /* RMPTR59 */ - union iodefine_reg32_t RMDF059; /* RMDF059 */ - union iodefine_reg32_t RMDF159; /* RMDF159 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID60; /* RMID60 */ - union iodefine_reg32_t RMPTR60; /* RMPTR60 */ - union iodefine_reg32_t RMDF060; /* RMDF060 */ - union iodefine_reg32_t RMDF160; /* RMDF160 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID61; /* RMID61 */ - union iodefine_reg32_t RMPTR61; /* RMPTR61 */ - union iodefine_reg32_t RMDF061; /* RMDF061 */ - union iodefine_reg32_t RMDF161; /* RMDF161 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID62; /* RMID62 */ - union iodefine_reg32_t RMPTR62; /* RMPTR62 */ - union iodefine_reg32_t RMDF062; /* RMDF062 */ - union iodefine_reg32_t RMDF162; /* RMDF162 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID63; /* RMID63 */ - union iodefine_reg32_t RMPTR63; /* RMPTR63 */ - union iodefine_reg32_t RMDF063; /* RMDF063 */ - union iodefine_reg32_t RMDF163; /* RMDF163 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID64; /* RMID64 */ - union iodefine_reg32_t RMPTR64; /* RMPTR64 */ - union iodefine_reg32_t RMDF064; /* RMDF064 */ - union iodefine_reg32_t RMDF164; /* RMDF164 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID65; /* RMID65 */ - union iodefine_reg32_t RMPTR65; /* RMPTR65 */ - union iodefine_reg32_t RMDF065; /* RMDF065 */ - union iodefine_reg32_t RMDF165; /* RMDF165 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID66; /* RMID66 */ - union iodefine_reg32_t RMPTR66; /* RMPTR66 */ - union iodefine_reg32_t RMDF066; /* RMDF066 */ - union iodefine_reg32_t RMDF166; /* RMDF166 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID67; /* RMID67 */ - union iodefine_reg32_t RMPTR67; /* RMPTR67 */ - union iodefine_reg32_t RMDF067; /* RMDF067 */ - union iodefine_reg32_t RMDF167; /* RMDF167 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID68; /* RMID68 */ - union iodefine_reg32_t RMPTR68; /* RMPTR68 */ - union iodefine_reg32_t RMDF068; /* RMDF068 */ - union iodefine_reg32_t RMDF168; /* RMDF168 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID69; /* RMID69 */ - union iodefine_reg32_t RMPTR69; /* RMPTR69 */ - union iodefine_reg32_t RMDF069; /* RMDF069 */ - union iodefine_reg32_t RMDF169; /* RMDF169 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID70; /* RMID70 */ - union iodefine_reg32_t RMPTR70; /* RMPTR70 */ - union iodefine_reg32_t RMDF070; /* RMDF070 */ - union iodefine_reg32_t RMDF170; /* RMDF170 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID71; /* RMID71 */ - union iodefine_reg32_t RMPTR71; /* RMPTR71 */ - union iodefine_reg32_t RMDF071; /* RMDF071 */ - union iodefine_reg32_t RMDF171; /* RMDF171 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID72; /* RMID72 */ - union iodefine_reg32_t RMPTR72; /* RMPTR72 */ - union iodefine_reg32_t RMDF072; /* RMDF072 */ - union iodefine_reg32_t RMDF172; /* RMDF172 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID73; /* RMID73 */ - union iodefine_reg32_t RMPTR73; /* RMPTR73 */ - union iodefine_reg32_t RMDF073; /* RMDF073 */ - union iodefine_reg32_t RMDF173; /* RMDF173 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID74; /* RMID74 */ - union iodefine_reg32_t RMPTR74; /* RMPTR74 */ - union iodefine_reg32_t RMDF074; /* RMDF074 */ - union iodefine_reg32_t RMDF174; /* RMDF174 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID75; /* RMID75 */ - union iodefine_reg32_t RMPTR75; /* RMPTR75 */ - union iodefine_reg32_t RMDF075; /* RMDF075 */ - union iodefine_reg32_t RMDF175; /* RMDF175 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID76; /* RMID76 */ - union iodefine_reg32_t RMPTR76; /* RMPTR76 */ - union iodefine_reg32_t RMDF076; /* RMDF076 */ - union iodefine_reg32_t RMDF176; /* RMDF176 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID77; /* RMID77 */ - union iodefine_reg32_t RMPTR77; /* RMPTR77 */ - union iodefine_reg32_t RMDF077; /* RMDF077 */ - union iodefine_reg32_t RMDF177; /* RMDF177 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID78; /* RMID78 */ - union iodefine_reg32_t RMPTR78; /* RMPTR78 */ - union iodefine_reg32_t RMDF078; /* RMDF078 */ - union iodefine_reg32_t RMDF178; /* RMDF178 */ -/* end of struct st_rscan_from_rscan0rmidp */ - -/* start of struct st_rscan_from_rscan0rmidp */ - union iodefine_reg32_t RMID79; /* RMID79 */ - union iodefine_reg32_t RMPTR79; /* RMPTR79 */ - union iodefine_reg32_t RMDF079; /* RMDF079 */ - union iodefine_reg32_t RMDF179; /* RMDF179 */ -/* end of struct st_rscan_from_rscan0rmidp */ - - volatile uint8_t dummy179[768]; /* */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID0; /* RFID0 */ - union iodefine_reg32_t RFPTR0; /* RFPTR0 */ - union iodefine_reg32_t RFDF00; /* RFDF00 */ - union iodefine_reg32_t RFDF10; /* RFDF10 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID1; /* RFID1 */ - union iodefine_reg32_t RFPTR1; /* RFPTR1 */ - union iodefine_reg32_t RFDF01; /* RFDF01 */ - union iodefine_reg32_t RFDF11; /* RFDF11 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID2; /* RFID2 */ - union iodefine_reg32_t RFPTR2; /* RFPTR2 */ - union iodefine_reg32_t RFDF02; /* RFDF02 */ - union iodefine_reg32_t RFDF12; /* RFDF12 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID3; /* RFID3 */ - union iodefine_reg32_t RFPTR3; /* RFPTR3 */ - union iodefine_reg32_t RFDF03; /* RFDF03 */ - union iodefine_reg32_t RFDF13; /* RFDF13 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID4; /* RFID4 */ - union iodefine_reg32_t RFPTR4; /* RFPTR4 */ - union iodefine_reg32_t RFDF04; /* RFDF04 */ - union iodefine_reg32_t RFDF14; /* RFDF14 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID5; /* RFID5 */ - union iodefine_reg32_t RFPTR5; /* RFPTR5 */ - union iodefine_reg32_t RFDF05; /* RFDF05 */ - union iodefine_reg32_t RFDF15; /* RFDF15 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID6; /* RFID6 */ - union iodefine_reg32_t RFPTR6; /* RFPTR6 */ - union iodefine_reg32_t RFDF06; /* RFDF06 */ - union iodefine_reg32_t RFDF16; /* RFDF16 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0rfidm */ - union iodefine_reg32_t RFID7; /* RFID7 */ - union iodefine_reg32_t RFPTR7; /* RFPTR7 */ - union iodefine_reg32_t RFDF07; /* RFDF07 */ - union iodefine_reg32_t RFDF17; /* RFDF17 */ -/* end of struct st_rscan_from_rscan0rfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID0; /* CFID0 */ - union iodefine_reg32_t CFPTR0; /* CFPTR0 */ - union iodefine_reg32_t CFDF00; /* CFDF00 */ - union iodefine_reg32_t CFDF10; /* CFDF10 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID1; /* CFID1 */ - union iodefine_reg32_t CFPTR1; /* CFPTR1 */ - union iodefine_reg32_t CFDF01; /* CFDF01 */ - union iodefine_reg32_t CFDF11; /* CFDF11 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID2; /* CFID2 */ - union iodefine_reg32_t CFPTR2; /* CFPTR2 */ - union iodefine_reg32_t CFDF02; /* CFDF02 */ - union iodefine_reg32_t CFDF12; /* CFDF12 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID3; /* CFID3 */ - union iodefine_reg32_t CFPTR3; /* CFPTR3 */ - union iodefine_reg32_t CFDF03; /* CFDF03 */ - union iodefine_reg32_t CFDF13; /* CFDF13 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID4; /* CFID4 */ - union iodefine_reg32_t CFPTR4; /* CFPTR4 */ - union iodefine_reg32_t CFDF04; /* CFDF04 */ - union iodefine_reg32_t CFDF14; /* CFDF14 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID5; /* CFID5 */ - union iodefine_reg32_t CFPTR5; /* CFPTR5 */ - union iodefine_reg32_t CFDF05; /* CFDF05 */ - union iodefine_reg32_t CFDF15; /* CFDF15 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID6; /* CFID6 */ - union iodefine_reg32_t CFPTR6; /* CFPTR6 */ - union iodefine_reg32_t CFDF06; /* CFDF06 */ - union iodefine_reg32_t CFDF16; /* CFDF16 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID7; /* CFID7 */ - union iodefine_reg32_t CFPTR7; /* CFPTR7 */ - union iodefine_reg32_t CFDF07; /* CFDF07 */ - union iodefine_reg32_t CFDF17; /* CFDF17 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID8; /* CFID8 */ - union iodefine_reg32_t CFPTR8; /* CFPTR8 */ - union iodefine_reg32_t CFDF08; /* CFDF08 */ - union iodefine_reg32_t CFDF18; /* CFDF18 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID9; /* CFID9 */ - union iodefine_reg32_t CFPTR9; /* CFPTR9 */ - union iodefine_reg32_t CFDF09; /* CFDF09 */ - union iodefine_reg32_t CFDF19; /* CFDF19 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID10; /* CFID10 */ - union iodefine_reg32_t CFPTR10; /* CFPTR10 */ - union iodefine_reg32_t CFDF010; /* CFDF010 */ - union iodefine_reg32_t CFDF110; /* CFDF110 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID11; /* CFID11 */ - union iodefine_reg32_t CFPTR11; /* CFPTR11 */ - union iodefine_reg32_t CFDF011; /* CFDF011 */ - union iodefine_reg32_t CFDF111; /* CFDF111 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID12; /* CFID12 */ - union iodefine_reg32_t CFPTR12; /* CFPTR12 */ - union iodefine_reg32_t CFDF012; /* CFDF012 */ - union iodefine_reg32_t CFDF112; /* CFDF112 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID13; /* CFID13 */ - union iodefine_reg32_t CFPTR13; /* CFPTR13 */ - union iodefine_reg32_t CFDF013; /* CFDF013 */ - union iodefine_reg32_t CFDF113; /* CFDF113 */ -/* end of struct st_rscan_from_rscan0cfidm */ - -/* start of struct st_rscan_from_rscan0cfidm */ - union iodefine_reg32_t CFID14; /* CFID14 */ - union iodefine_reg32_t CFPTR14; /* CFPTR14 */ - union iodefine_reg32_t CFDF014; /* CFDF014 */ - union iodefine_reg32_t CFDF114; /* CFDF114 */ -/* end of struct st_rscan_from_rscan0cfidm */ - - volatile uint8_t dummy180[144]; /* */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID0; /* TMID0 */ - union iodefine_reg32_t TMPTR0; /* TMPTR0 */ - union iodefine_reg32_t TMDF00; /* TMDF00 */ - union iodefine_reg32_t TMDF10; /* TMDF10 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID1; /* TMID1 */ - union iodefine_reg32_t TMPTR1; /* TMPTR1 */ - union iodefine_reg32_t TMDF01; /* TMDF01 */ - union iodefine_reg32_t TMDF11; /* TMDF11 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID2; /* TMID2 */ - union iodefine_reg32_t TMPTR2; /* TMPTR2 */ - union iodefine_reg32_t TMDF02; /* TMDF02 */ - union iodefine_reg32_t TMDF12; /* TMDF12 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID3; /* TMID3 */ - union iodefine_reg32_t TMPTR3; /* TMPTR3 */ - union iodefine_reg32_t TMDF03; /* TMDF03 */ - union iodefine_reg32_t TMDF13; /* TMDF13 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID4; /* TMID4 */ - union iodefine_reg32_t TMPTR4; /* TMPTR4 */ - union iodefine_reg32_t TMDF04; /* TMDF04 */ - union iodefine_reg32_t TMDF14; /* TMDF14 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID5; /* TMID5 */ - union iodefine_reg32_t TMPTR5; /* TMPTR5 */ - union iodefine_reg32_t TMDF05; /* TMDF05 */ - union iodefine_reg32_t TMDF15; /* TMDF15 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID6; /* TMID6 */ - union iodefine_reg32_t TMPTR6; /* TMPTR6 */ - union iodefine_reg32_t TMDF06; /* TMDF06 */ - union iodefine_reg32_t TMDF16; /* TMDF16 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID7; /* TMID7 */ - union iodefine_reg32_t TMPTR7; /* TMPTR7 */ - union iodefine_reg32_t TMDF07; /* TMDF07 */ - union iodefine_reg32_t TMDF17; /* TMDF17 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID8; /* TMID8 */ - union iodefine_reg32_t TMPTR8; /* TMPTR8 */ - union iodefine_reg32_t TMDF08; /* TMDF08 */ - union iodefine_reg32_t TMDF18; /* TMDF18 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID9; /* TMID9 */ - union iodefine_reg32_t TMPTR9; /* TMPTR9 */ - union iodefine_reg32_t TMDF09; /* TMDF09 */ - union iodefine_reg32_t TMDF19; /* TMDF19 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID10; /* TMID10 */ - union iodefine_reg32_t TMPTR10; /* TMPTR10 */ - union iodefine_reg32_t TMDF010; /* TMDF010 */ - union iodefine_reg32_t TMDF110; /* TMDF110 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID11; /* TMID11 */ - union iodefine_reg32_t TMPTR11; /* TMPTR11 */ - union iodefine_reg32_t TMDF011; /* TMDF011 */ - union iodefine_reg32_t TMDF111; /* TMDF111 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID12; /* TMID12 */ - union iodefine_reg32_t TMPTR12; /* TMPTR12 */ - union iodefine_reg32_t TMDF012; /* TMDF012 */ - union iodefine_reg32_t TMDF112; /* TMDF112 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID13; /* TMID13 */ - union iodefine_reg32_t TMPTR13; /* TMPTR13 */ - union iodefine_reg32_t TMDF013; /* TMDF013 */ - union iodefine_reg32_t TMDF113; /* TMDF113 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID14; /* TMID14 */ - union iodefine_reg32_t TMPTR14; /* TMPTR14 */ - union iodefine_reg32_t TMDF014; /* TMDF014 */ - union iodefine_reg32_t TMDF114; /* TMDF114 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID15; /* TMID15 */ - union iodefine_reg32_t TMPTR15; /* TMPTR15 */ - union iodefine_reg32_t TMDF015; /* TMDF015 */ - union iodefine_reg32_t TMDF115; /* TMDF115 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID16; /* TMID16 */ - union iodefine_reg32_t TMPTR16; /* TMPTR16 */ - union iodefine_reg32_t TMDF016; /* TMDF016 */ - union iodefine_reg32_t TMDF116; /* TMDF116 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID17; /* TMID17 */ - union iodefine_reg32_t TMPTR17; /* TMPTR17 */ - union iodefine_reg32_t TMDF017; /* TMDF017 */ - union iodefine_reg32_t TMDF117; /* TMDF117 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID18; /* TMID18 */ - union iodefine_reg32_t TMPTR18; /* TMPTR18 */ - union iodefine_reg32_t TMDF018; /* TMDF018 */ - union iodefine_reg32_t TMDF118; /* TMDF118 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID19; /* TMID19 */ - union iodefine_reg32_t TMPTR19; /* TMPTR19 */ - union iodefine_reg32_t TMDF019; /* TMDF019 */ - union iodefine_reg32_t TMDF119; /* TMDF119 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID20; /* TMID20 */ - union iodefine_reg32_t TMPTR20; /* TMPTR20 */ - union iodefine_reg32_t TMDF020; /* TMDF020 */ - union iodefine_reg32_t TMDF120; /* TMDF120 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID21; /* TMID21 */ - union iodefine_reg32_t TMPTR21; /* TMPTR21 */ - union iodefine_reg32_t TMDF021; /* TMDF021 */ - union iodefine_reg32_t TMDF121; /* TMDF121 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID22; /* TMID22 */ - union iodefine_reg32_t TMPTR22; /* TMPTR22 */ - union iodefine_reg32_t TMDF022; /* TMDF022 */ - union iodefine_reg32_t TMDF122; /* TMDF122 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID23; /* TMID23 */ - union iodefine_reg32_t TMPTR23; /* TMPTR23 */ - union iodefine_reg32_t TMDF023; /* TMDF023 */ - union iodefine_reg32_t TMDF123; /* TMDF123 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID24; /* TMID24 */ - union iodefine_reg32_t TMPTR24; /* TMPTR24 */ - union iodefine_reg32_t TMDF024; /* TMDF024 */ - union iodefine_reg32_t TMDF124; /* TMDF124 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID25; /* TMID25 */ - union iodefine_reg32_t TMPTR25; /* TMPTR25 */ - union iodefine_reg32_t TMDF025; /* TMDF025 */ - union iodefine_reg32_t TMDF125; /* TMDF125 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID26; /* TMID26 */ - union iodefine_reg32_t TMPTR26; /* TMPTR26 */ - union iodefine_reg32_t TMDF026; /* TMDF026 */ - union iodefine_reg32_t TMDF126; /* TMDF126 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID27; /* TMID27 */ - union iodefine_reg32_t TMPTR27; /* TMPTR27 */ - union iodefine_reg32_t TMDF027; /* TMDF027 */ - union iodefine_reg32_t TMDF127; /* TMDF127 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID28; /* TMID28 */ - union iodefine_reg32_t TMPTR28; /* TMPTR28 */ - union iodefine_reg32_t TMDF028; /* TMDF028 */ - union iodefine_reg32_t TMDF128; /* TMDF128 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID29; /* TMID29 */ - union iodefine_reg32_t TMPTR29; /* TMPTR29 */ - union iodefine_reg32_t TMDF029; /* TMDF029 */ - union iodefine_reg32_t TMDF129; /* TMDF129 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID30; /* TMID30 */ - union iodefine_reg32_t TMPTR30; /* TMPTR30 */ - union iodefine_reg32_t TMDF030; /* TMDF030 */ - union iodefine_reg32_t TMDF130; /* TMDF130 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID31; /* TMID31 */ - union iodefine_reg32_t TMPTR31; /* TMPTR31 */ - union iodefine_reg32_t TMDF031; /* TMDF031 */ - union iodefine_reg32_t TMDF131; /* TMDF131 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID32; /* TMID32 */ - union iodefine_reg32_t TMPTR32; /* TMPTR32 */ - union iodefine_reg32_t TMDF032; /* TMDF032 */ - union iodefine_reg32_t TMDF132; /* TMDF132 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID33; /* TMID33 */ - union iodefine_reg32_t TMPTR33; /* TMPTR33 */ - union iodefine_reg32_t TMDF033; /* TMDF033 */ - union iodefine_reg32_t TMDF133; /* TMDF133 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID34; /* TMID34 */ - union iodefine_reg32_t TMPTR34; /* TMPTR34 */ - union iodefine_reg32_t TMDF034; /* TMDF034 */ - union iodefine_reg32_t TMDF134; /* TMDF134 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID35; /* TMID35 */ - union iodefine_reg32_t TMPTR35; /* TMPTR35 */ - union iodefine_reg32_t TMDF035; /* TMDF035 */ - union iodefine_reg32_t TMDF135; /* TMDF135 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID36; /* TMID36 */ - union iodefine_reg32_t TMPTR36; /* TMPTR36 */ - union iodefine_reg32_t TMDF036; /* TMDF036 */ - union iodefine_reg32_t TMDF136; /* TMDF136 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID37; /* TMID37 */ - union iodefine_reg32_t TMPTR37; /* TMPTR37 */ - union iodefine_reg32_t TMDF037; /* TMDF037 */ - union iodefine_reg32_t TMDF137; /* TMDF137 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID38; /* TMID38 */ - union iodefine_reg32_t TMPTR38; /* TMPTR38 */ - union iodefine_reg32_t TMDF038; /* TMDF038 */ - union iodefine_reg32_t TMDF138; /* TMDF138 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID39; /* TMID39 */ - union iodefine_reg32_t TMPTR39; /* TMPTR39 */ - union iodefine_reg32_t TMDF039; /* TMDF039 */ - union iodefine_reg32_t TMDF139; /* TMDF139 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID40; /* TMID40 */ - union iodefine_reg32_t TMPTR40; /* TMPTR40 */ - union iodefine_reg32_t TMDF040; /* TMDF040 */ - union iodefine_reg32_t TMDF140; /* TMDF140 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID41; /* TMID41 */ - union iodefine_reg32_t TMPTR41; /* TMPTR41 */ - union iodefine_reg32_t TMDF041; /* TMDF041 */ - union iodefine_reg32_t TMDF141; /* TMDF141 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID42; /* TMID42 */ - union iodefine_reg32_t TMPTR42; /* TMPTR42 */ - union iodefine_reg32_t TMDF042; /* TMDF042 */ - union iodefine_reg32_t TMDF142; /* TMDF142 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID43; /* TMID43 */ - union iodefine_reg32_t TMPTR43; /* TMPTR43 */ - union iodefine_reg32_t TMDF043; /* TMDF043 */ - union iodefine_reg32_t TMDF143; /* TMDF143 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID44; /* TMID44 */ - union iodefine_reg32_t TMPTR44; /* TMPTR44 */ - union iodefine_reg32_t TMDF044; /* TMDF044 */ - union iodefine_reg32_t TMDF144; /* TMDF144 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID45; /* TMID45 */ - union iodefine_reg32_t TMPTR45; /* TMPTR45 */ - union iodefine_reg32_t TMDF045; /* TMDF045 */ - union iodefine_reg32_t TMDF145; /* TMDF145 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID46; /* TMID46 */ - union iodefine_reg32_t TMPTR46; /* TMPTR46 */ - union iodefine_reg32_t TMDF046; /* TMDF046 */ - union iodefine_reg32_t TMDF146; /* TMDF146 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID47; /* TMID47 */ - union iodefine_reg32_t TMPTR47; /* TMPTR47 */ - union iodefine_reg32_t TMDF047; /* TMDF047 */ - union iodefine_reg32_t TMDF147; /* TMDF147 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID48; /* TMID48 */ - union iodefine_reg32_t TMPTR48; /* TMPTR48 */ - union iodefine_reg32_t TMDF048; /* TMDF048 */ - union iodefine_reg32_t TMDF148; /* TMDF148 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID49; /* TMID49 */ - union iodefine_reg32_t TMPTR49; /* TMPTR49 */ - union iodefine_reg32_t TMDF049; /* TMDF049 */ - union iodefine_reg32_t TMDF149; /* TMDF149 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID50; /* TMID50 */ - union iodefine_reg32_t TMPTR50; /* TMPTR50 */ - union iodefine_reg32_t TMDF050; /* TMDF050 */ - union iodefine_reg32_t TMDF150; /* TMDF150 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID51; /* TMID51 */ - union iodefine_reg32_t TMPTR51; /* TMPTR51 */ - union iodefine_reg32_t TMDF051; /* TMDF051 */ - union iodefine_reg32_t TMDF151; /* TMDF151 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID52; /* TMID52 */ - union iodefine_reg32_t TMPTR52; /* TMPTR52 */ - union iodefine_reg32_t TMDF052; /* TMDF052 */ - union iodefine_reg32_t TMDF152; /* TMDF152 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID53; /* TMID53 */ - union iodefine_reg32_t TMPTR53; /* TMPTR53 */ - union iodefine_reg32_t TMDF053; /* TMDF053 */ - union iodefine_reg32_t TMDF153; /* TMDF153 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID54; /* TMID54 */ - union iodefine_reg32_t TMPTR54; /* TMPTR54 */ - union iodefine_reg32_t TMDF054; /* TMDF054 */ - union iodefine_reg32_t TMDF154; /* TMDF154 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID55; /* TMID55 */ - union iodefine_reg32_t TMPTR55; /* TMPTR55 */ - union iodefine_reg32_t TMDF055; /* TMDF055 */ - union iodefine_reg32_t TMDF155; /* TMDF155 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID56; /* TMID56 */ - union iodefine_reg32_t TMPTR56; /* TMPTR56 */ - union iodefine_reg32_t TMDF056; /* TMDF056 */ - union iodefine_reg32_t TMDF156; /* TMDF156 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID57; /* TMID57 */ - union iodefine_reg32_t TMPTR57; /* TMPTR57 */ - union iodefine_reg32_t TMDF057; /* TMDF057 */ - union iodefine_reg32_t TMDF157; /* TMDF157 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID58; /* TMID58 */ - union iodefine_reg32_t TMPTR58; /* TMPTR58 */ - union iodefine_reg32_t TMDF058; /* TMDF058 */ - union iodefine_reg32_t TMDF158; /* TMDF158 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID59; /* TMID59 */ - union iodefine_reg32_t TMPTR59; /* TMPTR59 */ - union iodefine_reg32_t TMDF059; /* TMDF059 */ - union iodefine_reg32_t TMDF159; /* TMDF159 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID60; /* TMID60 */ - union iodefine_reg32_t TMPTR60; /* TMPTR60 */ - union iodefine_reg32_t TMDF060; /* TMDF060 */ - union iodefine_reg32_t TMDF160; /* TMDF160 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID61; /* TMID61 */ - union iodefine_reg32_t TMPTR61; /* TMPTR61 */ - union iodefine_reg32_t TMDF061; /* TMDF061 */ - union iodefine_reg32_t TMDF161; /* TMDF161 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID62; /* TMID62 */ - union iodefine_reg32_t TMPTR62; /* TMPTR62 */ - union iodefine_reg32_t TMDF062; /* TMDF062 */ - union iodefine_reg32_t TMDF162; /* TMDF162 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID63; /* TMID63 */ - union iodefine_reg32_t TMPTR63; /* TMPTR63 */ - union iodefine_reg32_t TMDF063; /* TMDF063 */ - union iodefine_reg32_t TMDF163; /* TMDF163 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID64; /* TMID64 */ - union iodefine_reg32_t TMPTR64; /* TMPTR64 */ - union iodefine_reg32_t TMDF064; /* TMDF064 */ - union iodefine_reg32_t TMDF164; /* TMDF164 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID65; /* TMID65 */ - union iodefine_reg32_t TMPTR65; /* TMPTR65 */ - union iodefine_reg32_t TMDF065; /* TMDF065 */ - union iodefine_reg32_t TMDF165; /* TMDF165 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID66; /* TMID66 */ - union iodefine_reg32_t TMPTR66; /* TMPTR66 */ - union iodefine_reg32_t TMDF066; /* TMDF066 */ - union iodefine_reg32_t TMDF166; /* TMDF166 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID67; /* TMID67 */ - union iodefine_reg32_t TMPTR67; /* TMPTR67 */ - union iodefine_reg32_t TMDF067; /* TMDF067 */ - union iodefine_reg32_t TMDF167; /* TMDF167 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID68; /* TMID68 */ - union iodefine_reg32_t TMPTR68; /* TMPTR68 */ - union iodefine_reg32_t TMDF068; /* TMDF068 */ - union iodefine_reg32_t TMDF168; /* TMDF168 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID69; /* TMID69 */ - union iodefine_reg32_t TMPTR69; /* TMPTR69 */ - union iodefine_reg32_t TMDF069; /* TMDF069 */ - union iodefine_reg32_t TMDF169; /* TMDF169 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID70; /* TMID70 */ - union iodefine_reg32_t TMPTR70; /* TMPTR70 */ - union iodefine_reg32_t TMDF070; /* TMDF070 */ - union iodefine_reg32_t TMDF170; /* TMDF170 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID71; /* TMID71 */ - union iodefine_reg32_t TMPTR71; /* TMPTR71 */ - union iodefine_reg32_t TMDF071; /* TMDF071 */ - union iodefine_reg32_t TMDF171; /* TMDF171 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID72; /* TMID72 */ - union iodefine_reg32_t TMPTR72; /* TMPTR72 */ - union iodefine_reg32_t TMDF072; /* TMDF072 */ - union iodefine_reg32_t TMDF172; /* TMDF172 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID73; /* TMID73 */ - union iodefine_reg32_t TMPTR73; /* TMPTR73 */ - union iodefine_reg32_t TMDF073; /* TMDF073 */ - union iodefine_reg32_t TMDF173; /* TMDF173 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID74; /* TMID74 */ - union iodefine_reg32_t TMPTR74; /* TMPTR74 */ - union iodefine_reg32_t TMDF074; /* TMDF074 */ - union iodefine_reg32_t TMDF174; /* TMDF174 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID75; /* TMID75 */ - union iodefine_reg32_t TMPTR75; /* TMPTR75 */ - union iodefine_reg32_t TMDF075; /* TMDF075 */ - union iodefine_reg32_t TMDF175; /* TMDF175 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID76; /* TMID76 */ - union iodefine_reg32_t TMPTR76; /* TMPTR76 */ - union iodefine_reg32_t TMDF076; /* TMDF076 */ - union iodefine_reg32_t TMDF176; /* TMDF176 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID77; /* TMID77 */ - union iodefine_reg32_t TMPTR77; /* TMPTR77 */ - union iodefine_reg32_t TMDF077; /* TMDF077 */ - union iodefine_reg32_t TMDF177; /* TMDF177 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID78; /* TMID78 */ - union iodefine_reg32_t TMPTR78; /* TMPTR78 */ - union iodefine_reg32_t TMDF078; /* TMDF078 */ - union iodefine_reg32_t TMDF178; /* TMDF178 */ -/* end of struct st_rscan_from_rscan0tmidp */ - -/* start of struct st_rscan_from_rscan0tmidp */ - union iodefine_reg32_t TMID79; /* TMID79 */ - union iodefine_reg32_t TMPTR79; /* TMPTR79 */ - union iodefine_reg32_t TMDF079; /* TMDF079 */ - union iodefine_reg32_t TMDF179; /* TMDF179 */ -/* end of struct st_rscan_from_rscan0tmidp */ - - volatile uint8_t dummy181[768]; /* */ -#define RSCAN0_THLACC0_COUNT 5 - union iodefine_reg32_t THLACC0; /* THLACC0 */ - union iodefine_reg32_t THLACC1; /* THLACC1 */ - union iodefine_reg32_t THLACC2; /* THLACC2 */ - union iodefine_reg32_t THLACC3; /* THLACC3 */ - union iodefine_reg32_t THLACC4; /* THLACC4 */ - -}; - - -struct st_rscan_from_rscan0cncfg -{ - union iodefine_reg32_t CnCFG; /* CnCFG */ - union iodefine_reg32_t CnCTR; /* CnCTR */ - union iodefine_reg32_t CnSTS; /* CnSTS */ - union iodefine_reg32_t CnERFL; /* CnERFL */ -}; - - -struct st_rscan_from_rscan0gaflidj -{ - union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ - union iodefine_reg32_t GAFLMj; /* GAFLMj */ - union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ - union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ -}; - - -struct st_rscan_from_rscan0rmidp -{ - union iodefine_reg32_t RMIDp; /* RMIDp */ - union iodefine_reg32_t RMPTRp; /* RMPTRp */ - union iodefine_reg32_t RMDF0p; /* RMDF0p */ - union iodefine_reg32_t RMDF1p; /* RMDF1p */ -}; - - -struct st_rscan_from_rscan0rfidm -{ - union iodefine_reg32_t RFIDm; /* RFIDm */ - union iodefine_reg32_t RFPTRm; /* RFPTRm */ - union iodefine_reg32_t RFDF0m; /* RFDF0m */ - union iodefine_reg32_t RFDF1m; /* RFDF1m */ -}; - - -struct st_rscan_from_rscan0tmidp -{ - union iodefine_reg32_t TMIDp; /* TMIDp */ - union iodefine_reg32_t TMPTRp; /* TMPTRp */ - union iodefine_reg32_t TMDF0p; /* TMDF0p */ - union iodefine_reg32_t TMDF1p; /* TMDF1p */ -}; - - -struct st_rscan_from_rscan0cfidm -{ - union iodefine_reg32_t CFIDm; /* CFIDm */ - union iodefine_reg32_t CFPTRm; /* CFPTRm */ - union iodefine_reg32_t CFDF0m; /* CFDF0m */ - union iodefine_reg32_t CFDF1m; /* CFDF1m */ -}; - - #define RSCAN0 (*(struct st_rscan0 *)0xE803A000uL) /* RSCAN0 */ -/* Start of channnel array defines of RSCAN0 */ +/* Start of channel array defines of RSCAN0 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0CFIDm_COUNT 15 -#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_CFIDm_COUNT (15) +#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \ &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \ @@ -1919,10 +63,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0TMIDp_COUNT 80 -#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_TMIDp_COUNT (80) +#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \ &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \ @@ -2017,10 +161,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */ -/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */ -#define RSCAN_FROM_RSCAN0RFIDm_COUNT 8 -#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */ +#define RSCAN_FROM_RSCAN0_RFIDm_COUNT (8) +#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ @@ -2034,10 +178,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */ -/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */ -#define RSCAN_FROM_RSCAN0RMIDp_COUNT 80 -#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */ +/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */ +#define RSCAN_FROM_RSCAN0_RMIDp_COUNT (80) +#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \ &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \ @@ -2132,10 +276,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */ -/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */ -#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT 16 -#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */ +/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */ +#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT (16) +#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \ &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \ @@ -2158,10 +302,10 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */ -/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */ -/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */ -#define RSCAN_FROM_RSCAN0CnCFG_COUNT 5 -#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \ +/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */ +/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */ +#define RSCAN_FROM_RSCAN0_CnCFG_COUNT (5) +#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ @@ -2171,6868 +315,9032 @@ struct st_rscan_from_rscan0cfidm #define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */ #define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */ -/* End of channnel array defines of RSCAN0 */ +/* End of channel array defines of RSCAN0 */ + + +#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32) +#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L]) +#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL]) +#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH]) +#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H]) +#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL]) +#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH]) +#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32) +#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L]) +#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL]) +#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH]) +#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H]) +#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL]) +#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH]) +#define RSCAN0C0STS (RSCAN0.C0STS.UINT32) +#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L]) +#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL]) +#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH]) +#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H]) +#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL]) +#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH]) +#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32) +#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L]) +#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL]) +#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH]) +#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H]) +#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL]) +#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH]) +#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32) +#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L]) +#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL]) +#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH]) +#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H]) +#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL]) +#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH]) +#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32) +#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L]) +#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL]) +#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH]) +#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H]) +#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL]) +#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH]) +#define RSCAN0C1STS (RSCAN0.C1STS.UINT32) +#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L]) +#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL]) +#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH]) +#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H]) +#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL]) +#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH]) +#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32) +#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L]) +#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL]) +#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH]) +#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H]) +#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL]) +#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH]) +#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32) +#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L]) +#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL]) +#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH]) +#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H]) +#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL]) +#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH]) +#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32) +#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L]) +#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL]) +#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH]) +#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H]) +#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL]) +#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH]) +#define RSCAN0C2STS (RSCAN0.C2STS.UINT32) +#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L]) +#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL]) +#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH]) +#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H]) +#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL]) +#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH]) +#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32) +#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L]) +#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL]) +#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH]) +#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H]) +#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL]) +#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH]) +#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32) +#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L]) +#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL]) +#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH]) +#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H]) +#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL]) +#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH]) +#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32) +#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L]) +#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL]) +#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH]) +#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H]) +#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL]) +#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH]) +#define RSCAN0C3STS (RSCAN0.C3STS.UINT32) +#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L]) +#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL]) +#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH]) +#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H]) +#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL]) +#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH]) +#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32) +#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L]) +#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL]) +#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH]) +#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H]) +#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL]) +#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH]) +#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32) +#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L]) +#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL]) +#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH]) +#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H]) +#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL]) +#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH]) +#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32) +#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L]) +#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL]) +#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH]) +#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H]) +#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL]) +#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH]) +#define RSCAN0C4STS (RSCAN0.C4STS.UINT32) +#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L]) +#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL]) +#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH]) +#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H]) +#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL]) +#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH]) +#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32) +#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L]) +#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL]) +#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH]) +#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H]) +#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL]) +#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH]) +#define RSCAN0GCFG (RSCAN0.GCFG.UINT32) +#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L]) +#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL]) +#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH]) +#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H]) +#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL]) +#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH]) +#define RSCAN0GCTR (RSCAN0.GCTR.UINT32) +#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L]) +#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL]) +#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH]) +#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H]) +#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL]) +#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH]) +#define RSCAN0GSTS (RSCAN0.GSTS.UINT32) +#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L]) +#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL]) +#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH]) +#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H]) +#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL]) +#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH]) +#define RSCAN0GERFL (RSCAN0.GERFL.UINT32) +#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L]) +#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL]) +#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH]) +#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H]) +#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL]) +#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH]) +#define RSCAN0GTSC (RSCAN0.GTSC.UINT32) +#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L]) +#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H]) +#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32) +#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L]) +#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL]) +#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH]) +#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H]) +#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL]) +#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32) +#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH]) +#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32) +#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L]) +#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL]) +#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH]) +#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H]) +#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL]) +#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH]) +#define RSCAN0RMNB (RSCAN0.RMNB.UINT32) +#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L]) +#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL]) +#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH]) +#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H]) +#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL]) +#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH]) +#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32) +#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L]) +#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL]) +#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH]) +#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H]) +#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL]) +#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH]) +#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32) +#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L]) +#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL]) +#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH]) +#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H]) +#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL]) +#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH]) +#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32) +#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L]) +#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL]) +#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH]) +#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H]) +#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL]) +#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH]) +#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32) +#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L]) +#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL]) +#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH]) +#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H]) +#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL]) +#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH]) +#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32) +#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L]) +#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL]) +#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH]) +#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H]) +#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL]) +#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH]) +#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32) +#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L]) +#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL]) +#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH]) +#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H]) +#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL]) +#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH]) +#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32) +#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L]) +#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL]) +#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH]) +#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H]) +#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL]) +#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH]) +#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32) +#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L]) +#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL]) +#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH]) +#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H]) +#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL]) +#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH]) +#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32) +#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L]) +#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL]) +#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH]) +#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H]) +#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL]) +#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH]) +#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32) +#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L]) +#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL]) +#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH]) +#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H]) +#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL]) +#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH]) +#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32) +#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L]) +#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL]) +#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH]) +#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H]) +#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL]) +#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH]) +#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32) +#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L]) +#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL]) +#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH]) +#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H]) +#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL]) +#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH]) +#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32) +#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L]) +#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL]) +#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH]) +#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H]) +#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL]) +#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH]) +#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32) +#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L]) +#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL]) +#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH]) +#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H]) +#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL]) +#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH]) +#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32) +#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L]) +#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL]) +#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH]) +#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H]) +#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL]) +#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH]) +#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32) +#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L]) +#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL]) +#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH]) +#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H]) +#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL]) +#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH]) +#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32) +#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L]) +#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL]) +#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH]) +#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H]) +#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL]) +#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH]) +#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32) +#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L]) +#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL]) +#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH]) +#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H]) +#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL]) +#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH]) +#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32) +#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L]) +#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL]) +#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH]) +#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H]) +#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL]) +#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32) +#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L]) +#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H]) +#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32) +#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L]) +#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H]) +#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32) +#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L]) +#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H]) +#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32) +#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L]) +#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H]) +#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32) +#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L]) +#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H]) +#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32) +#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L]) +#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H]) +#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32) +#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L]) +#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H]) +#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32) +#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L]) +#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H]) +#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32) +#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L]) +#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL]) +#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH]) +#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H]) +#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL]) +#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH]) +#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32) +#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L]) +#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL]) +#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH]) +#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H]) +#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL]) +#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH]) +#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32) +#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L]) +#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL]) +#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH]) +#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H]) +#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL]) +#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH]) +#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32) +#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L]) +#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL]) +#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH]) +#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H]) +#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL]) +#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH]) +#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32) +#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L]) +#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL]) +#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH]) +#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H]) +#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL]) +#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH]) +#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32) +#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L]) +#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL]) +#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH]) +#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H]) +#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL]) +#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH]) +#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32) +#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L]) +#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL]) +#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH]) +#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H]) +#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL]) +#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH]) +#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32) +#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L]) +#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL]) +#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH]) +#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H]) +#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL]) +#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH]) +#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32) +#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L]) +#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL]) +#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH]) +#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H]) +#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL]) +#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH]) +#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32) +#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L]) +#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL]) +#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH]) +#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H]) +#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL]) +#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH]) +#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32) +#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L]) +#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL]) +#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH]) +#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H]) +#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL]) +#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH]) +#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32) +#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L]) +#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL]) +#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH]) +#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H]) +#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL]) +#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH]) +#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32) +#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L]) +#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL]) +#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH]) +#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H]) +#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL]) +#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH]) +#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32) +#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L]) +#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL]) +#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH]) +#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H]) +#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL]) +#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH]) +#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32) +#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L]) +#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL]) +#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH]) +#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H]) +#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL]) +#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH]) +#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32) +#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L]) +#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL]) +#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH]) +#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H]) +#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL]) +#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH]) +#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32) +#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L]) +#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL]) +#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH]) +#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H]) +#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL]) +#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH]) +#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32) +#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L]) +#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL]) +#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH]) +#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H]) +#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL]) +#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH]) +#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32) +#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L]) +#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL]) +#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH]) +#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H]) +#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL]) +#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH]) +#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32) +#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L]) +#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL]) +#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH]) +#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H]) +#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL]) +#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH]) +#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32) +#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L]) +#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL]) +#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH]) +#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H]) +#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL]) +#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH]) +#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32) +#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L]) +#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL]) +#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH]) +#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H]) +#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL]) +#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH]) +#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32) +#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L]) +#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL]) +#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH]) +#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H]) +#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL]) +#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH]) +#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32) +#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L]) +#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL]) +#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH]) +#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H]) +#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL]) +#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH]) +#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32) +#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L]) +#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL]) +#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH]) +#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H]) +#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL]) +#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH]) +#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32) +#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L]) +#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL]) +#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH]) +#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H]) +#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL]) +#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH]) +#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32) +#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L]) +#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL]) +#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH]) +#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H]) +#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL]) +#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH]) +#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32) +#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L]) +#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL]) +#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH]) +#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H]) +#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL]) +#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH]) +#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32) +#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L]) +#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL]) +#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH]) +#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H]) +#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL]) +#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH]) +#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32) +#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L]) +#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL]) +#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH]) +#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H]) +#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL]) +#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32) +#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L]) +#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H]) +#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32) +#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L]) +#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H]) +#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32) +#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L]) +#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H]) +#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32) +#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L]) +#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H]) +#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32) +#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L]) +#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H]) +#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32) +#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L]) +#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H]) +#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32) +#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L]) +#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H]) +#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32) +#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L]) +#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H]) +#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32) +#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L]) +#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H]) +#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32) +#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L]) +#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H]) +#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32) +#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L]) +#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H]) +#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32) +#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L]) +#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H]) +#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32) +#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L]) +#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H]) +#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32) +#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L]) +#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H]) +#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH]) +#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32) +#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L]) +#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL]) +#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH]) +#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H]) +#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL]) +#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH]) +#define RSCAN0FESTS (RSCAN0.FESTS.UINT32) +#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L]) +#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL]) +#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH]) +#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H]) +#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL]) +#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH]) +#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32) +#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L]) +#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL]) +#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH]) +#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H]) +#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL]) +#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH]) +#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32) +#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L]) +#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL]) +#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH]) +#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H]) +#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL]) +#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH]) +#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32) +#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L]) +#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL]) +#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH]) +#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H]) +#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL]) +#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH]) +#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32) +#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L]) +#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL]) +#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH]) +#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H]) +#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL]) +#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH]) +#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32) +#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L]) +#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL]) +#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH]) +#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H]) +#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL]) +#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH]) +#define RSCAN0TMC0 (RSCAN0.TMC0) +#define RSCAN0TMC1 (RSCAN0.TMC1) +#define RSCAN0TMC2 (RSCAN0.TMC2) +#define RSCAN0TMC3 (RSCAN0.TMC3) +#define RSCAN0TMC4 (RSCAN0.TMC4) +#define RSCAN0TMC5 (RSCAN0.TMC5) +#define RSCAN0TMC6 (RSCAN0.TMC6) +#define RSCAN0TMC7 (RSCAN0.TMC7) +#define RSCAN0TMC8 (RSCAN0.TMC8) +#define RSCAN0TMC9 (RSCAN0.TMC9) +#define RSCAN0TMC10 (RSCAN0.TMC10) +#define RSCAN0TMC11 (RSCAN0.TMC11) +#define RSCAN0TMC12 (RSCAN0.TMC12) +#define RSCAN0TMC13 (RSCAN0.TMC13) +#define RSCAN0TMC14 (RSCAN0.TMC14) +#define RSCAN0TMC15 (RSCAN0.TMC15) +#define RSCAN0TMC16 (RSCAN0.TMC16) +#define RSCAN0TMC17 (RSCAN0.TMC17) +#define RSCAN0TMC18 (RSCAN0.TMC18) +#define RSCAN0TMC19 (RSCAN0.TMC19) +#define RSCAN0TMC20 (RSCAN0.TMC20) +#define RSCAN0TMC21 (RSCAN0.TMC21) +#define RSCAN0TMC22 (RSCAN0.TMC22) +#define RSCAN0TMC23 (RSCAN0.TMC23) +#define RSCAN0TMC24 (RSCAN0.TMC24) +#define RSCAN0TMC25 (RSCAN0.TMC25) +#define RSCAN0TMC26 (RSCAN0.TMC26) +#define RSCAN0TMC27 (RSCAN0.TMC27) +#define RSCAN0TMC28 (RSCAN0.TMC28) +#define RSCAN0TMC29 (RSCAN0.TMC29) +#define RSCAN0TMC30 (RSCAN0.TMC30) +#define RSCAN0TMC31 (RSCAN0.TMC31) +#define RSCAN0TMC32 (RSCAN0.TMC32) +#define RSCAN0TMC33 (RSCAN0.TMC33) +#define RSCAN0TMC34 (RSCAN0.TMC34) +#define RSCAN0TMC35 (RSCAN0.TMC35) +#define RSCAN0TMC36 (RSCAN0.TMC36) +#define RSCAN0TMC37 (RSCAN0.TMC37) +#define RSCAN0TMC38 (RSCAN0.TMC38) +#define RSCAN0TMC39 (RSCAN0.TMC39) +#define RSCAN0TMC40 (RSCAN0.TMC40) +#define RSCAN0TMC41 (RSCAN0.TMC41) +#define RSCAN0TMC42 (RSCAN0.TMC42) +#define RSCAN0TMC43 (RSCAN0.TMC43) +#define RSCAN0TMC44 (RSCAN0.TMC44) +#define RSCAN0TMC45 (RSCAN0.TMC45) +#define RSCAN0TMC46 (RSCAN0.TMC46) +#define RSCAN0TMC47 (RSCAN0.TMC47) +#define RSCAN0TMC48 (RSCAN0.TMC48) +#define RSCAN0TMC49 (RSCAN0.TMC49) +#define RSCAN0TMC50 (RSCAN0.TMC50) +#define RSCAN0TMC51 (RSCAN0.TMC51) +#define RSCAN0TMC52 (RSCAN0.TMC52) +#define RSCAN0TMC53 (RSCAN0.TMC53) +#define RSCAN0TMC54 (RSCAN0.TMC54) +#define RSCAN0TMC55 (RSCAN0.TMC55) +#define RSCAN0TMC56 (RSCAN0.TMC56) +#define RSCAN0TMC57 (RSCAN0.TMC57) +#define RSCAN0TMC58 (RSCAN0.TMC58) +#define RSCAN0TMC59 (RSCAN0.TMC59) +#define RSCAN0TMC60 (RSCAN0.TMC60) +#define RSCAN0TMC61 (RSCAN0.TMC61) +#define RSCAN0TMC62 (RSCAN0.TMC62) +#define RSCAN0TMC63 (RSCAN0.TMC63) +#define RSCAN0TMC64 (RSCAN0.TMC64) +#define RSCAN0TMC65 (RSCAN0.TMC65) +#define RSCAN0TMC66 (RSCAN0.TMC66) +#define RSCAN0TMC67 (RSCAN0.TMC67) +#define RSCAN0TMC68 (RSCAN0.TMC68) +#define RSCAN0TMC69 (RSCAN0.TMC69) +#define RSCAN0TMC70 (RSCAN0.TMC70) +#define RSCAN0TMC71 (RSCAN0.TMC71) +#define RSCAN0TMC72 (RSCAN0.TMC72) +#define RSCAN0TMC73 (RSCAN0.TMC73) +#define RSCAN0TMC74 (RSCAN0.TMC74) +#define RSCAN0TMC75 (RSCAN0.TMC75) +#define RSCAN0TMC76 (RSCAN0.TMC76) +#define RSCAN0TMC77 (RSCAN0.TMC77) +#define RSCAN0TMC78 (RSCAN0.TMC78) +#define RSCAN0TMC79 (RSCAN0.TMC79) +#define RSCAN0TMSTS0 (RSCAN0.TMSTS0) +#define RSCAN0TMSTS1 (RSCAN0.TMSTS1) +#define RSCAN0TMSTS2 (RSCAN0.TMSTS2) +#define RSCAN0TMSTS3 (RSCAN0.TMSTS3) +#define RSCAN0TMSTS4 (RSCAN0.TMSTS4) +#define RSCAN0TMSTS5 (RSCAN0.TMSTS5) +#define RSCAN0TMSTS6 (RSCAN0.TMSTS6) +#define RSCAN0TMSTS7 (RSCAN0.TMSTS7) +#define RSCAN0TMSTS8 (RSCAN0.TMSTS8) +#define RSCAN0TMSTS9 (RSCAN0.TMSTS9) +#define RSCAN0TMSTS10 (RSCAN0.TMSTS10) +#define RSCAN0TMSTS11 (RSCAN0.TMSTS11) +#define RSCAN0TMSTS12 (RSCAN0.TMSTS12) +#define RSCAN0TMSTS13 (RSCAN0.TMSTS13) +#define RSCAN0TMSTS14 (RSCAN0.TMSTS14) +#define RSCAN0TMSTS15 (RSCAN0.TMSTS15) +#define RSCAN0TMSTS16 (RSCAN0.TMSTS16) +#define RSCAN0TMSTS17 (RSCAN0.TMSTS17) +#define RSCAN0TMSTS18 (RSCAN0.TMSTS18) +#define RSCAN0TMSTS19 (RSCAN0.TMSTS19) +#define RSCAN0TMSTS20 (RSCAN0.TMSTS20) +#define RSCAN0TMSTS21 (RSCAN0.TMSTS21) +#define RSCAN0TMSTS22 (RSCAN0.TMSTS22) +#define RSCAN0TMSTS23 (RSCAN0.TMSTS23) +#define RSCAN0TMSTS24 (RSCAN0.TMSTS24) +#define RSCAN0TMSTS25 (RSCAN0.TMSTS25) +#define RSCAN0TMSTS26 (RSCAN0.TMSTS26) +#define RSCAN0TMSTS27 (RSCAN0.TMSTS27) +#define RSCAN0TMSTS28 (RSCAN0.TMSTS28) +#define RSCAN0TMSTS29 (RSCAN0.TMSTS29) +#define RSCAN0TMSTS30 (RSCAN0.TMSTS30) +#define RSCAN0TMSTS31 (RSCAN0.TMSTS31) +#define RSCAN0TMSTS32 (RSCAN0.TMSTS32) +#define RSCAN0TMSTS33 (RSCAN0.TMSTS33) +#define RSCAN0TMSTS34 (RSCAN0.TMSTS34) +#define RSCAN0TMSTS35 (RSCAN0.TMSTS35) +#define RSCAN0TMSTS36 (RSCAN0.TMSTS36) +#define RSCAN0TMSTS37 (RSCAN0.TMSTS37) +#define RSCAN0TMSTS38 (RSCAN0.TMSTS38) +#define RSCAN0TMSTS39 (RSCAN0.TMSTS39) +#define RSCAN0TMSTS40 (RSCAN0.TMSTS40) +#define RSCAN0TMSTS41 (RSCAN0.TMSTS41) +#define RSCAN0TMSTS42 (RSCAN0.TMSTS42) +#define RSCAN0TMSTS43 (RSCAN0.TMSTS43) +#define RSCAN0TMSTS44 (RSCAN0.TMSTS44) +#define RSCAN0TMSTS45 (RSCAN0.TMSTS45) +#define RSCAN0TMSTS46 (RSCAN0.TMSTS46) +#define RSCAN0TMSTS47 (RSCAN0.TMSTS47) +#define RSCAN0TMSTS48 (RSCAN0.TMSTS48) +#define RSCAN0TMSTS49 (RSCAN0.TMSTS49) +#define RSCAN0TMSTS50 (RSCAN0.TMSTS50) +#define RSCAN0TMSTS51 (RSCAN0.TMSTS51) +#define RSCAN0TMSTS52 (RSCAN0.TMSTS52) +#define RSCAN0TMSTS53 (RSCAN0.TMSTS53) +#define RSCAN0TMSTS54 (RSCAN0.TMSTS54) +#define RSCAN0TMSTS55 (RSCAN0.TMSTS55) +#define RSCAN0TMSTS56 (RSCAN0.TMSTS56) +#define RSCAN0TMSTS57 (RSCAN0.TMSTS57) +#define RSCAN0TMSTS58 (RSCAN0.TMSTS58) +#define RSCAN0TMSTS59 (RSCAN0.TMSTS59) +#define RSCAN0TMSTS60 (RSCAN0.TMSTS60) +#define RSCAN0TMSTS61 (RSCAN0.TMSTS61) +#define RSCAN0TMSTS62 (RSCAN0.TMSTS62) +#define RSCAN0TMSTS63 (RSCAN0.TMSTS63) +#define RSCAN0TMSTS64 (RSCAN0.TMSTS64) +#define RSCAN0TMSTS65 (RSCAN0.TMSTS65) +#define RSCAN0TMSTS66 (RSCAN0.TMSTS66) +#define RSCAN0TMSTS67 (RSCAN0.TMSTS67) +#define RSCAN0TMSTS68 (RSCAN0.TMSTS68) +#define RSCAN0TMSTS69 (RSCAN0.TMSTS69) +#define RSCAN0TMSTS70 (RSCAN0.TMSTS70) +#define RSCAN0TMSTS71 (RSCAN0.TMSTS71) +#define RSCAN0TMSTS72 (RSCAN0.TMSTS72) +#define RSCAN0TMSTS73 (RSCAN0.TMSTS73) +#define RSCAN0TMSTS74 (RSCAN0.TMSTS74) +#define RSCAN0TMSTS75 (RSCAN0.TMSTS75) +#define RSCAN0TMSTS76 (RSCAN0.TMSTS76) +#define RSCAN0TMSTS77 (RSCAN0.TMSTS77) +#define RSCAN0TMSTS78 (RSCAN0.TMSTS78) +#define RSCAN0TMSTS79 (RSCAN0.TMSTS79) +#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32) +#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32) +#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32) +#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32) +#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32) +#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32) +#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32) +#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32) +#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32) +#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L]) +#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H]) +#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32) +#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L]) +#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H]) +#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32) +#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L]) +#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H]) +#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH]) +#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32) +#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L]) +#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL]) +#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH]) +#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H]) +#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL]) +#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH]) +#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32) +#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L]) +#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL]) +#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH]) +#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H]) +#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL]) +#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH]) +#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32) +#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L]) +#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL]) +#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH]) +#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H]) +#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL]) +#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH]) +#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32) +#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L]) +#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL]) +#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH]) +#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H]) +#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL]) +#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH]) +#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32) +#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L]) +#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL]) +#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH]) +#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H]) +#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL]) +#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH]) +#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32) +#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L]) +#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL]) +#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH]) +#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H]) +#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL]) +#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH]) +#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32) +#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L]) +#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL]) +#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH]) +#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H]) +#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL]) +#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH]) +#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32) +#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L]) +#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL]) +#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH]) +#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H]) +#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL]) +#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH]) +#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32) +#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L]) +#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL]) +#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH]) +#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H]) +#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL]) +#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32) +#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L]) +#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H]) +#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32) +#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L]) +#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H]) +#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32) +#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L]) +#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H]) +#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32) +#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L]) +#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H]) +#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH]) +#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32) +#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L]) +#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL]) +#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH]) +#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H]) +#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL]) +#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32) +#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32) +#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32) +#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32) +#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH]) +#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32) +#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L]) +#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL]) +#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH]) +#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H]) +#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL]) +#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH]) +#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32) +#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L]) +#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL]) +#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH]) +#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H]) +#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL]) +#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH]) +#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32) +#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L]) +#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL]) +#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH]) +#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H]) +#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL]) +#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH]) +#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32) +#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L]) +#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL]) +#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH]) +#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H]) +#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL]) +#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH]) +#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32) +#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L]) +#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL]) +#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH]) +#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H]) +#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL]) +#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH]) +#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32) +#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L]) +#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL]) +#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH]) +#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H]) +#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL]) +#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH]) +#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32) +#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L]) +#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL]) +#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH]) +#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H]) +#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL]) +#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH]) +#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32) +#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L]) +#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL]) +#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH]) +#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H]) +#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL]) +#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH]) +#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32) +#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L]) +#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL]) +#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH]) +#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H]) +#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL]) +#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH]) +#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32) +#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L]) +#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL]) +#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH]) +#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H]) +#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL]) +#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH]) +#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32) +#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L]) +#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL]) +#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH]) +#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H]) +#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL]) +#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32) +#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L]) +#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H]) +#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32) +#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L]) +#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H]) +#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32) +#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L]) +#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H]) +#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32) +#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L]) +#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H]) +#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH]) +#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32) +#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L]) +#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL]) +#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH]) +#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H]) +#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL]) +#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32) +#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH]) +#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32) +#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L]) +#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL]) +#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH]) +#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H]) +#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL]) +#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH]) +#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32) +#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L]) +#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL]) +#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH]) +#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H]) +#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL]) +#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH]) +#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32) +#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L]) +#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL]) +#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH]) +#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H]) +#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL]) +#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH]) +#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32) +#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L]) +#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H]) +#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32) +#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L]) +#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL]) +#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH]) +#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H]) +#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL]) +#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH]) +#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32) +#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L]) +#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL]) +#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH]) +#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H]) +#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL]) +#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH]) +#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32) +#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L]) +#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL]) +#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH]) +#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H]) +#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL]) +#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH]) +#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32) +#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L]) +#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL]) +#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH]) +#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H]) +#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL]) +#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH]) +#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32) +#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L]) +#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL]) +#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH]) +#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H]) +#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL]) +#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH]) +#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32) +#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L]) +#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL]) +#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH]) +#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H]) +#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL]) +#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH]) +#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32) +#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L]) +#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL]) +#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH]) +#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H]) +#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL]) +#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH]) +#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32) +#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L]) +#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL]) +#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH]) +#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H]) +#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL]) +#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH]) +#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32) +#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L]) +#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL]) +#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH]) +#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H]) +#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL]) +#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH]) +#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32) +#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L]) +#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL]) +#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH]) +#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H]) +#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL]) +#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH]) +#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32) +#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L]) +#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL]) +#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH]) +#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H]) +#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL]) +#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH]) +#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32) +#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L]) +#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL]) +#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH]) +#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H]) +#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL]) +#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH]) +#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32) +#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L]) +#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL]) +#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH]) +#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H]) +#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL]) +#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH]) +#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32) +#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L]) +#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL]) +#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH]) +#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H]) +#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL]) +#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH]) +#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32) +#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L]) +#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL]) +#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH]) +#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H]) +#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL]) +#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH]) +#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32) +#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L]) +#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL]) +#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH]) +#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H]) +#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL]) +#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH]) +#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32) +#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L]) +#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL]) +#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH]) +#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H]) +#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL]) +#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH]) +#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32) +#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L]) +#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL]) +#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH]) +#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H]) +#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL]) +#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH]) +#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32) +#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L]) +#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL]) +#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH]) +#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H]) +#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL]) +#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH]) +#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32) +#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L]) +#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL]) +#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH]) +#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H]) +#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL]) +#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH]) +#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32) +#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L]) +#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL]) +#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH]) +#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H]) +#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL]) +#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH]) +#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32) +#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L]) +#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL]) +#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH]) +#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H]) +#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL]) +#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH]) +#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32) +#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L]) +#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL]) +#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH]) +#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H]) +#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL]) +#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH]) +#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32) +#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L]) +#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL]) +#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH]) +#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H]) +#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL]) +#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH]) +#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32) +#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L]) +#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL]) +#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH]) +#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H]) +#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL]) +#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH]) +#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32) +#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L]) +#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL]) +#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH]) +#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H]) +#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL]) +#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH]) +#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32) +#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L]) +#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL]) +#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH]) +#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H]) +#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL]) +#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH]) +#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32) +#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L]) +#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL]) +#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH]) +#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H]) +#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL]) +#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH]) +#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32) +#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L]) +#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL]) +#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH]) +#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H]) +#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL]) +#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH]) +#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32) +#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L]) +#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL]) +#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH]) +#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H]) +#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL]) +#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH]) +#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32) +#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L]) +#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL]) +#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH]) +#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H]) +#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL]) +#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH]) +#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32) +#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L]) +#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL]) +#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH]) +#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H]) +#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL]) +#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH]) +#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32) +#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L]) +#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL]) +#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH]) +#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H]) +#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL]) +#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH]) +#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32) +#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L]) +#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL]) +#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH]) +#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H]) +#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL]) +#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH]) +#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32) +#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L]) +#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL]) +#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH]) +#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H]) +#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL]) +#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH]) +#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32) +#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L]) +#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL]) +#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH]) +#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H]) +#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL]) +#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH]) +#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32) +#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L]) +#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL]) +#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH]) +#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H]) +#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL]) +#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH]) +#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32) +#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L]) +#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL]) +#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH]) +#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H]) +#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL]) +#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH]) +#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32) +#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L]) +#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL]) +#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH]) +#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H]) +#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL]) +#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH]) +#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32) +#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L]) +#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL]) +#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH]) +#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H]) +#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL]) +#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH]) +#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32) +#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L]) +#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL]) +#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH]) +#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H]) +#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL]) +#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH]) +#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32) +#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L]) +#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL]) +#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH]) +#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H]) +#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL]) +#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH]) +#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32) +#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L]) +#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL]) +#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH]) +#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H]) +#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL]) +#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH]) +#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32) +#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L]) +#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL]) +#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH]) +#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H]) +#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL]) +#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH]) +#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32) +#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L]) +#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL]) +#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH]) +#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H]) +#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL]) +#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH]) +#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32) +#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L]) +#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL]) +#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH]) +#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H]) +#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL]) +#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH]) +#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32) +#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L]) +#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL]) +#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH]) +#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H]) +#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL]) +#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH]) +#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32) +#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L]) +#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL]) +#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH]) +#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H]) +#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL]) +#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH]) +#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32) +#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L]) +#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL]) +#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH]) +#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H]) +#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL]) +#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH]) +#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32) +#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L]) +#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL]) +#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH]) +#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H]) +#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL]) +#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH]) +#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32) +#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L]) +#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL]) +#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH]) +#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H]) +#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL]) +#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH]) +#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32) +#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L]) +#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL]) +#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH]) +#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H]) +#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL]) +#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH]) +#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32) +#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L]) +#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL]) +#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH]) +#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H]) +#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL]) +#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH]) +#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32) +#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L]) +#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL]) +#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH]) +#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H]) +#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL]) +#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH]) +#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32) +#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L]) +#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL]) +#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH]) +#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H]) +#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL]) +#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH]) +#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32) +#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L]) +#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL]) +#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH]) +#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H]) +#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL]) +#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH]) +#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32) +#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L]) +#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL]) +#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH]) +#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H]) +#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL]) +#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH]) +#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32) +#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L]) +#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL]) +#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH]) +#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H]) +#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL]) +#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH]) +#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32) +#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L]) +#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL]) +#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH]) +#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H]) +#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL]) +#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH]) +#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32) +#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L]) +#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL]) +#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH]) +#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H]) +#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL]) +#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH]) +#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32) +#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L]) +#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL]) +#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH]) +#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H]) +#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL]) +#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH]) +#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32) +#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L]) +#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL]) +#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH]) +#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H]) +#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL]) +#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH]) +#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32) +#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L]) +#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL]) +#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH]) +#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H]) +#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL]) +#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH]) +#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32) +#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L]) +#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL]) +#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH]) +#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H]) +#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL]) +#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH]) +#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32) +#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L]) +#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL]) +#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH]) +#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H]) +#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL]) +#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH]) +#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32) +#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L]) +#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL]) +#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH]) +#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H]) +#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL]) +#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH]) +#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32) +#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L]) +#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL]) +#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH]) +#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H]) +#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL]) +#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH]) +#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32) +#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L]) +#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL]) +#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH]) +#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H]) +#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL]) +#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH]) +#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32) +#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L]) +#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL]) +#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH]) +#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H]) +#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL]) +#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH]) +#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32) +#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L]) +#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL]) +#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH]) +#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H]) +#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL]) +#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH]) +#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32) +#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L]) +#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL]) +#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH]) +#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H]) +#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL]) +#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH]) +#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32) +#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L]) +#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL]) +#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH]) +#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H]) +#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL]) +#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH]) +#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32) +#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L]) +#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL]) +#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH]) +#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H]) +#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL]) +#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH]) +#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32) +#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L]) +#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL]) +#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH]) +#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H]) +#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL]) +#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH]) +#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32) +#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L]) +#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL]) +#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH]) +#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H]) +#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL]) +#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH]) +#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32) +#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L]) +#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL]) +#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH]) +#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H]) +#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL]) +#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH]) +#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32) +#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L]) +#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL]) +#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH]) +#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H]) +#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL]) +#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH]) +#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32) +#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L]) +#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL]) +#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH]) +#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H]) +#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL]) +#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH]) +#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32) +#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L]) +#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL]) +#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH]) +#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H]) +#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL]) +#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH]) +#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32) +#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L]) +#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL]) +#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH]) +#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H]) +#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL]) +#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH]) +#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32) +#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L]) +#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL]) +#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH]) +#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H]) +#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL]) +#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH]) +#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32) +#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L]) +#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL]) +#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH]) +#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H]) +#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL]) +#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH]) +#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32) +#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L]) +#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL]) +#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH]) +#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H]) +#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL]) +#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH]) +#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32) +#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L]) +#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL]) +#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH]) +#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H]) +#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL]) +#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH]) +#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32) +#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L]) +#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL]) +#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH]) +#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H]) +#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL]) +#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH]) +#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32) +#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L]) +#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL]) +#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH]) +#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H]) +#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL]) +#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH]) +#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32) +#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L]) +#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL]) +#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH]) +#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H]) +#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL]) +#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH]) +#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32) +#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L]) +#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL]) +#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH]) +#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H]) +#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL]) +#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH]) +#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32) +#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L]) +#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL]) +#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH]) +#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H]) +#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL]) +#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH]) +#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32) +#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L]) +#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL]) +#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH]) +#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H]) +#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL]) +#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH]) +#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32) +#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L]) +#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL]) +#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH]) +#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H]) +#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL]) +#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH]) +#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32) +#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L]) +#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL]) +#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH]) +#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H]) +#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL]) +#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH]) +#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32) +#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L]) +#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL]) +#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH]) +#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H]) +#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL]) +#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH]) +#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32) +#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L]) +#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL]) +#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH]) +#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H]) +#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL]) +#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH]) +#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32) +#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L]) +#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL]) +#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH]) +#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H]) +#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL]) +#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH]) +#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32) +#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L]) +#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL]) +#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH]) +#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H]) +#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL]) +#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH]) +#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32) +#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L]) +#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL]) +#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH]) +#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H]) +#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL]) +#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH]) +#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32) +#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L]) +#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL]) +#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH]) +#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H]) +#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL]) +#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH]) +#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32) +#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L]) +#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL]) +#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH]) +#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H]) +#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL]) +#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH]) +#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32) +#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L]) +#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL]) +#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH]) +#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H]) +#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL]) +#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH]) +#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32) +#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L]) +#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL]) +#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH]) +#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H]) +#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL]) +#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH]) +#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32) +#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L]) +#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL]) +#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH]) +#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H]) +#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL]) +#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH]) +#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32) +#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L]) +#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL]) +#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH]) +#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H]) +#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL]) +#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH]) +#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32) +#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L]) +#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL]) +#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH]) +#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H]) +#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL]) +#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH]) +#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32) +#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L]) +#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL]) +#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH]) +#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H]) +#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL]) +#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH]) +#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32) +#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L]) +#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL]) +#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH]) +#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H]) +#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL]) +#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH]) +#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32) +#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L]) +#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL]) +#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH]) +#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H]) +#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL]) +#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH]) +#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32) +#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L]) +#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL]) +#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH]) +#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H]) +#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL]) +#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH]) +#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32) +#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L]) +#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL]) +#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH]) +#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H]) +#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL]) +#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH]) +#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32) +#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L]) +#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL]) +#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH]) +#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H]) +#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL]) +#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH]) +#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32) +#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L]) +#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL]) +#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH]) +#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H]) +#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL]) +#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH]) +#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32) +#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L]) +#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL]) +#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH]) +#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H]) +#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL]) +#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH]) +#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32) +#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L]) +#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL]) +#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH]) +#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H]) +#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL]) +#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH]) +#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32) +#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L]) +#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL]) +#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH]) +#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H]) +#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL]) +#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH]) +#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32) +#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L]) +#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL]) +#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH]) +#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H]) +#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL]) +#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH]) +#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32) +#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L]) +#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL]) +#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH]) +#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H]) +#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL]) +#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH]) +#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32) +#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L]) +#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL]) +#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH]) +#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H]) +#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL]) +#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH]) +#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32) +#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L]) +#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL]) +#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH]) +#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H]) +#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL]) +#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH]) +#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32) +#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L]) +#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL]) +#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH]) +#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H]) +#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL]) +#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH]) +#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32) +#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L]) +#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL]) +#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH]) +#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H]) +#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL]) +#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH]) +#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32) +#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L]) +#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL]) +#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH]) +#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H]) +#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL]) +#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH]) +#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32) +#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L]) +#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL]) +#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH]) +#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H]) +#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL]) +#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH]) +#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32) +#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L]) +#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL]) +#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH]) +#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H]) +#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL]) +#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH]) +#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32) +#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L]) +#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL]) +#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH]) +#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H]) +#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL]) +#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH]) +#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32) +#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L]) +#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL]) +#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH]) +#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H]) +#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL]) +#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH]) +#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32) +#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L]) +#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL]) +#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH]) +#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H]) +#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL]) +#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH]) +#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32) +#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L]) +#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL]) +#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH]) +#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H]) +#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL]) +#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH]) +#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32) +#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L]) +#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL]) +#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH]) +#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H]) +#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL]) +#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH]) +#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32) +#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L]) +#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL]) +#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH]) +#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H]) +#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL]) +#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH]) +#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32) +#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L]) +#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL]) +#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH]) +#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H]) +#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL]) +#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH]) +#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32) +#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L]) +#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL]) +#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH]) +#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H]) +#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL]) +#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH]) +#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32) +#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L]) +#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL]) +#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH]) +#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H]) +#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL]) +#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH]) +#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32) +#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L]) +#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL]) +#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH]) +#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H]) +#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL]) +#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH]) +#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32) +#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L]) +#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL]) +#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH]) +#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H]) +#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL]) +#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH]) +#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32) +#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L]) +#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL]) +#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH]) +#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H]) +#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL]) +#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH]) +#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32) +#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L]) +#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL]) +#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH]) +#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H]) +#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL]) +#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH]) +#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32) +#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L]) +#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL]) +#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH]) +#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H]) +#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL]) +#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH]) +#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32) +#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L]) +#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL]) +#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH]) +#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H]) +#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL]) +#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH]) +#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32) +#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L]) +#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL]) +#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH]) +#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H]) +#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL]) +#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH]) +#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32) +#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L]) +#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL]) +#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH]) +#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H]) +#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL]) +#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH]) +#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32) +#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L]) +#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL]) +#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH]) +#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H]) +#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL]) +#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH]) +#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32) +#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L]) +#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL]) +#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH]) +#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H]) +#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL]) +#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH]) +#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32) +#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L]) +#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL]) +#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH]) +#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H]) +#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL]) +#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH]) +#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32) +#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L]) +#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL]) +#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH]) +#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H]) +#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL]) +#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH]) +#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32) +#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L]) +#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL]) +#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH]) +#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H]) +#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL]) +#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH]) +#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32) +#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L]) +#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL]) +#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH]) +#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H]) +#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL]) +#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH]) +#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32) +#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L]) +#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL]) +#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH]) +#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H]) +#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL]) +#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH]) +#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32) +#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L]) +#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL]) +#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH]) +#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H]) +#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL]) +#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH]) +#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32) +#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L]) +#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL]) +#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH]) +#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H]) +#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL]) +#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH]) +#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32) +#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L]) +#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL]) +#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH]) +#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H]) +#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL]) +#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH]) +#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32) +#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L]) +#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL]) +#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH]) +#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H]) +#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL]) +#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH]) +#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32) +#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L]) +#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL]) +#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH]) +#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H]) +#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL]) +#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH]) +#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32) +#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L]) +#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL]) +#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH]) +#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H]) +#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL]) +#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH]) +#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32) +#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L]) +#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL]) +#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH]) +#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H]) +#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL]) +#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH]) +#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32) +#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L]) +#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL]) +#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH]) +#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H]) +#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL]) +#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH]) +#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32) +#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L]) +#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL]) +#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH]) +#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H]) +#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL]) +#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH]) +#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32) +#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L]) +#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL]) +#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH]) +#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H]) +#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL]) +#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH]) +#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32) +#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L]) +#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL]) +#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH]) +#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H]) +#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL]) +#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH]) +#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32) +#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L]) +#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL]) +#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH]) +#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H]) +#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL]) +#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH]) +#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32) +#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L]) +#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL]) +#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH]) +#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H]) +#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL]) +#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH]) +#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32) +#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L]) +#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL]) +#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH]) +#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H]) +#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL]) +#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH]) +#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32) +#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L]) +#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL]) +#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH]) +#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H]) +#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL]) +#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH]) +#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32) +#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L]) +#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL]) +#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH]) +#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H]) +#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL]) +#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH]) +#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32) +#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L]) +#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL]) +#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH]) +#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H]) +#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL]) +#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH]) +#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32) +#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L]) +#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL]) +#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH]) +#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H]) +#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL]) +#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH]) +#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32) +#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L]) +#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL]) +#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH]) +#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H]) +#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL]) +#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH]) +#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32) +#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L]) +#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL]) +#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH]) +#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H]) +#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL]) +#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH]) +#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32) +#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L]) +#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL]) +#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH]) +#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H]) +#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL]) +#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH]) +#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32) +#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L]) +#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL]) +#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH]) +#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H]) +#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL]) +#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH]) +#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32) +#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L]) +#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL]) +#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH]) +#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H]) +#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL]) +#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH]) +#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32) +#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L]) +#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL]) +#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH]) +#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H]) +#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL]) +#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH]) +#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32) +#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L]) +#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL]) +#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH]) +#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H]) +#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL]) +#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH]) +#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32) +#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L]) +#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL]) +#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH]) +#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H]) +#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL]) +#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH]) +#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32) +#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L]) +#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL]) +#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH]) +#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H]) +#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL]) +#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH]) +#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32) +#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L]) +#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL]) +#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH]) +#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H]) +#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL]) +#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH]) +#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32) +#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L]) +#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL]) +#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH]) +#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H]) +#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL]) +#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH]) +#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32) +#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L]) +#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL]) +#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH]) +#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H]) +#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL]) +#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH]) +#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32) +#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L]) +#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL]) +#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH]) +#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H]) +#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL]) +#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH]) +#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32) +#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L]) +#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL]) +#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH]) +#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H]) +#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL]) +#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH]) +#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32) +#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L]) +#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL]) +#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH]) +#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H]) +#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL]) +#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH]) +#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32) +#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L]) +#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL]) +#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH]) +#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H]) +#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL]) +#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH]) +#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32) +#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L]) +#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL]) +#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH]) +#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H]) +#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL]) +#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH]) +#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32) +#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L]) +#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL]) +#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH]) +#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H]) +#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL]) +#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH]) +#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32) +#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L]) +#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL]) +#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH]) +#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H]) +#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL]) +#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH]) +#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32) +#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L]) +#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL]) +#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH]) +#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H]) +#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL]) +#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH]) +#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32) +#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L]) +#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL]) +#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH]) +#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H]) +#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL]) +#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH]) +#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32) +#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L]) +#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL]) +#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH]) +#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H]) +#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL]) +#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH]) +#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32) +#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L]) +#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL]) +#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH]) +#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H]) +#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL]) +#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH]) +#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32) +#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L]) +#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL]) +#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH]) +#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H]) +#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL]) +#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH]) +#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32) +#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L]) +#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL]) +#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH]) +#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H]) +#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL]) +#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH]) +#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32) +#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L]) +#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL]) +#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH]) +#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H]) +#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL]) +#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH]) +#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32) +#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L]) +#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL]) +#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH]) +#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H]) +#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL]) +#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH]) +#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32) +#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L]) +#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL]) +#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH]) +#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H]) +#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL]) +#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH]) +#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32) +#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L]) +#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL]) +#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH]) +#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H]) +#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL]) +#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH]) +#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32) +#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L]) +#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL]) +#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH]) +#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H]) +#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL]) +#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH]) +#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32) +#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L]) +#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL]) +#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH]) +#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H]) +#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL]) +#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH]) +#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32) +#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L]) +#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL]) +#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH]) +#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H]) +#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL]) +#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH]) +#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32) +#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L]) +#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL]) +#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH]) +#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H]) +#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL]) +#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH]) +#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32) +#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L]) +#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL]) +#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH]) +#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H]) +#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL]) +#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH]) +#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32) +#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L]) +#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL]) +#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH]) +#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H]) +#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL]) +#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH]) +#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32) +#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L]) +#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL]) +#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH]) +#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H]) +#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL]) +#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH]) +#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32) +#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L]) +#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL]) +#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH]) +#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H]) +#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL]) +#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH]) +#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32) +#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L]) +#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL]) +#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH]) +#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H]) +#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL]) +#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH]) +#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32) +#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L]) +#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL]) +#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH]) +#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H]) +#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL]) +#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH]) +#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32) +#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L]) +#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL]) +#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH]) +#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H]) +#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL]) +#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH]) +#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32) +#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L]) +#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL]) +#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH]) +#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H]) +#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL]) +#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH]) +#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32) +#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L]) +#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL]) +#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH]) +#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H]) +#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL]) +#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH]) +#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32) +#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L]) +#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL]) +#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH]) +#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H]) +#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL]) +#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH]) +#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32) +#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L]) +#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL]) +#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH]) +#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H]) +#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL]) +#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH]) +#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32) +#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L]) +#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL]) +#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH]) +#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H]) +#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL]) +#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH]) +#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32) +#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L]) +#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL]) +#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH]) +#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H]) +#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL]) +#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH]) +#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32) +#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L]) +#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL]) +#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH]) +#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H]) +#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL]) +#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH]) +#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32) +#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L]) +#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL]) +#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH]) +#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H]) +#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL]) +#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH]) +#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32) +#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L]) +#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL]) +#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH]) +#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H]) +#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL]) +#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH]) +#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32) +#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L]) +#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL]) +#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH]) +#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H]) +#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL]) +#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH]) +#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32) +#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L]) +#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL]) +#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH]) +#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H]) +#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL]) +#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH]) +#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32) +#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L]) +#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL]) +#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH]) +#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H]) +#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL]) +#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH]) +#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32) +#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L]) +#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL]) +#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH]) +#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H]) +#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL]) +#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH]) +#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32) +#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L]) +#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL]) +#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH]) +#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H]) +#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL]) +#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH]) +#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32) +#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L]) +#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL]) +#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH]) +#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H]) +#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL]) +#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH]) +#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32) +#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L]) +#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL]) +#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH]) +#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H]) +#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL]) +#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH]) +#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32) +#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L]) +#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL]) +#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH]) +#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H]) +#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL]) +#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH]) +#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32) +#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L]) +#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL]) +#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH]) +#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H]) +#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL]) +#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH]) +#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32) +#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L]) +#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL]) +#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH]) +#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H]) +#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL]) +#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH]) +#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32) +#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L]) +#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL]) +#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH]) +#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H]) +#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL]) +#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH]) +#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32) +#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L]) +#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL]) +#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH]) +#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H]) +#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL]) +#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH]) +#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32) +#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L]) +#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL]) +#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH]) +#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H]) +#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL]) +#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH]) +#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32) +#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L]) +#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL]) +#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH]) +#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H]) +#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL]) +#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH]) +#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32) +#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L]) +#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL]) +#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH]) +#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H]) +#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL]) +#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH]) +#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32) +#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L]) +#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL]) +#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH]) +#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H]) +#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL]) +#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH]) +#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32) +#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L]) +#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL]) +#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH]) +#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H]) +#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL]) +#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH]) +#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32) +#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L]) +#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL]) +#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH]) +#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H]) +#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL]) +#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH]) +#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32) +#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L]) +#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL]) +#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH]) +#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H]) +#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL]) +#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH]) +#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32) +#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L]) +#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL]) +#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH]) +#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H]) +#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL]) +#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH]) +#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32) +#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L]) +#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL]) +#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH]) +#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H]) +#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL]) +#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH]) +#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32) +#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L]) +#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL]) +#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH]) +#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H]) +#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL]) +#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH]) +#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32) +#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L]) +#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL]) +#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH]) +#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H]) +#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL]) +#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH]) +#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32) +#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L]) +#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL]) +#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH]) +#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H]) +#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL]) +#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH]) +#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32) +#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L]) +#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL]) +#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH]) +#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H]) +#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL]) +#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH]) +#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32) +#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L]) +#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL]) +#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH]) +#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H]) +#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL]) +#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH]) +#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32) +#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L]) +#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL]) +#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH]) +#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H]) +#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL]) +#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH]) +#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32) +#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L]) +#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL]) +#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH]) +#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H]) +#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL]) +#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH]) +#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32) +#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L]) +#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL]) +#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH]) +#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H]) +#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL]) +#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH]) +#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32) +#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L]) +#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL]) +#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH]) +#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H]) +#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL]) +#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH]) +#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32) +#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L]) +#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL]) +#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH]) +#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H]) +#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL]) +#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH]) +#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32) +#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L]) +#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL]) +#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH]) +#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H]) +#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL]) +#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH]) +#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32) +#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L]) +#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL]) +#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH]) +#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H]) +#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL]) +#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH]) +#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32) +#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L]) +#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL]) +#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH]) +#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H]) +#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL]) +#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH]) +#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32) +#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L]) +#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL]) +#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH]) +#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H]) +#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL]) +#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH]) +#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32) +#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L]) +#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL]) +#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH]) +#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H]) +#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL]) +#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH]) +#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32) +#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L]) +#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL]) +#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH]) +#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H]) +#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL]) +#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH]) +#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32) +#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L]) +#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL]) +#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH]) +#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H]) +#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL]) +#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH]) +#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32) +#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L]) +#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL]) +#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH]) +#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H]) +#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL]) +#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH]) +#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32) +#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L]) +#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL]) +#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH]) +#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H]) +#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL]) +#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH]) +#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32) +#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L]) +#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL]) +#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH]) +#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H]) +#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL]) +#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH]) +#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32) +#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L]) +#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL]) +#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH]) +#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H]) +#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL]) +#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH]) +#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32) +#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L]) +#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL]) +#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH]) +#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H]) +#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL]) +#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH]) +#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32) +#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L]) +#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL]) +#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH]) +#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H]) +#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL]) +#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH]) +#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32) +#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L]) +#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL]) +#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH]) +#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H]) +#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL]) +#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH]) +#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32) +#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L]) +#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL]) +#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH]) +#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H]) +#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL]) +#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH]) +#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32) +#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L]) +#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL]) +#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH]) +#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H]) +#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL]) +#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH]) +#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32) +#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L]) +#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL]) +#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH]) +#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H]) +#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL]) +#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH]) +#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32) +#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L]) +#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL]) +#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH]) +#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H]) +#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL]) +#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH]) +#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32) +#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L]) +#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL]) +#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH]) +#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H]) +#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL]) +#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH]) +#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32) +#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L]) +#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL]) +#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH]) +#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H]) +#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL]) +#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH]) +#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32) +#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L]) +#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL]) +#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH]) +#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H]) +#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL]) +#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH]) +#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32) +#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L]) +#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL]) +#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH]) +#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H]) +#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL]) +#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH]) +#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32) +#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L]) +#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL]) +#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH]) +#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H]) +#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL]) +#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH]) +#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32) +#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L]) +#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL]) +#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH]) +#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H]) +#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL]) +#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH]) +#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32) +#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L]) +#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL]) +#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH]) +#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H]) +#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL]) +#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH]) +#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32) +#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L]) +#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL]) +#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH]) +#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H]) +#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL]) +#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH]) +#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32) +#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L]) +#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL]) +#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH]) +#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H]) +#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL]) +#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH]) +#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32) +#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L]) +#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL]) +#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH]) +#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H]) +#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL]) +#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH]) +#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32) +#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L]) +#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL]) +#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH]) +#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H]) +#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL]) +#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH]) +#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32) +#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L]) +#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL]) +#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH]) +#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H]) +#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL]) +#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH]) +#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32) +#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L]) +#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL]) +#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH]) +#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H]) +#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL]) +#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH]) +#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32) +#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L]) +#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL]) +#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH]) +#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H]) +#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL]) +#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH]) +#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32) +#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L]) +#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL]) +#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH]) +#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H]) +#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL]) +#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH]) +#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32) +#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L]) +#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL]) +#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH]) +#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H]) +#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL]) +#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH]) +#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32) +#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L]) +#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL]) +#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH]) +#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H]) +#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL]) +#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH]) +#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32) +#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L]) +#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL]) +#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH]) +#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H]) +#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL]) +#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH]) +#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32) +#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L]) +#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL]) +#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH]) +#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H]) +#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL]) +#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH]) +#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32) +#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L]) +#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL]) +#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH]) +#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H]) +#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL]) +#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH]) +#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32) +#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L]) +#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL]) +#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH]) +#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H]) +#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL]) +#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH]) +#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32) +#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L]) +#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL]) +#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH]) +#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H]) +#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL]) +#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH]) +#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32) +#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L]) +#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL]) +#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH]) +#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H]) +#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL]) +#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH]) +#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32) +#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L]) +#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL]) +#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH]) +#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H]) +#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL]) +#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH]) +#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32) +#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L]) +#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL]) +#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH]) +#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H]) +#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL]) +#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH]) +#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32) +#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L]) +#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL]) +#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH]) +#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H]) +#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL]) +#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH]) +#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32) +#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L]) +#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL]) +#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH]) +#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H]) +#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL]) +#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH]) +#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32) +#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L]) +#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL]) +#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH]) +#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H]) +#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL]) +#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH]) +#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32) +#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L]) +#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL]) +#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH]) +#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H]) +#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL]) +#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH]) +#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32) +#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L]) +#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL]) +#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH]) +#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H]) +#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL]) +#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH]) +#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32) +#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L]) +#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL]) +#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH]) +#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H]) +#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL]) +#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH]) +#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32) +#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L]) +#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL]) +#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH]) +#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H]) +#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL]) +#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH]) +#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32) +#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L]) +#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL]) +#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH]) +#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H]) +#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL]) +#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH]) +#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32) +#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L]) +#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL]) +#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH]) +#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H]) +#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL]) +#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH]) +#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32) +#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L]) +#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL]) +#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH]) +#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H]) +#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL]) +#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH]) +#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32) +#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L]) +#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL]) +#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH]) +#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H]) +#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL]) +#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH]) +#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32) +#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L]) +#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL]) +#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH]) +#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H]) +#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL]) +#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH]) +#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32) +#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L]) +#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL]) +#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH]) +#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H]) +#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL]) +#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH]) +#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32) +#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L]) +#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL]) +#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH]) +#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H]) +#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL]) +#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH]) +#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32) +#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L]) +#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL]) +#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH]) +#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H]) +#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL]) +#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH]) +#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32) +#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L]) +#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL]) +#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH]) +#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H]) +#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL]) +#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH]) +#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32) +#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L]) +#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL]) +#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH]) +#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H]) +#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL]) +#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH]) +#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32) +#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L]) +#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL]) +#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH]) +#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H]) +#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL]) +#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH]) +#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32) +#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L]) +#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL]) +#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH]) +#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H]) +#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL]) +#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH]) +#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32) +#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L]) +#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL]) +#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH]) +#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H]) +#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL]) +#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH]) +#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32) +#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L]) +#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL]) +#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH]) +#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H]) +#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL]) +#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH]) +#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32) +#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L]) +#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL]) +#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH]) +#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H]) +#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL]) +#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH]) +#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32) +#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L]) +#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL]) +#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH]) +#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H]) +#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL]) +#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH]) +#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32) +#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L]) +#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL]) +#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH]) +#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H]) +#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL]) +#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH]) +#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32) +#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L]) +#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL]) +#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH]) +#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H]) +#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL]) +#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH]) +#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32) +#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L]) +#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL]) +#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH]) +#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H]) +#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL]) +#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH]) +#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32) +#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L]) +#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL]) +#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH]) +#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H]) +#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL]) +#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH]) +#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32) +#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L]) +#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL]) +#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH]) +#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H]) +#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL]) +#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH]) +#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32) +#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L]) +#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL]) +#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH]) +#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H]) +#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL]) +#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH]) +#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32) +#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L]) +#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL]) +#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH]) +#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H]) +#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL]) +#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH]) +#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32) +#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L]) +#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL]) +#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH]) +#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H]) +#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL]) +#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH]) +#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32) +#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L]) +#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL]) +#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH]) +#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H]) +#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL]) +#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH]) +#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32) +#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L]) +#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL]) +#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH]) +#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H]) +#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL]) +#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH]) +#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32) +#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L]) +#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL]) +#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH]) +#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H]) +#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL]) +#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH]) +#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32) +#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L]) +#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL]) +#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH]) +#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H]) +#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL]) +#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH]) +#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32) +#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L]) +#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL]) +#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH]) +#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H]) +#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL]) +#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH]) +#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32) +#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L]) +#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL]) +#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH]) +#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H]) +#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL]) +#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH]) +#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32) +#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L]) +#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL]) +#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH]) +#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H]) +#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL]) +#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH]) +#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32) +#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L]) +#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL]) +#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH]) +#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H]) +#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL]) +#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH]) +#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32) +#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L]) +#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL]) +#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH]) +#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H]) +#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL]) +#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH]) +#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32) +#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L]) +#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL]) +#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH]) +#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H]) +#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL]) +#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH]) +#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32) +#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L]) +#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL]) +#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH]) +#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H]) +#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL]) +#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH]) +#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32) +#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L]) +#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL]) +#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH]) +#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H]) +#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL]) +#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH]) +#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32) +#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L]) +#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL]) +#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH]) +#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H]) +#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL]) +#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH]) +#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32) +#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L]) +#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL]) +#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH]) +#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H]) +#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL]) +#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH]) +#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32) +#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L]) +#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL]) +#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH]) +#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H]) +#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL]) +#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH]) +#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32) +#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L]) +#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL]) +#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH]) +#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H]) +#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL]) +#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH]) +#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32) +#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L]) +#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL]) +#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH]) +#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H]) +#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL]) +#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH]) +#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32) +#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L]) +#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL]) +#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH]) +#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H]) +#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL]) +#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH]) +#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32) +#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L]) +#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL]) +#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH]) +#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H]) +#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL]) +#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH]) +#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32) +#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L]) +#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL]) +#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH]) +#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H]) +#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL]) +#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH]) +#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32) +#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L]) +#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL]) +#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH]) +#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H]) +#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL]) +#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH]) +#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32) +#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L]) +#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL]) +#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH]) +#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H]) +#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL]) +#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH]) +#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32) +#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L]) +#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL]) +#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH]) +#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H]) +#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL]) +#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH]) +#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32) +#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L]) +#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL]) +#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH]) +#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H]) +#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL]) +#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH]) +#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32) +#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L]) +#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL]) +#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH]) +#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H]) +#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL]) +#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH]) +#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32) +#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L]) +#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL]) +#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH]) +#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H]) +#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL]) +#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH]) +#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32) +#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L]) +#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL]) +#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH]) +#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H]) +#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL]) +#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH]) +#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32) +#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L]) +#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL]) +#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH]) +#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H]) +#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL]) +#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH]) +#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32) +#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L]) +#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL]) +#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH]) +#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H]) +#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL]) +#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH]) +#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32) +#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L]) +#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL]) +#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH]) +#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H]) +#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL]) +#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH]) +#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32) +#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L]) +#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL]) +#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH]) +#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H]) +#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL]) +#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH]) +#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32) +#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L]) +#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL]) +#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH]) +#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H]) +#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL]) +#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH]) +#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32) +#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L]) +#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL]) +#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH]) +#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H]) +#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL]) +#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH]) +#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32) +#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L]) +#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL]) +#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH]) +#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H]) +#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL]) +#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH]) +#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32) +#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L]) +#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL]) +#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH]) +#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H]) +#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL]) +#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH]) +#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32) +#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L]) +#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL]) +#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH]) +#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H]) +#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL]) +#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH]) +#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32) +#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L]) +#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL]) +#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH]) +#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H]) +#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL]) +#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH]) +#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32) +#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L]) +#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL]) +#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH]) +#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H]) +#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL]) +#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH]) +#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32) +#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L]) +#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL]) +#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH]) +#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H]) +#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL]) +#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH]) +#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32) +#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L]) +#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL]) +#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH]) +#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H]) +#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL]) +#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH]) +#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32) +#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L]) +#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL]) +#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH]) +#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H]) +#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL]) +#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH]) +#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32) +#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L]) +#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL]) +#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH]) +#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H]) +#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL]) +#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH]) +#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32) +#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L]) +#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL]) +#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH]) +#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H]) +#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL]) +#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH]) +#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32) +#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L]) +#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL]) +#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH]) +#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H]) +#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL]) +#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH]) +#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32) +#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L]) +#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL]) +#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH]) +#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H]) +#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL]) +#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH]) +#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32) +#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L]) +#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL]) +#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH]) +#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H]) +#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL]) +#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH]) +#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32) +#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L]) +#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL]) +#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH]) +#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H]) +#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL]) +#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH]) +#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32) +#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L]) +#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL]) +#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH]) +#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H]) +#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL]) +#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH]) +#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32) +#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L]) +#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL]) +#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH]) +#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H]) +#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL]) +#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH]) +#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32) +#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L]) +#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL]) +#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH]) +#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H]) +#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL]) +#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH]) +#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32) +#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L]) +#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL]) +#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH]) +#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H]) +#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL]) +#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH]) +#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32) +#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L]) +#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL]) +#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH]) +#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H]) +#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL]) +#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH]) +#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32) +#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L]) +#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL]) +#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH]) +#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H]) +#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL]) +#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH]) +#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32) +#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L]) +#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL]) +#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH]) +#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H]) +#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL]) +#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH]) +#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32) +#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L]) +#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL]) +#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH]) +#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H]) +#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL]) +#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH]) +#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32) +#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L]) +#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL]) +#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH]) +#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H]) +#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL]) +#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH]) +#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32) +#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L]) +#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL]) +#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH]) +#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H]) +#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL]) +#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH]) +#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32) +#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L]) +#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL]) +#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH]) +#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H]) +#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL]) +#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH]) +#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32) +#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L]) +#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL]) +#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH]) +#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H]) +#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL]) +#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH]) +#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32) +#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L]) +#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL]) +#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH]) +#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H]) +#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL]) +#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH]) +#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32) +#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L]) +#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL]) +#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH]) +#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H]) +#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL]) +#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH]) +#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32) +#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L]) +#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL]) +#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH]) +#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H]) +#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL]) +#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH]) +#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32) +#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L]) +#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL]) +#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH]) +#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H]) +#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL]) +#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH]) +#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32) +#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L]) +#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL]) +#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH]) +#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H]) +#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL]) +#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH]) +#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32) +#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L]) +#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL]) +#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH]) +#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H]) +#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL]) +#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH]) +#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32) +#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L]) +#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL]) +#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH]) +#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H]) +#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL]) +#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH]) +#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32) +#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L]) +#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL]) +#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH]) +#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H]) +#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL]) +#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH]) +#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32) +#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L]) +#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL]) +#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH]) +#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H]) +#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL]) +#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH]) +#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32) +#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L]) +#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL]) +#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH]) +#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H]) +#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL]) +#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH]) +#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32) +#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L]) +#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL]) +#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH]) +#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H]) +#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL]) +#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH]) +#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32) +#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L]) +#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL]) +#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH]) +#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H]) +#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL]) +#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH]) +#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32) +#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L]) +#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL]) +#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH]) +#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H]) +#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL]) +#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH]) +#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32) +#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L]) +#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL]) +#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH]) +#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H]) +#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL]) +#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH]) +#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32) +#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L]) +#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL]) +#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH]) +#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H]) +#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL]) +#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH]) +#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32) +#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L]) +#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL]) +#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH]) +#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H]) +#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL]) +#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH]) +#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32) +#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L]) +#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL]) +#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH]) +#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H]) +#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL]) +#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH]) +#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32) +#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L]) +#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL]) +#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH]) +#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H]) +#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL]) +#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH]) +#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32) +#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L]) +#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL]) +#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH]) +#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H]) +#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL]) +#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH]) +#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32) +#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L]) +#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL]) +#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH]) +#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H]) +#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL]) +#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH]) +#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32) +#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L]) +#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL]) +#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH]) +#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H]) +#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL]) +#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH]) +#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32) +#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L]) +#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL]) +#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH]) +#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H]) +#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL]) +#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH]) +#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32) +#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L]) +#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL]) +#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH]) +#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H]) +#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL]) +#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH]) +#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32) +#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L]) +#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL]) +#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH]) +#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H]) +#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL]) +#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH]) +#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32) +#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L]) +#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL]) +#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH]) +#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H]) +#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL]) +#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH]) +#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32) +#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L]) +#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL]) +#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH]) +#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H]) +#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL]) +#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH]) +#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32) +#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L]) +#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL]) +#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH]) +#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H]) +#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL]) +#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH]) +#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32) +#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L]) +#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL]) +#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH]) +#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H]) +#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL]) +#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH]) +#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32) +#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L]) +#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL]) +#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH]) +#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H]) +#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL]) +#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH]) +#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32) +#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L]) +#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL]) +#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH]) +#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H]) +#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL]) +#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH]) +#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32) +#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L]) +#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL]) +#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH]) +#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H]) +#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL]) +#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH]) +#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32) +#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L]) +#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL]) +#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH]) +#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H]) +#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL]) +#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH]) +#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32) +#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L]) +#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL]) +#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH]) +#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H]) +#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL]) +#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH]) +#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32) +#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L]) +#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL]) +#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH]) +#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H]) +#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL]) +#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH]) +#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32) +#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L]) +#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL]) +#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH]) +#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H]) +#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL]) +#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH]) +#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32) +#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L]) +#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL]) +#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH]) +#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H]) +#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL]) +#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH]) +#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32) +#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L]) +#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL]) +#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH]) +#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H]) +#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL]) +#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH]) +#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32) +#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L]) +#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL]) +#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH]) +#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H]) +#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL]) +#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32) +#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L]) +#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL]) +#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH]) +#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H]) +#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL]) +#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH]) +#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32) +#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L]) +#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL]) +#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH]) +#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H]) +#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL]) +#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH]) +#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32) +#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L]) +#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL]) +#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH]) +#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H]) +#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL]) +#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH]) +#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32) +#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L]) +#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL]) +#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH]) +#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H]) +#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL]) +#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH]) +#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32) +#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L]) +#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL]) +#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH]) +#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H]) +#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL]) +#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH]) +#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32) +#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L]) +#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL]) +#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH]) +#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H]) +#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL]) +#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH]) +#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32) +#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L]) +#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL]) +#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH]) +#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H]) +#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL]) +#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH]) +#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32) +#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L]) +#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL]) +#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH]) +#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H]) +#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL]) +#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH]) +#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32) +#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L]) +#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL]) +#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH]) +#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H]) +#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL]) +#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH]) +#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32) +#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L]) +#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL]) +#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH]) +#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H]) +#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL]) +#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH]) +#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32) +#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L]) +#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL]) +#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH]) +#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H]) +#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL]) +#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH]) +#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32) +#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L]) +#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL]) +#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH]) +#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H]) +#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL]) +#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH]) +#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32) +#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L]) +#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL]) +#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH]) +#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H]) +#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL]) +#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH]) +#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32) +#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L]) +#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL]) +#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH]) +#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H]) +#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL]) +#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH]) +#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32) +#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L]) +#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL]) +#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH]) +#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H]) +#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL]) +#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH]) +#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32) +#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L]) +#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL]) +#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH]) +#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H]) +#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL]) +#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH]) +#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32) +#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L]) +#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL]) +#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH]) +#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H]) +#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL]) +#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH]) +#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32) +#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L]) +#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL]) +#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH]) +#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H]) +#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL]) +#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH]) +#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32) +#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L]) +#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL]) +#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH]) +#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H]) +#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL]) +#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH]) +#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32) +#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L]) +#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL]) +#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH]) +#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H]) +#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL]) +#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH]) +#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32) +#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L]) +#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL]) +#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH]) +#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H]) +#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL]) +#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH]) +#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32) +#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L]) +#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL]) +#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH]) +#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H]) +#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL]) +#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH]) +#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32) +#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L]) +#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL]) +#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH]) +#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H]) +#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL]) +#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH]) +#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32) +#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L]) +#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL]) +#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH]) +#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H]) +#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL]) +#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH]) +#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32) +#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L]) +#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL]) +#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH]) +#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H]) +#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL]) +#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH]) +#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32) +#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L]) +#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL]) +#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH]) +#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H]) +#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL]) +#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH]) +#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32) +#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L]) +#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL]) +#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH]) +#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H]) +#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL]) +#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH]) +#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32) +#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L]) +#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL]) +#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH]) +#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H]) +#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL]) +#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH]) +#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32) +#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L]) +#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL]) +#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH]) +#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H]) +#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL]) +#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH]) +#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32) +#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L]) +#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL]) +#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH]) +#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H]) +#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL]) +#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH]) +#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32) +#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L]) +#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL]) +#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH]) +#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H]) +#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL]) +#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH]) +#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32) +#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L]) +#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL]) +#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH]) +#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H]) +#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL]) +#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH]) +#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32) +#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L]) +#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL]) +#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH]) +#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H]) +#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL]) +#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH]) +#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32) +#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L]) +#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL]) +#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH]) +#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H]) +#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL]) +#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH]) +#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32) +#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L]) +#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL]) +#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH]) +#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H]) +#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL]) +#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH]) +#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32) +#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L]) +#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL]) +#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH]) +#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H]) +#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL]) +#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH]) +#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32) +#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L]) +#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL]) +#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH]) +#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H]) +#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL]) +#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH]) +#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32) +#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L]) +#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL]) +#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH]) +#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H]) +#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL]) +#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH]) +#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32) +#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L]) +#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL]) +#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH]) +#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H]) +#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL]) +#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH]) +#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32) +#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L]) +#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL]) +#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH]) +#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H]) +#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL]) +#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH]) +#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32) +#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L]) +#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL]) +#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH]) +#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H]) +#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL]) +#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH]) +#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32) +#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L]) +#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL]) +#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH]) +#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H]) +#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL]) +#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH]) +#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32) +#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L]) +#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL]) +#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH]) +#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H]) +#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL]) +#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH]) +#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32) +#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L]) +#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL]) +#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH]) +#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H]) +#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL]) +#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH]) +#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32) +#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L]) +#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL]) +#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH]) +#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H]) +#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL]) +#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH]) +#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32) +#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L]) +#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL]) +#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH]) +#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H]) +#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL]) +#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH]) +#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32) +#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L]) +#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL]) +#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH]) +#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H]) +#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL]) +#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH]) +#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32) +#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L]) +#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL]) +#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH]) +#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H]) +#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL]) +#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH]) +#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32) +#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L]) +#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL]) +#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH]) +#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H]) +#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL]) +#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH]) +#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32) +#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L]) +#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL]) +#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH]) +#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H]) +#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL]) +#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH]) +#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32) +#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L]) +#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL]) +#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH]) +#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H]) +#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL]) +#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH]) +#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32) +#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L]) +#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL]) +#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH]) +#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H]) +#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL]) +#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH]) +#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32) +#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L]) +#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL]) +#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH]) +#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H]) +#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL]) +#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH]) +#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32) +#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L]) +#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL]) +#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH]) +#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H]) +#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL]) +#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH]) +#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32) +#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L]) +#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL]) +#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH]) +#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H]) +#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL]) +#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH]) +#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32) +#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L]) +#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL]) +#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH]) +#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H]) +#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL]) +#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH]) +#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32) +#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L]) +#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL]) +#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH]) +#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H]) +#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL]) +#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH]) +#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32) +#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L]) +#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL]) +#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH]) +#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H]) +#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL]) +#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH]) +#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32) +#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L]) +#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL]) +#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH]) +#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H]) +#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL]) +#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH]) +#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32) +#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L]) +#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL]) +#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH]) +#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H]) +#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL]) +#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32) +#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L]) +#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL]) +#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH]) +#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H]) +#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL]) +#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH]) +#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32) +#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L]) +#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL]) +#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH]) +#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H]) +#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL]) +#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH]) +#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32) +#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L]) +#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL]) +#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH]) +#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H]) +#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL]) +#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH]) +#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32) +#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L]) +#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL]) +#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH]) +#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H]) +#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL]) +#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH]) +#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32) +#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L]) +#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL]) +#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH]) +#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H]) +#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL]) +#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH]) +#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32) +#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L]) +#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL]) +#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH]) +#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H]) +#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL]) +#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH]) +#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32) +#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L]) +#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL]) +#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH]) +#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H]) +#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL]) +#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH]) +#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32) +#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L]) +#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL]) +#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH]) +#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H]) +#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL]) +#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH]) +#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32) +#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L]) +#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL]) +#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH]) +#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H]) +#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL]) +#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH]) +#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32) +#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L]) +#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL]) +#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH]) +#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H]) +#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL]) +#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH]) +#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32) +#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L]) +#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL]) +#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH]) +#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H]) +#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL]) +#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH]) +#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32) +#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L]) +#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL]) +#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH]) +#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H]) +#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL]) +#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH]) +#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32) +#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L]) +#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL]) +#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH]) +#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H]) +#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL]) +#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH]) +#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32) +#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L]) +#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL]) +#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH]) +#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H]) +#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL]) +#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH]) +#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32) +#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L]) +#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL]) +#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH]) +#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H]) +#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL]) +#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH]) +#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32) +#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L]) +#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL]) +#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH]) +#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H]) +#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL]) +#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH]) +#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32) +#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L]) +#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL]) +#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH]) +#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H]) +#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL]) +#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH]) +#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32) +#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L]) +#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL]) +#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH]) +#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H]) +#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL]) +#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH]) +#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32) +#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L]) +#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL]) +#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH]) +#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H]) +#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL]) +#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH]) +#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32) +#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L]) +#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL]) +#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH]) +#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H]) +#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL]) +#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH]) +#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32) +#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L]) +#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL]) +#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH]) +#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H]) +#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL]) +#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH]) +#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32) +#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L]) +#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL]) +#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH]) +#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H]) +#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL]) +#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH]) +#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32) +#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L]) +#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL]) +#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH]) +#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H]) +#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL]) +#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH]) +#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32) +#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L]) +#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL]) +#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH]) +#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H]) +#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL]) +#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH]) +#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32) +#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L]) +#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL]) +#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH]) +#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H]) +#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL]) +#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH]) +#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32) +#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L]) +#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL]) +#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH]) +#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H]) +#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL]) +#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH]) +#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32) +#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L]) +#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL]) +#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH]) +#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H]) +#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL]) +#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH]) +#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32) +#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L]) +#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL]) +#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH]) +#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H]) +#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL]) +#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH]) +#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32) +#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L]) +#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL]) +#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH]) +#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H]) +#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL]) +#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH]) +#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32) +#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L]) +#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL]) +#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH]) +#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H]) +#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL]) +#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH]) +#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32) +#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L]) +#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL]) +#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH]) +#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H]) +#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL]) +#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH]) +#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32) +#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L]) +#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL]) +#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH]) +#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H]) +#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL]) +#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH]) +#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32) +#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L]) +#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL]) +#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH]) +#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H]) +#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL]) +#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH]) +#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32) +#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L]) +#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL]) +#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH]) +#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H]) +#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL]) +#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH]) +#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32) +#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L]) +#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL]) +#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH]) +#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H]) +#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL]) +#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH]) +#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32) +#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L]) +#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL]) +#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH]) +#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H]) +#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL]) +#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH]) +#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32) +#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L]) +#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL]) +#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH]) +#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H]) +#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL]) +#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH]) +#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32) +#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L]) +#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL]) +#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH]) +#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H]) +#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL]) +#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH]) +#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32) +#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L]) +#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL]) +#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH]) +#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H]) +#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL]) +#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH]) +#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32) +#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L]) +#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL]) +#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH]) +#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H]) +#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL]) +#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH]) +#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32) +#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L]) +#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL]) +#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH]) +#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H]) +#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL]) +#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH]) +#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32) +#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L]) +#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL]) +#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH]) +#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H]) +#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL]) +#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH]) +#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32) +#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L]) +#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL]) +#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH]) +#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H]) +#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL]) +#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH]) +#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32) +#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L]) +#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL]) +#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH]) +#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H]) +#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL]) +#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH]) +#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32) +#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L]) +#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL]) +#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH]) +#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H]) +#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL]) +#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH]) +#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32) +#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L]) +#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL]) +#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH]) +#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H]) +#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL]) +#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH]) +#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32) +#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L]) +#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL]) +#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH]) +#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H]) +#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL]) +#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH]) +#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32) +#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L]) +#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL]) +#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH]) +#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H]) +#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL]) +#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH]) +#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32) +#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L]) +#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL]) +#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH]) +#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H]) +#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL]) +#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH]) +#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32) +#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L]) +#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL]) +#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH]) +#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H]) +#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL]) +#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH]) +#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32) +#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L]) +#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL]) +#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH]) +#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H]) +#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL]) +#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH]) +#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32) +#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L]) +#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL]) +#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH]) +#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H]) +#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL]) +#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH]) +#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32) +#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L]) +#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL]) +#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH]) +#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H]) +#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL]) +#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH]) +#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32) +#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L]) +#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL]) +#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH]) +#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H]) +#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL]) +#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH]) +#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32) +#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L]) +#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL]) +#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH]) +#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H]) +#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL]) +#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH]) +#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32) +#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L]) +#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL]) +#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH]) +#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H]) +#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL]) +#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH]) +#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32) +#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L]) +#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL]) +#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH]) +#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H]) +#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL]) +#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH]) +#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32) +#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L]) +#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL]) +#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH]) +#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H]) +#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL]) +#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH]) +#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32) +#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L]) +#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL]) +#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH]) +#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H]) +#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL]) +#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH]) +#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32) +#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L]) +#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL]) +#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH]) +#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H]) +#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL]) +#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH]) +#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32) +#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L]) +#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL]) +#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH]) +#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H]) +#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL]) +#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH]) +#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32) +#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L]) +#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL]) +#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH]) +#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H]) +#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL]) +#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH]) +#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32) +#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L]) +#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL]) +#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH]) +#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H]) +#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL]) +#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH]) +#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32) +#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L]) +#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL]) +#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH]) +#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H]) +#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL]) +#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH]) +#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32) +#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L]) +#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL]) +#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH]) +#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H]) +#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL]) +#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH]) +#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32) +#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L]) +#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL]) +#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH]) +#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H]) +#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL]) +#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH]) +#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32) +#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L]) +#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL]) +#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH]) +#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H]) +#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL]) +#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH]) +#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32) +#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L]) +#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL]) +#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH]) +#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H]) +#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL]) +#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH]) +#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32) +#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L]) +#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL]) +#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH]) +#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H]) +#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL]) +#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH]) +#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32) +#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L]) +#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL]) +#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH]) +#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H]) +#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL]) +#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH]) +#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32) +#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L]) +#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL]) +#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH]) +#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H]) +#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL]) +#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH]) +#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32) +#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L]) +#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL]) +#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH]) +#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H]) +#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL]) +#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH]) +#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32) +#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L]) +#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL]) +#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH]) +#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H]) +#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL]) +#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH]) +#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32) +#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L]) +#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL]) +#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH]) +#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H]) +#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL]) +#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH]) +#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32) +#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L]) +#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL]) +#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH]) +#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H]) +#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL]) +#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH]) +#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32) +#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L]) +#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL]) +#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH]) +#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H]) +#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL]) +#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH]) +#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32) +#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L]) +#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL]) +#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH]) +#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H]) +#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL]) +#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH]) +#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32) +#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L]) +#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL]) +#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH]) +#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H]) +#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL]) +#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH]) +#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32) +#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L]) +#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL]) +#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH]) +#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H]) +#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL]) +#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH]) +#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32) +#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L]) +#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL]) +#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH]) +#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H]) +#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL]) +#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH]) +#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32) +#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L]) +#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL]) +#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH]) +#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H]) +#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL]) +#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH]) +#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32) +#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L]) +#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL]) +#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH]) +#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H]) +#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL]) +#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH]) +#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32) +#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L]) +#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL]) +#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH]) +#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H]) +#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL]) +#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH]) +#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32) +#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L]) +#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL]) +#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH]) +#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H]) +#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL]) +#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH]) +#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32) +#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L]) +#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL]) +#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH]) +#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H]) +#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL]) +#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH]) +#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32) +#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L]) +#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL]) +#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH]) +#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H]) +#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL]) +#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH]) +#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32) +#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L]) +#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL]) +#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH]) +#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H]) +#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL]) +#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH]) +#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32) +#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L]) +#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL]) +#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH]) +#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H]) +#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL]) +#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH]) +#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32) +#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L]) +#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL]) +#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH]) +#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H]) +#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL]) +#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH]) +#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32) +#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L]) +#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL]) +#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH]) +#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H]) +#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL]) +#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH]) +#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32) +#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L]) +#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL]) +#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH]) +#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H]) +#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL]) +#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH]) +#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32) +#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L]) +#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL]) +#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH]) +#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H]) +#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL]) +#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH]) +#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32) +#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L]) +#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL]) +#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH]) +#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H]) +#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL]) +#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH]) +#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32) +#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L]) +#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL]) +#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH]) +#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H]) +#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL]) +#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH]) +#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32) +#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L]) +#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL]) +#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH]) +#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H]) +#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL]) +#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH]) +#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32) +#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L]) +#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL]) +#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH]) +#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H]) +#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL]) +#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH]) +#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32) +#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L]) +#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL]) +#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH]) +#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H]) +#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL]) +#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH]) +#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32) +#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L]) +#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL]) +#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH]) +#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H]) +#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL]) +#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH]) +#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32) +#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L]) +#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL]) +#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH]) +#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H]) +#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL]) +#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH]) +#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32) +#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L]) +#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL]) +#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH]) +#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H]) +#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL]) +#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH]) +#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32) +#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L]) +#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL]) +#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH]) +#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H]) +#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL]) +#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH]) +#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32) +#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L]) +#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL]) +#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH]) +#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H]) +#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL]) +#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH]) +#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32) +#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L]) +#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL]) +#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH]) +#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H]) +#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL]) +#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH]) +#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32) +#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L]) +#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL]) +#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH]) +#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H]) +#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL]) +#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH]) +#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32) +#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L]) +#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL]) +#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH]) +#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H]) +#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL]) +#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH]) +#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32) +#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L]) +#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL]) +#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH]) +#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H]) +#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL]) +#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH]) +#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32) +#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L]) +#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL]) +#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH]) +#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H]) +#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL]) +#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH]) +#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32) +#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L]) +#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL]) +#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH]) +#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H]) +#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL]) +#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH]) +#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32) +#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L]) +#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL]) +#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH]) +#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H]) +#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL]) +#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH]) +#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32) +#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L]) +#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL]) +#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH]) +#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H]) +#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL]) +#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH]) +#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32) +#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L]) +#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL]) +#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH]) +#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H]) +#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL]) +#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH]) +#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32) +#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L]) +#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL]) +#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH]) +#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H]) +#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL]) +#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH]) +#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32) +#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L]) +#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL]) +#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH]) +#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H]) +#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL]) +#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH]) +#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32) +#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L]) +#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL]) +#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH]) +#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H]) +#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL]) +#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH]) +#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32) +#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L]) +#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL]) +#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH]) +#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H]) +#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL]) +#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH]) +#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32) +#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L]) +#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL]) +#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH]) +#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H]) +#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL]) +#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH]) +#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32) +#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L]) +#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL]) +#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH]) +#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H]) +#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL]) +#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH]) +#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32) +#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L]) +#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL]) +#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH]) +#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H]) +#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL]) +#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH]) +#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32) +#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L]) +#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL]) +#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH]) +#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H]) +#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL]) +#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH]) +#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32) +#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L]) +#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL]) +#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH]) +#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H]) +#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL]) +#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH]) +#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32) +#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L]) +#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL]) +#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH]) +#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H]) +#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL]) +#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH]) +#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32) +#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L]) +#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL]) +#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH]) +#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H]) +#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL]) +#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH]) +#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32) +#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L]) +#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL]) +#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH]) +#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H]) +#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL]) +#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH]) +#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32) +#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L]) +#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL]) +#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH]) +#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H]) +#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL]) +#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH]) +#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32) +#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L]) +#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL]) +#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH]) +#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H]) +#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL]) +#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH]) +#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32) +#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L]) +#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL]) +#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH]) +#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H]) +#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL]) +#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH]) +#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32) +#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L]) +#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL]) +#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH]) +#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H]) +#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL]) +#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH]) +#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32) +#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L]) +#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL]) +#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH]) +#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H]) +#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL]) +#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH]) +#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32) +#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L]) +#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL]) +#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH]) +#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H]) +#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL]) +#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH]) +#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32) +#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L]) +#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL]) +#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH]) +#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H]) +#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL]) +#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH]) +#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32) +#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L]) +#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL]) +#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH]) +#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H]) +#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL]) +#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH]) +#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32) +#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L]) +#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL]) +#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH]) +#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H]) +#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL]) +#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH]) +#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32) +#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L]) +#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL]) +#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH]) +#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H]) +#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL]) +#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH]) +#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32) +#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L]) +#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL]) +#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH]) +#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H]) +#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL]) +#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH]) +#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32) +#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L]) +#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL]) +#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH]) +#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H]) +#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL]) +#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH]) +#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32) +#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L]) +#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL]) +#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH]) +#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H]) +#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL]) +#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH]) +#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32) +#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L]) +#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL]) +#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH]) +#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H]) +#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL]) +#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH]) +#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32) +#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L]) +#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL]) +#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH]) +#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H]) +#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL]) +#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH]) +#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32) +#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L]) +#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL]) +#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH]) +#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H]) +#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL]) +#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH]) +#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32) +#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L]) +#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL]) +#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH]) +#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H]) +#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL]) +#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH]) +#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32) +#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L]) +#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL]) +#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH]) +#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H]) +#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL]) +#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH]) +#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32) +#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L]) +#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL]) +#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH]) +#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H]) +#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL]) +#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH]) +#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32) +#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L]) +#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL]) +#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH]) +#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H]) +#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL]) +#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH]) +#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32) +#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L]) +#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL]) +#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH]) +#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H]) +#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL]) +#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH]) +#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32) +#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L]) +#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL]) +#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH]) +#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H]) +#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL]) +#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH]) +#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32) +#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L]) +#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL]) +#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH]) +#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H]) +#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL]) +#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH]) +#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32) +#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L]) +#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL]) +#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH]) +#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H]) +#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL]) +#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH]) +#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32) +#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L]) +#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL]) +#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH]) +#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H]) +#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL]) +#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH]) +#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32) +#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L]) +#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL]) +#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH]) +#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H]) +#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL]) +#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH]) +#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32) +#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L]) +#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL]) +#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH]) +#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H]) +#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL]) +#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH]) +#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32) +#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L]) +#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL]) +#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH]) +#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H]) +#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL]) +#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH]) +#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32) +#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L]) +#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL]) +#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH]) +#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H]) +#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL]) +#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH]) +#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32) +#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L]) +#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL]) +#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH]) +#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H]) +#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL]) +#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH]) +#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32) +#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L]) +#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL]) +#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH]) +#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H]) +#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL]) +#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH]) +#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32) +#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L]) +#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL]) +#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH]) +#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H]) +#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL]) +#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH]) +#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32) +#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L]) +#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL]) +#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH]) +#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H]) +#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL]) +#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH]) +#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32) +#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L]) +#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL]) +#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH]) +#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H]) +#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL]) +#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH]) +#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32) +#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L]) +#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL]) +#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH]) +#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H]) +#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL]) +#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH]) +#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32) +#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L]) +#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL]) +#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH]) +#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H]) +#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL]) +#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH]) +#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32) +#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L]) +#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL]) +#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH]) +#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H]) +#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL]) +#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH]) +#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32) +#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L]) +#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL]) +#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH]) +#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H]) +#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL]) +#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH]) +#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32) +#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L]) +#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL]) +#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH]) +#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H]) +#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL]) +#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH]) +#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32) +#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L]) +#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL]) +#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH]) +#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H]) +#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL]) +#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH]) +#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32) +#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L]) +#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL]) +#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH]) +#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H]) +#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL]) +#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH]) +#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32) +#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L]) +#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL]) +#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH]) +#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H]) +#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL]) +#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH]) +#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32) +#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L]) +#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL]) +#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH]) +#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H]) +#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL]) +#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH]) +#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32) +#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L]) +#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL]) +#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH]) +#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H]) +#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL]) +#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH]) +#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32) +#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L]) +#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL]) +#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH]) +#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H]) +#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL]) +#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH]) +#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32) +#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L]) +#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL]) +#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH]) +#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H]) +#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL]) +#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH]) +#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32) +#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L]) +#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL]) +#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH]) +#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H]) +#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL]) +#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH]) +#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32) +#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L]) +#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL]) +#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH]) +#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H]) +#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL]) +#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH]) +#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32) +#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L]) +#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL]) +#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH]) +#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H]) +#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL]) +#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH]) +#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32) +#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L]) +#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL]) +#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH]) +#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H]) +#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL]) +#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH]) +#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32) +#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L]) +#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL]) +#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH]) +#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H]) +#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL]) +#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH]) +#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32) +#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L]) +#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL]) +#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH]) +#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H]) +#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL]) +#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH]) +#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32) +#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L]) +#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL]) +#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH]) +#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H]) +#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL]) +#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH]) +#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32) +#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L]) +#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL]) +#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH]) +#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H]) +#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL]) +#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH]) +#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32) +#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L]) +#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL]) +#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH]) +#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H]) +#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL]) +#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH]) +#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32) +#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L]) +#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL]) +#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH]) +#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H]) +#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL]) +#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH]) +#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32) +#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L]) +#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL]) +#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH]) +#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H]) +#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL]) +#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH]) +#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32) +#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L]) +#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL]) +#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH]) +#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H]) +#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL]) +#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH]) +#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32) +#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L]) +#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL]) +#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH]) +#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H]) +#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL]) +#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH]) +#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32) +#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L]) +#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL]) +#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH]) +#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H]) +#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL]) +#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH]) +#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32) +#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L]) +#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL]) +#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH]) +#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H]) +#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL]) +#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH]) +#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32) +#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L]) +#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL]) +#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH]) +#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H]) +#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL]) +#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH]) +#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32) +#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L]) +#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL]) +#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH]) +#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H]) +#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL]) +#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH]) +#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32) +#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L]) +#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL]) +#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH]) +#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H]) +#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL]) +#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH]) +#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32) +#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L]) +#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL]) +#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH]) +#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H]) +#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL]) +#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH]) +#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32) +#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L]) +#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL]) +#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH]) +#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H]) +#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL]) +#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH]) +#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32) +#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L]) +#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL]) +#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH]) +#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H]) +#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL]) +#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH]) +#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32) +#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L]) +#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL]) +#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH]) +#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H]) +#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL]) +#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH]) +#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32) +#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L]) +#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL]) +#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH]) +#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H]) +#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL]) +#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH]) +#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32) +#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L]) +#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL]) +#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH]) +#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H]) +#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL]) +#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH]) +#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32) +#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L]) +#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL]) +#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH]) +#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H]) +#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL]) +#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH]) +#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32) +#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L]) +#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL]) +#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH]) +#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H]) +#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL]) +#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH]) +#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32) +#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L]) +#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL]) +#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH]) +#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H]) +#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL]) +#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH]) +#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32) +#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L]) +#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL]) +#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH]) +#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H]) +#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL]) +#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH]) +#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32) +#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L]) +#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL]) +#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH]) +#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H]) +#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL]) +#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH]) +#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32) +#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L]) +#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL]) +#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH]) +#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H]) +#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL]) +#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH]) +#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32) +#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L]) +#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL]) +#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH]) +#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H]) +#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL]) +#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH]) +#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32) +#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L]) +#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL]) +#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH]) +#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H]) +#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL]) +#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH]) +#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32) +#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L]) +#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL]) +#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH]) +#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H]) +#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL]) +#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH]) +#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32) +#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L]) +#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL]) +#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH]) +#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H]) +#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL]) +#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH]) +#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32) +#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L]) +#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL]) +#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH]) +#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H]) +#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL]) +#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH]) +#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32) +#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L]) +#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL]) +#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH]) +#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H]) +#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL]) +#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH]) +#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32) +#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L]) +#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL]) +#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH]) +#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H]) +#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL]) +#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH]) +#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32) +#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L]) +#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL]) +#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH]) +#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H]) +#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL]) +#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH]) +#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32) +#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L]) +#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL]) +#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH]) +#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H]) +#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL]) +#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH]) +#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32) +#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L]) +#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL]) +#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH]) +#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H]) +#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL]) +#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH]) +#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32) +#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L]) +#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL]) +#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH]) +#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H]) +#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL]) +#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH]) +#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32) +#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L]) +#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL]) +#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH]) +#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H]) +#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL]) +#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH]) +#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32) +#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L]) +#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL]) +#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH]) +#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H]) +#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL]) +#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH]) +#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32) +#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L]) +#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL]) +#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH]) +#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H]) +#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL]) +#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH]) +#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32) +#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L]) +#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL]) +#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH]) +#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H]) +#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL]) +#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH]) +#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32) +#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L]) +#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL]) +#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH]) +#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H]) +#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL]) +#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH]) +#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32) +#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L]) +#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL]) +#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH]) +#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H]) +#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL]) +#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH]) +#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32) +#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L]) +#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL]) +#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH]) +#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H]) +#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL]) +#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH]) +#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32) +#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L]) +#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL]) +#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH]) +#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H]) +#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL]) +#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH]) +#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32) +#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L]) +#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL]) +#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH]) +#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H]) +#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL]) +#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH]) +#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32) +#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L]) +#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL]) +#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH]) +#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H]) +#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL]) +#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH]) +#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32) +#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L]) +#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL]) +#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH]) +#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H]) +#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL]) +#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH]) +#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32) +#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L]) +#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL]) +#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH]) +#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H]) +#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL]) +#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH]) +#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32) +#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L]) +#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL]) +#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH]) +#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H]) +#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL]) +#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH]) +#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32) +#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L]) +#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL]) +#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH]) +#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H]) +#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL]) +#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH]) +#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32) +#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L]) +#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL]) +#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH]) +#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H]) +#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL]) +#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH]) +#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32) +#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L]) +#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL]) +#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH]) +#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H]) +#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL]) +#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH]) +#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32) +#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L]) +#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL]) +#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH]) +#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H]) +#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL]) +#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH]) +#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32) +#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L]) +#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL]) +#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH]) +#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H]) +#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL]) +#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH]) +#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32) +#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L]) +#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL]) +#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH]) +#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H]) +#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL]) +#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH]) +#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32) +#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L]) +#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL]) +#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH]) +#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H]) +#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL]) +#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH]) +#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32) +#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L]) +#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL]) +#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH]) +#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H]) +#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL]) +#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH]) +#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32) +#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L]) +#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL]) +#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH]) +#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H]) +#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL]) +#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH]) +#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32) +#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L]) +#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL]) +#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH]) +#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H]) +#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL]) +#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH]) +#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32) +#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L]) +#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL]) +#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH]) +#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H]) +#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL]) +#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH]) +#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32) +#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L]) +#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL]) +#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH]) +#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H]) +#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL]) +#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH]) +#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32) +#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L]) +#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL]) +#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH]) +#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H]) +#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL]) +#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH]) +#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32) +#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L]) +#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL]) +#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH]) +#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H]) +#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL]) +#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH]) +#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32) +#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L]) +#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL]) +#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH]) +#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H]) +#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL]) +#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH]) +#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32) +#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L]) +#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL]) +#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH]) +#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H]) +#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL]) +#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH]) +#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32) +#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L]) +#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL]) +#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH]) +#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H]) +#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL]) +#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH]) +#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32) +#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L]) +#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL]) +#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH]) +#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H]) +#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL]) +#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH]) +#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32) +#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L]) +#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL]) +#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH]) +#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H]) +#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL]) +#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH]) +#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32) +#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L]) +#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL]) +#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH]) +#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H]) +#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL]) +#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH]) +#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32) +#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L]) +#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL]) +#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH]) +#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H]) +#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL]) +#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH]) +#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32) +#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L]) +#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL]) +#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH]) +#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H]) +#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL]) +#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH]) +#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32) +#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L]) +#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL]) +#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH]) +#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H]) +#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL]) +#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH]) +#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32) +#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L]) +#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL]) +#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH]) +#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H]) +#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL]) +#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH]) +#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32) +#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L]) +#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL]) +#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH]) +#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H]) +#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL]) +#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH]) +#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32) +#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L]) +#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL]) +#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH]) +#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H]) +#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL]) +#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH]) +#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32) +#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L]) +#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL]) +#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH]) +#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H]) +#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL]) +#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH]) +#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32) +#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L]) +#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL]) +#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH]) +#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H]) +#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL]) +#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH]) +#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32) +#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L]) +#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL]) +#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH]) +#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H]) +#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL]) +#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH]) +#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32) +#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L]) +#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL]) +#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH]) +#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H]) +#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL]) +#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH]) +#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32) +#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L]) +#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL]) +#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH]) +#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H]) +#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL]) +#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH]) +#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32) +#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L]) +#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL]) +#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH]) +#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H]) +#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL]) +#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH]) +#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32) +#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L]) +#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL]) +#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH]) +#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H]) +#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL]) +#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH]) +#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32) +#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L]) +#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL]) +#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH]) +#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H]) +#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL]) +#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH]) +#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32) +#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L]) +#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL]) +#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH]) +#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H]) +#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL]) +#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH]) +#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32) +#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L]) +#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL]) +#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH]) +#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H]) +#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL]) +#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH]) +#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32) +#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L]) +#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL]) +#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH]) +#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H]) +#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL]) +#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH]) +#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32) +#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L]) +#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL]) +#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH]) +#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H]) +#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL]) +#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH]) +#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32) +#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L]) +#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL]) +#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH]) +#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H]) +#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL]) +#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH]) +#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32) +#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L]) +#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL]) +#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH]) +#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H]) +#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL]) +#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH]) +#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32) +#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L]) +#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL]) +#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH]) +#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H]) +#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL]) +#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH]) +#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32) +#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L]) +#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL]) +#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH]) +#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H]) +#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL]) +#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH]) +#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32) +#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L]) +#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL]) +#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH]) +#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H]) +#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL]) +#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH]) +#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32) +#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L]) +#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL]) +#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH]) +#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H]) +#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL]) +#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH]) +#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32) +#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L]) +#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL]) +#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH]) +#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H]) +#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL]) +#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH]) +#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32) +#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L]) +#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL]) +#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH]) +#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H]) +#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL]) +#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH]) +#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32) +#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L]) +#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL]) +#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH]) +#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H]) +#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL]) +#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH]) +#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32) +#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L]) +#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL]) +#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH]) +#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H]) +#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL]) +#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH]) +#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32) +#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L]) +#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL]) +#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH]) +#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H]) +#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL]) +#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH]) +#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32) +#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L]) +#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL]) +#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH]) +#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H]) +#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL]) +#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH]) +#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32) +#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L]) +#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL]) +#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH]) +#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H]) +#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL]) +#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH]) +#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32) +#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L]) +#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL]) +#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH]) +#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H]) +#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL]) +#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH]) +#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32) +#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L]) +#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL]) +#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH]) +#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H]) +#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL]) +#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH]) +#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32) +#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L]) +#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL]) +#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH]) +#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H]) +#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL]) +#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH]) +#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32) +#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L]) +#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL]) +#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH]) +#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H]) +#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL]) +#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH]) +#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32) +#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L]) +#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL]) +#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH]) +#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H]) +#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL]) +#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH]) +#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32) +#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L]) +#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL]) +#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH]) +#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H]) +#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL]) +#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH]) +#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32) +#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L]) +#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL]) +#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH]) +#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H]) +#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL]) +#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH]) +#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32) +#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L]) +#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL]) +#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH]) +#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H]) +#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL]) +#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH]) +#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32) +#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L]) +#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL]) +#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH]) +#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H]) +#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL]) +#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH]) +#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32) +#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L]) +#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL]) +#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH]) +#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H]) +#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL]) +#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH]) +#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32) +#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L]) +#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL]) +#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH]) +#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H]) +#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL]) +#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH]) +#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32) +#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L]) +#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL]) +#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH]) +#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H]) +#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL]) +#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH]) +#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32) +#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L]) +#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL]) +#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH]) +#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H]) +#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL]) +#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH]) +#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32) +#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L]) +#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL]) +#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH]) +#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H]) +#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL]) +#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH]) +#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32) +#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L]) +#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL]) +#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH]) +#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H]) +#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL]) +#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH]) +#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32) +#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L]) +#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL]) +#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH]) +#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H]) +#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL]) +#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH]) +#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32) +#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L]) +#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL]) +#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH]) +#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H]) +#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL]) +#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH]) +#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32) +#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L]) +#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL]) +#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH]) +#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H]) +#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL]) +#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH]) +#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32) +#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L]) +#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL]) +#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH]) +#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H]) +#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL]) +#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH]) +#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32) +#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L]) +#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL]) +#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH]) +#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H]) +#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL]) +#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH]) +#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32) +#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L]) +#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL]) +#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH]) +#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H]) +#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL]) +#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH]) +#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32) +#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L]) +#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL]) +#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH]) +#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H]) +#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL]) +#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH]) +#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32) +#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L]) +#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL]) +#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH]) +#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H]) +#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL]) +#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH]) +#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32) +#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L]) +#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL]) +#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH]) +#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H]) +#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL]) +#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH]) +#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32) +#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L]) +#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL]) +#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH]) +#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H]) +#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL]) +#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH]) +#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32) +#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L]) +#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL]) +#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH]) +#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H]) +#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL]) +#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH]) +#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32) +#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L]) +#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL]) +#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH]) +#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H]) +#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL]) +#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH]) +#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32) +#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L]) +#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL]) +#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH]) +#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H]) +#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL]) +#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH]) +#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32) +#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L]) +#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL]) +#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH]) +#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H]) +#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL]) +#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH]) +#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32) +#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L]) +#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL]) +#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH]) +#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H]) +#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL]) +#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH]) +#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32) +#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L]) +#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL]) +#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH]) +#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H]) +#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL]) +#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH]) +#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32) +#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L]) +#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL]) +#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH]) +#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H]) +#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL]) +#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH]) +#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32) +#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L]) +#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL]) +#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH]) +#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H]) +#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL]) +#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH]) +#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32) +#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L]) +#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL]) +#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH]) +#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H]) +#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL]) +#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH]) +#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32) +#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L]) +#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL]) +#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH]) +#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H]) +#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL]) +#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH]) +#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32) +#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L]) +#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL]) +#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH]) +#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H]) +#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL]) +#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH]) +#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32) +#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L]) +#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL]) +#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH]) +#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H]) +#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL]) +#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH]) +#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32) +#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L]) +#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL]) +#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH]) +#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H]) +#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL]) +#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH]) +#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32) +#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L]) +#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL]) +#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH]) +#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H]) +#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL]) +#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH]) +#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32) +#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L]) +#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL]) +#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH]) +#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H]) +#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL]) +#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH]) +#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32) +#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L]) +#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL]) +#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH]) +#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H]) +#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL]) +#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH]) +#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32) +#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L]) +#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL]) +#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH]) +#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H]) +#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL]) +#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH]) +#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32) +#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L]) +#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL]) +#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH]) +#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H]) +#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL]) +#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH]) +#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32) +#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L]) +#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL]) +#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH]) +#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H]) +#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL]) +#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH]) +#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32) +#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L]) +#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL]) +#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH]) +#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H]) +#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL]) +#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH]) +#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32) +#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L]) +#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL]) +#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH]) +#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H]) +#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL]) +#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH]) +#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32) +#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L]) +#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL]) +#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH]) +#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H]) +#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL]) +#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH]) +#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32) +#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L]) +#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL]) +#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH]) +#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H]) +#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL]) +#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH]) +#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32) +#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L]) +#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL]) +#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH]) +#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H]) +#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL]) +#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH]) +#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32) +#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L]) +#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL]) +#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH]) +#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H]) +#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL]) +#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH]) +#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32) +#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L]) +#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL]) +#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH]) +#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H]) +#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL]) +#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH]) + +#define RSCAN0_GAFLCFG0_COUNT (2) +#define RSCAN0_RMND0_COUNT (3) +#define RSCAN0_RFCC0_COUNT (8) +#define RSCAN0_RFSTS0_COUNT (8) +#define RSCAN0_RFPCTR0_COUNT (8) +#define RSCAN0_CFCC0_COUNT (15) +#define RSCAN0_CFSTS0_COUNT (15) +#define RSCAN0_CFPCTR0_COUNT (15) +#define RSCAN0_TMC0_COUNT (80) +#define RSCAN0_TMSTS0_COUNT (80) +#define RSCAN0_TMTRSTS0_COUNT (3) +#define RSCAN0_TMTARSTS0_COUNT (3) +#define RSCAN0_TMTCSTS0_COUNT (3) +#define RSCAN0_TMTASTS0_COUNT (3) +#define RSCAN0_TMIEC0_COUNT (3) +#define RSCAN0_TXQCC0_COUNT (5) +#define RSCAN0_TXQSTS0_COUNT (5) +#define RSCAN0_TXQPCTR0_COUNT (5) +#define RSCAN0_THLCC0_COUNT (5) +#define RSCAN0_THLSTS0_COUNT (5) +#define RSCAN0_THLPCTR0_COUNT (5) +#define RSCAN0_GTINTSTS0_COUNT (2) +#define RSCAN0_THLACC0_COUNT (5) + + +typedef struct st_rscan0 +{ + /* RSCAN0 */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C0CFG; /* C0CFG */ + union iodefine_reg32_t C0CTR; /* C0CTR */ + union iodefine_reg32_t C0STS; /* C0STS */ + union iodefine_reg32_t C0ERFL; /* C0ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C1CFG; /* C1CFG */ + union iodefine_reg32_t C1CTR; /* C1CTR */ + union iodefine_reg32_t C1STS; /* C1STS */ + union iodefine_reg32_t C1ERFL; /* C1ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C2CFG; /* C2CFG */ + union iodefine_reg32_t C2CTR; /* C2CTR */ + union iodefine_reg32_t C2STS; /* C2STS */ + union iodefine_reg32_t C2ERFL; /* C2ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C3CFG; /* C3CFG */ + union iodefine_reg32_t C3CTR; /* C3CTR */ + union iodefine_reg32_t C3STS; /* C3STS */ + union iodefine_reg32_t C3ERFL; /* C3ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + +/* start of struct st_rscan_from_rscan0cncfg */ + union iodefine_reg32_t C4CFG; /* C4CFG */ + union iodefine_reg32_t C4CTR; /* C4CTR */ + union iodefine_reg32_t C4STS; /* C4STS */ + union iodefine_reg32_t C4ERFL; /* C4ERFL */ + +/* end of struct st_rscan_from_rscan0cncfg */ + + volatile uint8_t dummy159[52]; /* */ + union iodefine_reg32_t GCFG; /* GCFG */ + union iodefine_reg32_t GCTR; /* GCTR */ + union iodefine_reg32_t GSTS; /* GSTS */ + union iodefine_reg32_t GERFL; /* GERFL */ + union iodefine_reg32_16_t GTSC; /* GTSC */ + union iodefine_reg32_t GAFLECTR; /* GAFLECTR */ + +/* #define RSCAN0_GAFLCFG0_COUNT (2) */ + union iodefine_reg32_t GAFLCFG0; /* GAFLCFG0 */ + union iodefine_reg32_t GAFLCFG1; /* GAFLCFG1 */ + union iodefine_reg32_t RMNB; /* RMNB */ + +/* #define RSCAN0_RMND0_COUNT (3) */ + union iodefine_reg32_t RMND0; /* RMND0 */ + union iodefine_reg32_t RMND1; /* RMND1 */ + union iodefine_reg32_t RMND2; /* RMND2 */ + + volatile uint8_t dummy160[4]; /* */ + +/* #define RSCAN0_RFCC0_COUNT (8) */ + union iodefine_reg32_t RFCC0; /* RFCC0 */ + union iodefine_reg32_t RFCC1; /* RFCC1 */ + union iodefine_reg32_t RFCC2; /* RFCC2 */ + union iodefine_reg32_t RFCC3; /* RFCC3 */ + union iodefine_reg32_t RFCC4; /* RFCC4 */ + union iodefine_reg32_t RFCC5; /* RFCC5 */ + union iodefine_reg32_t RFCC6; /* RFCC6 */ + union iodefine_reg32_t RFCC7; /* RFCC7 */ + +/* #define RSCAN0_RFSTS0_COUNT (8) */ + union iodefine_reg32_t RFSTS0; /* RFSTS0 */ + union iodefine_reg32_t RFSTS1; /* RFSTS1 */ + union iodefine_reg32_t RFSTS2; /* RFSTS2 */ + union iodefine_reg32_t RFSTS3; /* RFSTS3 */ + union iodefine_reg32_t RFSTS4; /* RFSTS4 */ + union iodefine_reg32_t RFSTS5; /* RFSTS5 */ + union iodefine_reg32_t RFSTS6; /* RFSTS6 */ + union iodefine_reg32_t RFSTS7; /* RFSTS7 */ + +/* #define RSCAN0_RFPCTR0_COUNT (8) */ + union iodefine_reg32_t RFPCTR0; /* RFPCTR0 */ + union iodefine_reg32_t RFPCTR1; /* RFPCTR1 */ + union iodefine_reg32_t RFPCTR2; /* RFPCTR2 */ + union iodefine_reg32_t RFPCTR3; /* RFPCTR3 */ + union iodefine_reg32_t RFPCTR4; /* RFPCTR4 */ + union iodefine_reg32_t RFPCTR5; /* RFPCTR5 */ + union iodefine_reg32_t RFPCTR6; /* RFPCTR6 */ + union iodefine_reg32_t RFPCTR7; /* RFPCTR7 */ + +/* #define RSCAN0_CFCC0_COUNT (15) */ + union iodefine_reg32_t CFCC0; /* CFCC0 */ + union iodefine_reg32_t CFCC1; /* CFCC1 */ + union iodefine_reg32_t CFCC2; /* CFCC2 */ + union iodefine_reg32_t CFCC3; /* CFCC3 */ + union iodefine_reg32_t CFCC4; /* CFCC4 */ + union iodefine_reg32_t CFCC5; /* CFCC5 */ + union iodefine_reg32_t CFCC6; /* CFCC6 */ + union iodefine_reg32_t CFCC7; /* CFCC7 */ + union iodefine_reg32_t CFCC8; /* CFCC8 */ + union iodefine_reg32_t CFCC9; /* CFCC9 */ + union iodefine_reg32_t CFCC10; /* CFCC10 */ + union iodefine_reg32_t CFCC11; /* CFCC11 */ + union iodefine_reg32_t CFCC12; /* CFCC12 */ + union iodefine_reg32_t CFCC13; /* CFCC13 */ + union iodefine_reg32_t CFCC14; /* CFCC14 */ + + volatile uint8_t dummy161[36]; /* */ + +/* #define RSCAN0_CFSTS0_COUNT (15) */ + union iodefine_reg32_t CFSTS0; /* CFSTS0 */ + union iodefine_reg32_t CFSTS1; /* CFSTS1 */ + union iodefine_reg32_t CFSTS2; /* CFSTS2 */ + union iodefine_reg32_t CFSTS3; /* CFSTS3 */ + union iodefine_reg32_t CFSTS4; /* CFSTS4 */ + union iodefine_reg32_t CFSTS5; /* CFSTS5 */ + union iodefine_reg32_t CFSTS6; /* CFSTS6 */ + union iodefine_reg32_t CFSTS7; /* CFSTS7 */ + union iodefine_reg32_t CFSTS8; /* CFSTS8 */ + union iodefine_reg32_t CFSTS9; /* CFSTS9 */ + union iodefine_reg32_t CFSTS10; /* CFSTS10 */ + union iodefine_reg32_t CFSTS11; /* CFSTS11 */ + union iodefine_reg32_t CFSTS12; /* CFSTS12 */ + union iodefine_reg32_t CFSTS13; /* CFSTS13 */ + union iodefine_reg32_t CFSTS14; /* CFSTS14 */ + + volatile uint8_t dummy162[36]; /* */ + +/* #define RSCAN0_CFPCTR0_COUNT (15) */ + union iodefine_reg32_t CFPCTR0; /* CFPCTR0 */ + union iodefine_reg32_t CFPCTR1; /* CFPCTR1 */ + union iodefine_reg32_t CFPCTR2; /* CFPCTR2 */ + union iodefine_reg32_t CFPCTR3; /* CFPCTR3 */ + union iodefine_reg32_t CFPCTR4; /* CFPCTR4 */ + union iodefine_reg32_t CFPCTR5; /* CFPCTR5 */ + union iodefine_reg32_t CFPCTR6; /* CFPCTR6 */ + union iodefine_reg32_t CFPCTR7; /* CFPCTR7 */ + union iodefine_reg32_t CFPCTR8; /* CFPCTR8 */ + union iodefine_reg32_t CFPCTR9; /* CFPCTR9 */ + union iodefine_reg32_t CFPCTR10; /* CFPCTR10 */ + union iodefine_reg32_t CFPCTR11; /* CFPCTR11 */ + union iodefine_reg32_t CFPCTR12; /* CFPCTR12 */ + union iodefine_reg32_t CFPCTR13; /* CFPCTR13 */ + union iodefine_reg32_t CFPCTR14; /* CFPCTR14 */ + + volatile uint8_t dummy163[36]; /* */ + union iodefine_reg32_t FESTS; /* FESTS */ + union iodefine_reg32_t FFSTS; /* FFSTS */ + union iodefine_reg32_t FMSTS; /* FMSTS */ + union iodefine_reg32_t RFISTS; /* RFISTS */ + union iodefine_reg32_t CFRISTS; /* CFRISTS */ + union iodefine_reg32_t CFTISTS; /* CFTISTS */ + + +/* #define RSCAN0_TMC0_COUNT (80) */ + volatile uint8_t TMC0; /* TMC0 */ + volatile uint8_t TMC1; /* TMC1 */ + volatile uint8_t TMC2; /* TMC2 */ + volatile uint8_t TMC3; /* TMC3 */ + volatile uint8_t TMC4; /* TMC4 */ + volatile uint8_t TMC5; /* TMC5 */ + volatile uint8_t TMC6; /* TMC6 */ + volatile uint8_t TMC7; /* TMC7 */ + volatile uint8_t TMC8; /* TMC8 */ + volatile uint8_t TMC9; /* TMC9 */ + volatile uint8_t TMC10; /* TMC10 */ + volatile uint8_t TMC11; /* TMC11 */ + volatile uint8_t TMC12; /* TMC12 */ + volatile uint8_t TMC13; /* TMC13 */ + volatile uint8_t TMC14; /* TMC14 */ + volatile uint8_t TMC15; /* TMC15 */ + volatile uint8_t TMC16; /* TMC16 */ + volatile uint8_t TMC17; /* TMC17 */ + volatile uint8_t TMC18; /* TMC18 */ + volatile uint8_t TMC19; /* TMC19 */ + volatile uint8_t TMC20; /* TMC20 */ + volatile uint8_t TMC21; /* TMC21 */ + volatile uint8_t TMC22; /* TMC22 */ + volatile uint8_t TMC23; /* TMC23 */ + volatile uint8_t TMC24; /* TMC24 */ + volatile uint8_t TMC25; /* TMC25 */ + volatile uint8_t TMC26; /* TMC26 */ + volatile uint8_t TMC27; /* TMC27 */ + volatile uint8_t TMC28; /* TMC28 */ + volatile uint8_t TMC29; /* TMC29 */ + volatile uint8_t TMC30; /* TMC30 */ + volatile uint8_t TMC31; /* TMC31 */ + volatile uint8_t TMC32; /* TMC32 */ + volatile uint8_t TMC33; /* TMC33 */ + volatile uint8_t TMC34; /* TMC34 */ + volatile uint8_t TMC35; /* TMC35 */ + volatile uint8_t TMC36; /* TMC36 */ + volatile uint8_t TMC37; /* TMC37 */ + volatile uint8_t TMC38; /* TMC38 */ + volatile uint8_t TMC39; /* TMC39 */ + volatile uint8_t TMC40; /* TMC40 */ + volatile uint8_t TMC41; /* TMC41 */ + volatile uint8_t TMC42; /* TMC42 */ + volatile uint8_t TMC43; /* TMC43 */ + volatile uint8_t TMC44; /* TMC44 */ + volatile uint8_t TMC45; /* TMC45 */ + volatile uint8_t TMC46; /* TMC46 */ + volatile uint8_t TMC47; /* TMC47 */ + volatile uint8_t TMC48; /* TMC48 */ + volatile uint8_t TMC49; /* TMC49 */ + volatile uint8_t TMC50; /* TMC50 */ + volatile uint8_t TMC51; /* TMC51 */ + volatile uint8_t TMC52; /* TMC52 */ + volatile uint8_t TMC53; /* TMC53 */ + volatile uint8_t TMC54; /* TMC54 */ + volatile uint8_t TMC55; /* TMC55 */ + volatile uint8_t TMC56; /* TMC56 */ + volatile uint8_t TMC57; /* TMC57 */ + volatile uint8_t TMC58; /* TMC58 */ + volatile uint8_t TMC59; /* TMC59 */ + volatile uint8_t TMC60; /* TMC60 */ + volatile uint8_t TMC61; /* TMC61 */ + volatile uint8_t TMC62; /* TMC62 */ + volatile uint8_t TMC63; /* TMC63 */ + volatile uint8_t TMC64; /* TMC64 */ + volatile uint8_t TMC65; /* TMC65 */ + volatile uint8_t TMC66; /* TMC66 */ + volatile uint8_t TMC67; /* TMC67 */ + volatile uint8_t TMC68; /* TMC68 */ + volatile uint8_t TMC69; /* TMC69 */ + volatile uint8_t TMC70; /* TMC70 */ + volatile uint8_t TMC71; /* TMC71 */ + volatile uint8_t TMC72; /* TMC72 */ + volatile uint8_t TMC73; /* TMC73 */ + volatile uint8_t TMC74; /* TMC74 */ + volatile uint8_t TMC75; /* TMC75 */ + volatile uint8_t TMC76; /* TMC76 */ + volatile uint8_t TMC77; /* TMC77 */ + volatile uint8_t TMC78; /* TMC78 */ + volatile uint8_t TMC79; /* TMC79 */ + volatile uint8_t dummy164[48]; /* */ + +/* #define RSCAN0_TMSTS0_COUNT (80) */ + volatile uint8_t TMSTS0; /* TMSTS0 */ + volatile uint8_t TMSTS1; /* TMSTS1 */ + volatile uint8_t TMSTS2; /* TMSTS2 */ + volatile uint8_t TMSTS3; /* TMSTS3 */ + volatile uint8_t TMSTS4; /* TMSTS4 */ + volatile uint8_t TMSTS5; /* TMSTS5 */ + volatile uint8_t TMSTS6; /* TMSTS6 */ + volatile uint8_t TMSTS7; /* TMSTS7 */ + volatile uint8_t TMSTS8; /* TMSTS8 */ + volatile uint8_t TMSTS9; /* TMSTS9 */ + volatile uint8_t TMSTS10; /* TMSTS10 */ + volatile uint8_t TMSTS11; /* TMSTS11 */ + volatile uint8_t TMSTS12; /* TMSTS12 */ + volatile uint8_t TMSTS13; /* TMSTS13 */ + volatile uint8_t TMSTS14; /* TMSTS14 */ + volatile uint8_t TMSTS15; /* TMSTS15 */ + volatile uint8_t TMSTS16; /* TMSTS16 */ + volatile uint8_t TMSTS17; /* TMSTS17 */ + volatile uint8_t TMSTS18; /* TMSTS18 */ + volatile uint8_t TMSTS19; /* TMSTS19 */ + volatile uint8_t TMSTS20; /* TMSTS20 */ + volatile uint8_t TMSTS21; /* TMSTS21 */ + volatile uint8_t TMSTS22; /* TMSTS22 */ + volatile uint8_t TMSTS23; /* TMSTS23 */ + volatile uint8_t TMSTS24; /* TMSTS24 */ + volatile uint8_t TMSTS25; /* TMSTS25 */ + volatile uint8_t TMSTS26; /* TMSTS26 */ + volatile uint8_t TMSTS27; /* TMSTS27 */ + volatile uint8_t TMSTS28; /* TMSTS28 */ + volatile uint8_t TMSTS29; /* TMSTS29 */ + volatile uint8_t TMSTS30; /* TMSTS30 */ + volatile uint8_t TMSTS31; /* TMSTS31 */ + volatile uint8_t TMSTS32; /* TMSTS32 */ + volatile uint8_t TMSTS33; /* TMSTS33 */ + volatile uint8_t TMSTS34; /* TMSTS34 */ + volatile uint8_t TMSTS35; /* TMSTS35 */ + volatile uint8_t TMSTS36; /* TMSTS36 */ + volatile uint8_t TMSTS37; /* TMSTS37 */ + volatile uint8_t TMSTS38; /* TMSTS38 */ + volatile uint8_t TMSTS39; /* TMSTS39 */ + volatile uint8_t TMSTS40; /* TMSTS40 */ + volatile uint8_t TMSTS41; /* TMSTS41 */ + volatile uint8_t TMSTS42; /* TMSTS42 */ + volatile uint8_t TMSTS43; /* TMSTS43 */ + volatile uint8_t TMSTS44; /* TMSTS44 */ + volatile uint8_t TMSTS45; /* TMSTS45 */ + volatile uint8_t TMSTS46; /* TMSTS46 */ + volatile uint8_t TMSTS47; /* TMSTS47 */ + volatile uint8_t TMSTS48; /* TMSTS48 */ + volatile uint8_t TMSTS49; /* TMSTS49 */ + volatile uint8_t TMSTS50; /* TMSTS50 */ + volatile uint8_t TMSTS51; /* TMSTS51 */ + volatile uint8_t TMSTS52; /* TMSTS52 */ + volatile uint8_t TMSTS53; /* TMSTS53 */ + volatile uint8_t TMSTS54; /* TMSTS54 */ + volatile uint8_t TMSTS55; /* TMSTS55 */ + volatile uint8_t TMSTS56; /* TMSTS56 */ + volatile uint8_t TMSTS57; /* TMSTS57 */ + volatile uint8_t TMSTS58; /* TMSTS58 */ + volatile uint8_t TMSTS59; /* TMSTS59 */ + volatile uint8_t TMSTS60; /* TMSTS60 */ + volatile uint8_t TMSTS61; /* TMSTS61 */ + volatile uint8_t TMSTS62; /* TMSTS62 */ + volatile uint8_t TMSTS63; /* TMSTS63 */ + volatile uint8_t TMSTS64; /* TMSTS64 */ + volatile uint8_t TMSTS65; /* TMSTS65 */ + volatile uint8_t TMSTS66; /* TMSTS66 */ + volatile uint8_t TMSTS67; /* TMSTS67 */ + volatile uint8_t TMSTS68; /* TMSTS68 */ + volatile uint8_t TMSTS69; /* TMSTS69 */ + volatile uint8_t TMSTS70; /* TMSTS70 */ + volatile uint8_t TMSTS71; /* TMSTS71 */ + volatile uint8_t TMSTS72; /* TMSTS72 */ + volatile uint8_t TMSTS73; /* TMSTS73 */ + volatile uint8_t TMSTS74; /* TMSTS74 */ + volatile uint8_t TMSTS75; /* TMSTS75 */ + volatile uint8_t TMSTS76; /* TMSTS76 */ + volatile uint8_t TMSTS77; /* TMSTS77 */ + volatile uint8_t TMSTS78; /* TMSTS78 */ + volatile uint8_t TMSTS79; /* TMSTS79 */ + volatile uint8_t dummy165[48]; /* */ + +/* #define RSCAN0_TMTRSTS0_COUNT (3) */ + union iodefine_reg32_t TMTRSTS0; /* TMTRSTS0 */ + union iodefine_reg32_t TMTRSTS1; /* TMTRSTS1 */ + union iodefine_reg32_t TMTRSTS2; /* TMTRSTS2 */ + + volatile uint8_t dummy166[4]; /* */ + +/* #define RSCAN0_TMTARSTS0_COUNT (3) */ + union iodefine_reg32_t TMTARSTS0; /* TMTARSTS0 */ + union iodefine_reg32_t TMTARSTS1; /* TMTARSTS1 */ + union iodefine_reg32_t TMTARSTS2; /* TMTARSTS2 */ + + volatile uint8_t dummy167[4]; /* */ + +/* #define RSCAN0_TMTCSTS0_COUNT (3) */ + union iodefine_reg32_t TMTCSTS0; /* TMTCSTS0 */ + union iodefine_reg32_t TMTCSTS1; /* TMTCSTS1 */ + union iodefine_reg32_t TMTCSTS2; /* TMTCSTS2 */ + + volatile uint8_t dummy168[4]; /* */ + +/* #define RSCAN0_TMTASTS0_COUNT (3) */ + union iodefine_reg32_t TMTASTS0; /* TMTASTS0 */ + union iodefine_reg32_t TMTASTS1; /* TMTASTS1 */ + union iodefine_reg32_t TMTASTS2; /* TMTASTS2 */ + + volatile uint8_t dummy169[4]; /* */ + +/* #define RSCAN0_TMIEC0_COUNT (3) */ + union iodefine_reg32_t TMIEC0; /* TMIEC0 */ + union iodefine_reg32_t TMIEC1; /* TMIEC1 */ + union iodefine_reg32_t TMIEC2; /* TMIEC2 */ + + volatile uint8_t dummy170[4]; /* */ + +/* #define RSCAN0_TXQCC0_COUNT (5) */ + union iodefine_reg32_t TXQCC0; /* TXQCC0 */ + union iodefine_reg32_t TXQCC1; /* TXQCC1 */ + union iodefine_reg32_t TXQCC2; /* TXQCC2 */ + union iodefine_reg32_t TXQCC3; /* TXQCC3 */ + union iodefine_reg32_t TXQCC4; /* TXQCC4 */ + + volatile uint8_t dummy171[12]; /* */ + +/* #define RSCAN0_TXQSTS0_COUNT (5) */ + union iodefine_reg32_t TXQSTS0; /* TXQSTS0 */ + union iodefine_reg32_t TXQSTS1; /* TXQSTS1 */ + union iodefine_reg32_t TXQSTS2; /* TXQSTS2 */ + union iodefine_reg32_t TXQSTS3; /* TXQSTS3 */ + union iodefine_reg32_t TXQSTS4; /* TXQSTS4 */ + + volatile uint8_t dummy172[12]; /* */ + +/* #define RSCAN0_TXQPCTR0_COUNT (5) */ + union iodefine_reg32_t TXQPCTR0; /* TXQPCTR0 */ + union iodefine_reg32_t TXQPCTR1; /* TXQPCTR1 */ + union iodefine_reg32_t TXQPCTR2; /* TXQPCTR2 */ + union iodefine_reg32_t TXQPCTR3; /* TXQPCTR3 */ + union iodefine_reg32_t TXQPCTR4; /* TXQPCTR4 */ + + volatile uint8_t dummy173[12]; /* */ + +/* #define RSCAN0_THLCC0_COUNT (5) */ + union iodefine_reg32_t THLCC0; /* THLCC0 */ + union iodefine_reg32_t THLCC1; /* THLCC1 */ + union iodefine_reg32_t THLCC2; /* THLCC2 */ + union iodefine_reg32_t THLCC3; /* THLCC3 */ + union iodefine_reg32_t THLCC4; /* THLCC4 */ + + volatile uint8_t dummy174[12]; /* */ + +/* #define RSCAN0_THLSTS0_COUNT (5) */ + union iodefine_reg32_t THLSTS0; /* THLSTS0 */ + union iodefine_reg32_t THLSTS1; /* THLSTS1 */ + union iodefine_reg32_t THLSTS2; /* THLSTS2 */ + union iodefine_reg32_t THLSTS3; /* THLSTS3 */ + union iodefine_reg32_t THLSTS4; /* THLSTS4 */ + + volatile uint8_t dummy175[12]; /* */ + +/* #define RSCAN0_THLPCTR0_COUNT (5) */ + union iodefine_reg32_t THLPCTR0; /* THLPCTR0 */ + union iodefine_reg32_t THLPCTR1; /* THLPCTR1 */ + union iodefine_reg32_t THLPCTR2; /* THLPCTR2 */ + union iodefine_reg32_t THLPCTR3; /* THLPCTR3 */ + union iodefine_reg32_t THLPCTR4; /* THLPCTR4 */ + + volatile uint8_t dummy176[12]; /* */ + +/* #define RSCAN0_GTINTSTS0_COUNT (2) */ + union iodefine_reg32_t GTINTSTS0; /* GTINTSTS0 */ + union iodefine_reg32_t GTINTSTS1; /* GTINTSTS1 */ + union iodefine_reg32_t GTSTCFG; /* GTSTCFG */ + union iodefine_reg32_t GTSTCTR; /* GTSTCTR */ + + volatile uint8_t dummy177[12]; /* */ + union iodefine_reg32_16_t GLOCKK; /* GLOCKK */ + + volatile uint8_t dummy178[128]; /* */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID0; /* GAFLID0 */ + union iodefine_reg32_t GAFLM0; /* GAFLM0 */ + union iodefine_reg32_t GAFLP00; /* GAFLP00 */ + union iodefine_reg32_t GAFLP10; /* GAFLP10 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID1; /* GAFLID1 */ + union iodefine_reg32_t GAFLM1; /* GAFLM1 */ + union iodefine_reg32_t GAFLP01; /* GAFLP01 */ + union iodefine_reg32_t GAFLP11; /* GAFLP11 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID2; /* GAFLID2 */ + union iodefine_reg32_t GAFLM2; /* GAFLM2 */ + union iodefine_reg32_t GAFLP02; /* GAFLP02 */ + union iodefine_reg32_t GAFLP12; /* GAFLP12 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID3; /* GAFLID3 */ + union iodefine_reg32_t GAFLM3; /* GAFLM3 */ + union iodefine_reg32_t GAFLP03; /* GAFLP03 */ + union iodefine_reg32_t GAFLP13; /* GAFLP13 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID4; /* GAFLID4 */ + union iodefine_reg32_t GAFLM4; /* GAFLM4 */ + union iodefine_reg32_t GAFLP04; /* GAFLP04 */ + union iodefine_reg32_t GAFLP14; /* GAFLP14 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID5; /* GAFLID5 */ + union iodefine_reg32_t GAFLM5; /* GAFLM5 */ + union iodefine_reg32_t GAFLP05; /* GAFLP05 */ + union iodefine_reg32_t GAFLP15; /* GAFLP15 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID6; /* GAFLID6 */ + union iodefine_reg32_t GAFLM6; /* GAFLM6 */ + union iodefine_reg32_t GAFLP06; /* GAFLP06 */ + union iodefine_reg32_t GAFLP16; /* GAFLP16 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID7; /* GAFLID7 */ + union iodefine_reg32_t GAFLM7; /* GAFLM7 */ + union iodefine_reg32_t GAFLP07; /* GAFLP07 */ + union iodefine_reg32_t GAFLP17; /* GAFLP17 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID8; /* GAFLID8 */ + union iodefine_reg32_t GAFLM8; /* GAFLM8 */ + union iodefine_reg32_t GAFLP08; /* GAFLP08 */ + union iodefine_reg32_t GAFLP18; /* GAFLP18 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID9; /* GAFLID9 */ + union iodefine_reg32_t GAFLM9; /* GAFLM9 */ + union iodefine_reg32_t GAFLP09; /* GAFLP09 */ + union iodefine_reg32_t GAFLP19; /* GAFLP19 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID10; /* GAFLID10 */ + union iodefine_reg32_t GAFLM10; /* GAFLM10 */ + union iodefine_reg32_t GAFLP010; /* GAFLP010 */ + union iodefine_reg32_t GAFLP110; /* GAFLP110 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID11; /* GAFLID11 */ + union iodefine_reg32_t GAFLM11; /* GAFLM11 */ + union iodefine_reg32_t GAFLP011; /* GAFLP011 */ + union iodefine_reg32_t GAFLP111; /* GAFLP111 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID12; /* GAFLID12 */ + union iodefine_reg32_t GAFLM12; /* GAFLM12 */ + union iodefine_reg32_t GAFLP012; /* GAFLP012 */ + union iodefine_reg32_t GAFLP112; /* GAFLP112 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID13; /* GAFLID13 */ + union iodefine_reg32_t GAFLM13; /* GAFLM13 */ + union iodefine_reg32_t GAFLP013; /* GAFLP013 */ + union iodefine_reg32_t GAFLP113; /* GAFLP113 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID14; /* GAFLID14 */ + union iodefine_reg32_t GAFLM14; /* GAFLM14 */ + union iodefine_reg32_t GAFLP014; /* GAFLP014 */ + union iodefine_reg32_t GAFLP114; /* GAFLP114 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0gaflidj */ + union iodefine_reg32_t GAFLID15; /* GAFLID15 */ + union iodefine_reg32_t GAFLM15; /* GAFLM15 */ + union iodefine_reg32_t GAFLP015; /* GAFLP015 */ + union iodefine_reg32_t GAFLP115; /* GAFLP115 */ + +/* end of struct st_rscan_from_rscan0gaflidj */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID0; /* RMID0 */ + union iodefine_reg32_t RMPTR0; /* RMPTR0 */ + union iodefine_reg32_t RMDF00; /* RMDF00 */ + union iodefine_reg32_t RMDF10; /* RMDF10 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID1; /* RMID1 */ + union iodefine_reg32_t RMPTR1; /* RMPTR1 */ + union iodefine_reg32_t RMDF01; /* RMDF01 */ + union iodefine_reg32_t RMDF11; /* RMDF11 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID2; /* RMID2 */ + union iodefine_reg32_t RMPTR2; /* RMPTR2 */ + union iodefine_reg32_t RMDF02; /* RMDF02 */ + union iodefine_reg32_t RMDF12; /* RMDF12 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID3; /* RMID3 */ + union iodefine_reg32_t RMPTR3; /* RMPTR3 */ + union iodefine_reg32_t RMDF03; /* RMDF03 */ + union iodefine_reg32_t RMDF13; /* RMDF13 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID4; /* RMID4 */ + union iodefine_reg32_t RMPTR4; /* RMPTR4 */ + union iodefine_reg32_t RMDF04; /* RMDF04 */ + union iodefine_reg32_t RMDF14; /* RMDF14 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID5; /* RMID5 */ + union iodefine_reg32_t RMPTR5; /* RMPTR5 */ + union iodefine_reg32_t RMDF05; /* RMDF05 */ + union iodefine_reg32_t RMDF15; /* RMDF15 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID6; /* RMID6 */ + union iodefine_reg32_t RMPTR6; /* RMPTR6 */ + union iodefine_reg32_t RMDF06; /* RMDF06 */ + union iodefine_reg32_t RMDF16; /* RMDF16 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID7; /* RMID7 */ + union iodefine_reg32_t RMPTR7; /* RMPTR7 */ + union iodefine_reg32_t RMDF07; /* RMDF07 */ + union iodefine_reg32_t RMDF17; /* RMDF17 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID8; /* RMID8 */ + union iodefine_reg32_t RMPTR8; /* RMPTR8 */ + union iodefine_reg32_t RMDF08; /* RMDF08 */ + union iodefine_reg32_t RMDF18; /* RMDF18 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID9; /* RMID9 */ + union iodefine_reg32_t RMPTR9; /* RMPTR9 */ + union iodefine_reg32_t RMDF09; /* RMDF09 */ + union iodefine_reg32_t RMDF19; /* RMDF19 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID10; /* RMID10 */ + union iodefine_reg32_t RMPTR10; /* RMPTR10 */ + union iodefine_reg32_t RMDF010; /* RMDF010 */ + union iodefine_reg32_t RMDF110; /* RMDF110 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID11; /* RMID11 */ + union iodefine_reg32_t RMPTR11; /* RMPTR11 */ + union iodefine_reg32_t RMDF011; /* RMDF011 */ + union iodefine_reg32_t RMDF111; /* RMDF111 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID12; /* RMID12 */ + union iodefine_reg32_t RMPTR12; /* RMPTR12 */ + union iodefine_reg32_t RMDF012; /* RMDF012 */ + union iodefine_reg32_t RMDF112; /* RMDF112 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID13; /* RMID13 */ + union iodefine_reg32_t RMPTR13; /* RMPTR13 */ + union iodefine_reg32_t RMDF013; /* RMDF013 */ + union iodefine_reg32_t RMDF113; /* RMDF113 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID14; /* RMID14 */ + union iodefine_reg32_t RMPTR14; /* RMPTR14 */ + union iodefine_reg32_t RMDF014; /* RMDF014 */ + union iodefine_reg32_t RMDF114; /* RMDF114 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID15; /* RMID15 */ + union iodefine_reg32_t RMPTR15; /* RMPTR15 */ + union iodefine_reg32_t RMDF015; /* RMDF015 */ + union iodefine_reg32_t RMDF115; /* RMDF115 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID16; /* RMID16 */ + union iodefine_reg32_t RMPTR16; /* RMPTR16 */ + union iodefine_reg32_t RMDF016; /* RMDF016 */ + union iodefine_reg32_t RMDF116; /* RMDF116 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID17; /* RMID17 */ + union iodefine_reg32_t RMPTR17; /* RMPTR17 */ + union iodefine_reg32_t RMDF017; /* RMDF017 */ + union iodefine_reg32_t RMDF117; /* RMDF117 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID18; /* RMID18 */ + union iodefine_reg32_t RMPTR18; /* RMPTR18 */ + union iodefine_reg32_t RMDF018; /* RMDF018 */ + union iodefine_reg32_t RMDF118; /* RMDF118 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID19; /* RMID19 */ + union iodefine_reg32_t RMPTR19; /* RMPTR19 */ + union iodefine_reg32_t RMDF019; /* RMDF019 */ + union iodefine_reg32_t RMDF119; /* RMDF119 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID20; /* RMID20 */ + union iodefine_reg32_t RMPTR20; /* RMPTR20 */ + union iodefine_reg32_t RMDF020; /* RMDF020 */ + union iodefine_reg32_t RMDF120; /* RMDF120 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID21; /* RMID21 */ + union iodefine_reg32_t RMPTR21; /* RMPTR21 */ + union iodefine_reg32_t RMDF021; /* RMDF021 */ + union iodefine_reg32_t RMDF121; /* RMDF121 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID22; /* RMID22 */ + union iodefine_reg32_t RMPTR22; /* RMPTR22 */ + union iodefine_reg32_t RMDF022; /* RMDF022 */ + union iodefine_reg32_t RMDF122; /* RMDF122 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID23; /* RMID23 */ + union iodefine_reg32_t RMPTR23; /* RMPTR23 */ + union iodefine_reg32_t RMDF023; /* RMDF023 */ + union iodefine_reg32_t RMDF123; /* RMDF123 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID24; /* RMID24 */ + union iodefine_reg32_t RMPTR24; /* RMPTR24 */ + union iodefine_reg32_t RMDF024; /* RMDF024 */ + union iodefine_reg32_t RMDF124; /* RMDF124 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID25; /* RMID25 */ + union iodefine_reg32_t RMPTR25; /* RMPTR25 */ + union iodefine_reg32_t RMDF025; /* RMDF025 */ + union iodefine_reg32_t RMDF125; /* RMDF125 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID26; /* RMID26 */ + union iodefine_reg32_t RMPTR26; /* RMPTR26 */ + union iodefine_reg32_t RMDF026; /* RMDF026 */ + union iodefine_reg32_t RMDF126; /* RMDF126 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID27; /* RMID27 */ + union iodefine_reg32_t RMPTR27; /* RMPTR27 */ + union iodefine_reg32_t RMDF027; /* RMDF027 */ + union iodefine_reg32_t RMDF127; /* RMDF127 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID28; /* RMID28 */ + union iodefine_reg32_t RMPTR28; /* RMPTR28 */ + union iodefine_reg32_t RMDF028; /* RMDF028 */ + union iodefine_reg32_t RMDF128; /* RMDF128 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID29; /* RMID29 */ + union iodefine_reg32_t RMPTR29; /* RMPTR29 */ + union iodefine_reg32_t RMDF029; /* RMDF029 */ + union iodefine_reg32_t RMDF129; /* RMDF129 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID30; /* RMID30 */ + union iodefine_reg32_t RMPTR30; /* RMPTR30 */ + union iodefine_reg32_t RMDF030; /* RMDF030 */ + union iodefine_reg32_t RMDF130; /* RMDF130 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID31; /* RMID31 */ + union iodefine_reg32_t RMPTR31; /* RMPTR31 */ + union iodefine_reg32_t RMDF031; /* RMDF031 */ + union iodefine_reg32_t RMDF131; /* RMDF131 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID32; /* RMID32 */ + union iodefine_reg32_t RMPTR32; /* RMPTR32 */ + union iodefine_reg32_t RMDF032; /* RMDF032 */ + union iodefine_reg32_t RMDF132; /* RMDF132 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID33; /* RMID33 */ + union iodefine_reg32_t RMPTR33; /* RMPTR33 */ + union iodefine_reg32_t RMDF033; /* RMDF033 */ + union iodefine_reg32_t RMDF133; /* RMDF133 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID34; /* RMID34 */ + union iodefine_reg32_t RMPTR34; /* RMPTR34 */ + union iodefine_reg32_t RMDF034; /* RMDF034 */ + union iodefine_reg32_t RMDF134; /* RMDF134 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID35; /* RMID35 */ + union iodefine_reg32_t RMPTR35; /* RMPTR35 */ + union iodefine_reg32_t RMDF035; /* RMDF035 */ + union iodefine_reg32_t RMDF135; /* RMDF135 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID36; /* RMID36 */ + union iodefine_reg32_t RMPTR36; /* RMPTR36 */ + union iodefine_reg32_t RMDF036; /* RMDF036 */ + union iodefine_reg32_t RMDF136; /* RMDF136 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID37; /* RMID37 */ + union iodefine_reg32_t RMPTR37; /* RMPTR37 */ + union iodefine_reg32_t RMDF037; /* RMDF037 */ + union iodefine_reg32_t RMDF137; /* RMDF137 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID38; /* RMID38 */ + union iodefine_reg32_t RMPTR38; /* RMPTR38 */ + union iodefine_reg32_t RMDF038; /* RMDF038 */ + union iodefine_reg32_t RMDF138; /* RMDF138 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID39; /* RMID39 */ + union iodefine_reg32_t RMPTR39; /* RMPTR39 */ + union iodefine_reg32_t RMDF039; /* RMDF039 */ + union iodefine_reg32_t RMDF139; /* RMDF139 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID40; /* RMID40 */ + union iodefine_reg32_t RMPTR40; /* RMPTR40 */ + union iodefine_reg32_t RMDF040; /* RMDF040 */ + union iodefine_reg32_t RMDF140; /* RMDF140 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID41; /* RMID41 */ + union iodefine_reg32_t RMPTR41; /* RMPTR41 */ + union iodefine_reg32_t RMDF041; /* RMDF041 */ + union iodefine_reg32_t RMDF141; /* RMDF141 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID42; /* RMID42 */ + union iodefine_reg32_t RMPTR42; /* RMPTR42 */ + union iodefine_reg32_t RMDF042; /* RMDF042 */ + union iodefine_reg32_t RMDF142; /* RMDF142 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID43; /* RMID43 */ + union iodefine_reg32_t RMPTR43; /* RMPTR43 */ + union iodefine_reg32_t RMDF043; /* RMDF043 */ + union iodefine_reg32_t RMDF143; /* RMDF143 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID44; /* RMID44 */ + union iodefine_reg32_t RMPTR44; /* RMPTR44 */ + union iodefine_reg32_t RMDF044; /* RMDF044 */ + union iodefine_reg32_t RMDF144; /* RMDF144 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID45; /* RMID45 */ + union iodefine_reg32_t RMPTR45; /* RMPTR45 */ + union iodefine_reg32_t RMDF045; /* RMDF045 */ + union iodefine_reg32_t RMDF145; /* RMDF145 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID46; /* RMID46 */ + union iodefine_reg32_t RMPTR46; /* RMPTR46 */ + union iodefine_reg32_t RMDF046; /* RMDF046 */ + union iodefine_reg32_t RMDF146; /* RMDF146 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID47; /* RMID47 */ + union iodefine_reg32_t RMPTR47; /* RMPTR47 */ + union iodefine_reg32_t RMDF047; /* RMDF047 */ + union iodefine_reg32_t RMDF147; /* RMDF147 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID48; /* RMID48 */ + union iodefine_reg32_t RMPTR48; /* RMPTR48 */ + union iodefine_reg32_t RMDF048; /* RMDF048 */ + union iodefine_reg32_t RMDF148; /* RMDF148 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID49; /* RMID49 */ + union iodefine_reg32_t RMPTR49; /* RMPTR49 */ + union iodefine_reg32_t RMDF049; /* RMDF049 */ + union iodefine_reg32_t RMDF149; /* RMDF149 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID50; /* RMID50 */ + union iodefine_reg32_t RMPTR50; /* RMPTR50 */ + union iodefine_reg32_t RMDF050; /* RMDF050 */ + union iodefine_reg32_t RMDF150; /* RMDF150 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID51; /* RMID51 */ + union iodefine_reg32_t RMPTR51; /* RMPTR51 */ + union iodefine_reg32_t RMDF051; /* RMDF051 */ + union iodefine_reg32_t RMDF151; /* RMDF151 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID52; /* RMID52 */ + union iodefine_reg32_t RMPTR52; /* RMPTR52 */ + union iodefine_reg32_t RMDF052; /* RMDF052 */ + union iodefine_reg32_t RMDF152; /* RMDF152 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID53; /* RMID53 */ + union iodefine_reg32_t RMPTR53; /* RMPTR53 */ + union iodefine_reg32_t RMDF053; /* RMDF053 */ + union iodefine_reg32_t RMDF153; /* RMDF153 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID54; /* RMID54 */ + union iodefine_reg32_t RMPTR54; /* RMPTR54 */ + union iodefine_reg32_t RMDF054; /* RMDF054 */ + union iodefine_reg32_t RMDF154; /* RMDF154 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID55; /* RMID55 */ + union iodefine_reg32_t RMPTR55; /* RMPTR55 */ + union iodefine_reg32_t RMDF055; /* RMDF055 */ + union iodefine_reg32_t RMDF155; /* RMDF155 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID56; /* RMID56 */ + union iodefine_reg32_t RMPTR56; /* RMPTR56 */ + union iodefine_reg32_t RMDF056; /* RMDF056 */ + union iodefine_reg32_t RMDF156; /* RMDF156 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID57; /* RMID57 */ + union iodefine_reg32_t RMPTR57; /* RMPTR57 */ + union iodefine_reg32_t RMDF057; /* RMDF057 */ + union iodefine_reg32_t RMDF157; /* RMDF157 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID58; /* RMID58 */ + union iodefine_reg32_t RMPTR58; /* RMPTR58 */ + union iodefine_reg32_t RMDF058; /* RMDF058 */ + union iodefine_reg32_t RMDF158; /* RMDF158 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID59; /* RMID59 */ + union iodefine_reg32_t RMPTR59; /* RMPTR59 */ + union iodefine_reg32_t RMDF059; /* RMDF059 */ + union iodefine_reg32_t RMDF159; /* RMDF159 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID60; /* RMID60 */ + union iodefine_reg32_t RMPTR60; /* RMPTR60 */ + union iodefine_reg32_t RMDF060; /* RMDF060 */ + union iodefine_reg32_t RMDF160; /* RMDF160 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID61; /* RMID61 */ + union iodefine_reg32_t RMPTR61; /* RMPTR61 */ + union iodefine_reg32_t RMDF061; /* RMDF061 */ + union iodefine_reg32_t RMDF161; /* RMDF161 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID62; /* RMID62 */ + union iodefine_reg32_t RMPTR62; /* RMPTR62 */ + union iodefine_reg32_t RMDF062; /* RMDF062 */ + union iodefine_reg32_t RMDF162; /* RMDF162 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID63; /* RMID63 */ + union iodefine_reg32_t RMPTR63; /* RMPTR63 */ + union iodefine_reg32_t RMDF063; /* RMDF063 */ + union iodefine_reg32_t RMDF163; /* RMDF163 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID64; /* RMID64 */ + union iodefine_reg32_t RMPTR64; /* RMPTR64 */ + union iodefine_reg32_t RMDF064; /* RMDF064 */ + union iodefine_reg32_t RMDF164; /* RMDF164 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID65; /* RMID65 */ + union iodefine_reg32_t RMPTR65; /* RMPTR65 */ + union iodefine_reg32_t RMDF065; /* RMDF065 */ + union iodefine_reg32_t RMDF165; /* RMDF165 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID66; /* RMID66 */ + union iodefine_reg32_t RMPTR66; /* RMPTR66 */ + union iodefine_reg32_t RMDF066; /* RMDF066 */ + union iodefine_reg32_t RMDF166; /* RMDF166 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID67; /* RMID67 */ + union iodefine_reg32_t RMPTR67; /* RMPTR67 */ + union iodefine_reg32_t RMDF067; /* RMDF067 */ + union iodefine_reg32_t RMDF167; /* RMDF167 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID68; /* RMID68 */ + union iodefine_reg32_t RMPTR68; /* RMPTR68 */ + union iodefine_reg32_t RMDF068; /* RMDF068 */ + union iodefine_reg32_t RMDF168; /* RMDF168 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID69; /* RMID69 */ + union iodefine_reg32_t RMPTR69; /* RMPTR69 */ + union iodefine_reg32_t RMDF069; /* RMDF069 */ + union iodefine_reg32_t RMDF169; /* RMDF169 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID70; /* RMID70 */ + union iodefine_reg32_t RMPTR70; /* RMPTR70 */ + union iodefine_reg32_t RMDF070; /* RMDF070 */ + union iodefine_reg32_t RMDF170; /* RMDF170 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID71; /* RMID71 */ + union iodefine_reg32_t RMPTR71; /* RMPTR71 */ + union iodefine_reg32_t RMDF071; /* RMDF071 */ + union iodefine_reg32_t RMDF171; /* RMDF171 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID72; /* RMID72 */ + union iodefine_reg32_t RMPTR72; /* RMPTR72 */ + union iodefine_reg32_t RMDF072; /* RMDF072 */ + union iodefine_reg32_t RMDF172; /* RMDF172 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID73; /* RMID73 */ + union iodefine_reg32_t RMPTR73; /* RMPTR73 */ + union iodefine_reg32_t RMDF073; /* RMDF073 */ + union iodefine_reg32_t RMDF173; /* RMDF173 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID74; /* RMID74 */ + union iodefine_reg32_t RMPTR74; /* RMPTR74 */ + union iodefine_reg32_t RMDF074; /* RMDF074 */ + union iodefine_reg32_t RMDF174; /* RMDF174 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID75; /* RMID75 */ + union iodefine_reg32_t RMPTR75; /* RMPTR75 */ + union iodefine_reg32_t RMDF075; /* RMDF075 */ + union iodefine_reg32_t RMDF175; /* RMDF175 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID76; /* RMID76 */ + union iodefine_reg32_t RMPTR76; /* RMPTR76 */ + union iodefine_reg32_t RMDF076; /* RMDF076 */ + union iodefine_reg32_t RMDF176; /* RMDF176 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID77; /* RMID77 */ + union iodefine_reg32_t RMPTR77; /* RMPTR77 */ + union iodefine_reg32_t RMDF077; /* RMDF077 */ + union iodefine_reg32_t RMDF177; /* RMDF177 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID78; /* RMID78 */ + union iodefine_reg32_t RMPTR78; /* RMPTR78 */ + union iodefine_reg32_t RMDF078; /* RMDF078 */ + union iodefine_reg32_t RMDF178; /* RMDF178 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + +/* start of struct st_rscan_from_rscan0rmidp */ + union iodefine_reg32_t RMID79; /* RMID79 */ + union iodefine_reg32_t RMPTR79; /* RMPTR79 */ + union iodefine_reg32_t RMDF079; /* RMDF079 */ + union iodefine_reg32_t RMDF179; /* RMDF179 */ + +/* end of struct st_rscan_from_rscan0rmidp */ + + volatile uint8_t dummy179[768]; /* */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID0; /* RFID0 */ + union iodefine_reg32_t RFPTR0; /* RFPTR0 */ + union iodefine_reg32_t RFDF00; /* RFDF00 */ + union iodefine_reg32_t RFDF10; /* RFDF10 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID1; /* RFID1 */ + union iodefine_reg32_t RFPTR1; /* RFPTR1 */ + union iodefine_reg32_t RFDF01; /* RFDF01 */ + union iodefine_reg32_t RFDF11; /* RFDF11 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID2; /* RFID2 */ + union iodefine_reg32_t RFPTR2; /* RFPTR2 */ + union iodefine_reg32_t RFDF02; /* RFDF02 */ + union iodefine_reg32_t RFDF12; /* RFDF12 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID3; /* RFID3 */ + union iodefine_reg32_t RFPTR3; /* RFPTR3 */ + union iodefine_reg32_t RFDF03; /* RFDF03 */ + union iodefine_reg32_t RFDF13; /* RFDF13 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID4; /* RFID4 */ + union iodefine_reg32_t RFPTR4; /* RFPTR4 */ + union iodefine_reg32_t RFDF04; /* RFDF04 */ + union iodefine_reg32_t RFDF14; /* RFDF14 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID5; /* RFID5 */ + union iodefine_reg32_t RFPTR5; /* RFPTR5 */ + union iodefine_reg32_t RFDF05; /* RFDF05 */ + union iodefine_reg32_t RFDF15; /* RFDF15 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID6; /* RFID6 */ + union iodefine_reg32_t RFPTR6; /* RFPTR6 */ + union iodefine_reg32_t RFDF06; /* RFDF06 */ + union iodefine_reg32_t RFDF16; /* RFDF16 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0rfidm */ + union iodefine_reg32_t RFID7; /* RFID7 */ + union iodefine_reg32_t RFPTR7; /* RFPTR7 */ + union iodefine_reg32_t RFDF07; /* RFDF07 */ + union iodefine_reg32_t RFDF17; /* RFDF17 */ + +/* end of struct st_rscan_from_rscan0rfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID0; /* CFID0 */ + union iodefine_reg32_t CFPTR0; /* CFPTR0 */ + union iodefine_reg32_t CFDF00; /* CFDF00 */ + union iodefine_reg32_t CFDF10; /* CFDF10 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID1; /* CFID1 */ + union iodefine_reg32_t CFPTR1; /* CFPTR1 */ + union iodefine_reg32_t CFDF01; /* CFDF01 */ + union iodefine_reg32_t CFDF11; /* CFDF11 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID2; /* CFID2 */ + union iodefine_reg32_t CFPTR2; /* CFPTR2 */ + union iodefine_reg32_t CFDF02; /* CFDF02 */ + union iodefine_reg32_t CFDF12; /* CFDF12 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID3; /* CFID3 */ + union iodefine_reg32_t CFPTR3; /* CFPTR3 */ + union iodefine_reg32_t CFDF03; /* CFDF03 */ + union iodefine_reg32_t CFDF13; /* CFDF13 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID4; /* CFID4 */ + union iodefine_reg32_t CFPTR4; /* CFPTR4 */ + union iodefine_reg32_t CFDF04; /* CFDF04 */ + union iodefine_reg32_t CFDF14; /* CFDF14 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID5; /* CFID5 */ + union iodefine_reg32_t CFPTR5; /* CFPTR5 */ + union iodefine_reg32_t CFDF05; /* CFDF05 */ + union iodefine_reg32_t CFDF15; /* CFDF15 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID6; /* CFID6 */ + union iodefine_reg32_t CFPTR6; /* CFPTR6 */ + union iodefine_reg32_t CFDF06; /* CFDF06 */ + union iodefine_reg32_t CFDF16; /* CFDF16 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID7; /* CFID7 */ + union iodefine_reg32_t CFPTR7; /* CFPTR7 */ + union iodefine_reg32_t CFDF07; /* CFDF07 */ + union iodefine_reg32_t CFDF17; /* CFDF17 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID8; /* CFID8 */ + union iodefine_reg32_t CFPTR8; /* CFPTR8 */ + union iodefine_reg32_t CFDF08; /* CFDF08 */ + union iodefine_reg32_t CFDF18; /* CFDF18 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID9; /* CFID9 */ + union iodefine_reg32_t CFPTR9; /* CFPTR9 */ + union iodefine_reg32_t CFDF09; /* CFDF09 */ + union iodefine_reg32_t CFDF19; /* CFDF19 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID10; /* CFID10 */ + union iodefine_reg32_t CFPTR10; /* CFPTR10 */ + union iodefine_reg32_t CFDF010; /* CFDF010 */ + union iodefine_reg32_t CFDF110; /* CFDF110 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID11; /* CFID11 */ + union iodefine_reg32_t CFPTR11; /* CFPTR11 */ + union iodefine_reg32_t CFDF011; /* CFDF011 */ + union iodefine_reg32_t CFDF111; /* CFDF111 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID12; /* CFID12 */ + union iodefine_reg32_t CFPTR12; /* CFPTR12 */ + union iodefine_reg32_t CFDF012; /* CFDF012 */ + union iodefine_reg32_t CFDF112; /* CFDF112 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID13; /* CFID13 */ + union iodefine_reg32_t CFPTR13; /* CFPTR13 */ + union iodefine_reg32_t CFDF013; /* CFDF013 */ + union iodefine_reg32_t CFDF113; /* CFDF113 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + +/* start of struct st_rscan_from_rscan0cfidm */ + union iodefine_reg32_t CFID14; /* CFID14 */ + union iodefine_reg32_t CFPTR14; /* CFPTR14 */ + union iodefine_reg32_t CFDF014; /* CFDF014 */ + union iodefine_reg32_t CFDF114; /* CFDF114 */ + +/* end of struct st_rscan_from_rscan0cfidm */ + + volatile uint8_t dummy180[144]; /* */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID0; /* TMID0 */ + union iodefine_reg32_t TMPTR0; /* TMPTR0 */ + union iodefine_reg32_t TMDF00; /* TMDF00 */ + union iodefine_reg32_t TMDF10; /* TMDF10 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID1; /* TMID1 */ + union iodefine_reg32_t TMPTR1; /* TMPTR1 */ + union iodefine_reg32_t TMDF01; /* TMDF01 */ + union iodefine_reg32_t TMDF11; /* TMDF11 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID2; /* TMID2 */ + union iodefine_reg32_t TMPTR2; /* TMPTR2 */ + union iodefine_reg32_t TMDF02; /* TMDF02 */ + union iodefine_reg32_t TMDF12; /* TMDF12 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID3; /* TMID3 */ + union iodefine_reg32_t TMPTR3; /* TMPTR3 */ + union iodefine_reg32_t TMDF03; /* TMDF03 */ + union iodefine_reg32_t TMDF13; /* TMDF13 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID4; /* TMID4 */ + union iodefine_reg32_t TMPTR4; /* TMPTR4 */ + union iodefine_reg32_t TMDF04; /* TMDF04 */ + union iodefine_reg32_t TMDF14; /* TMDF14 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID5; /* TMID5 */ + union iodefine_reg32_t TMPTR5; /* TMPTR5 */ + union iodefine_reg32_t TMDF05; /* TMDF05 */ + union iodefine_reg32_t TMDF15; /* TMDF15 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID6; /* TMID6 */ + union iodefine_reg32_t TMPTR6; /* TMPTR6 */ + union iodefine_reg32_t TMDF06; /* TMDF06 */ + union iodefine_reg32_t TMDF16; /* TMDF16 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID7; /* TMID7 */ + union iodefine_reg32_t TMPTR7; /* TMPTR7 */ + union iodefine_reg32_t TMDF07; /* TMDF07 */ + union iodefine_reg32_t TMDF17; /* TMDF17 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID8; /* TMID8 */ + union iodefine_reg32_t TMPTR8; /* TMPTR8 */ + union iodefine_reg32_t TMDF08; /* TMDF08 */ + union iodefine_reg32_t TMDF18; /* TMDF18 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID9; /* TMID9 */ + union iodefine_reg32_t TMPTR9; /* TMPTR9 */ + union iodefine_reg32_t TMDF09; /* TMDF09 */ + union iodefine_reg32_t TMDF19; /* TMDF19 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID10; /* TMID10 */ + union iodefine_reg32_t TMPTR10; /* TMPTR10 */ + union iodefine_reg32_t TMDF010; /* TMDF010 */ + union iodefine_reg32_t TMDF110; /* TMDF110 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID11; /* TMID11 */ + union iodefine_reg32_t TMPTR11; /* TMPTR11 */ + union iodefine_reg32_t TMDF011; /* TMDF011 */ + union iodefine_reg32_t TMDF111; /* TMDF111 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID12; /* TMID12 */ + union iodefine_reg32_t TMPTR12; /* TMPTR12 */ + union iodefine_reg32_t TMDF012; /* TMDF012 */ + union iodefine_reg32_t TMDF112; /* TMDF112 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID13; /* TMID13 */ + union iodefine_reg32_t TMPTR13; /* TMPTR13 */ + union iodefine_reg32_t TMDF013; /* TMDF013 */ + union iodefine_reg32_t TMDF113; /* TMDF113 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID14; /* TMID14 */ + union iodefine_reg32_t TMPTR14; /* TMPTR14 */ + union iodefine_reg32_t TMDF014; /* TMDF014 */ + union iodefine_reg32_t TMDF114; /* TMDF114 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID15; /* TMID15 */ + union iodefine_reg32_t TMPTR15; /* TMPTR15 */ + union iodefine_reg32_t TMDF015; /* TMDF015 */ + union iodefine_reg32_t TMDF115; /* TMDF115 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID16; /* TMID16 */ + union iodefine_reg32_t TMPTR16; /* TMPTR16 */ + union iodefine_reg32_t TMDF016; /* TMDF016 */ + union iodefine_reg32_t TMDF116; /* TMDF116 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID17; /* TMID17 */ + union iodefine_reg32_t TMPTR17; /* TMPTR17 */ + union iodefine_reg32_t TMDF017; /* TMDF017 */ + union iodefine_reg32_t TMDF117; /* TMDF117 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID18; /* TMID18 */ + union iodefine_reg32_t TMPTR18; /* TMPTR18 */ + union iodefine_reg32_t TMDF018; /* TMDF018 */ + union iodefine_reg32_t TMDF118; /* TMDF118 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID19; /* TMID19 */ + union iodefine_reg32_t TMPTR19; /* TMPTR19 */ + union iodefine_reg32_t TMDF019; /* TMDF019 */ + union iodefine_reg32_t TMDF119; /* TMDF119 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID20; /* TMID20 */ + union iodefine_reg32_t TMPTR20; /* TMPTR20 */ + union iodefine_reg32_t TMDF020; /* TMDF020 */ + union iodefine_reg32_t TMDF120; /* TMDF120 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID21; /* TMID21 */ + union iodefine_reg32_t TMPTR21; /* TMPTR21 */ + union iodefine_reg32_t TMDF021; /* TMDF021 */ + union iodefine_reg32_t TMDF121; /* TMDF121 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID22; /* TMID22 */ + union iodefine_reg32_t TMPTR22; /* TMPTR22 */ + union iodefine_reg32_t TMDF022; /* TMDF022 */ + union iodefine_reg32_t TMDF122; /* TMDF122 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID23; /* TMID23 */ + union iodefine_reg32_t TMPTR23; /* TMPTR23 */ + union iodefine_reg32_t TMDF023; /* TMDF023 */ + union iodefine_reg32_t TMDF123; /* TMDF123 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID24; /* TMID24 */ + union iodefine_reg32_t TMPTR24; /* TMPTR24 */ + union iodefine_reg32_t TMDF024; /* TMDF024 */ + union iodefine_reg32_t TMDF124; /* TMDF124 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID25; /* TMID25 */ + union iodefine_reg32_t TMPTR25; /* TMPTR25 */ + union iodefine_reg32_t TMDF025; /* TMDF025 */ + union iodefine_reg32_t TMDF125; /* TMDF125 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID26; /* TMID26 */ + union iodefine_reg32_t TMPTR26; /* TMPTR26 */ + union iodefine_reg32_t TMDF026; /* TMDF026 */ + union iodefine_reg32_t TMDF126; /* TMDF126 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID27; /* TMID27 */ + union iodefine_reg32_t TMPTR27; /* TMPTR27 */ + union iodefine_reg32_t TMDF027; /* TMDF027 */ + union iodefine_reg32_t TMDF127; /* TMDF127 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID28; /* TMID28 */ + union iodefine_reg32_t TMPTR28; /* TMPTR28 */ + union iodefine_reg32_t TMDF028; /* TMDF028 */ + union iodefine_reg32_t TMDF128; /* TMDF128 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID29; /* TMID29 */ + union iodefine_reg32_t TMPTR29; /* TMPTR29 */ + union iodefine_reg32_t TMDF029; /* TMDF029 */ + union iodefine_reg32_t TMDF129; /* TMDF129 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID30; /* TMID30 */ + union iodefine_reg32_t TMPTR30; /* TMPTR30 */ + union iodefine_reg32_t TMDF030; /* TMDF030 */ + union iodefine_reg32_t TMDF130; /* TMDF130 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID31; /* TMID31 */ + union iodefine_reg32_t TMPTR31; /* TMPTR31 */ + union iodefine_reg32_t TMDF031; /* TMDF031 */ + union iodefine_reg32_t TMDF131; /* TMDF131 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID32; /* TMID32 */ + union iodefine_reg32_t TMPTR32; /* TMPTR32 */ + union iodefine_reg32_t TMDF032; /* TMDF032 */ + union iodefine_reg32_t TMDF132; /* TMDF132 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID33; /* TMID33 */ + union iodefine_reg32_t TMPTR33; /* TMPTR33 */ + union iodefine_reg32_t TMDF033; /* TMDF033 */ + union iodefine_reg32_t TMDF133; /* TMDF133 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID34; /* TMID34 */ + union iodefine_reg32_t TMPTR34; /* TMPTR34 */ + union iodefine_reg32_t TMDF034; /* TMDF034 */ + union iodefine_reg32_t TMDF134; /* TMDF134 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID35; /* TMID35 */ + union iodefine_reg32_t TMPTR35; /* TMPTR35 */ + union iodefine_reg32_t TMDF035; /* TMDF035 */ + union iodefine_reg32_t TMDF135; /* TMDF135 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID36; /* TMID36 */ + union iodefine_reg32_t TMPTR36; /* TMPTR36 */ + union iodefine_reg32_t TMDF036; /* TMDF036 */ + union iodefine_reg32_t TMDF136; /* TMDF136 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID37; /* TMID37 */ + union iodefine_reg32_t TMPTR37; /* TMPTR37 */ + union iodefine_reg32_t TMDF037; /* TMDF037 */ + union iodefine_reg32_t TMDF137; /* TMDF137 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID38; /* TMID38 */ + union iodefine_reg32_t TMPTR38; /* TMPTR38 */ + union iodefine_reg32_t TMDF038; /* TMDF038 */ + union iodefine_reg32_t TMDF138; /* TMDF138 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID39; /* TMID39 */ + union iodefine_reg32_t TMPTR39; /* TMPTR39 */ + union iodefine_reg32_t TMDF039; /* TMDF039 */ + union iodefine_reg32_t TMDF139; /* TMDF139 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID40; /* TMID40 */ + union iodefine_reg32_t TMPTR40; /* TMPTR40 */ + union iodefine_reg32_t TMDF040; /* TMDF040 */ + union iodefine_reg32_t TMDF140; /* TMDF140 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID41; /* TMID41 */ + union iodefine_reg32_t TMPTR41; /* TMPTR41 */ + union iodefine_reg32_t TMDF041; /* TMDF041 */ + union iodefine_reg32_t TMDF141; /* TMDF141 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID42; /* TMID42 */ + union iodefine_reg32_t TMPTR42; /* TMPTR42 */ + union iodefine_reg32_t TMDF042; /* TMDF042 */ + union iodefine_reg32_t TMDF142; /* TMDF142 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID43; /* TMID43 */ + union iodefine_reg32_t TMPTR43; /* TMPTR43 */ + union iodefine_reg32_t TMDF043; /* TMDF043 */ + union iodefine_reg32_t TMDF143; /* TMDF143 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID44; /* TMID44 */ + union iodefine_reg32_t TMPTR44; /* TMPTR44 */ + union iodefine_reg32_t TMDF044; /* TMDF044 */ + union iodefine_reg32_t TMDF144; /* TMDF144 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID45; /* TMID45 */ + union iodefine_reg32_t TMPTR45; /* TMPTR45 */ + union iodefine_reg32_t TMDF045; /* TMDF045 */ + union iodefine_reg32_t TMDF145; /* TMDF145 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID46; /* TMID46 */ + union iodefine_reg32_t TMPTR46; /* TMPTR46 */ + union iodefine_reg32_t TMDF046; /* TMDF046 */ + union iodefine_reg32_t TMDF146; /* TMDF146 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID47; /* TMID47 */ + union iodefine_reg32_t TMPTR47; /* TMPTR47 */ + union iodefine_reg32_t TMDF047; /* TMDF047 */ + union iodefine_reg32_t TMDF147; /* TMDF147 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID48; /* TMID48 */ + union iodefine_reg32_t TMPTR48; /* TMPTR48 */ + union iodefine_reg32_t TMDF048; /* TMDF048 */ + union iodefine_reg32_t TMDF148; /* TMDF148 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID49; /* TMID49 */ + union iodefine_reg32_t TMPTR49; /* TMPTR49 */ + union iodefine_reg32_t TMDF049; /* TMDF049 */ + union iodefine_reg32_t TMDF149; /* TMDF149 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID50; /* TMID50 */ + union iodefine_reg32_t TMPTR50; /* TMPTR50 */ + union iodefine_reg32_t TMDF050; /* TMDF050 */ + union iodefine_reg32_t TMDF150; /* TMDF150 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID51; /* TMID51 */ + union iodefine_reg32_t TMPTR51; /* TMPTR51 */ + union iodefine_reg32_t TMDF051; /* TMDF051 */ + union iodefine_reg32_t TMDF151; /* TMDF151 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID52; /* TMID52 */ + union iodefine_reg32_t TMPTR52; /* TMPTR52 */ + union iodefine_reg32_t TMDF052; /* TMDF052 */ + union iodefine_reg32_t TMDF152; /* TMDF152 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID53; /* TMID53 */ + union iodefine_reg32_t TMPTR53; /* TMPTR53 */ + union iodefine_reg32_t TMDF053; /* TMDF053 */ + union iodefine_reg32_t TMDF153; /* TMDF153 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID54; /* TMID54 */ + union iodefine_reg32_t TMPTR54; /* TMPTR54 */ + union iodefine_reg32_t TMDF054; /* TMDF054 */ + union iodefine_reg32_t TMDF154; /* TMDF154 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID55; /* TMID55 */ + union iodefine_reg32_t TMPTR55; /* TMPTR55 */ + union iodefine_reg32_t TMDF055; /* TMDF055 */ + union iodefine_reg32_t TMDF155; /* TMDF155 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID56; /* TMID56 */ + union iodefine_reg32_t TMPTR56; /* TMPTR56 */ + union iodefine_reg32_t TMDF056; /* TMDF056 */ + union iodefine_reg32_t TMDF156; /* TMDF156 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID57; /* TMID57 */ + union iodefine_reg32_t TMPTR57; /* TMPTR57 */ + union iodefine_reg32_t TMDF057; /* TMDF057 */ + union iodefine_reg32_t TMDF157; /* TMDF157 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID58; /* TMID58 */ + union iodefine_reg32_t TMPTR58; /* TMPTR58 */ + union iodefine_reg32_t TMDF058; /* TMDF058 */ + union iodefine_reg32_t TMDF158; /* TMDF158 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID59; /* TMID59 */ + union iodefine_reg32_t TMPTR59; /* TMPTR59 */ + union iodefine_reg32_t TMDF059; /* TMDF059 */ + union iodefine_reg32_t TMDF159; /* TMDF159 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID60; /* TMID60 */ + union iodefine_reg32_t TMPTR60; /* TMPTR60 */ + union iodefine_reg32_t TMDF060; /* TMDF060 */ + union iodefine_reg32_t TMDF160; /* TMDF160 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID61; /* TMID61 */ + union iodefine_reg32_t TMPTR61; /* TMPTR61 */ + union iodefine_reg32_t TMDF061; /* TMDF061 */ + union iodefine_reg32_t TMDF161; /* TMDF161 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID62; /* TMID62 */ + union iodefine_reg32_t TMPTR62; /* TMPTR62 */ + union iodefine_reg32_t TMDF062; /* TMDF062 */ + union iodefine_reg32_t TMDF162; /* TMDF162 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID63; /* TMID63 */ + union iodefine_reg32_t TMPTR63; /* TMPTR63 */ + union iodefine_reg32_t TMDF063; /* TMDF063 */ + union iodefine_reg32_t TMDF163; /* TMDF163 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID64; /* TMID64 */ + union iodefine_reg32_t TMPTR64; /* TMPTR64 */ + union iodefine_reg32_t TMDF064; /* TMDF064 */ + union iodefine_reg32_t TMDF164; /* TMDF164 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID65; /* TMID65 */ + union iodefine_reg32_t TMPTR65; /* TMPTR65 */ + union iodefine_reg32_t TMDF065; /* TMDF065 */ + union iodefine_reg32_t TMDF165; /* TMDF165 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID66; /* TMID66 */ + union iodefine_reg32_t TMPTR66; /* TMPTR66 */ + union iodefine_reg32_t TMDF066; /* TMDF066 */ + union iodefine_reg32_t TMDF166; /* TMDF166 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID67; /* TMID67 */ + union iodefine_reg32_t TMPTR67; /* TMPTR67 */ + union iodefine_reg32_t TMDF067; /* TMDF067 */ + union iodefine_reg32_t TMDF167; /* TMDF167 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID68; /* TMID68 */ + union iodefine_reg32_t TMPTR68; /* TMPTR68 */ + union iodefine_reg32_t TMDF068; /* TMDF068 */ + union iodefine_reg32_t TMDF168; /* TMDF168 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID69; /* TMID69 */ + union iodefine_reg32_t TMPTR69; /* TMPTR69 */ + union iodefine_reg32_t TMDF069; /* TMDF069 */ + union iodefine_reg32_t TMDF169; /* TMDF169 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID70; /* TMID70 */ + union iodefine_reg32_t TMPTR70; /* TMPTR70 */ + union iodefine_reg32_t TMDF070; /* TMDF070 */ + union iodefine_reg32_t TMDF170; /* TMDF170 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID71; /* TMID71 */ + union iodefine_reg32_t TMPTR71; /* TMPTR71 */ + union iodefine_reg32_t TMDF071; /* TMDF071 */ + union iodefine_reg32_t TMDF171; /* TMDF171 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID72; /* TMID72 */ + union iodefine_reg32_t TMPTR72; /* TMPTR72 */ + union iodefine_reg32_t TMDF072; /* TMDF072 */ + union iodefine_reg32_t TMDF172; /* TMDF172 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID73; /* TMID73 */ + union iodefine_reg32_t TMPTR73; /* TMPTR73 */ + union iodefine_reg32_t TMDF073; /* TMDF073 */ + union iodefine_reg32_t TMDF173; /* TMDF173 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID74; /* TMID74 */ + union iodefine_reg32_t TMPTR74; /* TMPTR74 */ + union iodefine_reg32_t TMDF074; /* TMDF074 */ + union iodefine_reg32_t TMDF174; /* TMDF174 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID75; /* TMID75 */ + union iodefine_reg32_t TMPTR75; /* TMPTR75 */ + union iodefine_reg32_t TMDF075; /* TMDF075 */ + union iodefine_reg32_t TMDF175; /* TMDF175 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID76; /* TMID76 */ + union iodefine_reg32_t TMPTR76; /* TMPTR76 */ + union iodefine_reg32_t TMDF076; /* TMDF076 */ + union iodefine_reg32_t TMDF176; /* TMDF176 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID77; /* TMID77 */ + union iodefine_reg32_t TMPTR77; /* TMPTR77 */ + union iodefine_reg32_t TMDF077; /* TMDF077 */ + union iodefine_reg32_t TMDF177; /* TMDF177 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID78; /* TMID78 */ + union iodefine_reg32_t TMPTR78; /* TMPTR78 */ + union iodefine_reg32_t TMDF078; /* TMDF078 */ + union iodefine_reg32_t TMDF178; /* TMDF178 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + +/* start of struct st_rscan_from_rscan0tmidp */ + union iodefine_reg32_t TMID79; /* TMID79 */ + union iodefine_reg32_t TMPTR79; /* TMPTR79 */ + union iodefine_reg32_t TMDF079; /* TMDF079 */ + union iodefine_reg32_t TMDF179; /* TMDF179 */ + +/* end of struct st_rscan_from_rscan0tmidp */ + + volatile uint8_t dummy181[768]; /* */ + +/* #define RSCAN0_THLACC0_COUNT (5) */ + union iodefine_reg32_t THLACC0; /* THLACC0 */ + union iodefine_reg32_t THLACC1; /* THLACC1 */ + union iodefine_reg32_t THLACC2; /* THLACC2 */ + union iodefine_reg32_t THLACC3; /* THLACC3 */ + union iodefine_reg32_t THLACC4; /* THLACC4 */ + +} r_io_rscan0_t; + + +typedef struct st_rscan_from_rscan0cncfg +{ + + union iodefine_reg32_t CnCFG; /* CnCFG */ + union iodefine_reg32_t CnCTR; /* CnCTR */ + union iodefine_reg32_t CnSTS; /* CnSTS */ + union iodefine_reg32_t CnERFL; /* CnERFL */ +} r_io_rscan_from_rscan0cncfg_t; + + +typedef struct st_rscan_from_rscan0gaflidj +{ + + union iodefine_reg32_t GAFLIDj; /* GAFLIDj */ + union iodefine_reg32_t GAFLMj; /* GAFLMj */ + union iodefine_reg32_t GAFLP0j; /* GAFLP0j */ + union iodefine_reg32_t GAFLP1j; /* GAFLP1j */ +} r_io_rscan_from_rscan0gaflidj_t; + + +typedef struct st_rscan_from_rscan0rmidp +{ + + union iodefine_reg32_t RMIDp; /* RMIDp */ + union iodefine_reg32_t RMPTRp; /* RMPTRp */ + union iodefine_reg32_t RMDF0p; /* RMDF0p */ + union iodefine_reg32_t RMDF1p; /* RMDF1p */ +} r_io_rscan_from_rscan0rmidp_t; + + +typedef struct st_rscan_from_rscan0rfidm +{ + + union iodefine_reg32_t RFIDm; /* RFIDm */ + union iodefine_reg32_t RFPTRm; /* RFPTRm */ + union iodefine_reg32_t RFDF0m; /* RFDF0m */ + union iodefine_reg32_t RFDF1m; /* RFDF1m */ +} r_io_rscan_from_rscan0rfidm_t; + + +typedef struct st_rscan_from_rscan0tmidp +{ + + union iodefine_reg32_t TMIDp; /* TMIDp */ + union iodefine_reg32_t TMPTRp; /* TMPTRp */ + union iodefine_reg32_t TMDF0p; /* TMDF0p */ + union iodefine_reg32_t TMDF1p; /* TMDF1p */ +} r_io_rscan_from_rscan0tmidp_t; + + +typedef struct st_rscan_from_rscan0cfidm +{ + + union iodefine_reg32_t CFIDm; /* CFIDm */ + union iodefine_reg32_t CFPTRm; /* CFPTRm */ + union iodefine_reg32_t CFDF0m; /* CFDF0m */ + union iodefine_reg32_t CFDF1m; /* CFDF1m */ +} r_io_rscan_from_rscan0cfidm_t; + + +/* Channel array defines of RSCAN0 (2)*/ +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS +volatile struct st_rscan_from_rscan0cfidm* RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS +volatile struct st_rscan_from_rscan0tmidp* RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS +volatile struct st_rscan_from_rscan0rfidm* RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS +volatile struct st_rscan_from_rscan0rmidp* RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS +volatile struct st_rscan_from_rscan0gaflidj* RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */ + +#ifdef DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS +volatile struct st_rscan_from_rscan0cncfg* RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */ +/* End of channel array defines of RSCAN0 (2)*/ -#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32 -#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L] -#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL] -#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH] -#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H] -#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL] -#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH] -#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32 -#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L] -#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL] -#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH] -#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H] -#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL] -#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH] -#define RSCAN0C0STS RSCAN0.C0STS.UINT32 -#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L] -#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL] -#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH] -#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H] -#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL] -#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH] -#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32 -#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L] -#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL] -#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH] -#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H] -#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL] -#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH] -#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32 -#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L] -#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL] -#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH] -#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H] -#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL] -#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH] -#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32 -#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L] -#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL] -#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH] -#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H] -#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL] -#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH] -#define RSCAN0C1STS RSCAN0.C1STS.UINT32 -#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L] -#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL] -#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH] -#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H] -#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL] -#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH] -#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32 -#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L] -#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL] -#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH] -#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H] -#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL] -#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH] -#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32 -#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L] -#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL] -#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH] -#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H] -#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL] -#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH] -#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32 -#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L] -#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL] -#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH] -#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H] -#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL] -#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH] -#define RSCAN0C2STS RSCAN0.C2STS.UINT32 -#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L] -#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL] -#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH] -#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H] -#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL] -#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH] -#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32 -#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L] -#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL] -#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH] -#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H] -#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL] -#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH] -#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32 -#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L] -#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL] -#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH] -#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H] -#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL] -#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH] -#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32 -#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L] -#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL] -#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH] -#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H] -#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL] -#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH] -#define RSCAN0C3STS RSCAN0.C3STS.UINT32 -#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L] -#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL] -#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH] -#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H] -#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL] -#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH] -#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32 -#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L] -#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL] -#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH] -#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H] -#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL] -#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH] -#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32 -#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L] -#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL] -#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH] -#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H] -#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL] -#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH] -#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32 -#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L] -#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL] -#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH] -#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H] -#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL] -#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH] -#define RSCAN0C4STS RSCAN0.C4STS.UINT32 -#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L] -#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL] -#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH] -#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H] -#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL] -#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH] -#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32 -#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L] -#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL] -#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH] -#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H] -#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL] -#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH] -#define RSCAN0GCFG RSCAN0.GCFG.UINT32 -#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L] -#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL] -#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH] -#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H] -#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL] -#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH] -#define RSCAN0GCTR RSCAN0.GCTR.UINT32 -#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L] -#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL] -#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH] -#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H] -#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL] -#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH] -#define RSCAN0GSTS RSCAN0.GSTS.UINT32 -#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L] -#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL] -#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH] -#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H] -#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL] -#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH] -#define RSCAN0GERFL RSCAN0.GERFL.UINT32 -#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L] -#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL] -#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH] -#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H] -#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL] -#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH] -#define RSCAN0GTSC RSCAN0.GTSC.UINT32 -#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L] -#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H] -#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32 -#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L] -#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL] -#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH] -#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H] -#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL] -#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH] -#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32 -#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L] -#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL] -#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH] -#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H] -#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL] -#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH] -#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32 -#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L] -#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL] -#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH] -#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H] -#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL] -#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH] -#define RSCAN0RMNB RSCAN0.RMNB.UINT32 -#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L] -#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL] -#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH] -#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H] -#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL] -#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH] -#define RSCAN0RMND0 RSCAN0.RMND0.UINT32 -#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L] -#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL] -#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH] -#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H] -#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL] -#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH] -#define RSCAN0RMND1 RSCAN0.RMND1.UINT32 -#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L] -#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL] -#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH] -#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H] -#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL] -#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH] -#define RSCAN0RMND2 RSCAN0.RMND2.UINT32 -#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L] -#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL] -#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH] -#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H] -#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL] -#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH] -#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32 -#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L] -#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL] -#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH] -#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H] -#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL] -#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH] -#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32 -#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L] -#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL] -#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH] -#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H] -#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL] -#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH] -#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32 -#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L] -#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL] -#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH] -#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H] -#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL] -#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH] -#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32 -#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L] -#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL] -#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH] -#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H] -#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL] -#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH] -#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32 -#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L] -#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL] -#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH] -#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H] -#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL] -#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH] -#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32 -#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L] -#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL] -#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH] -#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H] -#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL] -#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH] -#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32 -#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L] -#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL] -#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH] -#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H] -#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL] -#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH] -#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32 -#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L] -#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL] -#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH] -#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H] -#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL] -#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH] -#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32 -#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L] -#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL] -#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH] -#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H] -#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL] -#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH] -#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32 -#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L] -#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL] -#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH] -#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H] -#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL] -#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH] -#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32 -#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L] -#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL] -#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH] -#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H] -#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL] -#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH] -#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32 -#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L] -#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL] -#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH] -#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H] -#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL] -#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH] -#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32 -#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L] -#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL] -#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH] -#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H] -#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL] -#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH] -#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32 -#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L] -#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL] -#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH] -#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H] -#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL] -#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH] -#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32 -#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L] -#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL] -#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH] -#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H] -#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL] -#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH] -#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32 -#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L] -#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL] -#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH] -#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H] -#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL] -#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH] -#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32 -#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L] -#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL] -#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH] -#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H] -#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL] -#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH] -#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32 -#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L] -#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL] -#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH] -#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H] -#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL] -#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH] -#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32 -#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L] -#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL] -#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH] -#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H] -#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL] -#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH] -#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32 -#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L] -#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL] -#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH] -#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H] -#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL] -#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH] -#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32 -#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L] -#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL] -#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH] -#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H] -#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL] -#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH] -#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32 -#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L] -#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL] -#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH] -#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H] -#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL] -#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH] -#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32 -#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L] -#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL] -#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH] -#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H] -#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL] -#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH] -#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32 -#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L] -#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL] -#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH] -#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H] -#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL] -#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH] -#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32 -#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L] -#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL] -#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH] -#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H] -#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL] -#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH] -#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32 -#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L] -#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL] -#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH] -#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H] -#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL] -#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH] -#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32 -#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L] -#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL] -#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH] -#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H] -#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL] -#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH] -#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32 -#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L] -#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL] -#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH] -#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H] -#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL] -#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH] -#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32 -#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L] -#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL] -#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH] -#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H] -#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL] -#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH] -#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32 -#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L] -#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL] -#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH] -#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H] -#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL] -#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH] -#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32 -#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L] -#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL] -#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH] -#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H] -#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL] -#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH] -#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32 -#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L] -#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL] -#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH] -#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H] -#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL] -#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH] -#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32 -#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L] -#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL] -#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH] -#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H] -#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL] -#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH] -#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32 -#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L] -#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL] -#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH] -#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H] -#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL] -#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH] -#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32 -#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L] -#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL] -#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH] -#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H] -#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL] -#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH] -#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32 -#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L] -#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL] -#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH] -#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H] -#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL] -#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH] -#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32 -#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L] -#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL] -#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH] -#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H] -#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL] -#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH] -#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32 -#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L] -#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL] -#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH] -#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H] -#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL] -#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH] -#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32 -#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L] -#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL] -#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH] -#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H] -#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL] -#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH] -#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32 -#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L] -#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL] -#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH] -#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H] -#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL] -#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH] -#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32 -#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L] -#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL] -#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH] -#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H] -#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL] -#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH] -#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32 -#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L] -#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL] -#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH] -#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H] -#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL] -#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH] -#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32 -#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L] -#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL] -#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH] -#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H] -#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL] -#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH] -#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32 -#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L] -#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL] -#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH] -#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H] -#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL] -#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH] -#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32 -#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L] -#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL] -#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH] -#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H] -#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL] -#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH] -#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32 -#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L] -#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL] -#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH] -#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H] -#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL] -#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH] -#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32 -#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L] -#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL] -#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH] -#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H] -#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL] -#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH] -#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32 -#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L] -#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL] -#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH] -#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H] -#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL] -#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH] -#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32 -#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L] -#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL] -#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH] -#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H] -#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL] -#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH] -#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32 -#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L] -#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL] -#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH] -#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H] -#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL] -#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH] -#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32 -#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L] -#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL] -#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH] -#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H] -#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL] -#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH] -#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32 -#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L] -#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL] -#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH] -#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H] -#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL] -#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH] -#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32 -#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L] -#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL] -#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH] -#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H] -#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL] -#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH] -#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32 -#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L] -#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL] -#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH] -#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H] -#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL] -#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH] -#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32 -#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L] -#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL] -#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH] -#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H] -#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL] -#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH] -#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32 -#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L] -#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL] -#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH] -#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H] -#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL] -#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH] -#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32 -#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L] -#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL] -#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH] -#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H] -#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL] -#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH] -#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32 -#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L] -#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL] -#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH] -#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H] -#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL] -#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH] -#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32 -#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L] -#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL] -#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH] -#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H] -#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL] -#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH] -#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32 -#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L] -#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL] -#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH] -#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H] -#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL] -#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH] -#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32 -#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L] -#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL] -#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH] -#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H] -#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL] -#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH] -#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32 -#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L] -#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL] -#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH] -#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H] -#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL] -#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH] -#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32 -#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L] -#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL] -#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH] -#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H] -#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL] -#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH] -#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32 -#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L] -#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL] -#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH] -#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H] -#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL] -#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH] -#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32 -#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L] -#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL] -#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH] -#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H] -#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL] -#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH] -#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32 -#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L] -#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL] -#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH] -#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H] -#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL] -#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH] -#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32 -#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L] -#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL] -#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH] -#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H] -#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL] -#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH] -#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32 -#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L] -#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL] -#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH] -#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H] -#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL] -#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH] -#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32 -#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L] -#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL] -#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH] -#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H] -#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL] -#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH] -#define RSCAN0FESTS RSCAN0.FESTS.UINT32 -#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L] -#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL] -#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH] -#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H] -#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL] -#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH] -#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32 -#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L] -#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL] -#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH] -#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H] -#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL] -#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH] -#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32 -#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L] -#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL] -#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH] -#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H] -#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL] -#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH] -#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32 -#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L] -#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL] -#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH] -#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H] -#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL] -#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH] -#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32 -#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L] -#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL] -#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH] -#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H] -#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL] -#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH] -#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32 -#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L] -#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL] -#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH] -#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H] -#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL] -#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH] -#define RSCAN0TMC0 RSCAN0.TMC0 -#define RSCAN0TMC1 RSCAN0.TMC1 -#define RSCAN0TMC2 RSCAN0.TMC2 -#define RSCAN0TMC3 RSCAN0.TMC3 -#define RSCAN0TMC4 RSCAN0.TMC4 -#define RSCAN0TMC5 RSCAN0.TMC5 -#define RSCAN0TMC6 RSCAN0.TMC6 -#define RSCAN0TMC7 RSCAN0.TMC7 -#define RSCAN0TMC8 RSCAN0.TMC8 -#define RSCAN0TMC9 RSCAN0.TMC9 -#define RSCAN0TMC10 RSCAN0.TMC10 -#define RSCAN0TMC11 RSCAN0.TMC11 -#define RSCAN0TMC12 RSCAN0.TMC12 -#define RSCAN0TMC13 RSCAN0.TMC13 -#define RSCAN0TMC14 RSCAN0.TMC14 -#define RSCAN0TMC15 RSCAN0.TMC15 -#define RSCAN0TMC16 RSCAN0.TMC16 -#define RSCAN0TMC17 RSCAN0.TMC17 -#define RSCAN0TMC18 RSCAN0.TMC18 -#define RSCAN0TMC19 RSCAN0.TMC19 -#define RSCAN0TMC20 RSCAN0.TMC20 -#define RSCAN0TMC21 RSCAN0.TMC21 -#define RSCAN0TMC22 RSCAN0.TMC22 -#define RSCAN0TMC23 RSCAN0.TMC23 -#define RSCAN0TMC24 RSCAN0.TMC24 -#define RSCAN0TMC25 RSCAN0.TMC25 -#define RSCAN0TMC26 RSCAN0.TMC26 -#define RSCAN0TMC27 RSCAN0.TMC27 -#define RSCAN0TMC28 RSCAN0.TMC28 -#define RSCAN0TMC29 RSCAN0.TMC29 -#define RSCAN0TMC30 RSCAN0.TMC30 -#define RSCAN0TMC31 RSCAN0.TMC31 -#define RSCAN0TMC32 RSCAN0.TMC32 -#define RSCAN0TMC33 RSCAN0.TMC33 -#define RSCAN0TMC34 RSCAN0.TMC34 -#define RSCAN0TMC35 RSCAN0.TMC35 -#define RSCAN0TMC36 RSCAN0.TMC36 -#define RSCAN0TMC37 RSCAN0.TMC37 -#define RSCAN0TMC38 RSCAN0.TMC38 -#define RSCAN0TMC39 RSCAN0.TMC39 -#define RSCAN0TMC40 RSCAN0.TMC40 -#define RSCAN0TMC41 RSCAN0.TMC41 -#define RSCAN0TMC42 RSCAN0.TMC42 -#define RSCAN0TMC43 RSCAN0.TMC43 -#define RSCAN0TMC44 RSCAN0.TMC44 -#define RSCAN0TMC45 RSCAN0.TMC45 -#define RSCAN0TMC46 RSCAN0.TMC46 -#define RSCAN0TMC47 RSCAN0.TMC47 -#define RSCAN0TMC48 RSCAN0.TMC48 -#define RSCAN0TMC49 RSCAN0.TMC49 -#define RSCAN0TMC50 RSCAN0.TMC50 -#define RSCAN0TMC51 RSCAN0.TMC51 -#define RSCAN0TMC52 RSCAN0.TMC52 -#define RSCAN0TMC53 RSCAN0.TMC53 -#define RSCAN0TMC54 RSCAN0.TMC54 -#define RSCAN0TMC55 RSCAN0.TMC55 -#define RSCAN0TMC56 RSCAN0.TMC56 -#define RSCAN0TMC57 RSCAN0.TMC57 -#define RSCAN0TMC58 RSCAN0.TMC58 -#define RSCAN0TMC59 RSCAN0.TMC59 -#define RSCAN0TMC60 RSCAN0.TMC60 -#define RSCAN0TMC61 RSCAN0.TMC61 -#define RSCAN0TMC62 RSCAN0.TMC62 -#define RSCAN0TMC63 RSCAN0.TMC63 -#define RSCAN0TMC64 RSCAN0.TMC64 -#define RSCAN0TMC65 RSCAN0.TMC65 -#define RSCAN0TMC66 RSCAN0.TMC66 -#define RSCAN0TMC67 RSCAN0.TMC67 -#define RSCAN0TMC68 RSCAN0.TMC68 -#define RSCAN0TMC69 RSCAN0.TMC69 -#define RSCAN0TMC70 RSCAN0.TMC70 -#define RSCAN0TMC71 RSCAN0.TMC71 -#define RSCAN0TMC72 RSCAN0.TMC72 -#define RSCAN0TMC73 RSCAN0.TMC73 -#define RSCAN0TMC74 RSCAN0.TMC74 -#define RSCAN0TMC75 RSCAN0.TMC75 -#define RSCAN0TMC76 RSCAN0.TMC76 -#define RSCAN0TMC77 RSCAN0.TMC77 -#define RSCAN0TMC78 RSCAN0.TMC78 -#define RSCAN0TMC79 RSCAN0.TMC79 -#define RSCAN0TMSTS0 RSCAN0.TMSTS0 -#define RSCAN0TMSTS1 RSCAN0.TMSTS1 -#define RSCAN0TMSTS2 RSCAN0.TMSTS2 -#define RSCAN0TMSTS3 RSCAN0.TMSTS3 -#define RSCAN0TMSTS4 RSCAN0.TMSTS4 -#define RSCAN0TMSTS5 RSCAN0.TMSTS5 -#define RSCAN0TMSTS6 RSCAN0.TMSTS6 -#define RSCAN0TMSTS7 RSCAN0.TMSTS7 -#define RSCAN0TMSTS8 RSCAN0.TMSTS8 -#define RSCAN0TMSTS9 RSCAN0.TMSTS9 -#define RSCAN0TMSTS10 RSCAN0.TMSTS10 -#define RSCAN0TMSTS11 RSCAN0.TMSTS11 -#define RSCAN0TMSTS12 RSCAN0.TMSTS12 -#define RSCAN0TMSTS13 RSCAN0.TMSTS13 -#define RSCAN0TMSTS14 RSCAN0.TMSTS14 -#define RSCAN0TMSTS15 RSCAN0.TMSTS15 -#define RSCAN0TMSTS16 RSCAN0.TMSTS16 -#define RSCAN0TMSTS17 RSCAN0.TMSTS17 -#define RSCAN0TMSTS18 RSCAN0.TMSTS18 -#define RSCAN0TMSTS19 RSCAN0.TMSTS19 -#define RSCAN0TMSTS20 RSCAN0.TMSTS20 -#define RSCAN0TMSTS21 RSCAN0.TMSTS21 -#define RSCAN0TMSTS22 RSCAN0.TMSTS22 -#define RSCAN0TMSTS23 RSCAN0.TMSTS23 -#define RSCAN0TMSTS24 RSCAN0.TMSTS24 -#define RSCAN0TMSTS25 RSCAN0.TMSTS25 -#define RSCAN0TMSTS26 RSCAN0.TMSTS26 -#define RSCAN0TMSTS27 RSCAN0.TMSTS27 -#define RSCAN0TMSTS28 RSCAN0.TMSTS28 -#define RSCAN0TMSTS29 RSCAN0.TMSTS29 -#define RSCAN0TMSTS30 RSCAN0.TMSTS30 -#define RSCAN0TMSTS31 RSCAN0.TMSTS31 -#define RSCAN0TMSTS32 RSCAN0.TMSTS32 -#define RSCAN0TMSTS33 RSCAN0.TMSTS33 -#define RSCAN0TMSTS34 RSCAN0.TMSTS34 -#define RSCAN0TMSTS35 RSCAN0.TMSTS35 -#define RSCAN0TMSTS36 RSCAN0.TMSTS36 -#define RSCAN0TMSTS37 RSCAN0.TMSTS37 -#define RSCAN0TMSTS38 RSCAN0.TMSTS38 -#define RSCAN0TMSTS39 RSCAN0.TMSTS39 -#define RSCAN0TMSTS40 RSCAN0.TMSTS40 -#define RSCAN0TMSTS41 RSCAN0.TMSTS41 -#define RSCAN0TMSTS42 RSCAN0.TMSTS42 -#define RSCAN0TMSTS43 RSCAN0.TMSTS43 -#define RSCAN0TMSTS44 RSCAN0.TMSTS44 -#define RSCAN0TMSTS45 RSCAN0.TMSTS45 -#define RSCAN0TMSTS46 RSCAN0.TMSTS46 -#define RSCAN0TMSTS47 RSCAN0.TMSTS47 -#define RSCAN0TMSTS48 RSCAN0.TMSTS48 -#define RSCAN0TMSTS49 RSCAN0.TMSTS49 -#define RSCAN0TMSTS50 RSCAN0.TMSTS50 -#define RSCAN0TMSTS51 RSCAN0.TMSTS51 -#define RSCAN0TMSTS52 RSCAN0.TMSTS52 -#define RSCAN0TMSTS53 RSCAN0.TMSTS53 -#define RSCAN0TMSTS54 RSCAN0.TMSTS54 -#define RSCAN0TMSTS55 RSCAN0.TMSTS55 -#define RSCAN0TMSTS56 RSCAN0.TMSTS56 -#define RSCAN0TMSTS57 RSCAN0.TMSTS57 -#define RSCAN0TMSTS58 RSCAN0.TMSTS58 -#define RSCAN0TMSTS59 RSCAN0.TMSTS59 -#define RSCAN0TMSTS60 RSCAN0.TMSTS60 -#define RSCAN0TMSTS61 RSCAN0.TMSTS61 -#define RSCAN0TMSTS62 RSCAN0.TMSTS62 -#define RSCAN0TMSTS63 RSCAN0.TMSTS63 -#define RSCAN0TMSTS64 RSCAN0.TMSTS64 -#define RSCAN0TMSTS65 RSCAN0.TMSTS65 -#define RSCAN0TMSTS66 RSCAN0.TMSTS66 -#define RSCAN0TMSTS67 RSCAN0.TMSTS67 -#define RSCAN0TMSTS68 RSCAN0.TMSTS68 -#define RSCAN0TMSTS69 RSCAN0.TMSTS69 -#define RSCAN0TMSTS70 RSCAN0.TMSTS70 -#define RSCAN0TMSTS71 RSCAN0.TMSTS71 -#define RSCAN0TMSTS72 RSCAN0.TMSTS72 -#define RSCAN0TMSTS73 RSCAN0.TMSTS73 -#define RSCAN0TMSTS74 RSCAN0.TMSTS74 -#define RSCAN0TMSTS75 RSCAN0.TMSTS75 -#define RSCAN0TMSTS76 RSCAN0.TMSTS76 -#define RSCAN0TMSTS77 RSCAN0.TMSTS77 -#define RSCAN0TMSTS78 RSCAN0.TMSTS78 -#define RSCAN0TMSTS79 RSCAN0.TMSTS79 -#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32 -#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L] -#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL] -#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH] -#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H] -#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL] -#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH] -#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32 -#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L] -#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL] -#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH] -#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H] -#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL] -#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH] -#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32 -#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L] -#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL] -#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH] -#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H] -#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL] -#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH] -#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32 -#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L] -#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL] -#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH] -#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H] -#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL] -#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH] -#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32 -#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L] -#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL] -#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH] -#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H] -#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL] -#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH] -#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32 -#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L] -#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL] -#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH] -#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H] -#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL] -#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH] -#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32 -#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L] -#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL] -#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH] -#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H] -#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL] -#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH] -#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32 -#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L] -#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL] -#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH] -#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H] -#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL] -#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH] -#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32 -#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L] -#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL] -#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH] -#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H] -#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL] -#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH] -#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32 -#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L] -#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL] -#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH] -#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H] -#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL] -#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH] -#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32 -#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L] -#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL] -#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH] -#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H] -#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL] -#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH] -#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32 -#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L] -#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL] -#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH] -#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H] -#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL] -#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH] -#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32 -#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L] -#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL] -#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH] -#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H] -#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL] -#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH] -#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32 -#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L] -#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL] -#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH] -#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H] -#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL] -#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH] -#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32 -#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L] -#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL] -#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH] -#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H] -#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL] -#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH] -#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32 -#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L] -#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL] -#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH] -#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H] -#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL] -#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH] -#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32 -#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L] -#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL] -#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH] -#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H] -#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL] -#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH] -#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32 -#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L] -#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL] -#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH] -#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H] -#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL] -#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH] -#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32 -#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L] -#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL] -#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH] -#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H] -#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL] -#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH] -#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32 -#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L] -#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL] -#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH] -#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H] -#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL] -#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH] -#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32 -#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L] -#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL] -#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH] -#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H] -#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL] -#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH] -#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32 -#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L] -#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL] -#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH] -#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H] -#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL] -#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH] -#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32 -#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L] -#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL] -#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH] -#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H] -#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL] -#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH] -#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32 -#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L] -#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL] -#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH] -#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H] -#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL] -#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH] -#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32 -#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L] -#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL] -#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH] -#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H] -#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL] -#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH] -#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32 -#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L] -#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL] -#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH] -#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H] -#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL] -#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH] -#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32 -#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L] -#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL] -#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH] -#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H] -#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL] -#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH] -#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32 -#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L] -#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL] -#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH] -#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H] -#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL] -#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH] -#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32 -#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L] -#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL] -#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH] -#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H] -#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL] -#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH] -#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32 -#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L] -#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL] -#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH] -#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H] -#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL] -#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH] -#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32 -#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L] -#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL] -#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH] -#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H] -#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL] -#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH] -#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32 -#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L] -#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL] -#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH] -#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H] -#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL] -#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH] -#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32 -#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L] -#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL] -#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH] -#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H] -#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL] -#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH] -#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32 -#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L] -#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL] -#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH] -#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H] -#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL] -#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH] -#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32 -#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L] -#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL] -#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH] -#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H] -#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL] -#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH] -#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32 -#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L] -#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL] -#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH] -#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H] -#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL] -#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH] -#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32 -#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L] -#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL] -#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH] -#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H] -#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL] -#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH] -#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32 -#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L] -#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL] -#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH] -#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H] -#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL] -#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH] -#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32 -#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L] -#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL] -#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH] -#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H] -#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL] -#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH] -#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32 -#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L] -#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL] -#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH] -#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H] -#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL] -#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH] -#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32 -#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L] -#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL] -#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH] -#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H] -#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL] -#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH] -#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32 -#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L] -#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL] -#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH] -#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H] -#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL] -#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH] -#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32 -#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L] -#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL] -#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH] -#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H] -#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL] -#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH] -#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32 -#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L] -#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL] -#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH] -#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H] -#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL] -#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH] -#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32 -#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L] -#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL] -#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH] -#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H] -#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL] -#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH] -#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32 -#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L] -#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL] -#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH] -#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H] -#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL] -#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH] -#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32 -#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L] -#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL] -#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH] -#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H] -#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL] -#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH] -#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32 -#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L] -#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL] -#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH] -#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H] -#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL] -#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH] -#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32 -#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L] -#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL] -#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH] -#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H] -#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL] -#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH] -#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32 -#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L] -#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H] -#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32 -#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L] -#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL] -#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH] -#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H] -#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL] -#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH] -#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32 -#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L] -#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL] -#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH] -#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H] -#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL] -#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH] -#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32 -#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L] -#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL] -#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH] -#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H] -#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL] -#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH] -#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32 -#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L] -#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL] -#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH] -#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H] -#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL] -#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH] -#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32 -#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L] -#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL] -#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH] -#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H] -#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL] -#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH] -#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32 -#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L] -#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL] -#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH] -#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H] -#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL] -#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH] -#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32 -#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L] -#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL] -#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH] -#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H] -#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL] -#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH] -#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32 -#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L] -#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL] -#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH] -#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H] -#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL] -#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH] -#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32 -#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L] -#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL] -#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH] -#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H] -#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL] -#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH] -#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32 -#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L] -#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL] -#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH] -#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H] -#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL] -#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH] -#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32 -#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L] -#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL] -#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH] -#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H] -#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL] -#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH] -#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32 -#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L] -#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL] -#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH] -#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H] -#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL] -#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH] -#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32 -#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L] -#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL] -#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH] -#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H] -#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL] -#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH] -#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32 -#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L] -#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL] -#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH] -#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H] -#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL] -#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH] -#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32 -#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L] -#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL] -#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH] -#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H] -#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL] -#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH] -#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32 -#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L] -#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL] -#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH] -#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H] -#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL] -#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH] -#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32 -#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L] -#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL] -#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH] -#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H] -#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL] -#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH] -#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32 -#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L] -#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL] -#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH] -#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H] -#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL] -#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH] -#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32 -#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L] -#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL] -#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH] -#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H] -#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL] -#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH] -#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32 -#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L] -#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL] -#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH] -#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H] -#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL] -#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH] -#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32 -#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L] -#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL] -#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH] -#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H] -#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL] -#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH] -#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32 -#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L] -#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL] -#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH] -#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H] -#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL] -#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH] -#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32 -#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L] -#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL] -#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH] -#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H] -#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL] -#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH] -#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32 -#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L] -#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL] -#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH] -#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H] -#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL] -#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH] -#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32 -#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L] -#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL] -#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH] -#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H] -#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL] -#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH] -#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32 -#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L] -#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL] -#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH] -#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H] -#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL] -#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH] -#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32 -#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L] -#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL] -#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH] -#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H] -#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL] -#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH] -#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32 -#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L] -#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL] -#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH] -#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H] -#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL] -#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH] -#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32 -#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L] -#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL] -#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH] -#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H] -#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL] -#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH] -#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32 -#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L] -#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL] -#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH] -#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H] -#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL] -#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH] -#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32 -#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L] -#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL] -#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH] -#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H] -#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL] -#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH] -#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32 -#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L] -#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL] -#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH] -#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H] -#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL] -#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH] -#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32 -#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L] -#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL] -#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH] -#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H] -#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL] -#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH] -#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32 -#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L] -#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL] -#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH] -#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H] -#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL] -#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH] -#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32 -#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L] -#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL] -#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH] -#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H] -#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL] -#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH] -#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32 -#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L] -#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL] -#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH] -#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H] -#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL] -#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH] -#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32 -#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L] -#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL] -#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH] -#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H] -#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL] -#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH] -#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32 -#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L] -#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL] -#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH] -#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H] -#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL] -#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH] -#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32 -#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L] -#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL] -#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH] -#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H] -#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL] -#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH] -#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32 -#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L] -#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL] -#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH] -#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H] -#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL] -#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH] -#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32 -#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L] -#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL] -#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH] -#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H] -#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL] -#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH] -#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32 -#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L] -#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL] -#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH] -#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H] -#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL] -#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH] -#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32 -#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L] -#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL] -#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH] -#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H] -#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL] -#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH] -#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32 -#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L] -#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL] -#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH] -#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H] -#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL] -#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH] -#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32 -#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L] -#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL] -#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH] -#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H] -#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL] -#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH] -#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32 -#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L] -#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL] -#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH] -#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H] -#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL] -#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH] -#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32 -#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L] -#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL] -#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH] -#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H] -#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL] -#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH] -#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32 -#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L] -#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL] -#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH] -#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H] -#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL] -#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH] -#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32 -#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L] -#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL] -#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH] -#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H] -#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL] -#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH] -#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32 -#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L] -#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL] -#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH] -#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H] -#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL] -#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH] -#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32 -#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L] -#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL] -#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH] -#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H] -#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL] -#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH] -#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32 -#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L] -#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL] -#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH] -#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H] -#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL] -#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH] -#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32 -#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L] -#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL] -#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH] -#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H] -#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL] -#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH] -#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32 -#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L] -#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL] -#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH] -#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H] -#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL] -#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH] -#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32 -#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L] -#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL] -#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH] -#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H] -#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL] -#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH] -#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32 -#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L] -#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL] -#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH] -#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H] -#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL] -#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH] -#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32 -#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L] -#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL] -#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH] -#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H] -#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL] -#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH] -#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32 -#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L] -#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL] -#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH] -#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H] -#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL] -#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH] -#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32 -#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L] -#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL] -#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH] -#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H] -#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL] -#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH] -#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32 -#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L] -#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL] -#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH] -#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H] -#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL] -#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH] -#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32 -#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L] -#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL] -#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH] -#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H] -#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL] -#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH] -#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32 -#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L] -#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL] -#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH] -#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H] -#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL] -#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH] -#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32 -#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L] -#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL] -#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH] -#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H] -#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL] -#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH] -#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32 -#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L] -#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL] -#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH] -#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H] -#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL] -#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH] -#define RSCAN0RMID0 RSCAN0.RMID0.UINT32 -#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L] -#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL] -#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH] -#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H] -#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL] -#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH] -#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32 -#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L] -#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL] -#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH] -#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H] -#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL] -#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH] -#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32 -#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L] -#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL] -#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH] -#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H] -#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL] -#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH] -#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32 -#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L] -#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL] -#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH] -#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H] -#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL] -#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH] -#define RSCAN0RMID1 RSCAN0.RMID1.UINT32 -#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L] -#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL] -#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH] -#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H] -#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL] -#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH] -#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32 -#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L] -#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL] -#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH] -#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H] -#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL] -#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH] -#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32 -#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L] -#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL] -#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH] -#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H] -#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL] -#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH] -#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32 -#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L] -#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL] -#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH] -#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H] -#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL] -#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH] -#define RSCAN0RMID2 RSCAN0.RMID2.UINT32 -#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L] -#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL] -#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH] -#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H] -#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL] -#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH] -#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32 -#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L] -#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL] -#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH] -#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H] -#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL] -#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH] -#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32 -#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L] -#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL] -#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH] -#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H] -#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL] -#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH] -#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32 -#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L] -#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL] -#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH] -#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H] -#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL] -#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH] -#define RSCAN0RMID3 RSCAN0.RMID3.UINT32 -#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L] -#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL] -#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH] -#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H] -#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL] -#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH] -#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32 -#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L] -#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL] -#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH] -#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H] -#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL] -#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH] -#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32 -#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L] -#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL] -#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH] -#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H] -#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL] -#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH] -#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32 -#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L] -#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL] -#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH] -#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H] -#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL] -#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH] -#define RSCAN0RMID4 RSCAN0.RMID4.UINT32 -#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L] -#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL] -#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH] -#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H] -#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL] -#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH] -#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32 -#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L] -#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL] -#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH] -#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H] -#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL] -#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH] -#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32 -#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L] -#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL] -#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH] -#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H] -#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL] -#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH] -#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32 -#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L] -#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL] -#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH] -#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H] -#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL] -#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH] -#define RSCAN0RMID5 RSCAN0.RMID5.UINT32 -#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L] -#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL] -#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH] -#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H] -#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL] -#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH] -#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32 -#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L] -#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL] -#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH] -#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H] -#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL] -#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH] -#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32 -#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L] -#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL] -#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH] -#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H] -#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL] -#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH] -#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32 -#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L] -#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL] -#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH] -#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H] -#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL] -#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH] -#define RSCAN0RMID6 RSCAN0.RMID6.UINT32 -#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L] -#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL] -#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH] -#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H] -#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL] -#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH] -#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32 -#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L] -#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL] -#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH] -#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H] -#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL] -#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH] -#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32 -#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L] -#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL] -#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH] -#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H] -#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL] -#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH] -#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32 -#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L] -#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL] -#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH] -#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H] -#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL] -#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH] -#define RSCAN0RMID7 RSCAN0.RMID7.UINT32 -#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L] -#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL] -#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH] -#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H] -#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL] -#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH] -#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32 -#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L] -#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL] -#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH] -#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H] -#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL] -#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH] -#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32 -#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L] -#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL] -#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH] -#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H] -#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL] -#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH] -#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32 -#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L] -#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL] -#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH] -#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H] -#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL] -#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH] -#define RSCAN0RMID8 RSCAN0.RMID8.UINT32 -#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L] -#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL] -#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH] -#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H] -#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL] -#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH] -#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32 -#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L] -#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL] -#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH] -#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H] -#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL] -#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH] -#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32 -#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L] -#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL] -#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH] -#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H] -#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL] -#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH] -#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32 -#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L] -#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL] -#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH] -#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H] -#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL] -#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH] -#define RSCAN0RMID9 RSCAN0.RMID9.UINT32 -#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L] -#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL] -#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH] -#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H] -#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL] -#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH] -#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32 -#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L] -#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL] -#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH] -#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H] -#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL] -#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH] -#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32 -#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L] -#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL] -#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH] -#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H] -#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL] -#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH] -#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32 -#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L] -#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL] -#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH] -#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H] -#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL] -#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH] -#define RSCAN0RMID10 RSCAN0.RMID10.UINT32 -#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L] -#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL] -#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH] -#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H] -#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL] -#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH] -#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32 -#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L] -#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL] -#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH] -#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H] -#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL] -#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH] -#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32 -#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L] -#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL] -#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH] -#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H] -#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL] -#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH] -#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32 -#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L] -#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL] -#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH] -#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H] -#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL] -#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH] -#define RSCAN0RMID11 RSCAN0.RMID11.UINT32 -#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L] -#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL] -#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH] -#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H] -#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL] -#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH] -#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32 -#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L] -#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL] -#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH] -#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H] -#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL] -#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH] -#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32 -#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L] -#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL] -#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH] -#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H] -#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL] -#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH] -#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32 -#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L] -#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL] -#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH] -#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H] -#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL] -#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH] -#define RSCAN0RMID12 RSCAN0.RMID12.UINT32 -#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L] -#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL] -#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH] -#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H] -#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL] -#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH] -#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32 -#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L] -#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL] -#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH] -#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H] -#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL] -#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH] -#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32 -#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L] -#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL] -#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH] -#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H] -#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL] -#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH] -#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32 -#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L] -#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL] -#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH] -#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H] -#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL] -#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH] -#define RSCAN0RMID13 RSCAN0.RMID13.UINT32 -#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L] -#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL] -#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH] -#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H] -#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL] -#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH] -#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32 -#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L] -#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL] -#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH] -#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H] -#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL] -#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH] -#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32 -#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L] -#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL] -#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH] -#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H] -#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL] -#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH] -#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32 -#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L] -#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL] -#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH] -#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H] -#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL] -#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH] -#define RSCAN0RMID14 RSCAN0.RMID14.UINT32 -#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L] -#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL] -#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH] -#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H] -#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL] -#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH] -#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32 -#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L] -#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL] -#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH] -#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H] -#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL] -#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH] -#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32 -#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L] -#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL] -#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH] -#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H] -#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL] -#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH] -#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32 -#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L] -#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL] -#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH] -#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H] -#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL] -#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH] -#define RSCAN0RMID15 RSCAN0.RMID15.UINT32 -#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L] -#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL] -#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH] -#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H] -#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL] -#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH] -#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32 -#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L] -#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL] -#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH] -#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H] -#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL] -#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH] -#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32 -#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L] -#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL] -#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH] -#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H] -#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL] -#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH] -#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32 -#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L] -#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL] -#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH] -#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H] -#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL] -#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH] -#define RSCAN0RMID16 RSCAN0.RMID16.UINT32 -#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L] -#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL] -#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH] -#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H] -#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL] -#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH] -#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32 -#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L] -#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL] -#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH] -#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H] -#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL] -#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH] -#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32 -#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L] -#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL] -#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH] -#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H] -#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL] -#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH] -#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32 -#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L] -#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL] -#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH] -#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H] -#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL] -#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH] -#define RSCAN0RMID17 RSCAN0.RMID17.UINT32 -#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L] -#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL] -#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH] -#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H] -#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL] -#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH] -#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32 -#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L] -#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL] -#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH] -#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H] -#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL] -#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH] -#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32 -#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L] -#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL] -#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH] -#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H] -#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL] -#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH] -#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32 -#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L] -#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL] -#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH] -#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H] -#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL] -#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH] -#define RSCAN0RMID18 RSCAN0.RMID18.UINT32 -#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L] -#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL] -#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH] -#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H] -#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL] -#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH] -#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32 -#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L] -#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL] -#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH] -#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H] -#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL] -#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH] -#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32 -#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L] -#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL] -#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH] -#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H] -#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL] -#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH] -#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32 -#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L] -#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL] -#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH] -#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H] -#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL] -#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH] -#define RSCAN0RMID19 RSCAN0.RMID19.UINT32 -#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L] -#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL] -#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH] -#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H] -#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL] -#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH] -#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32 -#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L] -#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL] -#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH] -#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H] -#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL] -#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH] -#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32 -#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L] -#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL] -#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH] -#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H] -#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL] -#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH] -#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32 -#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L] -#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL] -#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH] -#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H] -#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL] -#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH] -#define RSCAN0RMID20 RSCAN0.RMID20.UINT32 -#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L] -#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL] -#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH] -#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H] -#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL] -#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH] -#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32 -#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L] -#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL] -#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH] -#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H] -#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL] -#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH] -#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32 -#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L] -#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL] -#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH] -#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H] -#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL] -#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH] -#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32 -#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L] -#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL] -#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH] -#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H] -#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL] -#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH] -#define RSCAN0RMID21 RSCAN0.RMID21.UINT32 -#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L] -#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL] -#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH] -#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H] -#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL] -#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH] -#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32 -#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L] -#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL] -#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH] -#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H] -#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL] -#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH] -#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32 -#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L] -#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL] -#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH] -#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H] -#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL] -#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH] -#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32 -#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L] -#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL] -#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH] -#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H] -#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL] -#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH] -#define RSCAN0RMID22 RSCAN0.RMID22.UINT32 -#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L] -#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL] -#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH] -#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H] -#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL] -#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH] -#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32 -#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L] -#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL] -#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH] -#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H] -#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL] -#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH] -#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32 -#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L] -#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL] -#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH] -#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H] -#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL] -#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH] -#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32 -#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L] -#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL] -#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH] -#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H] -#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL] -#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH] -#define RSCAN0RMID23 RSCAN0.RMID23.UINT32 -#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L] -#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL] -#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH] -#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H] -#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL] -#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH] -#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32 -#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L] -#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL] -#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH] -#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H] -#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL] -#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH] -#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32 -#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L] -#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL] -#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH] -#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H] -#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL] -#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH] -#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32 -#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L] -#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL] -#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH] -#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H] -#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL] -#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH] -#define RSCAN0RMID24 RSCAN0.RMID24.UINT32 -#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L] -#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL] -#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH] -#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H] -#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL] -#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH] -#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32 -#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L] -#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL] -#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH] -#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H] -#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL] -#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH] -#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32 -#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L] -#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL] -#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH] -#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H] -#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL] -#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH] -#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32 -#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L] -#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL] -#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH] -#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H] -#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL] -#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH] -#define RSCAN0RMID25 RSCAN0.RMID25.UINT32 -#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L] -#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL] -#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH] -#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H] -#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL] -#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH] -#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32 -#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L] -#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL] -#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH] -#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H] -#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL] -#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH] -#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32 -#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L] -#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL] -#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH] -#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H] -#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL] -#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH] -#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32 -#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L] -#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL] -#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH] -#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H] -#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL] -#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH] -#define RSCAN0RMID26 RSCAN0.RMID26.UINT32 -#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L] -#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL] -#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH] -#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H] -#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL] -#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH] -#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32 -#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L] -#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL] -#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH] -#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H] -#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL] -#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH] -#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32 -#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L] -#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL] -#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH] -#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H] -#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL] -#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH] -#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32 -#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L] -#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL] -#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH] -#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H] -#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL] -#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH] -#define RSCAN0RMID27 RSCAN0.RMID27.UINT32 -#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L] -#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL] -#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH] -#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H] -#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL] -#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH] -#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32 -#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L] -#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL] -#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH] -#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H] -#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL] -#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH] -#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32 -#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L] -#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL] -#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH] -#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H] -#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL] -#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH] -#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32 -#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L] -#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL] -#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH] -#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H] -#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL] -#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH] -#define RSCAN0RMID28 RSCAN0.RMID28.UINT32 -#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L] -#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL] -#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH] -#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H] -#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL] -#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH] -#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32 -#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L] -#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL] -#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH] -#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H] -#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL] -#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH] -#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32 -#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L] -#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL] -#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH] -#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H] -#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL] -#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH] -#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32 -#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L] -#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL] -#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH] -#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H] -#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL] -#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH] -#define RSCAN0RMID29 RSCAN0.RMID29.UINT32 -#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L] -#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL] -#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH] -#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H] -#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL] -#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH] -#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32 -#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L] -#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL] -#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH] -#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H] -#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL] -#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH] -#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32 -#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L] -#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL] -#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH] -#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H] -#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL] -#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH] -#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32 -#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L] -#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL] -#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH] -#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H] -#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL] -#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH] -#define RSCAN0RMID30 RSCAN0.RMID30.UINT32 -#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L] -#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL] -#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH] -#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H] -#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL] -#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH] -#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32 -#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L] -#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL] -#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH] -#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H] -#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL] -#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH] -#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32 -#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L] -#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL] -#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH] -#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H] -#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL] -#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH] -#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32 -#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L] -#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL] -#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH] -#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H] -#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL] -#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH] -#define RSCAN0RMID31 RSCAN0.RMID31.UINT32 -#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L] -#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL] -#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH] -#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H] -#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL] -#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH] -#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32 -#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L] -#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL] -#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH] -#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H] -#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL] -#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH] -#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32 -#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L] -#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL] -#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH] -#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H] -#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL] -#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH] -#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32 -#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L] -#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL] -#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH] -#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H] -#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL] -#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH] -#define RSCAN0RMID32 RSCAN0.RMID32.UINT32 -#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L] -#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL] -#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH] -#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H] -#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL] -#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH] -#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32 -#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L] -#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL] -#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH] -#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H] -#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL] -#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH] -#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32 -#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L] -#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL] -#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH] -#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H] -#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL] -#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH] -#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32 -#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L] -#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL] -#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH] -#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H] -#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL] -#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH] -#define RSCAN0RMID33 RSCAN0.RMID33.UINT32 -#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L] -#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL] -#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH] -#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H] -#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL] -#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH] -#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32 -#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L] -#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL] -#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH] -#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H] -#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL] -#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH] -#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32 -#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L] -#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL] -#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH] -#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H] -#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL] -#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH] -#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32 -#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L] -#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL] -#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH] -#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H] -#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL] -#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH] -#define RSCAN0RMID34 RSCAN0.RMID34.UINT32 -#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L] -#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL] -#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH] -#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H] -#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL] -#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH] -#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32 -#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L] -#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL] -#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH] -#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H] -#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL] -#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH] -#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32 -#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L] -#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL] -#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH] -#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H] -#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL] -#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH] -#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32 -#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L] -#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL] -#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH] -#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H] -#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL] -#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH] -#define RSCAN0RMID35 RSCAN0.RMID35.UINT32 -#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L] -#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL] -#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH] -#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H] -#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL] -#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH] -#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32 -#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L] -#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL] -#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH] -#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H] -#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL] -#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH] -#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32 -#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L] -#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL] -#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH] -#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H] -#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL] -#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH] -#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32 -#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L] -#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL] -#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH] -#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H] -#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL] -#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH] -#define RSCAN0RMID36 RSCAN0.RMID36.UINT32 -#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L] -#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL] -#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH] -#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H] -#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL] -#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH] -#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32 -#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L] -#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL] -#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH] -#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H] -#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL] -#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH] -#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32 -#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L] -#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL] -#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH] -#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H] -#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL] -#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH] -#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32 -#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L] -#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL] -#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH] -#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H] -#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL] -#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH] -#define RSCAN0RMID37 RSCAN0.RMID37.UINT32 -#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L] -#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL] -#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH] -#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H] -#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL] -#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH] -#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32 -#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L] -#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL] -#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH] -#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H] -#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL] -#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH] -#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32 -#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L] -#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL] -#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH] -#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H] -#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL] -#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH] -#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32 -#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L] -#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL] -#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH] -#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H] -#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL] -#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH] -#define RSCAN0RMID38 RSCAN0.RMID38.UINT32 -#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L] -#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL] -#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH] -#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H] -#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL] -#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH] -#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32 -#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L] -#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL] -#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH] -#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H] -#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL] -#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH] -#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32 -#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L] -#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL] -#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH] -#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H] -#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL] -#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH] -#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32 -#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L] -#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL] -#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH] -#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H] -#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL] -#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH] -#define RSCAN0RMID39 RSCAN0.RMID39.UINT32 -#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L] -#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL] -#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH] -#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H] -#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL] -#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH] -#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32 -#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L] -#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL] -#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH] -#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H] -#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL] -#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH] -#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32 -#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L] -#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL] -#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH] -#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H] -#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL] -#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH] -#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32 -#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L] -#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL] -#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH] -#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H] -#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL] -#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH] -#define RSCAN0RMID40 RSCAN0.RMID40.UINT32 -#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L] -#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL] -#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH] -#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H] -#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL] -#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH] -#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32 -#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L] -#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL] -#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH] -#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H] -#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL] -#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH] -#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32 -#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L] -#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL] -#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH] -#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H] -#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL] -#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH] -#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32 -#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L] -#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL] -#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH] -#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H] -#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL] -#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH] -#define RSCAN0RMID41 RSCAN0.RMID41.UINT32 -#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L] -#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL] -#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH] -#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H] -#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL] -#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH] -#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32 -#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L] -#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL] -#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH] -#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H] -#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL] -#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH] -#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32 -#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L] -#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL] -#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH] -#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H] -#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL] -#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH] -#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32 -#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L] -#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL] -#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH] -#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H] -#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL] -#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH] -#define RSCAN0RMID42 RSCAN0.RMID42.UINT32 -#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L] -#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL] -#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH] -#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H] -#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL] -#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH] -#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32 -#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L] -#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL] -#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH] -#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H] -#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL] -#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH] -#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32 -#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L] -#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL] -#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH] -#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H] -#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL] -#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH] -#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32 -#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L] -#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL] -#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH] -#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H] -#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL] -#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH] -#define RSCAN0RMID43 RSCAN0.RMID43.UINT32 -#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L] -#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL] -#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH] -#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H] -#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL] -#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH] -#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32 -#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L] -#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL] -#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH] -#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H] -#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL] -#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH] -#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32 -#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L] -#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL] -#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH] -#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H] -#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL] -#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH] -#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32 -#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L] -#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL] -#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH] -#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H] -#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL] -#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH] -#define RSCAN0RMID44 RSCAN0.RMID44.UINT32 -#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L] -#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL] -#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH] -#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H] -#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL] -#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH] -#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32 -#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L] -#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL] -#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH] -#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H] -#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL] -#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH] -#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32 -#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L] -#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL] -#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH] -#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H] -#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL] -#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH] -#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32 -#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L] -#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL] -#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH] -#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H] -#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL] -#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH] -#define RSCAN0RMID45 RSCAN0.RMID45.UINT32 -#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L] -#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL] -#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH] -#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H] -#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL] -#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH] -#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32 -#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L] -#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL] -#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH] -#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H] -#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL] -#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH] -#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32 -#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L] -#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL] -#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH] -#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H] -#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL] -#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH] -#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32 -#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L] -#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL] -#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH] -#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H] -#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL] -#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH] -#define RSCAN0RMID46 RSCAN0.RMID46.UINT32 -#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L] -#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL] -#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH] -#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H] -#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL] -#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH] -#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32 -#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L] -#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL] -#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH] -#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H] -#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL] -#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH] -#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32 -#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L] -#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL] -#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH] -#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H] -#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL] -#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH] -#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32 -#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L] -#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL] -#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH] -#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H] -#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL] -#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH] -#define RSCAN0RMID47 RSCAN0.RMID47.UINT32 -#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L] -#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL] -#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH] -#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H] -#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL] -#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH] -#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32 -#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L] -#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL] -#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH] -#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H] -#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL] -#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH] -#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32 -#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L] -#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL] -#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH] -#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H] -#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL] -#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH] -#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32 -#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L] -#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL] -#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH] -#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H] -#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL] -#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH] -#define RSCAN0RMID48 RSCAN0.RMID48.UINT32 -#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L] -#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL] -#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH] -#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H] -#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL] -#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH] -#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32 -#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L] -#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL] -#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH] -#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H] -#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL] -#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH] -#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32 -#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L] -#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL] -#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH] -#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H] -#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL] -#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH] -#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32 -#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L] -#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL] -#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH] -#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H] -#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL] -#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH] -#define RSCAN0RMID49 RSCAN0.RMID49.UINT32 -#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L] -#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL] -#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH] -#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H] -#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL] -#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH] -#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32 -#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L] -#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL] -#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH] -#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H] -#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL] -#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH] -#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32 -#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L] -#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL] -#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH] -#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H] -#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL] -#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH] -#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32 -#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L] -#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL] -#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH] -#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H] -#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL] -#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH] -#define RSCAN0RMID50 RSCAN0.RMID50.UINT32 -#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L] -#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL] -#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH] -#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H] -#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL] -#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH] -#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32 -#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L] -#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL] -#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH] -#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H] -#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL] -#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH] -#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32 -#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L] -#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL] -#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH] -#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H] -#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL] -#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH] -#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32 -#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L] -#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL] -#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH] -#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H] -#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL] -#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH] -#define RSCAN0RMID51 RSCAN0.RMID51.UINT32 -#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L] -#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL] -#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH] -#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H] -#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL] -#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH] -#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32 -#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L] -#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL] -#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH] -#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H] -#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL] -#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH] -#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32 -#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L] -#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL] -#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH] -#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H] -#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL] -#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH] -#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32 -#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L] -#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL] -#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH] -#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H] -#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL] -#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH] -#define RSCAN0RMID52 RSCAN0.RMID52.UINT32 -#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L] -#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL] -#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH] -#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H] -#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL] -#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH] -#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32 -#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L] -#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL] -#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH] -#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H] -#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL] -#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH] -#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32 -#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L] -#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL] -#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH] -#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H] -#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL] -#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH] -#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32 -#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L] -#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL] -#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH] -#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H] -#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL] -#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH] -#define RSCAN0RMID53 RSCAN0.RMID53.UINT32 -#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L] -#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL] -#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH] -#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H] -#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL] -#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH] -#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32 -#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L] -#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL] -#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH] -#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H] -#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL] -#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH] -#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32 -#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L] -#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL] -#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH] -#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H] -#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL] -#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH] -#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32 -#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L] -#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL] -#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH] -#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H] -#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL] -#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH] -#define RSCAN0RMID54 RSCAN0.RMID54.UINT32 -#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L] -#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL] -#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH] -#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H] -#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL] -#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH] -#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32 -#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L] -#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL] -#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH] -#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H] -#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL] -#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH] -#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32 -#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L] -#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL] -#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH] -#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H] -#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL] -#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH] -#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32 -#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L] -#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL] -#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH] -#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H] -#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL] -#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH] -#define RSCAN0RMID55 RSCAN0.RMID55.UINT32 -#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L] -#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL] -#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH] -#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H] -#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL] -#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH] -#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32 -#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L] -#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL] -#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH] -#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H] -#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL] -#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH] -#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32 -#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L] -#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL] -#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH] -#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H] -#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL] -#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH] -#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32 -#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L] -#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL] -#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH] -#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H] -#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL] -#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH] -#define RSCAN0RMID56 RSCAN0.RMID56.UINT32 -#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L] -#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL] -#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH] -#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H] -#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL] -#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH] -#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32 -#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L] -#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL] -#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH] -#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H] -#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL] -#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH] -#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32 -#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L] -#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL] -#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH] -#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H] -#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL] -#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH] -#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32 -#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L] -#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL] -#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH] -#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H] -#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL] -#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH] -#define RSCAN0RMID57 RSCAN0.RMID57.UINT32 -#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L] -#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL] -#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH] -#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H] -#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL] -#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH] -#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32 -#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L] -#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL] -#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH] -#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H] -#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL] -#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH] -#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32 -#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L] -#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL] -#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH] -#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H] -#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL] -#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH] -#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32 -#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L] -#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL] -#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH] -#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H] -#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL] -#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH] -#define RSCAN0RMID58 RSCAN0.RMID58.UINT32 -#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L] -#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL] -#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH] -#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H] -#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL] -#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH] -#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32 -#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L] -#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL] -#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH] -#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H] -#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL] -#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH] -#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32 -#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L] -#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL] -#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH] -#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H] -#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL] -#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH] -#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32 -#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L] -#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL] -#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH] -#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H] -#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL] -#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH] -#define RSCAN0RMID59 RSCAN0.RMID59.UINT32 -#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L] -#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL] -#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH] -#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H] -#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL] -#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH] -#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32 -#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L] -#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL] -#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH] -#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H] -#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL] -#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH] -#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32 -#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L] -#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL] -#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH] -#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H] -#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL] -#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH] -#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32 -#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L] -#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL] -#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH] -#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H] -#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL] -#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH] -#define RSCAN0RMID60 RSCAN0.RMID60.UINT32 -#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L] -#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL] -#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH] -#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H] -#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL] -#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH] -#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32 -#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L] -#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL] -#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH] -#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H] -#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL] -#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH] -#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32 -#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L] -#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL] -#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH] -#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H] -#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL] -#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH] -#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32 -#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L] -#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL] -#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH] -#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H] -#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL] -#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH] -#define RSCAN0RMID61 RSCAN0.RMID61.UINT32 -#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L] -#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL] -#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH] -#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H] -#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL] -#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH] -#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32 -#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L] -#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL] -#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH] -#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H] -#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL] -#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH] -#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32 -#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L] -#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL] -#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH] -#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H] -#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL] -#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH] -#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32 -#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L] -#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL] -#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH] -#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H] -#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL] -#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH] -#define RSCAN0RMID62 RSCAN0.RMID62.UINT32 -#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L] -#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL] -#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH] -#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H] -#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL] -#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH] -#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32 -#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L] -#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL] -#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH] -#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H] -#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL] -#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH] -#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32 -#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L] -#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL] -#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH] -#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H] -#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL] -#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH] -#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32 -#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L] -#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL] -#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH] -#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H] -#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL] -#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH] -#define RSCAN0RMID63 RSCAN0.RMID63.UINT32 -#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L] -#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL] -#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH] -#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H] -#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL] -#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH] -#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32 -#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L] -#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL] -#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH] -#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H] -#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL] -#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH] -#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32 -#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L] -#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL] -#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH] -#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H] -#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL] -#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH] -#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32 -#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L] -#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL] -#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH] -#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H] -#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL] -#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH] -#define RSCAN0RMID64 RSCAN0.RMID64.UINT32 -#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L] -#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL] -#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH] -#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H] -#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL] -#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH] -#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32 -#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L] -#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL] -#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH] -#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H] -#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL] -#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH] -#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32 -#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L] -#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL] -#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH] -#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H] -#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL] -#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH] -#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32 -#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L] -#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL] -#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH] -#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H] -#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL] -#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH] -#define RSCAN0RMID65 RSCAN0.RMID65.UINT32 -#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L] -#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL] -#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH] -#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H] -#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL] -#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH] -#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32 -#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L] -#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL] -#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH] -#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H] -#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL] -#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH] -#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32 -#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L] -#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL] -#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH] -#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H] -#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL] -#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH] -#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32 -#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L] -#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL] -#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH] -#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H] -#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL] -#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH] -#define RSCAN0RMID66 RSCAN0.RMID66.UINT32 -#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L] -#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL] -#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH] -#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H] -#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL] -#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH] -#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32 -#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L] -#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL] -#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH] -#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H] -#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL] -#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH] -#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32 -#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L] -#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL] -#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH] -#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H] -#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL] -#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH] -#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32 -#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L] -#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL] -#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH] -#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H] -#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL] -#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH] -#define RSCAN0RMID67 RSCAN0.RMID67.UINT32 -#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L] -#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL] -#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH] -#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H] -#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL] -#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH] -#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32 -#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L] -#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL] -#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH] -#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H] -#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL] -#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH] -#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32 -#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L] -#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL] -#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH] -#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H] -#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL] -#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH] -#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32 -#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L] -#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL] -#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH] -#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H] -#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL] -#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH] -#define RSCAN0RMID68 RSCAN0.RMID68.UINT32 -#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L] -#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL] -#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH] -#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H] -#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL] -#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH] -#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32 -#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L] -#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL] -#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH] -#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H] -#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL] -#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH] -#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32 -#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L] -#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL] -#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH] -#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H] -#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL] -#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH] -#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32 -#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L] -#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL] -#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH] -#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H] -#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL] -#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH] -#define RSCAN0RMID69 RSCAN0.RMID69.UINT32 -#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L] -#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL] -#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH] -#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H] -#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL] -#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH] -#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32 -#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L] -#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL] -#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH] -#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H] -#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL] -#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH] -#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32 -#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L] -#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL] -#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH] -#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H] -#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL] -#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH] -#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32 -#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L] -#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL] -#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH] -#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H] -#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL] -#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH] -#define RSCAN0RMID70 RSCAN0.RMID70.UINT32 -#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L] -#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL] -#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH] -#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H] -#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL] -#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH] -#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32 -#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L] -#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL] -#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH] -#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H] -#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL] -#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH] -#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32 -#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L] -#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL] -#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH] -#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H] -#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL] -#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH] -#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32 -#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L] -#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL] -#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH] -#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H] -#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL] -#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH] -#define RSCAN0RMID71 RSCAN0.RMID71.UINT32 -#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L] -#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL] -#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH] -#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H] -#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL] -#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH] -#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32 -#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L] -#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL] -#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH] -#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H] -#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL] -#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH] -#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32 -#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L] -#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL] -#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH] -#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H] -#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL] -#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH] -#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32 -#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L] -#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL] -#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH] -#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H] -#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL] -#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH] -#define RSCAN0RMID72 RSCAN0.RMID72.UINT32 -#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L] -#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL] -#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH] -#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H] -#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL] -#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH] -#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32 -#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L] -#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL] -#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH] -#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H] -#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL] -#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH] -#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32 -#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L] -#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL] -#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH] -#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H] -#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL] -#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH] -#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32 -#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L] -#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL] -#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH] -#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H] -#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL] -#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH] -#define RSCAN0RMID73 RSCAN0.RMID73.UINT32 -#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L] -#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL] -#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH] -#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H] -#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL] -#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH] -#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32 -#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L] -#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL] -#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH] -#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H] -#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL] -#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH] -#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32 -#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L] -#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL] -#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH] -#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H] -#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL] -#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH] -#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32 -#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L] -#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL] -#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH] -#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H] -#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL] -#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH] -#define RSCAN0RMID74 RSCAN0.RMID74.UINT32 -#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L] -#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL] -#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH] -#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H] -#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL] -#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH] -#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32 -#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L] -#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL] -#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH] -#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H] -#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL] -#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH] -#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32 -#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L] -#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL] -#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH] -#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H] -#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL] -#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH] -#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32 -#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L] -#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL] -#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH] -#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H] -#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL] -#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH] -#define RSCAN0RMID75 RSCAN0.RMID75.UINT32 -#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L] -#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL] -#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH] -#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H] -#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL] -#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH] -#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32 -#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L] -#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL] -#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH] -#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H] -#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL] -#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH] -#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32 -#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L] -#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL] -#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH] -#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H] -#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL] -#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH] -#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32 -#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L] -#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL] -#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH] -#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H] -#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL] -#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH] -#define RSCAN0RMID76 RSCAN0.RMID76.UINT32 -#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L] -#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL] -#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH] -#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H] -#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL] -#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH] -#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32 -#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L] -#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL] -#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH] -#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H] -#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL] -#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH] -#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32 -#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L] -#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL] -#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH] -#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H] -#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL] -#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH] -#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32 -#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L] -#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL] -#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH] -#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H] -#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL] -#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH] -#define RSCAN0RMID77 RSCAN0.RMID77.UINT32 -#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L] -#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL] -#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH] -#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H] -#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL] -#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH] -#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32 -#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L] -#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL] -#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH] -#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H] -#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL] -#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH] -#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32 -#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L] -#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL] -#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH] -#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H] -#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL] -#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH] -#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32 -#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L] -#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL] -#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH] -#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H] -#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL] -#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH] -#define RSCAN0RMID78 RSCAN0.RMID78.UINT32 -#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L] -#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL] -#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH] -#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H] -#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL] -#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH] -#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32 -#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L] -#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL] -#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH] -#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H] -#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL] -#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH] -#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32 -#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L] -#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL] -#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH] -#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H] -#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL] -#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH] -#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32 -#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L] -#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL] -#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH] -#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H] -#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL] -#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH] -#define RSCAN0RMID79 RSCAN0.RMID79.UINT32 -#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L] -#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL] -#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH] -#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H] -#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL] -#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH] -#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32 -#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L] -#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL] -#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH] -#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H] -#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL] -#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH] -#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32 -#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L] -#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL] -#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH] -#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H] -#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL] -#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH] -#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32 -#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L] -#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL] -#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH] -#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H] -#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL] -#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH] -#define RSCAN0RFID0 RSCAN0.RFID0.UINT32 -#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L] -#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL] -#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH] -#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H] -#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL] -#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH] -#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32 -#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L] -#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL] -#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH] -#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H] -#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL] -#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH] -#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32 -#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L] -#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL] -#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH] -#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H] -#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL] -#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH] -#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32 -#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L] -#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL] -#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH] -#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H] -#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL] -#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH] -#define RSCAN0RFID1 RSCAN0.RFID1.UINT32 -#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L] -#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL] -#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH] -#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H] -#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL] -#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH] -#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32 -#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L] -#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL] -#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH] -#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H] -#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL] -#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH] -#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32 -#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L] -#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL] -#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH] -#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H] -#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL] -#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH] -#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32 -#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L] -#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL] -#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH] -#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H] -#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL] -#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH] -#define RSCAN0RFID2 RSCAN0.RFID2.UINT32 -#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L] -#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL] -#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH] -#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H] -#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL] -#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH] -#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32 -#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L] -#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL] -#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH] -#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H] -#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL] -#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH] -#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32 -#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L] -#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL] -#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH] -#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H] -#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL] -#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH] -#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32 -#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L] -#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL] -#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH] -#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H] -#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL] -#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH] -#define RSCAN0RFID3 RSCAN0.RFID3.UINT32 -#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L] -#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL] -#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH] -#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H] -#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL] -#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH] -#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32 -#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L] -#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL] -#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH] -#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H] -#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL] -#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH] -#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32 -#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L] -#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL] -#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH] -#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H] -#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL] -#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH] -#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32 -#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L] -#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL] -#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH] -#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H] -#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL] -#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH] -#define RSCAN0RFID4 RSCAN0.RFID4.UINT32 -#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L] -#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL] -#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH] -#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H] -#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL] -#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH] -#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32 -#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L] -#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL] -#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH] -#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H] -#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL] -#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH] -#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32 -#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L] -#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL] -#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH] -#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H] -#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL] -#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH] -#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32 -#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L] -#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL] -#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH] -#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H] -#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL] -#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH] -#define RSCAN0RFID5 RSCAN0.RFID5.UINT32 -#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L] -#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL] -#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH] -#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H] -#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL] -#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH] -#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32 -#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L] -#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL] -#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH] -#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H] -#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL] -#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH] -#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32 -#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L] -#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL] -#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH] -#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H] -#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL] -#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH] -#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32 -#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L] -#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL] -#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH] -#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H] -#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL] -#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH] -#define RSCAN0RFID6 RSCAN0.RFID6.UINT32 -#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L] -#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL] -#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH] -#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H] -#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL] -#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH] -#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32 -#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L] -#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL] -#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH] -#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H] -#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL] -#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH] -#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32 -#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L] -#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL] -#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH] -#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H] -#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL] -#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH] -#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32 -#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L] -#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL] -#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH] -#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H] -#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL] -#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH] -#define RSCAN0RFID7 RSCAN0.RFID7.UINT32 -#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L] -#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL] -#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH] -#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H] -#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL] -#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH] -#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32 -#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L] -#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL] -#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH] -#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H] -#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL] -#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH] -#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32 -#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L] -#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL] -#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH] -#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H] -#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL] -#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH] -#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32 -#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L] -#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL] -#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH] -#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H] -#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL] -#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH] -#define RSCAN0CFID0 RSCAN0.CFID0.UINT32 -#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L] -#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL] -#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH] -#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H] -#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL] -#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH] -#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32 -#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L] -#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL] -#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH] -#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H] -#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL] -#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH] -#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32 -#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L] -#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL] -#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH] -#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H] -#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL] -#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH] -#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32 -#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L] -#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL] -#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH] -#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H] -#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL] -#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH] -#define RSCAN0CFID1 RSCAN0.CFID1.UINT32 -#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L] -#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL] -#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH] -#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H] -#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL] -#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH] -#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32 -#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L] -#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL] -#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH] -#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H] -#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL] -#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH] -#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32 -#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L] -#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL] -#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH] -#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H] -#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL] -#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH] -#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32 -#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L] -#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL] -#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH] -#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H] -#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL] -#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH] -#define RSCAN0CFID2 RSCAN0.CFID2.UINT32 -#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L] -#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL] -#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH] -#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H] -#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL] -#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH] -#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32 -#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L] -#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL] -#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH] -#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H] -#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL] -#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH] -#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32 -#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L] -#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL] -#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH] -#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H] -#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL] -#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH] -#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32 -#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L] -#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL] -#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH] -#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H] -#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL] -#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH] -#define RSCAN0CFID3 RSCAN0.CFID3.UINT32 -#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L] -#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL] -#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH] -#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H] -#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL] -#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH] -#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32 -#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L] -#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL] -#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH] -#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H] -#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL] -#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH] -#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32 -#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L] -#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL] -#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH] -#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H] -#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL] -#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH] -#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32 -#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L] -#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL] -#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH] -#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H] -#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL] -#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH] -#define RSCAN0CFID4 RSCAN0.CFID4.UINT32 -#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L] -#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL] -#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH] -#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H] -#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL] -#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH] -#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32 -#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L] -#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL] -#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH] -#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H] -#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL] -#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH] -#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32 -#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L] -#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL] -#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH] -#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H] -#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL] -#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH] -#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32 -#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L] -#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL] -#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH] -#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H] -#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL] -#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH] -#define RSCAN0CFID5 RSCAN0.CFID5.UINT32 -#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L] -#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL] -#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH] -#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H] -#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL] -#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH] -#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32 -#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L] -#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL] -#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH] -#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H] -#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL] -#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH] -#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32 -#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L] -#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL] -#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH] -#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H] -#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL] -#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH] -#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32 -#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L] -#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL] -#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH] -#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H] -#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL] -#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH] -#define RSCAN0CFID6 RSCAN0.CFID6.UINT32 -#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L] -#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL] -#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH] -#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H] -#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL] -#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH] -#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32 -#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L] -#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL] -#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH] -#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H] -#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL] -#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH] -#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32 -#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L] -#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL] -#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH] -#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H] -#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL] -#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH] -#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32 -#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L] -#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL] -#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH] -#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H] -#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL] -#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH] -#define RSCAN0CFID7 RSCAN0.CFID7.UINT32 -#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L] -#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL] -#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH] -#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H] -#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL] -#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH] -#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32 -#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L] -#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL] -#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH] -#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H] -#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL] -#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH] -#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32 -#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L] -#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL] -#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH] -#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H] -#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL] -#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH] -#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32 -#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L] -#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL] -#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH] -#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H] -#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL] -#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH] -#define RSCAN0CFID8 RSCAN0.CFID8.UINT32 -#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L] -#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL] -#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH] -#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H] -#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL] -#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH] -#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32 -#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L] -#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL] -#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH] -#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H] -#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL] -#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH] -#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32 -#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L] -#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL] -#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH] -#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H] -#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL] -#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH] -#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32 -#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L] -#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL] -#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH] -#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H] -#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL] -#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH] -#define RSCAN0CFID9 RSCAN0.CFID9.UINT32 -#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L] -#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL] -#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH] -#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H] -#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL] -#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH] -#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32 -#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L] -#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL] -#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH] -#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H] -#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL] -#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH] -#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32 -#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L] -#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL] -#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH] -#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H] -#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL] -#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH] -#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32 -#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L] -#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL] -#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH] -#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H] -#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL] -#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH] -#define RSCAN0CFID10 RSCAN0.CFID10.UINT32 -#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L] -#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL] -#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH] -#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H] -#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL] -#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH] -#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32 -#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L] -#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL] -#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH] -#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H] -#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL] -#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH] -#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32 -#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L] -#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL] -#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH] -#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H] -#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL] -#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH] -#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32 -#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L] -#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL] -#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH] -#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H] -#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL] -#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH] -#define RSCAN0CFID11 RSCAN0.CFID11.UINT32 -#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L] -#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL] -#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH] -#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H] -#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL] -#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH] -#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32 -#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L] -#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL] -#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH] -#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H] -#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL] -#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH] -#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32 -#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L] -#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL] -#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH] -#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H] -#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL] -#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH] -#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32 -#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L] -#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL] -#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH] -#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H] -#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL] -#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH] -#define RSCAN0CFID12 RSCAN0.CFID12.UINT32 -#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L] -#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL] -#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH] -#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H] -#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL] -#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH] -#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32 -#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L] -#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL] -#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH] -#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H] -#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL] -#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH] -#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32 -#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L] -#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL] -#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH] -#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H] -#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL] -#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH] -#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32 -#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L] -#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL] -#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH] -#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H] -#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL] -#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH] -#define RSCAN0CFID13 RSCAN0.CFID13.UINT32 -#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L] -#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL] -#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH] -#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H] -#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL] -#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH] -#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32 -#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L] -#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL] -#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH] -#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H] -#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL] -#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH] -#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32 -#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L] -#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL] -#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH] -#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H] -#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL] -#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH] -#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32 -#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L] -#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL] -#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH] -#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H] -#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL] -#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH] -#define RSCAN0CFID14 RSCAN0.CFID14.UINT32 -#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L] -#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL] -#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH] -#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H] -#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL] -#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH] -#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32 -#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L] -#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL] -#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH] -#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H] -#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL] -#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH] -#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32 -#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L] -#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL] -#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH] -#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H] -#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL] -#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH] -#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32 -#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L] -#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL] -#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH] -#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H] -#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL] -#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH] -#define RSCAN0TMID0 RSCAN0.TMID0.UINT32 -#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L] -#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL] -#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH] -#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H] -#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL] -#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH] -#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32 -#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L] -#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL] -#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH] -#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H] -#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL] -#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH] -#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32 -#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L] -#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL] -#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH] -#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H] -#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL] -#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH] -#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32 -#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L] -#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL] -#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH] -#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H] -#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL] -#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH] -#define RSCAN0TMID1 RSCAN0.TMID1.UINT32 -#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L] -#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL] -#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH] -#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H] -#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL] -#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH] -#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32 -#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L] -#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL] -#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH] -#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H] -#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL] -#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH] -#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32 -#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L] -#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL] -#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH] -#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H] -#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL] -#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH] -#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32 -#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L] -#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL] -#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH] -#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H] -#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL] -#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH] -#define RSCAN0TMID2 RSCAN0.TMID2.UINT32 -#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L] -#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL] -#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH] -#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H] -#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL] -#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH] -#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32 -#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L] -#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL] -#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH] -#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H] -#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL] -#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH] -#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32 -#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L] -#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL] -#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH] -#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H] -#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL] -#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH] -#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32 -#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L] -#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL] -#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH] -#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H] -#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL] -#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH] -#define RSCAN0TMID3 RSCAN0.TMID3.UINT32 -#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L] -#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL] -#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH] -#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H] -#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL] -#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH] -#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32 -#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L] -#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL] -#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH] -#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H] -#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL] -#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH] -#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32 -#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L] -#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL] -#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH] -#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H] -#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL] -#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH] -#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32 -#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L] -#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL] -#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH] -#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H] -#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL] -#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH] -#define RSCAN0TMID4 RSCAN0.TMID4.UINT32 -#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L] -#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL] -#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH] -#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H] -#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL] -#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH] -#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32 -#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L] -#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL] -#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH] -#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H] -#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL] -#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH] -#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32 -#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L] -#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL] -#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH] -#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H] -#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL] -#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH] -#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32 -#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L] -#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL] -#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH] -#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H] -#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL] -#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH] -#define RSCAN0TMID5 RSCAN0.TMID5.UINT32 -#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L] -#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL] -#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH] -#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H] -#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL] -#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH] -#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32 -#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L] -#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL] -#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH] -#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H] -#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL] -#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH] -#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32 -#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L] -#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL] -#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH] -#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H] -#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL] -#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH] -#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32 -#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L] -#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL] -#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH] -#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H] -#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL] -#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH] -#define RSCAN0TMID6 RSCAN0.TMID6.UINT32 -#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L] -#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL] -#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH] -#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H] -#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL] -#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH] -#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32 -#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L] -#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL] -#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH] -#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H] -#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL] -#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH] -#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32 -#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L] -#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL] -#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH] -#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H] -#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL] -#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH] -#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32 -#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L] -#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL] -#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH] -#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H] -#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL] -#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH] -#define RSCAN0TMID7 RSCAN0.TMID7.UINT32 -#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L] -#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL] -#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH] -#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H] -#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL] -#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH] -#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32 -#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L] -#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL] -#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH] -#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H] -#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL] -#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH] -#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32 -#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L] -#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL] -#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH] -#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H] -#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL] -#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH] -#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32 -#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L] -#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL] -#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH] -#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H] -#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL] -#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH] -#define RSCAN0TMID8 RSCAN0.TMID8.UINT32 -#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L] -#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL] -#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH] -#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H] -#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL] -#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH] -#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32 -#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L] -#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL] -#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH] -#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H] -#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL] -#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH] -#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32 -#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L] -#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL] -#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH] -#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H] -#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL] -#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH] -#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32 -#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L] -#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL] -#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH] -#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H] -#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL] -#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH] -#define RSCAN0TMID9 RSCAN0.TMID9.UINT32 -#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L] -#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL] -#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH] -#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H] -#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL] -#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH] -#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32 -#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L] -#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL] -#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH] -#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H] -#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL] -#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH] -#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32 -#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L] -#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL] -#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH] -#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H] -#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL] -#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH] -#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32 -#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L] -#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL] -#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH] -#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H] -#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL] -#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH] -#define RSCAN0TMID10 RSCAN0.TMID10.UINT32 -#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L] -#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL] -#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH] -#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H] -#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL] -#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH] -#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32 -#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L] -#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL] -#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH] -#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H] -#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL] -#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH] -#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32 -#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L] -#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL] -#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH] -#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H] -#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL] -#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH] -#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32 -#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L] -#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL] -#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH] -#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H] -#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL] -#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH] -#define RSCAN0TMID11 RSCAN0.TMID11.UINT32 -#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L] -#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL] -#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH] -#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H] -#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL] -#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH] -#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32 -#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L] -#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL] -#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH] -#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H] -#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL] -#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH] -#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32 -#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L] -#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL] -#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH] -#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H] -#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL] -#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH] -#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32 -#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L] -#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL] -#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH] -#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H] -#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL] -#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH] -#define RSCAN0TMID12 RSCAN0.TMID12.UINT32 -#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L] -#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL] -#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH] -#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H] -#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL] -#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH] -#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32 -#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L] -#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL] -#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH] -#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H] -#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL] -#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH] -#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32 -#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L] -#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL] -#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH] -#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H] -#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL] -#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH] -#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32 -#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L] -#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL] -#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH] -#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H] -#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL] -#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH] -#define RSCAN0TMID13 RSCAN0.TMID13.UINT32 -#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L] -#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL] -#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH] -#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H] -#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL] -#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH] -#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32 -#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L] -#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL] -#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH] -#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H] -#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL] -#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH] -#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32 -#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L] -#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL] -#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH] -#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H] -#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL] -#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH] -#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32 -#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L] -#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL] -#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH] -#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H] -#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL] -#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH] -#define RSCAN0TMID14 RSCAN0.TMID14.UINT32 -#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L] -#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL] -#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH] -#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H] -#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL] -#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH] -#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32 -#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L] -#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL] -#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH] -#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H] -#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL] -#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH] -#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32 -#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L] -#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL] -#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH] -#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H] -#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL] -#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH] -#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32 -#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L] -#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL] -#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH] -#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H] -#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL] -#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH] -#define RSCAN0TMID15 RSCAN0.TMID15.UINT32 -#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L] -#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL] -#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH] -#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H] -#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL] -#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH] -#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32 -#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L] -#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL] -#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH] -#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H] -#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL] -#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH] -#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32 -#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L] -#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL] -#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH] -#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H] -#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL] -#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH] -#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32 -#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L] -#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL] -#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH] -#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H] -#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL] -#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH] -#define RSCAN0TMID16 RSCAN0.TMID16.UINT32 -#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L] -#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL] -#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH] -#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H] -#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL] -#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH] -#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32 -#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L] -#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL] -#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH] -#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H] -#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL] -#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH] -#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32 -#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L] -#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL] -#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH] -#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H] -#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL] -#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH] -#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32 -#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L] -#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL] -#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH] -#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H] -#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL] -#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH] -#define RSCAN0TMID17 RSCAN0.TMID17.UINT32 -#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L] -#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL] -#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH] -#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H] -#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL] -#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH] -#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32 -#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L] -#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL] -#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH] -#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H] -#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL] -#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH] -#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32 -#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L] -#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL] -#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH] -#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H] -#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL] -#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH] -#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32 -#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L] -#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL] -#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH] -#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H] -#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL] -#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH] -#define RSCAN0TMID18 RSCAN0.TMID18.UINT32 -#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L] -#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL] -#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH] -#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H] -#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL] -#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH] -#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32 -#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L] -#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL] -#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH] -#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H] -#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL] -#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH] -#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32 -#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L] -#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL] -#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH] -#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H] -#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL] -#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH] -#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32 -#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L] -#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL] -#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH] -#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H] -#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL] -#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH] -#define RSCAN0TMID19 RSCAN0.TMID19.UINT32 -#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L] -#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL] -#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH] -#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H] -#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL] -#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH] -#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32 -#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L] -#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL] -#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH] -#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H] -#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL] -#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH] -#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32 -#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L] -#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL] -#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH] -#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H] -#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL] -#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH] -#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32 -#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L] -#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL] -#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH] -#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H] -#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL] -#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH] -#define RSCAN0TMID20 RSCAN0.TMID20.UINT32 -#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L] -#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL] -#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH] -#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H] -#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL] -#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH] -#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32 -#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L] -#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL] -#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH] -#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H] -#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL] -#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH] -#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32 -#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L] -#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL] -#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH] -#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H] -#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL] -#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH] -#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32 -#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L] -#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL] -#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH] -#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H] -#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL] -#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH] -#define RSCAN0TMID21 RSCAN0.TMID21.UINT32 -#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L] -#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL] -#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH] -#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H] -#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL] -#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH] -#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32 -#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L] -#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL] -#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH] -#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H] -#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL] -#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH] -#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32 -#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L] -#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL] -#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH] -#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H] -#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL] -#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH] -#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32 -#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L] -#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL] -#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH] -#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H] -#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL] -#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH] -#define RSCAN0TMID22 RSCAN0.TMID22.UINT32 -#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L] -#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL] -#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH] -#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H] -#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL] -#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH] -#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32 -#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L] -#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL] -#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH] -#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H] -#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL] -#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH] -#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32 -#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L] -#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL] -#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH] -#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H] -#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL] -#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH] -#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32 -#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L] -#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL] -#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH] -#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H] -#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL] -#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH] -#define RSCAN0TMID23 RSCAN0.TMID23.UINT32 -#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L] -#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL] -#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH] -#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H] -#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL] -#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH] -#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32 -#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L] -#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL] -#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH] -#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H] -#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL] -#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH] -#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32 -#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L] -#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL] -#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH] -#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H] -#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL] -#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH] -#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32 -#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L] -#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL] -#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH] -#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H] -#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL] -#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH] -#define RSCAN0TMID24 RSCAN0.TMID24.UINT32 -#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L] -#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL] -#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH] -#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H] -#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL] -#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH] -#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32 -#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L] -#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL] -#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH] -#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H] -#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL] -#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH] -#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32 -#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L] -#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL] -#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH] -#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H] -#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL] -#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH] -#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32 -#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L] -#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL] -#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH] -#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H] -#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL] -#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH] -#define RSCAN0TMID25 RSCAN0.TMID25.UINT32 -#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L] -#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL] -#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH] -#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H] -#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL] -#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH] -#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32 -#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L] -#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL] -#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH] -#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H] -#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL] -#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH] -#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32 -#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L] -#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL] -#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH] -#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H] -#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL] -#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH] -#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32 -#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L] -#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL] -#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH] -#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H] -#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL] -#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH] -#define RSCAN0TMID26 RSCAN0.TMID26.UINT32 -#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L] -#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL] -#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH] -#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H] -#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL] -#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH] -#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32 -#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L] -#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL] -#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH] -#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H] -#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL] -#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH] -#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32 -#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L] -#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL] -#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH] -#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H] -#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL] -#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH] -#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32 -#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L] -#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL] -#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH] -#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H] -#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL] -#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH] -#define RSCAN0TMID27 RSCAN0.TMID27.UINT32 -#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L] -#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL] -#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH] -#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H] -#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL] -#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH] -#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32 -#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L] -#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL] -#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH] -#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H] -#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL] -#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH] -#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32 -#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L] -#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL] -#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH] -#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H] -#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL] -#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH] -#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32 -#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L] -#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL] -#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH] -#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H] -#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL] -#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH] -#define RSCAN0TMID28 RSCAN0.TMID28.UINT32 -#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L] -#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL] -#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH] -#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H] -#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL] -#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH] -#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32 -#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L] -#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL] -#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH] -#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H] -#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL] -#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH] -#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32 -#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L] -#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL] -#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH] -#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H] -#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL] -#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH] -#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32 -#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L] -#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL] -#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH] -#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H] -#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL] -#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH] -#define RSCAN0TMID29 RSCAN0.TMID29.UINT32 -#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L] -#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL] -#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH] -#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H] -#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL] -#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH] -#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32 -#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L] -#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL] -#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH] -#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H] -#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL] -#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH] -#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32 -#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L] -#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL] -#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH] -#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H] -#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL] -#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH] -#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32 -#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L] -#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL] -#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH] -#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H] -#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL] -#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH] -#define RSCAN0TMID30 RSCAN0.TMID30.UINT32 -#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L] -#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL] -#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH] -#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H] -#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL] -#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH] -#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32 -#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L] -#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL] -#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH] -#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H] -#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL] -#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH] -#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32 -#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L] -#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL] -#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH] -#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H] -#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL] -#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH] -#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32 -#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L] -#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL] -#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH] -#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H] -#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL] -#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH] -#define RSCAN0TMID31 RSCAN0.TMID31.UINT32 -#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L] -#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL] -#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH] -#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H] -#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL] -#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH] -#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32 -#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L] -#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL] -#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH] -#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H] -#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL] -#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH] -#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32 -#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L] -#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL] -#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH] -#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H] -#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL] -#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH] -#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32 -#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L] -#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL] -#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH] -#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H] -#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL] -#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH] -#define RSCAN0TMID32 RSCAN0.TMID32.UINT32 -#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L] -#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL] -#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH] -#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H] -#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL] -#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH] -#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32 -#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L] -#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL] -#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH] -#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H] -#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL] -#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH] -#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32 -#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L] -#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL] -#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH] -#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H] -#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL] -#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH] -#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32 -#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L] -#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL] -#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH] -#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H] -#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL] -#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH] -#define RSCAN0TMID33 RSCAN0.TMID33.UINT32 -#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L] -#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL] -#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH] -#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H] -#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL] -#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH] -#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32 -#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L] -#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL] -#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH] -#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H] -#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL] -#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH] -#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32 -#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L] -#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL] -#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH] -#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H] -#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL] -#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH] -#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32 -#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L] -#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL] -#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH] -#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H] -#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL] -#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH] -#define RSCAN0TMID34 RSCAN0.TMID34.UINT32 -#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L] -#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL] -#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH] -#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H] -#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL] -#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH] -#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32 -#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L] -#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL] -#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH] -#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H] -#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL] -#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH] -#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32 -#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L] -#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL] -#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH] -#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H] -#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL] -#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH] -#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32 -#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L] -#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL] -#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH] -#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H] -#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL] -#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH] -#define RSCAN0TMID35 RSCAN0.TMID35.UINT32 -#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L] -#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL] -#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH] -#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H] -#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL] -#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH] -#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32 -#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L] -#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL] -#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH] -#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H] -#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL] -#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH] -#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32 -#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L] -#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL] -#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH] -#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H] -#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL] -#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH] -#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32 -#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L] -#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL] -#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH] -#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H] -#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL] -#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH] -#define RSCAN0TMID36 RSCAN0.TMID36.UINT32 -#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L] -#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL] -#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH] -#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H] -#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL] -#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH] -#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32 -#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L] -#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL] -#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH] -#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H] -#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL] -#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH] -#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32 -#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L] -#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL] -#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH] -#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H] -#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL] -#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH] -#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32 -#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L] -#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL] -#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH] -#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H] -#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL] -#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH] -#define RSCAN0TMID37 RSCAN0.TMID37.UINT32 -#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L] -#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL] -#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH] -#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H] -#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL] -#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH] -#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32 -#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L] -#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL] -#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH] -#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H] -#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL] -#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH] -#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32 -#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L] -#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL] -#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH] -#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H] -#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL] -#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH] -#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32 -#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L] -#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL] -#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH] -#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H] -#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL] -#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH] -#define RSCAN0TMID38 RSCAN0.TMID38.UINT32 -#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L] -#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL] -#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH] -#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H] -#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL] -#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH] -#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32 -#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L] -#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL] -#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH] -#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H] -#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL] -#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH] -#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32 -#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L] -#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL] -#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH] -#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H] -#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL] -#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH] -#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32 -#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L] -#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL] -#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH] -#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H] -#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL] -#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH] -#define RSCAN0TMID39 RSCAN0.TMID39.UINT32 -#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L] -#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL] -#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH] -#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H] -#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL] -#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH] -#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32 -#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L] -#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL] -#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH] -#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H] -#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL] -#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH] -#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32 -#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L] -#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL] -#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH] -#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H] -#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL] -#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH] -#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32 -#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L] -#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL] -#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH] -#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H] -#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL] -#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH] -#define RSCAN0TMID40 RSCAN0.TMID40.UINT32 -#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L] -#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL] -#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH] -#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H] -#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL] -#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH] -#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32 -#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L] -#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL] -#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH] -#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H] -#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL] -#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH] -#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32 -#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L] -#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL] -#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH] -#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H] -#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL] -#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH] -#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32 -#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L] -#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL] -#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH] -#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H] -#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL] -#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH] -#define RSCAN0TMID41 RSCAN0.TMID41.UINT32 -#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L] -#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL] -#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH] -#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H] -#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL] -#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH] -#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32 -#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L] -#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL] -#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH] -#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H] -#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL] -#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH] -#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32 -#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L] -#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL] -#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH] -#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H] -#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL] -#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH] -#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32 -#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L] -#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL] -#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH] -#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H] -#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL] -#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH] -#define RSCAN0TMID42 RSCAN0.TMID42.UINT32 -#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L] -#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL] -#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH] -#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H] -#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL] -#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH] -#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32 -#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L] -#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL] -#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH] -#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H] -#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL] -#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH] -#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32 -#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L] -#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL] -#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH] -#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H] -#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL] -#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH] -#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32 -#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L] -#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL] -#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH] -#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H] -#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL] -#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH] -#define RSCAN0TMID43 RSCAN0.TMID43.UINT32 -#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L] -#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL] -#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH] -#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H] -#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL] -#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH] -#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32 -#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L] -#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL] -#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH] -#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H] -#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL] -#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH] -#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32 -#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L] -#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL] -#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH] -#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H] -#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL] -#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH] -#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32 -#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L] -#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL] -#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH] -#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H] -#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL] -#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH] -#define RSCAN0TMID44 RSCAN0.TMID44.UINT32 -#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L] -#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL] -#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH] -#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H] -#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL] -#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH] -#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32 -#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L] -#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL] -#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH] -#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H] -#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL] -#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH] -#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32 -#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L] -#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL] -#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH] -#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H] -#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL] -#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH] -#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32 -#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L] -#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL] -#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH] -#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H] -#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL] -#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH] -#define RSCAN0TMID45 RSCAN0.TMID45.UINT32 -#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L] -#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL] -#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH] -#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H] -#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL] -#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH] -#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32 -#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L] -#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL] -#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH] -#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H] -#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL] -#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH] -#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32 -#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L] -#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL] -#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH] -#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H] -#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL] -#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH] -#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32 -#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L] -#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL] -#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH] -#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H] -#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL] -#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH] -#define RSCAN0TMID46 RSCAN0.TMID46.UINT32 -#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L] -#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL] -#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH] -#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H] -#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL] -#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH] -#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32 -#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L] -#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL] -#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH] -#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H] -#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL] -#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH] -#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32 -#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L] -#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL] -#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH] -#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H] -#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL] -#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH] -#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32 -#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L] -#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL] -#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH] -#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H] -#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL] -#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH] -#define RSCAN0TMID47 RSCAN0.TMID47.UINT32 -#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L] -#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL] -#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH] -#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H] -#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL] -#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH] -#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32 -#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L] -#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL] -#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH] -#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H] -#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL] -#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH] -#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32 -#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L] -#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL] -#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH] -#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H] -#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL] -#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH] -#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32 -#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L] -#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL] -#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH] -#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H] -#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL] -#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH] -#define RSCAN0TMID48 RSCAN0.TMID48.UINT32 -#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L] -#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL] -#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH] -#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H] -#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL] -#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH] -#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32 -#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L] -#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL] -#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH] -#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H] -#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL] -#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH] -#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32 -#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L] -#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL] -#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH] -#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H] -#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL] -#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH] -#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32 -#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L] -#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL] -#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH] -#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H] -#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL] -#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH] -#define RSCAN0TMID49 RSCAN0.TMID49.UINT32 -#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L] -#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL] -#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH] -#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H] -#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL] -#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH] -#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32 -#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L] -#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL] -#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH] -#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H] -#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL] -#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH] -#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32 -#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L] -#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL] -#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH] -#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H] -#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL] -#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH] -#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32 -#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L] -#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL] -#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH] -#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H] -#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL] -#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH] -#define RSCAN0TMID50 RSCAN0.TMID50.UINT32 -#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L] -#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL] -#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH] -#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H] -#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL] -#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH] -#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32 -#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L] -#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL] -#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH] -#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H] -#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL] -#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH] -#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32 -#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L] -#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL] -#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH] -#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H] -#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL] -#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH] -#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32 -#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L] -#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL] -#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH] -#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H] -#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL] -#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH] -#define RSCAN0TMID51 RSCAN0.TMID51.UINT32 -#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L] -#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL] -#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH] -#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H] -#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL] -#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH] -#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32 -#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L] -#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL] -#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH] -#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H] -#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL] -#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH] -#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32 -#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L] -#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL] -#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH] -#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H] -#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL] -#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH] -#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32 -#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L] -#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL] -#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH] -#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H] -#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL] -#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH] -#define RSCAN0TMID52 RSCAN0.TMID52.UINT32 -#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L] -#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL] -#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH] -#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H] -#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL] -#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH] -#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32 -#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L] -#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL] -#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH] -#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H] -#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL] -#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH] -#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32 -#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L] -#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL] -#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH] -#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H] -#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL] -#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH] -#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32 -#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L] -#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL] -#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH] -#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H] -#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL] -#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH] -#define RSCAN0TMID53 RSCAN0.TMID53.UINT32 -#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L] -#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL] -#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH] -#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H] -#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL] -#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH] -#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32 -#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L] -#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL] -#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH] -#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H] -#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL] -#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH] -#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32 -#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L] -#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL] -#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH] -#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H] -#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL] -#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH] -#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32 -#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L] -#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL] -#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH] -#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H] -#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL] -#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH] -#define RSCAN0TMID54 RSCAN0.TMID54.UINT32 -#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L] -#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL] -#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH] -#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H] -#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL] -#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH] -#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32 -#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L] -#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL] -#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH] -#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H] -#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL] -#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH] -#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32 -#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L] -#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL] -#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH] -#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H] -#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL] -#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH] -#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32 -#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L] -#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL] -#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH] -#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H] -#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL] -#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH] -#define RSCAN0TMID55 RSCAN0.TMID55.UINT32 -#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L] -#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL] -#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH] -#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H] -#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL] -#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH] -#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32 -#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L] -#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL] -#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH] -#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H] -#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL] -#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH] -#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32 -#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L] -#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL] -#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH] -#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H] -#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL] -#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH] -#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32 -#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L] -#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL] -#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH] -#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H] -#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL] -#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH] -#define RSCAN0TMID56 RSCAN0.TMID56.UINT32 -#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L] -#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL] -#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH] -#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H] -#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL] -#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH] -#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32 -#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L] -#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL] -#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH] -#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H] -#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL] -#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH] -#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32 -#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L] -#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL] -#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH] -#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H] -#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL] -#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH] -#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32 -#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L] -#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL] -#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH] -#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H] -#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL] -#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH] -#define RSCAN0TMID57 RSCAN0.TMID57.UINT32 -#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L] -#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL] -#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH] -#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H] -#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL] -#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH] -#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32 -#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L] -#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL] -#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH] -#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H] -#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL] -#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH] -#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32 -#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L] -#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL] -#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH] -#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H] -#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL] -#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH] -#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32 -#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L] -#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL] -#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH] -#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H] -#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL] -#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH] -#define RSCAN0TMID58 RSCAN0.TMID58.UINT32 -#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L] -#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL] -#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH] -#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H] -#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL] -#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH] -#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32 -#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L] -#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL] -#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH] -#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H] -#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL] -#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH] -#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32 -#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L] -#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL] -#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH] -#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H] -#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL] -#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH] -#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32 -#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L] -#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL] -#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH] -#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H] -#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL] -#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH] -#define RSCAN0TMID59 RSCAN0.TMID59.UINT32 -#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L] -#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL] -#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH] -#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H] -#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL] -#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH] -#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32 -#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L] -#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL] -#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH] -#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H] -#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL] -#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH] -#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32 -#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L] -#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL] -#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH] -#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H] -#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL] -#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH] -#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32 -#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L] -#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL] -#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH] -#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H] -#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL] -#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH] -#define RSCAN0TMID60 RSCAN0.TMID60.UINT32 -#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L] -#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL] -#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH] -#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H] -#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL] -#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH] -#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32 -#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L] -#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL] -#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH] -#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H] -#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL] -#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH] -#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32 -#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L] -#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL] -#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH] -#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H] -#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL] -#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH] -#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32 -#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L] -#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL] -#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH] -#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H] -#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL] -#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH] -#define RSCAN0TMID61 RSCAN0.TMID61.UINT32 -#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L] -#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL] -#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH] -#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H] -#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL] -#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH] -#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32 -#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L] -#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL] -#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH] -#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H] -#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL] -#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH] -#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32 -#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L] -#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL] -#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH] -#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H] -#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL] -#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH] -#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32 -#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L] -#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL] -#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH] -#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H] -#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL] -#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH] -#define RSCAN0TMID62 RSCAN0.TMID62.UINT32 -#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L] -#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL] -#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH] -#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H] -#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL] -#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH] -#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32 -#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L] -#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL] -#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH] -#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H] -#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL] -#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH] -#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32 -#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L] -#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL] -#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH] -#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H] -#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL] -#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH] -#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32 -#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L] -#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL] -#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH] -#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H] -#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL] -#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH] -#define RSCAN0TMID63 RSCAN0.TMID63.UINT32 -#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L] -#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL] -#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH] -#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H] -#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL] -#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH] -#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32 -#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L] -#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL] -#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH] -#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H] -#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL] -#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH] -#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32 -#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L] -#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL] -#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH] -#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H] -#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL] -#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH] -#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32 -#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L] -#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL] -#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH] -#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H] -#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL] -#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH] -#define RSCAN0TMID64 RSCAN0.TMID64.UINT32 -#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L] -#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL] -#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH] -#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H] -#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL] -#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH] -#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32 -#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L] -#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL] -#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH] -#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H] -#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL] -#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH] -#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32 -#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L] -#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL] -#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH] -#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H] -#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL] -#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH] -#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32 -#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L] -#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL] -#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH] -#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H] -#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL] -#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH] -#define RSCAN0TMID65 RSCAN0.TMID65.UINT32 -#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L] -#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL] -#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH] -#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H] -#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL] -#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH] -#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32 -#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L] -#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL] -#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH] -#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H] -#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL] -#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH] -#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32 -#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L] -#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL] -#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH] -#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H] -#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL] -#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH] -#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32 -#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L] -#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL] -#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH] -#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H] -#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL] -#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH] -#define RSCAN0TMID66 RSCAN0.TMID66.UINT32 -#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L] -#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL] -#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH] -#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H] -#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL] -#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH] -#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32 -#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L] -#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL] -#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH] -#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H] -#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL] -#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH] -#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32 -#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L] -#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL] -#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH] -#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H] -#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL] -#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH] -#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32 -#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L] -#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL] -#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH] -#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H] -#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL] -#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH] -#define RSCAN0TMID67 RSCAN0.TMID67.UINT32 -#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L] -#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL] -#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH] -#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H] -#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL] -#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH] -#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32 -#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L] -#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL] -#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH] -#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H] -#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL] -#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH] -#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32 -#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L] -#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL] -#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH] -#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H] -#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL] -#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH] -#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32 -#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L] -#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL] -#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH] -#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H] -#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL] -#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH] -#define RSCAN0TMID68 RSCAN0.TMID68.UINT32 -#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L] -#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL] -#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH] -#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H] -#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL] -#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH] -#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32 -#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L] -#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL] -#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH] -#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H] -#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL] -#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH] -#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32 -#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L] -#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL] -#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH] -#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H] -#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL] -#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH] -#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32 -#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L] -#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL] -#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH] -#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H] -#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL] -#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH] -#define RSCAN0TMID69 RSCAN0.TMID69.UINT32 -#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L] -#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL] -#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH] -#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H] -#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL] -#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH] -#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32 -#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L] -#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL] -#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH] -#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H] -#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL] -#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH] -#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32 -#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L] -#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL] -#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH] -#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H] -#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL] -#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH] -#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32 -#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L] -#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL] -#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH] -#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H] -#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL] -#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH] -#define RSCAN0TMID70 RSCAN0.TMID70.UINT32 -#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L] -#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL] -#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH] -#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H] -#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL] -#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH] -#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32 -#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L] -#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL] -#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH] -#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H] -#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL] -#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH] -#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32 -#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L] -#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL] -#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH] -#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H] -#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL] -#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH] -#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32 -#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L] -#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL] -#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH] -#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H] -#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL] -#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH] -#define RSCAN0TMID71 RSCAN0.TMID71.UINT32 -#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L] -#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL] -#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH] -#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H] -#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL] -#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH] -#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32 -#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L] -#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL] -#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH] -#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H] -#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL] -#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH] -#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32 -#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L] -#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL] -#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH] -#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H] -#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL] -#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH] -#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32 -#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L] -#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL] -#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH] -#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H] -#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL] -#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH] -#define RSCAN0TMID72 RSCAN0.TMID72.UINT32 -#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L] -#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL] -#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH] -#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H] -#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL] -#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH] -#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32 -#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L] -#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL] -#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH] -#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H] -#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL] -#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH] -#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32 -#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L] -#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL] -#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH] -#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H] -#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL] -#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH] -#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32 -#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L] -#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL] -#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH] -#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H] -#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL] -#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH] -#define RSCAN0TMID73 RSCAN0.TMID73.UINT32 -#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L] -#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL] -#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH] -#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H] -#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL] -#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH] -#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32 -#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L] -#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL] -#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH] -#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H] -#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL] -#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH] -#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32 -#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L] -#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL] -#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH] -#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H] -#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL] -#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH] -#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32 -#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L] -#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL] -#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH] -#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H] -#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL] -#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH] -#define RSCAN0TMID74 RSCAN0.TMID74.UINT32 -#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L] -#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL] -#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH] -#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H] -#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL] -#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH] -#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32 -#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L] -#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL] -#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH] -#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H] -#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL] -#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH] -#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32 -#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L] -#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL] -#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH] -#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H] -#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL] -#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH] -#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32 -#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L] -#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL] -#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH] -#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H] -#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL] -#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH] -#define RSCAN0TMID75 RSCAN0.TMID75.UINT32 -#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L] -#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL] -#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH] -#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H] -#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL] -#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH] -#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32 -#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L] -#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL] -#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH] -#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H] -#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL] -#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH] -#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32 -#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L] -#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL] -#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH] -#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H] -#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL] -#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH] -#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32 -#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L] -#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL] -#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH] -#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H] -#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL] -#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH] -#define RSCAN0TMID76 RSCAN0.TMID76.UINT32 -#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L] -#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL] -#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH] -#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H] -#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL] -#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH] -#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32 -#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L] -#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL] -#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH] -#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H] -#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL] -#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH] -#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32 -#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L] -#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL] -#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH] -#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H] -#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL] -#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH] -#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32 -#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L] -#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL] -#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH] -#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H] -#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL] -#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH] -#define RSCAN0TMID77 RSCAN0.TMID77.UINT32 -#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L] -#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL] -#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH] -#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H] -#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL] -#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH] -#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32 -#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L] -#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL] -#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH] -#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H] -#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL] -#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH] -#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32 -#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L] -#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL] -#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH] -#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H] -#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL] -#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH] -#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32 -#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L] -#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL] -#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH] -#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H] -#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL] -#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH] -#define RSCAN0TMID78 RSCAN0.TMID78.UINT32 -#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L] -#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL] -#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH] -#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H] -#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL] -#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH] -#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32 -#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L] -#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL] -#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH] -#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H] -#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL] -#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH] -#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32 -#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L] -#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL] -#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH] -#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H] -#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL] -#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH] -#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32 -#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L] -#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL] -#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH] -#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H] -#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL] -#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH] -#define RSCAN0TMID79 RSCAN0.TMID79.UINT32 -#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L] -#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL] -#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH] -#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H] -#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL] -#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH] -#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32 -#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L] -#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL] -#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH] -#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H] -#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL] -#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH] -#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32 -#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L] -#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL] -#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH] -#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H] -#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL] -#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH] -#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32 -#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L] -#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL] -#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH] -#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H] -#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL] -#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH] -#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32 -#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L] -#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL] -#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH] -#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H] -#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL] -#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH] -#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32 -#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L] -#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL] -#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH] -#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H] -#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL] -#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH] -#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32 -#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L] -#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL] -#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH] -#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H] -#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL] -#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH] -#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32 -#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L] -#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL] -#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH] -#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H] -#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL] -#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH] -#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32 -#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L] -#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL] -#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH] -#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H] -#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL] -#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH] /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h index 0fbd14e702..5c63e29346 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h @@ -18,27 +18,173 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rspi_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RSPI_IODEFINE_H #define RSPI_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -#include "reg32_t.h" +#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ +#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ +#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ +#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ +#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ -struct st_rspi -{ /* RSPI */ + +/* Start of channel array defines of RSPI */ + +/* Channel array defines of RSPI */ +/*(Sample) value = RSPI[ channel ]->SPCR; */ +#define RSPI_COUNT (5) +#define RSPI_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of RSPI */ + + +#define SPCR_0 (RSPI0.SPCR) +#define SSLP_0 (RSPI0.SSLP) +#define SPPCR_0 (RSPI0.SPPCR) +#define SPSR_0 (RSPI0.SPSR) +#define SPDR_0 (RSPI0.SPDR.UINT32) +#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L]) +#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H]) +#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL]) +#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH]) +#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL]) +#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH]) +#define SPSCR_0 (RSPI0.SPSCR) +#define SPSSR_0 (RSPI0.SPSSR) +#define SPBR_0 (RSPI0.SPBR) +#define SPDCR_0 (RSPI0.SPDCR) +#define SPCKD_0 (RSPI0.SPCKD) +#define SSLND_0 (RSPI0.SSLND) +#define SPND_0 (RSPI0.SPND) +#define SPCMD0_0 (RSPI0.SPCMD0) +#define SPCMD1_0 (RSPI0.SPCMD1) +#define SPCMD2_0 (RSPI0.SPCMD2) +#define SPCMD3_0 (RSPI0.SPCMD3) +#define SPBFCR_0 (RSPI0.SPBFCR) +#define SPBFDR_0 (RSPI0.SPBFDR) +#define SPCR_1 (RSPI1.SPCR) +#define SSLP_1 (RSPI1.SSLP) +#define SPPCR_1 (RSPI1.SPPCR) +#define SPSR_1 (RSPI1.SPSR) +#define SPDR_1 (RSPI1.SPDR.UINT32) +#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L]) +#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H]) +#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL]) +#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH]) +#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL]) +#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH]) +#define SPSCR_1 (RSPI1.SPSCR) +#define SPSSR_1 (RSPI1.SPSSR) +#define SPBR_1 (RSPI1.SPBR) +#define SPDCR_1 (RSPI1.SPDCR) +#define SPCKD_1 (RSPI1.SPCKD) +#define SSLND_1 (RSPI1.SSLND) +#define SPND_1 (RSPI1.SPND) +#define SPCMD0_1 (RSPI1.SPCMD0) +#define SPCMD1_1 (RSPI1.SPCMD1) +#define SPCMD2_1 (RSPI1.SPCMD2) +#define SPCMD3_1 (RSPI1.SPCMD3) +#define SPBFCR_1 (RSPI1.SPBFCR) +#define SPBFDR_1 (RSPI1.SPBFDR) +#define SPCR_2 (RSPI2.SPCR) +#define SSLP_2 (RSPI2.SSLP) +#define SPPCR_2 (RSPI2.SPPCR) +#define SPSR_2 (RSPI2.SPSR) +#define SPDR_2 (RSPI2.SPDR.UINT32) +#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L]) +#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H]) +#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL]) +#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH]) +#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL]) +#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH]) +#define SPSCR_2 (RSPI2.SPSCR) +#define SPSSR_2 (RSPI2.SPSSR) +#define SPBR_2 (RSPI2.SPBR) +#define SPDCR_2 (RSPI2.SPDCR) +#define SPCKD_2 (RSPI2.SPCKD) +#define SSLND_2 (RSPI2.SSLND) +#define SPND_2 (RSPI2.SPND) +#define SPCMD0_2 (RSPI2.SPCMD0) +#define SPCMD1_2 (RSPI2.SPCMD1) +#define SPCMD2_2 (RSPI2.SPCMD2) +#define SPCMD3_2 (RSPI2.SPCMD3) +#define SPBFCR_2 (RSPI2.SPBFCR) +#define SPBFDR_2 (RSPI2.SPBFDR) +#define SPCR_3 (RSPI3.SPCR) +#define SSLP_3 (RSPI3.SSLP) +#define SPPCR_3 (RSPI3.SPPCR) +#define SPSR_3 (RSPI3.SPSR) +#define SPDR_3 (RSPI3.SPDR.UINT32) +#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L]) +#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H]) +#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL]) +#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH]) +#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL]) +#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH]) +#define SPSCR_3 (RSPI3.SPSCR) +#define SPSSR_3 (RSPI3.SPSSR) +#define SPBR_3 (RSPI3.SPBR) +#define SPDCR_3 (RSPI3.SPDCR) +#define SPCKD_3 (RSPI3.SPCKD) +#define SSLND_3 (RSPI3.SSLND) +#define SPND_3 (RSPI3.SPND) +#define SPCMD0_3 (RSPI3.SPCMD0) +#define SPCMD1_3 (RSPI3.SPCMD1) +#define SPCMD2_3 (RSPI3.SPCMD2) +#define SPCMD3_3 (RSPI3.SPCMD3) +#define SPBFCR_3 (RSPI3.SPBFCR) +#define SPBFDR_3 (RSPI3.SPBFDR) +#define SPCR_4 (RSPI4.SPCR) +#define SSLP_4 (RSPI4.SSLP) +#define SPPCR_4 (RSPI4.SPPCR) +#define SPSR_4 (RSPI4.SPSR) +#define SPDR_4 (RSPI4.SPDR.UINT32) +#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L]) +#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H]) +#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL]) +#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH]) +#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL]) +#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH]) +#define SPSCR_4 (RSPI4.SPSCR) +#define SPSSR_4 (RSPI4.SPSSR) +#define SPBR_4 (RSPI4.SPBR) +#define SPDCR_4 (RSPI4.SPDCR) +#define SPCKD_4 (RSPI4.SPCKD) +#define SSLND_4 (RSPI4.SSLND) +#define SPND_4 (RSPI4.SPND) +#define SPCMD0_4 (RSPI4.SPCMD0) +#define SPCMD1_4 (RSPI4.SPCMD1) +#define SPCMD2_4 (RSPI4.SPCMD2) +#define SPCMD3_4 (RSPI4.SPCMD3) +#define SPBFCR_4 (RSPI4.SPBFCR) +#define SPBFDR_4 (RSPI4.SPBFDR) + +#define SPCMD_COUNT (4) + + +typedef struct st_rspi +{ + /* RSPI */ volatile uint8_t SPCR; /* SPCR */ volatile uint8_t SSLP; /* SSLP */ volatile uint8_t SPPCR; /* SPPCR */ volatile uint8_t SPSR; /* SPSR */ - union reg32_t SPDR; /* SPDR */ + union iodefine_reg32_t SPDR; /* SPDR */ volatile uint8_t SPSCR; /* SPSCR */ volatile uint8_t SPSSR; /* SPSSR */ @@ -48,7 +194,8 @@ struct st_rspi volatile uint8_t SSLND; /* SSLND */ volatile uint8_t SPND; /* SPND */ volatile uint8_t dummy1[1]; /* */ -#define SPCMD_COUNT 4 + +/* #define SPCMD_COUNT (4) */ volatile uint16_t SPCMD0; /* SPCMD0 */ volatile uint16_t SPCMD1; /* SPCMD1 */ volatile uint16_t SPCMD2; /* SPCMD2 */ @@ -57,148 +204,21 @@ struct st_rspi volatile uint8_t SPBFCR; /* SPBFCR */ volatile uint8_t dummy3[1]; /* */ volatile uint16_t SPBFDR; /* SPBFDR */ -}; +} r_io_rspi_t; -#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */ -#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */ -#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */ -#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */ -#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */ +/* Channel array defines of RSPI (2)*/ +#ifdef DECLARE_RSPI_CHANNELS +volatile struct st_rspi* RSPI[ RSPI_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + RSPI_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_RSPI_CHANNELS */ +/* End of channel array defines of RSPI (2)*/ -/* Start of channnel array defines of RSPI */ - -/* Channnel array defines of RSPI */ -/*(Sample) value = RSPI[ channel ]->SPCR; */ -#define RSPI_COUNT 5 -#define RSPI_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of RSPI */ - - -#define SPCR_0 RSPI0.SPCR -#define SSLP_0 RSPI0.SSLP -#define SPPCR_0 RSPI0.SPPCR -#define SPSR_0 RSPI0.SPSR -#define SPDR_0 RSPI0.SPDR.UINT32 -#define SPDR_0L RSPI0.SPDR.UINT16[L] -#define SPDR_0H RSPI0.SPDR.UINT16[H] -#define SPDR_0LL RSPI0.SPDR.UINT8[LL] -#define SPDR_0LH RSPI0.SPDR.UINT8[LH] -#define SPDR_0HL RSPI0.SPDR.UINT8[HL] -#define SPDR_0HH RSPI0.SPDR.UINT8[HH] -#define SPSCR_0 RSPI0.SPSCR -#define SPSSR_0 RSPI0.SPSSR -#define SPBR_0 RSPI0.SPBR -#define SPDCR_0 RSPI0.SPDCR -#define SPCKD_0 RSPI0.SPCKD -#define SSLND_0 RSPI0.SSLND -#define SPND_0 RSPI0.SPND -#define SPCMD0_0 RSPI0.SPCMD0 -#define SPCMD1_0 RSPI0.SPCMD1 -#define SPCMD2_0 RSPI0.SPCMD2 -#define SPCMD3_0 RSPI0.SPCMD3 -#define SPBFCR_0 RSPI0.SPBFCR -#define SPBFDR_0 RSPI0.SPBFDR -#define SPCR_1 RSPI1.SPCR -#define SSLP_1 RSPI1.SSLP -#define SPPCR_1 RSPI1.SPPCR -#define SPSR_1 RSPI1.SPSR -#define SPDR_1 RSPI1.SPDR.UINT32 -#define SPDR_1L RSPI1.SPDR.UINT16[L] -#define SPDR_1H RSPI1.SPDR.UINT16[H] -#define SPDR_1LL RSPI1.SPDR.UINT8[LL] -#define SPDR_1LH RSPI1.SPDR.UINT8[LH] -#define SPDR_1HL RSPI1.SPDR.UINT8[HL] -#define SPDR_1HH RSPI1.SPDR.UINT8[HH] -#define SPSCR_1 RSPI1.SPSCR -#define SPSSR_1 RSPI1.SPSSR -#define SPBR_1 RSPI1.SPBR -#define SPDCR_1 RSPI1.SPDCR -#define SPCKD_1 RSPI1.SPCKD -#define SSLND_1 RSPI1.SSLND -#define SPND_1 RSPI1.SPND -#define SPCMD0_1 RSPI1.SPCMD0 -#define SPCMD1_1 RSPI1.SPCMD1 -#define SPCMD2_1 RSPI1.SPCMD2 -#define SPCMD3_1 RSPI1.SPCMD3 -#define SPBFCR_1 RSPI1.SPBFCR -#define SPBFDR_1 RSPI1.SPBFDR -#define SPCR_2 RSPI2.SPCR -#define SSLP_2 RSPI2.SSLP -#define SPPCR_2 RSPI2.SPPCR -#define SPSR_2 RSPI2.SPSR -#define SPDR_2 RSPI2.SPDR.UINT32 -#define SPDR_2L RSPI2.SPDR.UINT16[L] -#define SPDR_2H RSPI2.SPDR.UINT16[H] -#define SPDR_2LL RSPI2.SPDR.UINT8[LL] -#define SPDR_2LH RSPI2.SPDR.UINT8[LH] -#define SPDR_2HL RSPI2.SPDR.UINT8[HL] -#define SPDR_2HH RSPI2.SPDR.UINT8[HH] -#define SPSCR_2 RSPI2.SPSCR -#define SPSSR_2 RSPI2.SPSSR -#define SPBR_2 RSPI2.SPBR -#define SPDCR_2 RSPI2.SPDCR -#define SPCKD_2 RSPI2.SPCKD -#define SSLND_2 RSPI2.SSLND -#define SPND_2 RSPI2.SPND -#define SPCMD0_2 RSPI2.SPCMD0 -#define SPCMD1_2 RSPI2.SPCMD1 -#define SPCMD2_2 RSPI2.SPCMD2 -#define SPCMD3_2 RSPI2.SPCMD3 -#define SPBFCR_2 RSPI2.SPBFCR -#define SPBFDR_2 RSPI2.SPBFDR -#define SPCR_3 RSPI3.SPCR -#define SSLP_3 RSPI3.SSLP -#define SPPCR_3 RSPI3.SPPCR -#define SPSR_3 RSPI3.SPSR -#define SPDR_3 RSPI3.SPDR.UINT32 -#define SPDR_3L RSPI3.SPDR.UINT16[L] -#define SPDR_3H RSPI3.SPDR.UINT16[H] -#define SPDR_3LL RSPI3.SPDR.UINT8[LL] -#define SPDR_3LH RSPI3.SPDR.UINT8[LH] -#define SPDR_3HL RSPI3.SPDR.UINT8[HL] -#define SPDR_3HH RSPI3.SPDR.UINT8[HH] -#define SPSCR_3 RSPI3.SPSCR -#define SPSSR_3 RSPI3.SPSSR -#define SPBR_3 RSPI3.SPBR -#define SPDCR_3 RSPI3.SPDCR -#define SPCKD_3 RSPI3.SPCKD -#define SSLND_3 RSPI3.SSLND -#define SPND_3 RSPI3.SPND -#define SPCMD0_3 RSPI3.SPCMD0 -#define SPCMD1_3 RSPI3.SPCMD1 -#define SPCMD2_3 RSPI3.SPCMD2 -#define SPCMD3_3 RSPI3.SPCMD3 -#define SPBFCR_3 RSPI3.SPBFCR -#define SPBFDR_3 RSPI3.SPBFDR -#define SPCR_4 RSPI4.SPCR -#define SSLP_4 RSPI4.SSLP -#define SPPCR_4 RSPI4.SPPCR -#define SPSR_4 RSPI4.SPSR -#define SPDR_4 RSPI4.SPDR.UINT32 -#define SPDR_4L RSPI4.SPDR.UINT16[L] -#define SPDR_4H RSPI4.SPDR.UINT16[H] -#define SPDR_4LL RSPI4.SPDR.UINT8[LL] -#define SPDR_4LH RSPI4.SPDR.UINT8[LH] -#define SPDR_4HL RSPI4.SPDR.UINT8[HL] -#define SPDR_4HH RSPI4.SPDR.UINT8[HH] -#define SPSCR_4 RSPI4.SPSCR -#define SPSSR_4 RSPI4.SPSSR -#define SPBR_4 RSPI4.SPBR -#define SPDCR_4 RSPI4.SPDCR -#define SPCKD_4 RSPI4.SPCKD -#define SSLND_4 RSPI4.SSLND -#define SPND_4 RSPI4.SPND -#define SPCMD0_4 RSPI4.SPCMD0 -#define SPCMD1_4 RSPI4.SPCMD1 -#define SPCMD2_4 RSPI4.SPCMD2 -#define SPCMD3_4 RSPI4.SPCMD3 -#define SPBFCR_4 RSPI4.SPBFCR -#define SPBFDR_4 RSPI4.SPBFDR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h index 6cfb46dde3..1df2c7c3d1 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h @@ -18,20 +18,50 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : rtc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef RTC_IODEFINE_H #define RTC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_rtc -{ /* RTC */ +#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ + + +#define RTCR64CNT (RTC.R64CNT) +#define RTCRSECCNT (RTC.RSECCNT) +#define RTCRMINCNT (RTC.RMINCNT) +#define RTCRHRCNT (RTC.RHRCNT) +#define RTCRWKCNT (RTC.RWKCNT) +#define RTCRDAYCNT (RTC.RDAYCNT) +#define RTCRMONCNT (RTC.RMONCNT) +#define RTCRYRCNT (RTC.RYRCNT) +#define RTCRSECAR (RTC.RSECAR) +#define RTCRMINAR (RTC.RMINAR) +#define RTCRHRAR (RTC.RHRAR) +#define RTCRWKAR (RTC.RWKAR) +#define RTCRDAYAR (RTC.RDAYAR) +#define RTCRMONAR (RTC.RMONAR) +#define RTCRCR1 (RTC.RCR1) +#define RTCRCR2 (RTC.RCR2) +#define RTCRYRAR (RTC.RYRAR) +#define RTCRCR3 (RTC.RCR3) +#define RTCRCR5 (RTC.RCR5) +#define RTCRFRH (RTC.RFRH) +#define RTCRFRL (RTC.RFRL) + + +typedef struct st_rtc +{ + /* RTC */ volatile uint8_t R64CNT; /* R64CNT */ volatile uint8_t dummy537[1]; /* */ volatile uint8_t RSECCNT; /* RSECCNT */ @@ -71,32 +101,11 @@ struct st_rtc volatile uint8_t dummy554[3]; /* */ volatile uint16_t RFRH; /* RFRH */ volatile uint16_t RFRL; /* RFRL */ -}; +} r_io_rtc_t; -#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */ - - -#define RTCR64CNT RTC.R64CNT -#define RTCRSECCNT RTC.RSECCNT -#define RTCRMINCNT RTC.RMINCNT -#define RTCRHRCNT RTC.RHRCNT -#define RTCRWKCNT RTC.RWKCNT -#define RTCRDAYCNT RTC.RDAYCNT -#define RTCRMONCNT RTC.RMONCNT -#define RTCRYRCNT RTC.RYRCNT -#define RTCRSECAR RTC.RSECAR -#define RTCRMINAR RTC.RMINAR -#define RTCRHRAR RTC.RHRAR -#define RTCRWKAR RTC.RWKAR -#define RTCRDAYAR RTC.RDAYAR -#define RTCRMONAR RTC.RMONAR -#define RTCRCR1 RTC.RCR1 -#define RTCRCR2 RTC.RCR2 -#define RTCRYRAR RTC.RYRAR -#define RTCRCR3 RTC.RCR3 -#define RTCRCR5 RTC.RCR5 -#define RTCRFRH RTC.RFRH -#define RTCRFRL RTC.RFRL /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h index 9a710604ce..de594577e2 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h @@ -18,21 +18,137 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCIF_IODEFINE_H #define SCIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ /* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scif -{ /* SCIF */ +#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ +#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ +#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ +#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ +#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ +#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ +#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ +#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ + + +/* Start of channel array defines of SCIF */ + +/* Channel array defines of SCIF */ +/*(Sample) value = SCIF[ channel ]->SCSMR; */ +#define SCIF_COUNT (8) +#define SCIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIF */ + + +#define SCSMR_0 (SCIF0.SCSMR) +#define SCBRR_0 (SCIF0.SCBRR) +#define SCSCR_0 (SCIF0.SCSCR) +#define SCFTDR_0 (SCIF0.SCFTDR) +#define SCFSR_0 (SCIF0.SCFSR) +#define SCFRDR_0 (SCIF0.SCFRDR) +#define SCFCR_0 (SCIF0.SCFCR) +#define SCFDR_0 (SCIF0.SCFDR) +#define SCSPTR_0 (SCIF0.SCSPTR) +#define SCLSR_0 (SCIF0.SCLSR) +#define SCEMR_0 (SCIF0.SCEMR) +#define SCSMR_1 (SCIF1.SCSMR) +#define SCBRR_1 (SCIF1.SCBRR) +#define SCSCR_1 (SCIF1.SCSCR) +#define SCFTDR_1 (SCIF1.SCFTDR) +#define SCFSR_1 (SCIF1.SCFSR) +#define SCFRDR_1 (SCIF1.SCFRDR) +#define SCFCR_1 (SCIF1.SCFCR) +#define SCFDR_1 (SCIF1.SCFDR) +#define SCSPTR_1 (SCIF1.SCSPTR) +#define SCLSR_1 (SCIF1.SCLSR) +#define SCEMR_1 (SCIF1.SCEMR) +#define SCSMR_2 (SCIF2.SCSMR) +#define SCBRR_2 (SCIF2.SCBRR) +#define SCSCR_2 (SCIF2.SCSCR) +#define SCFTDR_2 (SCIF2.SCFTDR) +#define SCFSR_2 (SCIF2.SCFSR) +#define SCFRDR_2 (SCIF2.SCFRDR) +#define SCFCR_2 (SCIF2.SCFCR) +#define SCFDR_2 (SCIF2.SCFDR) +#define SCSPTR_2 (SCIF2.SCSPTR) +#define SCLSR_2 (SCIF2.SCLSR) +#define SCEMR_2 (SCIF2.SCEMR) +#define SCSMR_3 (SCIF3.SCSMR) +#define SCBRR_3 (SCIF3.SCBRR) +#define SCSCR_3 (SCIF3.SCSCR) +#define SCFTDR_3 (SCIF3.SCFTDR) +#define SCFSR_3 (SCIF3.SCFSR) +#define SCFRDR_3 (SCIF3.SCFRDR) +#define SCFCR_3 (SCIF3.SCFCR) +#define SCFDR_3 (SCIF3.SCFDR) +#define SCSPTR_3 (SCIF3.SCSPTR) +#define SCLSR_3 (SCIF3.SCLSR) +#define SCEMR_3 (SCIF3.SCEMR) +#define SCSMR_4 (SCIF4.SCSMR) +#define SCBRR_4 (SCIF4.SCBRR) +#define SCSCR_4 (SCIF4.SCSCR) +#define SCFTDR_4 (SCIF4.SCFTDR) +#define SCFSR_4 (SCIF4.SCFSR) +#define SCFRDR_4 (SCIF4.SCFRDR) +#define SCFCR_4 (SCIF4.SCFCR) +#define SCFDR_4 (SCIF4.SCFDR) +#define SCSPTR_4 (SCIF4.SCSPTR) +#define SCLSR_4 (SCIF4.SCLSR) +#define SCEMR_4 (SCIF4.SCEMR) +#define SCSMR_5 (SCIF5.SCSMR) +#define SCBRR_5 (SCIF5.SCBRR) +#define SCSCR_5 (SCIF5.SCSCR) +#define SCFTDR_5 (SCIF5.SCFTDR) +#define SCFSR_5 (SCIF5.SCFSR) +#define SCFRDR_5 (SCIF5.SCFRDR) +#define SCFCR_5 (SCIF5.SCFCR) +#define SCFDR_5 (SCIF5.SCFDR) +#define SCSPTR_5 (SCIF5.SCSPTR) +#define SCLSR_5 (SCIF5.SCLSR) +#define SCEMR_5 (SCIF5.SCEMR) +#define SCSMR_6 (SCIF6.SCSMR) +#define SCBRR_6 (SCIF6.SCBRR) +#define SCSCR_6 (SCIF6.SCSCR) +#define SCFTDR_6 (SCIF6.SCFTDR) +#define SCFSR_6 (SCIF6.SCFSR) +#define SCFRDR_6 (SCIF6.SCFRDR) +#define SCFCR_6 (SCIF6.SCFCR) +#define SCFDR_6 (SCIF6.SCFDR) +#define SCSPTR_6 (SCIF6.SCSPTR) +#define SCLSR_6 (SCIF6.SCLSR) +#define SCEMR_6 (SCIF6.SCEMR) +#define SCSMR_7 (SCIF7.SCSMR) +#define SCBRR_7 (SCIF7.SCBRR) +#define SCSCR_7 (SCIF7.SCSCR) +#define SCFTDR_7 (SCIF7.SCFTDR) +#define SCFSR_7 (SCIF7.SCFSR) +#define SCFRDR_7 (SCIF7.SCFRDR) +#define SCFCR_7 (SCIF7.SCFCR) +#define SCFDR_7 (SCIF7.SCFDR) +#define SCSPTR_7 (SCIF7.SCSPTR) +#define SCLSR_7 (SCIF7.SCLSR) +#define SCEMR_7 (SCIF7.SCEMR) + + +typedef struct st_scif +{ + /* SCIF */ volatile uint16_t SCSMR; /* SCSMR */ volatile uint8_t dummy1[2]; /* */ volatile uint8_t SCBRR; /* SCBRR */ @@ -54,129 +170,21 @@ struct st_scif volatile uint16_t SCLSR; /* SCLSR */ volatile uint8_t dummy10[2]; /* */ volatile uint16_t SCEMR; /* SCEMR */ -}; +} r_io_scif_t; -#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */ -#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */ -#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */ -#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */ -#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */ -#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */ -#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */ -#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */ - -#define P_SCIF0 (0xE8007000uL) /* SCIF0 */ -#define P_SCIF1 (0xE8007800uL) /* SCIF1 */ -#define P_SCIF2 (0xE8008000uL) /* SCIF2 */ -#define P_SCIF3 (0xE8008800uL) /* SCIF3 */ -#define P_SCIF4 (0xE8009000uL) /* SCIF4 */ -#define P_SCIF5 (0xE8009800uL) /* SCIF5 */ -#define P_SCIF6 (0xE800A000uL) /* SCIF6 */ -#define P_SCIF7 (0xE800A800uL) /* SCIF7 */ +/* Channel array defines of SCIF (2)*/ +#ifdef DECLARE_SCIF_CHANNELS +volatile struct st_scif* SCIF[ SCIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIF_CHANNELS */ +/* End of channel array defines of SCIF (2)*/ -/* Start of channnel array defines of SCIF */ - -/* Channnel array defines of SCIF */ -/*(Sample) value = SCIF[ channel ]->SCSMR; */ -#define SCIF_COUNT 8 -#define SCIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SCIF */ - - -#define SCSMR_0 SCIF0.SCSMR -#define SCBRR_0 SCIF0.SCBRR -#define SCSCR_0 SCIF0.SCSCR -#define SCFTDR_0 SCIF0.SCFTDR -#define SCFSR_0 SCIF0.SCFSR -#define SCFRDR_0 SCIF0.SCFRDR -#define SCFCR_0 SCIF0.SCFCR -#define SCFDR_0 SCIF0.SCFDR -#define SCSPTR_0 SCIF0.SCSPTR -#define SCLSR_0 SCIF0.SCLSR -#define SCEMR_0 SCIF0.SCEMR -#define SCSMR_1 SCIF1.SCSMR -#define SCBRR_1 SCIF1.SCBRR -#define SCSCR_1 SCIF1.SCSCR -#define SCFTDR_1 SCIF1.SCFTDR -#define SCFSR_1 SCIF1.SCFSR -#define SCFRDR_1 SCIF1.SCFRDR -#define SCFCR_1 SCIF1.SCFCR -#define SCFDR_1 SCIF1.SCFDR -#define SCSPTR_1 SCIF1.SCSPTR -#define SCLSR_1 SCIF1.SCLSR -#define SCEMR_1 SCIF1.SCEMR -#define SCSMR_2 SCIF2.SCSMR -#define SCBRR_2 SCIF2.SCBRR -#define SCSCR_2 SCIF2.SCSCR -#define SCFTDR_2 SCIF2.SCFTDR -#define SCFSR_2 SCIF2.SCFSR -#define SCFRDR_2 SCIF2.SCFRDR -#define SCFCR_2 SCIF2.SCFCR -#define SCFDR_2 SCIF2.SCFDR -#define SCSPTR_2 SCIF2.SCSPTR -#define SCLSR_2 SCIF2.SCLSR -#define SCEMR_2 SCIF2.SCEMR -#define SCSMR_3 SCIF3.SCSMR -#define SCBRR_3 SCIF3.SCBRR -#define SCSCR_3 SCIF3.SCSCR -#define SCFTDR_3 SCIF3.SCFTDR -#define SCFSR_3 SCIF3.SCFSR -#define SCFRDR_3 SCIF3.SCFRDR -#define SCFCR_3 SCIF3.SCFCR -#define SCFDR_3 SCIF3.SCFDR -#define SCSPTR_3 SCIF3.SCSPTR -#define SCLSR_3 SCIF3.SCLSR -#define SCEMR_3 SCIF3.SCEMR -#define SCSMR_4 SCIF4.SCSMR -#define SCBRR_4 SCIF4.SCBRR -#define SCSCR_4 SCIF4.SCSCR -#define SCFTDR_4 SCIF4.SCFTDR -#define SCFSR_4 SCIF4.SCFSR -#define SCFRDR_4 SCIF4.SCFRDR -#define SCFCR_4 SCIF4.SCFCR -#define SCFDR_4 SCIF4.SCFDR -#define SCSPTR_4 SCIF4.SCSPTR -#define SCLSR_4 SCIF4.SCLSR -#define SCEMR_4 SCIF4.SCEMR -#define SCSMR_5 SCIF5.SCSMR -#define SCBRR_5 SCIF5.SCBRR -#define SCSCR_5 SCIF5.SCSCR -#define SCFTDR_5 SCIF5.SCFTDR -#define SCFSR_5 SCIF5.SCFSR -#define SCFRDR_5 SCIF5.SCFRDR -#define SCFCR_5 SCIF5.SCFCR -#define SCFDR_5 SCIF5.SCFDR -#define SCSPTR_5 SCIF5.SCSPTR -#define SCLSR_5 SCIF5.SCLSR -#define SCEMR_5 SCIF5.SCEMR -#define SCSMR_6 SCIF6.SCSMR -#define SCBRR_6 SCIF6.SCBRR -#define SCSCR_6 SCIF6.SCSCR -#define SCFTDR_6 SCIF6.SCFTDR -#define SCFSR_6 SCIF6.SCFSR -#define SCFRDR_6 SCIF6.SCFRDR -#define SCFCR_6 SCIF6.SCFCR -#define SCFDR_6 SCIF6.SCFDR -#define SCSPTR_6 SCIF6.SCSPTR -#define SCLSR_6 SCIF6.SCLSR -#define SCEMR_6 SCIF6.SCEMR -#define SCSMR_7 SCIF7.SCSMR -#define SCBRR_7 SCIF7.SCBRR -#define SCSCR_7 SCIF7.SCSCR -#define SCFTDR_7 SCIF7.SCFTDR -#define SCFSR_7 SCIF7.SCFSR -#define SCFRDR_7 SCIF7.SCFRDR -#define SCFCR_7 SCIF7.SCFCR -#define SCFDR_7 SCIF7.SCFDR -#define SCSPTR_7 SCIF7.SCSPTR -#define SCLSR_7 SCIF7.SCLSR -#define SCEMR_7 SCIF7.SCEMR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ /* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h index 2ddf1e61d9..fad306aca1 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h @@ -18,20 +18,63 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scim_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCIM_IODEFINE_H #define SCIM_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scim -{ /* SCIM */ +#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ +#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ + + +/* Start of channel array defines of SCIM */ + +/* Channel array defines of SCIM */ +/*(Sample) value = SCIM[ channel ]->SMR; */ +#define SCIM_COUNT (2) +#define SCIM_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCIM0, &SCIM1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SCIM */ + + +#define SMR0 (SCIM0.SMR) +#define BRR0 (SCIM0.BRR) +#define SCR0 (SCIM0.SCR) +#define TDR0 (SCIM0.TDR) +#define SSR0 (SCIM0.SSR) +#define RDR0 (SCIM0.RDR) +#define SCMR0 (SCIM0.SCMR) +#define SEMR0 (SCIM0.SEMR) +#define SNFR0 (SCIM0.SNFR) +#define SECR0 (SCIM0.SECR) +#define SMR1 (SCIM1.SMR) +#define BRR1 (SCIM1.BRR) +#define SCR1 (SCIM1.SCR) +#define TDR1 (SCIM1.TDR) +#define SSR1 (SCIM1.SSR) +#define RDR1 (SCIM1.RDR) +#define SCMR1 (SCIM1.SCMR) +#define SEMR1 (SCIM1.SEMR) +#define SNFR1 (SCIM1.SNFR) +#define SECR1 (SCIM1.SECR) + + +typedef struct st_scim +{ + /* SCIM */ volatile uint8_t SMR; /* SMR */ volatile uint8_t BRR; /* BRR */ volatile uint8_t SCR; /* SCR */ @@ -43,45 +86,21 @@ struct st_scim volatile uint8_t SNFR; /* SNFR */ volatile uint8_t dummy1[4]; /* */ volatile uint8_t SECR; /* SECR */ -}; +} r_io_scim_t; -#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */ -#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */ +/* Channel array defines of SCIM (2)*/ +#ifdef DECLARE_SCIM_CHANNELS +volatile struct st_scim* SCIM[ SCIM_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCIM_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCIM_CHANNELS */ +/* End of channel array defines of SCIM (2)*/ -/* Start of channnel array defines of SCIM */ - -/* Channnel array defines of SCIM */ -/*(Sample) value = SCIM[ channel ]->SMR; */ -#define SCIM_COUNT 2 -#define SCIM_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCIM0, &SCIM1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SCIM */ - - -#define SMR0 SCIM0.SMR -#define BRR0 SCIM0.BRR -#define SCR0 SCIM0.SCR -#define TDR0 SCIM0.TDR -#define SSR0 SCIM0.SSR -#define RDR0 SCIM0.RDR -#define SCMR0 SCIM0.SCMR -#define SEMR0 SCIM0.SEMR -#define SNFR0 SCIM0.SNFR -#define SECR0 SCIM0.SECR -#define SMR1 SCIM1.SMR -#define BRR1 SCIM1.BRR -#define SCR1 SCIM1.SCR -#define TDR1 SCIM1.TDR -#define SSR1 SCIM1.SSR -#define RDR1 SCIM1.RDR -#define SCMR1 SCIM1.SCMR -#define SEMR1 SCIM1.SEMR -#define SNFR1 SCIM1.SNFR -#define SECR1 SCIM1.SECR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h index a6d5646dcc..4293ec4277 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h @@ -18,61 +18,427 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : scux_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SCUX_IODEFINE_H #define SCUX_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_scux -{ /* SCUX */ +#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ + + +/* Start of channel array defines of SCUX */ + +/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ +#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ +#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ +#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ + + +/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2) +#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ +#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ + + +/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ +#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ +#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ +#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ + + +/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4) +#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ +#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ +#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ +#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ + + +/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ +#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ +#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ +#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ + + +/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ +/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4) +#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ +#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ +#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ +#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ + +/* End of channel array defines of SCUX */ + + +#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0) +#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0) +#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1) +#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1) +#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2) +#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2) +#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3) +#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3) +#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0) +#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0) +#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1) +#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1) +#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2) +#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2) +#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3) +#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3) +#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0) +#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0) +#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0) +#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0) +#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0) +#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0) +#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0) +#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1) +#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1) +#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1) +#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1) +#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1) +#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1) +#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1) +#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2) +#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2) +#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2) +#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2) +#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2) +#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2) +#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2) +#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3) +#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3) +#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3) +#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3) +#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3) +#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3) +#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3) +#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0) +#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0) +#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0) +#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0) +#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0) +#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0) +#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1) +#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1) +#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1) +#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1) +#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1) +#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1) +#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2) +#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2) +#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2) +#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2) +#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2) +#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2) +#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3) +#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3) +#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3) +#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3) +#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3) +#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3) +#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0) +#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0) +#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0) +#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0) +#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0) +#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0) +#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0) +#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0) +#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0) +#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0) +#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0) +#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0) +#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0) +#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0) +#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0) +#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0) +#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0) +#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0) +#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0) +#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0) +#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0) +#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0) +#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0) +#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0) +#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0) +#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1) +#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1) +#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1) +#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1) +#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1) +#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1) +#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1) +#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1) +#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1) +#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1) +#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1) +#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1) +#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1) +#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1) +#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1) +#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1) +#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1) +#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1) +#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1) +#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1) +#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1) +#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1) +#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1) +#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1) +#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1) +#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0) +#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0) +#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0) +#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0) +#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0) +#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0) +#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0) +#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0) +#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0) +#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0) +#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0) +#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0) +#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0) +#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0) +#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0) +#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0) +#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0) +#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0) +#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0) +#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0) +#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0) +#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1) +#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1) +#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1) +#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1) +#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1) +#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1) +#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1) +#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1) +#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1) +#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1) +#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1) +#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1) +#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1) +#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1) +#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1) +#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1) +#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1) +#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1) +#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1) +#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1) +#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1) +#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2) +#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2) +#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2) +#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2) +#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2) +#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2) +#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2) +#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2) +#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2) +#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2) +#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2) +#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2) +#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2) +#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2) +#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2) +#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2) +#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2) +#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2) +#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2) +#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2) +#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2) +#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3) +#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3) +#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3) +#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3) +#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3) +#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3) +#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3) +#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3) +#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3) +#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3) +#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3) +#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3) +#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3) +#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3) +#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3) +#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3) +#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3) +#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3) +#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3) +#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3) +#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3) +#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0) +#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0) +#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0) +#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0) +#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0) +#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0) +#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0) +#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0) +#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0) +#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0) +#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0) +#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM) +#define SCUXDMACR_CIM (SCUX.DMACR_CIM) +#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32) +#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L]) +#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H]) +#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32) +#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L]) +#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H]) +#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32) +#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L]) +#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H]) +#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32) +#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L]) +#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H]) +#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32) +#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L]) +#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H]) +#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32) +#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L]) +#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H]) +#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32) +#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L]) +#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H]) +#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32) +#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L]) +#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H]) +#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM) +#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM) +#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM) +#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM) +#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM) +#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM) +#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM) +#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM) +#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM) +#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM) +#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM) +#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM) +#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM) +#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM) +#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM) +#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM) + +#define SCUX_DMATDnCIM_COUNT (4) +#define SCUX_DMATUnCIM_COUNT (4) +#define SCUX_FDTSELnCIM_COUNT (4) +#define SCUX_FUTSELnCIM_COUNT (4) +#define SCUX_SRCRSELnCIM_COUNT (4) + + +typedef struct st_scux +{ + /* SCUX */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ volatile uint8_t dummy259[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */ volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */ volatile uint8_t dummy260[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */ volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */ volatile uint8_t dummy261[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_ipcir_ipc0_n */ volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */ volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */ volatile uint8_t dummy262[248]; /* */ + /* end of struct st_scux_from_ipcir_ipc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ volatile uint8_t dummy263[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */ volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */ volatile uint8_t dummy264[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */ volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */ volatile uint8_t dummy265[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_opcir_opc0_n */ volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */ volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */ volatile uint8_t dummy266[248]; /* */ + /* end of struct st_scux_from_opcir_opc0_n */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ @@ -82,8 +448,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ volatile uint8_t dummy267[4]; /* */ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy268[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */ volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */ @@ -93,8 +461,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */ volatile uint8_t dummy269[4]; /* */ volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy270[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */ volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */ @@ -104,8 +474,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */ volatile uint8_t dummy271[4]; /* */ volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy272[224]; /* */ + /* start of struct st_scux_from_ffdir_ffd0_n */ volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */ volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */ @@ -115,8 +487,10 @@ struct st_scux volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */ volatile uint8_t dummy273[4]; /* */ volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */ + /* end of struct st_scux_from_ffdir_ffd0_n */ volatile uint8_t dummy274[224]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ @@ -125,8 +499,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ volatile uint8_t dummy275[4]; /* */ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy276[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */ volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */ @@ -135,8 +511,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */ volatile uint8_t dummy277[4]; /* */ volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy278[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */ volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */ @@ -145,8 +523,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */ volatile uint8_t dummy279[4]; /* */ volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy280[228]; /* */ + /* start of struct st_scux_from_ffuir_ffu0_n */ volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */ volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */ @@ -155,8 +535,10 @@ struct st_scux volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */ volatile uint8_t dummy281[4]; /* */ volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */ + /* end of struct st_scux_from_ffuir_ffu0_n */ volatile uint8_t dummy282[228]; /* */ + /* start of struct st_scux_from_srcir0_2src0_n */ volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ @@ -185,8 +567,10 @@ struct st_scux volatile uint8_t dummy284[4]; /* */ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ + /* end of struct st_scux_from_srcir0_2src0_n */ volatile uint8_t dummy285[148]; /* */ + /* start of struct st_scux_from_srcir0_2src0_n */ volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */ volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */ @@ -215,8 +599,10 @@ struct st_scux volatile uint8_t dummy287[4]; /* */ volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */ volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */ + /* end of struct st_scux_from_srcir0_2src0_n */ volatile uint8_t dummy288[148]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ @@ -240,8 +626,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ volatile uint8_t dummy289[4]; /* */ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy290[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */ volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */ @@ -265,8 +653,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */ volatile uint8_t dummy291[4]; /* */ volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy292[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */ volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */ @@ -290,8 +680,10 @@ struct st_scux volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */ volatile uint8_t dummy293[4]; /* */ volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy294[168]; /* */ + /* start of struct st_scux_from_dvuir_dvu0_n */ volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */ volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */ @@ -315,6 +707,7 @@ struct st_scux volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */ volatile uint8_t dummy295[4]; /* */ volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */ + /* end of struct st_scux_from_dvuir_dvu0_n */ volatile uint8_t dummy296[168]; /* */ volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */ @@ -331,12 +724,14 @@ struct st_scux volatile uint8_t dummy297[212]; /* */ volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */ volatile uint32_t DMACR_CIM; /* DMACR_CIM */ -#define SCUX_DMATDn_CIM_COUNT 4 + +/* #define SCUX_DMATDnCIM_COUNT (4) */ union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */ union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */ union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */ union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */ -#define SCUX_DMATUn_CIM_COUNT 4 + +/* #define SCUX_DMATUnCIM_COUNT (4) */ union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */ union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */ union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */ @@ -344,45 +739,51 @@ struct st_scux volatile uint8_t dummy298[16]; /* */ volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */ -#define SCUX_FDTSELn_CIM_COUNT 4 + +/* #define SCUX_FDTSELnCIM_COUNT (4) */ volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */ volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */ volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */ volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */ -#define SCUX_FUTSELn_CIM_COUNT 4 + +/* #define SCUX_FUTSELnCIM_COUNT (4) */ volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */ volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */ volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */ volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */ volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */ volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */ -#define SCUX_SRCRSELn_CIM_COUNT 4 + +/* #define SCUX_SRCRSELnCIM_COUNT (4) */ volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */ volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */ volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */ volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */ volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */ -}; +} r_io_scux_t; -struct st_scux_from_ipcir_ipc0_n +typedef struct st_scux_from_ipcir_ipc0_n { + volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */ volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */ volatile uint8_t dummy1[248]; /* */ -}; +} r_io_scux_from_ipcir_ipc0_n_t; -struct st_scux_from_opcir_opc0_n +typedef struct st_scux_from_opcir_opc0_n { + volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */ volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */ volatile uint8_t dummy1[248]; /* */ -}; +} r_io_scux_from_opcir_opc0_n_t; -struct st_scux_from_ffdir_ffd0_n +typedef struct st_scux_from_ffdir_ffd0_n { + volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */ volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */ volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */ @@ -391,11 +792,12 @@ struct st_scux_from_ffdir_ffd0_n volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */ -}; +} r_io_scux_from_ffdir_ffd0_n_t; -struct st_scux_from_ffuir_ffu0_n +typedef struct st_scux_from_ffuir_ffu0_n { + volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */ volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */ volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */ @@ -403,11 +805,12 @@ struct st_scux_from_ffuir_ffu0_n volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */ -}; +} r_io_scux_from_ffuir_ffu0_n_t; -struct st_scux_from_srcir0_2src0_n +typedef struct st_scux_from_srcir0_2src0_n { + volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */ volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */ volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */ @@ -435,11 +838,12 @@ struct st_scux_from_srcir0_2src0_n volatile uint8_t dummy2[4]; /* */ volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */ volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */ -}; +} r_io_scux_from_srcir0_2src0_n_t; -struct st_scux_from_dvuir_dvu0_n +typedef struct st_scux_from_dvuir_dvu0_n { + volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */ volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */ volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */ @@ -462,347 +866,56 @@ struct st_scux_from_dvuir_dvu0_n volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */ volatile uint8_t dummy1[4]; /* */ volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */ -}; +} r_io_scux_from_dvuir_dvu0_n_t; -#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */ +/* Channel array defines of SCUX (2)*/ +#ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */ + +#ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS +volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */ +/* End of channel array defines of SCUX (2)*/ -/* Start of channnel array defines of SCUX */ - -/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */ -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4 -#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */ -#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */ -#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */ -#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */ - - -/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */ -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2 -#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */ -#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */ - - -/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */ -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4 -#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */ -#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */ -#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */ -#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */ - - -/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */ -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4 -#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */ -#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */ -#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */ -#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */ - - -/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */ -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4 -#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */ -#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */ -#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */ -#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */ - - -/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */ -/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */ -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4 -#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */ -#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */ -#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */ -#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */ - -/* End of channnel array defines of SCUX */ - - -#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0 -#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0 -#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1 -#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1 -#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2 -#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2 -#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3 -#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3 -#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0 -#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0 -#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1 -#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1 -#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2 -#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2 -#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3 -#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3 -#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0 -#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0 -#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0 -#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0 -#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0 -#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0 -#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0 -#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1 -#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1 -#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1 -#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1 -#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1 -#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1 -#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1 -#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2 -#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2 -#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2 -#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2 -#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2 -#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2 -#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2 -#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3 -#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3 -#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3 -#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3 -#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3 -#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3 -#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3 -#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0 -#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0 -#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0 -#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0 -#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0 -#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0 -#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1 -#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1 -#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1 -#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1 -#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1 -#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1 -#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2 -#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2 -#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2 -#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2 -#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2 -#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2 -#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3 -#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3 -#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3 -#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3 -#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3 -#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3 -#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0 -#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0 -#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0 -#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0 -#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0 -#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0 -#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0 -#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0 -#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0 -#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0 -#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0 -#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0 -#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0 -#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0 -#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0 -#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0 -#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0 -#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0 -#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0 -#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0 -#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0 -#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0 -#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0 -#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0 -#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0 -#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1 -#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1 -#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1 -#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1 -#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1 -#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1 -#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1 -#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1 -#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1 -#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1 -#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1 -#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1 -#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1 -#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1 -#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1 -#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1 -#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1 -#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1 -#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1 -#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1 -#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1 -#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1 -#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1 -#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1 -#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1 -#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0 -#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0 -#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0 -#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0 -#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0 -#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0 -#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0 -#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0 -#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0 -#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0 -#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0 -#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0 -#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0 -#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0 -#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0 -#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0 -#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0 -#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0 -#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0 -#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0 -#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0 -#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1 -#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1 -#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1 -#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1 -#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1 -#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1 -#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1 -#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1 -#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1 -#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1 -#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1 -#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1 -#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1 -#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1 -#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1 -#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1 -#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1 -#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1 -#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1 -#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1 -#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1 -#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2 -#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2 -#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2 -#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2 -#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2 -#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2 -#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2 -#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2 -#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2 -#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2 -#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2 -#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2 -#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2 -#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2 -#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2 -#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2 -#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2 -#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2 -#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2 -#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2 -#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2 -#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3 -#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3 -#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3 -#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3 -#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3 -#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3 -#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3 -#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3 -#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3 -#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3 -#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3 -#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3 -#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3 -#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3 -#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3 -#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3 -#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3 -#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3 -#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3 -#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3 -#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3 -#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0 -#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0 -#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0 -#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0 -#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0 -#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0 -#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0 -#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0 -#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0 -#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0 -#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0 -#define SCUXSWRSR_CIM SCUX.SWRSR_CIM -#define SCUXDMACR_CIM SCUX.DMACR_CIM -#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32 -#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L] -#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H] -#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32 -#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L] -#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H] -#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32 -#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L] -#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H] -#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32 -#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L] -#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H] -#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32 -#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L] -#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H] -#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32 -#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L] -#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H] -#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32 -#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L] -#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H] -#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32 -#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L] -#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H] -#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM -#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM -#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM -#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM -#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM -#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM -#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM -#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM -#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM -#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM -#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM -#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM -#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM -#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM -#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM -#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h index 78abfc08e8..dd6dee41d8 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h @@ -18,27 +18,20 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : sdg_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SDG_IODEFINE_H #define SDG_IODEFINE_H - -struct st_sdg -{ /* SDG */ - volatile uint8_t SGCR1; /* SGCR1 */ - volatile uint8_t SGCSR; /* SGCSR */ - volatile uint8_t SGCR2; /* SGCR2 */ - volatile uint8_t SGLR; /* SGLR */ - volatile uint8_t SGTFR; /* SGTFR */ - volatile uint8_t SGSFR; /* SGSFR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */ #define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */ @@ -46,41 +39,69 @@ struct st_sdg #define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */ -/* Start of channnel array defines of SDG */ +/* Start of channel array defines of SDG */ -/* Channnel array defines of SDG */ +/* Channel array defines of SDG */ /*(Sample) value = SDG[ channel ]->SGCR1; */ -#define SDG_COUNT 4 +#define SDG_COUNT (4) #define SDG_ADDRESS_LIST \ { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ &SDG0, &SDG1, &SDG2, &SDG3 \ } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -/* End of channnel array defines of SDG */ +/* End of channel array defines of SDG */ -#define SGCR1_0 SDG0.SGCR1 -#define SGCSR_0 SDG0.SGCSR -#define SGCR2_0 SDG0.SGCR2 -#define SGLR_0 SDG0.SGLR -#define SGTFR_0 SDG0.SGTFR -#define SGSFR_0 SDG0.SGSFR -#define SGCR1_1 SDG1.SGCR1 -#define SGCSR_1 SDG1.SGCSR -#define SGCR2_1 SDG1.SGCR2 -#define SGLR_1 SDG1.SGLR -#define SGTFR_1 SDG1.SGTFR -#define SGSFR_1 SDG1.SGSFR -#define SGCR1_2 SDG2.SGCR1 -#define SGCSR_2 SDG2.SGCSR -#define SGCR2_2 SDG2.SGCR2 -#define SGLR_2 SDG2.SGLR -#define SGTFR_2 SDG2.SGTFR -#define SGSFR_2 SDG2.SGSFR -#define SGCR1_3 SDG3.SGCR1 -#define SGCSR_3 SDG3.SGCSR -#define SGCR2_3 SDG3.SGCR2 -#define SGLR_3 SDG3.SGLR -#define SGTFR_3 SDG3.SGTFR -#define SGSFR_3 SDG3.SGSFR +#define SGCR1_0 (SDG0.SGCR1) +#define SGCSR_0 (SDG0.SGCSR) +#define SGCR2_0 (SDG0.SGCR2) +#define SGLR_0 (SDG0.SGLR) +#define SGTFR_0 (SDG0.SGTFR) +#define SGSFR_0 (SDG0.SGSFR) +#define SGCR1_1 (SDG1.SGCR1) +#define SGCSR_1 (SDG1.SGCSR) +#define SGCR2_1 (SDG1.SGCR2) +#define SGLR_1 (SDG1.SGLR) +#define SGTFR_1 (SDG1.SGTFR) +#define SGSFR_1 (SDG1.SGSFR) +#define SGCR1_2 (SDG2.SGCR1) +#define SGCSR_2 (SDG2.SGCSR) +#define SGCR2_2 (SDG2.SGCR2) +#define SGLR_2 (SDG2.SGLR) +#define SGTFR_2 (SDG2.SGTFR) +#define SGSFR_2 (SDG2.SGSFR) +#define SGCR1_3 (SDG3.SGCR1) +#define SGCSR_3 (SDG3.SGCSR) +#define SGCR2_3 (SDG3.SGCR2) +#define SGLR_3 (SDG3.SGLR) +#define SGTFR_3 (SDG3.SGTFR) +#define SGSFR_3 (SDG3.SGSFR) + + +typedef struct st_sdg +{ + /* SDG */ + volatile uint8_t SGCR1; /* SGCR1 */ + volatile uint8_t SGCSR; /* SGCSR */ + volatile uint8_t SGCR2; /* SGCR2 */ + volatile uint8_t SGLR; /* SGLR */ + volatile uint8_t SGTFR; /* SGTFR */ + volatile uint8_t SGSFR; /* SGSFR */ +} r_io_sdg_t; + + +/* Channel array defines of SDG (2)*/ +#ifdef DECLARE_SDG_CHANNELS +volatile struct st_sdg* SDG[ SDG_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SDG_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SDG_CHANNELS */ +/* End of channel array defines of SDG (2)*/ + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h index 6f69f80850..a7e4c82529 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h @@ -18,19 +18,43 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : spdif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SPDIF_IODEFINE_H #define SPDIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ -struct st_spdif -{ /* SPDIF */ +#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ + + +#define SPDIFTLCA (SPDIF.TLCA) +#define SPDIFTRCA (SPDIF.TRCA) +#define SPDIFTLCS (SPDIF.TLCS) +#define SPDIFTRCS (SPDIF.TRCS) +#define SPDIFTUI (SPDIF.TUI) +#define SPDIFRLCA (SPDIF.RLCA) +#define SPDIFRRCA (SPDIF.RRCA) +#define SPDIFRLCS (SPDIF.RLCS) +#define SPDIFRRCS (SPDIF.RRCS) +#define SPDIFRUI (SPDIF.RUI) +#define SPDIFCTRL (SPDIF.CTRL) +#define SPDIFSTAT (SPDIF.STAT) +#define SPDIFTDAD (SPDIF.TDAD) +#define SPDIFRDAD (SPDIF.RDAD) + + +typedef struct st_spdif +{ + /* SPDIF */ volatile uint32_t TLCA; /* TLCA */ volatile uint32_t TRCA; /* TRCA */ volatile uint32_t TLCS; /* TLCS */ @@ -45,24 +69,11 @@ struct st_spdif volatile uint32_t STAT; /* STAT */ volatile uint32_t TDAD; /* TDAD */ volatile uint32_t RDAD; /* RDAD */ -}; +} r_io_spdif_t; -#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */ - - -#define SPDIFTLCA SPDIF.TLCA -#define SPDIFTRCA SPDIF.TRCA -#define SPDIFTLCS SPDIF.TLCS -#define SPDIFTRCS SPDIF.TRCS -#define SPDIFTUI SPDIF.TUI -#define SPDIFRLCA SPDIF.RLCA -#define SPDIFRRCA SPDIF.RRCA -#define SPDIFRLCS SPDIF.RLCS -#define SPDIFRRCS SPDIF.RRCS -#define SPDIFRUI SPDIF.RUI -#define SPDIFCTRL SPDIF.CTRL -#define SPDIFSTAT SPDIF.STAT -#define SPDIFTDAD SPDIF.TDAD -#define SPDIFRDAD SPDIF.RDAD +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h index d25b903b89..6615aea8f7 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h @@ -18,20 +18,139 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : spibsc_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SPIBSC_IODEFINE_H #define SPIBSC_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_spibsc -{ /* SPIBSC */ +#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ +#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ + + +/* Start of channel array defines of SPIBSC */ + +/* Channel array defines of SPIBSC */ +/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ +#define SPIBSC_COUNT (2) +#define SPIBSC_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SPIBSC0, &SPIBSC1 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SPIBSC */ + + +#define CMNCR_0 (SPIBSC0.CMNCR) +#define SSLDR_0 (SPIBSC0.SSLDR) +#define SPBCR_0 (SPIBSC0.SPBCR) +#define DRCR_0 (SPIBSC0.DRCR) +#define DRCMR_0 (SPIBSC0.DRCMR) +#define DREAR_0 (SPIBSC0.DREAR) +#define DROPR_0 (SPIBSC0.DROPR) +#define DRENR_0 (SPIBSC0.DRENR) +#define SMCR_0 (SPIBSC0.SMCR) +#define SMCMR_0 (SPIBSC0.SMCMR) +#define SMADR_0 (SPIBSC0.SMADR) +#define SMOPR_0 (SPIBSC0.SMOPR) +#define SMENR_0 (SPIBSC0.SMENR) +#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32) +#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32) +#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32) +#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32) +#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_0 (SPIBSC0.CMNSR) +#define CKDLY_0 (SPIBSC0.CKDLY) +#define DRDMCR_0 (SPIBSC0.DRDMCR) +#define DRDRENR_0 (SPIBSC0.DRDRENR) +#define SMDMCR_0 (SPIBSC0.SMDMCR) +#define SMDRENR_0 (SPIBSC0.SMDRENR) +#define SPODLY_0 (SPIBSC0.SPODLY) +#define CMNCR_1 (SPIBSC1.CMNCR) +#define SSLDR_1 (SPIBSC1.SSLDR) +#define SPBCR_1 (SPIBSC1.SPBCR) +#define DRCR_1 (SPIBSC1.DRCR) +#define DRCMR_1 (SPIBSC1.DRCMR) +#define DREAR_1 (SPIBSC1.DREAR) +#define DROPR_1 (SPIBSC1.DROPR) +#define DRENR_1 (SPIBSC1.DRENR) +#define SMCR_1 (SPIBSC1.SMCR) +#define SMCMR_1 (SPIBSC1.SMCMR) +#define SMADR_1 (SPIBSC1.SMADR) +#define SMOPR_1 (SPIBSC1.SMOPR) +#define SMENR_1 (SPIBSC1.SMENR) +#define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32) +#define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L]) +#define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H]) +#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL]) +#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH]) +#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL]) +#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH]) +#define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32) +#define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L]) +#define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H]) +#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL]) +#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH]) +#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL]) +#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH]) +#define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32) +#define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L]) +#define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H]) +#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL]) +#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH]) +#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL]) +#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH]) +#define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32) +#define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L]) +#define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H]) +#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL]) +#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH]) +#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL]) +#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH]) +#define CMNSR_1 (SPIBSC1.CMNSR) +#define CKDLY_1 (SPIBSC1.CKDLY) +#define DRDMCR_1 (SPIBSC1.DRDMCR) +#define DRDRENR_1 (SPIBSC1.DRDRENR) +#define SMDMCR_1 (SPIBSC1.SMDMCR) +#define SMDRENR_1 (SPIBSC1.SMDRENR) +#define SPODLY_1 (SPIBSC1.SPODLY) + + +typedef struct st_spibsc +{ + /* SPIBSC */ volatile uint32_t CMNCR; /* CMNCR */ volatile uint32_t SSLDR; /* SSLDR */ volatile uint32_t SPBCR; /* SPBCR */ @@ -52,122 +171,29 @@ struct st_spibsc union iodefine_reg32_t SMWDR1; /* SMWDR1 */ volatile uint32_t CMNSR; /* CMNSR */ - volatile uint8_t dummy2[12]; /* */ + volatile uint8_t dummy2[4]; /* */ + volatile uint32_t CKDLY; /* CKDLY */ + volatile uint8_t dummy3[4]; /* */ volatile uint32_t DRDMCR; /* DRDMCR */ volatile uint32_t DRDRENR; /* DRDRENR */ volatile uint32_t SMDMCR; /* SMDMCR */ volatile uint32_t SMDRENR; /* SMDRENR */ -}; + volatile uint32_t SPODLY; /* SPODLY */ +} r_io_spibsc_t; -#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */ -#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */ +/* Channel array defines of SPIBSC (2)*/ +#ifdef DECLARE_SPIBSC_CHANNELS +volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SPIBSC_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SPIBSC_CHANNELS */ +/* End of channel array defines of SPIBSC (2)*/ -/* Start of channnel array defines of SPIBSC */ - -/* Channnel array defines of SPIBSC */ -/*(Sample) value = SPIBSC[ channel ]->CMNCR; */ -#define SPIBSC_COUNT 2 -#define SPIBSC_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SPIBSC0, &SPIBSC1 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SPIBSC */ - - -#define CMNCR_0 SPIBSC0.CMNCR -#define SSLDR_0 SPIBSC0.SSLDR -#define SPBCR_0 SPIBSC0.SPBCR -#define DRCR_0 SPIBSC0.DRCR -#define DRCMR_0 SPIBSC0.DRCMR -#define DREAR_0 SPIBSC0.DREAR -#define DROPR_0 SPIBSC0.DROPR -#define DRENR_0 SPIBSC0.DRENR -#define SMCR_0 SPIBSC0.SMCR -#define SMCMR_0 SPIBSC0.SMCMR -#define SMADR_0 SPIBSC0.SMADR -#define SMOPR_0 SPIBSC0.SMOPR -#define SMENR_0 SPIBSC0.SMENR -#define SMRDR0_0 SPIBSC0.SMRDR0.UINT32 -#define SMRDR0_0L SPIBSC0.SMRDR0.UINT16[L] -#define SMRDR0_0H SPIBSC0.SMRDR0.UINT16[H] -#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL] -#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH] -#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL] -#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH] -#define SMRDR1_0 SPIBSC0.SMRDR1.UINT32 -#define SMRDR1_0L SPIBSC0.SMRDR1.UINT16[L] -#define SMRDR1_0H SPIBSC0.SMRDR1.UINT16[H] -#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL] -#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH] -#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL] -#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH] -#define SMWDR0_0 SPIBSC0.SMWDR0.UINT32 -#define SMWDR0_0L SPIBSC0.SMWDR0.UINT16[L] -#define SMWDR0_0H SPIBSC0.SMWDR0.UINT16[H] -#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL] -#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH] -#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL] -#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH] -#define SMWDR1_0 SPIBSC0.SMWDR1.UINT32 -#define SMWDR1_0L SPIBSC0.SMWDR1.UINT16[L] -#define SMWDR1_0H SPIBSC0.SMWDR1.UINT16[H] -#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL] -#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH] -#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL] -#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH] -#define CMNSR_0 SPIBSC0.CMNSR -#define DRDMCR_0 SPIBSC0.DRDMCR -#define DRDRENR_0 SPIBSC0.DRDRENR -#define SMDMCR_0 SPIBSC0.SMDMCR -#define SMDRENR_0 SPIBSC0.SMDRENR -#define CMNCR_1 SPIBSC1.CMNCR -#define SSLDR_1 SPIBSC1.SSLDR -#define SPBCR_1 SPIBSC1.SPBCR -#define DRCR_1 SPIBSC1.DRCR -#define DRCMR_1 SPIBSC1.DRCMR -#define DREAR_1 SPIBSC1.DREAR -#define DROPR_1 SPIBSC1.DROPR -#define DRENR_1 SPIBSC1.DRENR -#define SMCR_1 SPIBSC1.SMCR -#define SMCMR_1 SPIBSC1.SMCMR -#define SMADR_1 SPIBSC1.SMADR -#define SMOPR_1 SPIBSC1.SMOPR -#define SMENR_1 SPIBSC1.SMENR -#define SMRDR0_1 SPIBSC1.SMRDR0.UINT32 -#define SMRDR0_1L SPIBSC1.SMRDR0.UINT16[L] -#define SMRDR0_1H SPIBSC1.SMRDR0.UINT16[H] -#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL] -#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH] -#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL] -#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH] -#define SMRDR1_1 SPIBSC1.SMRDR1.UINT32 -#define SMRDR1_1L SPIBSC1.SMRDR1.UINT16[L] -#define SMRDR1_1H SPIBSC1.SMRDR1.UINT16[H] -#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL] -#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH] -#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL] -#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH] -#define SMWDR0_1 SPIBSC1.SMWDR0.UINT32 -#define SMWDR0_1L SPIBSC1.SMWDR0.UINT16[L] -#define SMWDR0_1H SPIBSC1.SMWDR0.UINT16[H] -#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL] -#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH] -#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL] -#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH] -#define SMWDR1_1 SPIBSC1.SMWDR1.UINT32 -#define SMWDR1_1L SPIBSC1.SMWDR1.UINT16[L] -#define SMWDR1_1H SPIBSC1.SMWDR1.UINT16[H] -#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL] -#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH] -#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL] -#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH] -#define CMNSR_1 SPIBSC1.CMNSR -#define DRDMCR_1 SPIBSC1.DRDMCR -#define DRDRENR_1 SPIBSC1.DRDRENR -#define SMDMCR_1 SPIBSC1.SMDMCR -#define SMDRENR_1 SPIBSC1.SMDRENR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h index 045551c9f2..c0134a5d62 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h @@ -18,20 +18,107 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : ssif_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef SSIF_IODEFINE_H #define SSIF_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_ssif -{ /* SSIF */ +#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ +#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ +#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ +#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ +#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ +#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ + + +/* Start of channel array defines of SSIF */ + +/* Channel array defines of SSIF */ +/*(Sample) value = SSIF[ channel ]->SSICR; */ +#define SSIF_COUNT (6) +#define SSIF_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + +/* End of channel array defines of SSIF */ + + +#define SSICR_0 (SSIF0.SSICR) +#define SSISR_0 (SSIF0.SSISR) +#define SSIFCR_0 (SSIF0.SSIFCR) +#define SSIFSR_0 (SSIF0.SSIFSR) +#define SSIFTDR_0 (SSIF0.SSIFTDR) +#define SSIFRDR_0 (SSIF0.SSIFRDR) +#define SSITDMR_0 (SSIF0.SSITDMR) +#define SSIFCCR_0 (SSIF0.SSIFCCR) +#define SSIFCMR_0 (SSIF0.SSIFCMR) +#define SSIFCSR_0 (SSIF0.SSIFCSR) +#define SSICR_1 (SSIF1.SSICR) +#define SSISR_1 (SSIF1.SSISR) +#define SSIFCR_1 (SSIF1.SSIFCR) +#define SSIFSR_1 (SSIF1.SSIFSR) +#define SSIFTDR_1 (SSIF1.SSIFTDR) +#define SSIFRDR_1 (SSIF1.SSIFRDR) +#define SSITDMR_1 (SSIF1.SSITDMR) +#define SSIFCCR_1 (SSIF1.SSIFCCR) +#define SSIFCMR_1 (SSIF1.SSIFCMR) +#define SSIFCSR_1 (SSIF1.SSIFCSR) +#define SSICR_2 (SSIF2.SSICR) +#define SSISR_2 (SSIF2.SSISR) +#define SSIFCR_2 (SSIF2.SSIFCR) +#define SSIFSR_2 (SSIF2.SSIFSR) +#define SSIFTDR_2 (SSIF2.SSIFTDR) +#define SSIFRDR_2 (SSIF2.SSIFRDR) +#define SSITDMR_2 (SSIF2.SSITDMR) +#define SSIFCCR_2 (SSIF2.SSIFCCR) +#define SSIFCMR_2 (SSIF2.SSIFCMR) +#define SSIFCSR_2 (SSIF2.SSIFCSR) +#define SSICR_3 (SSIF3.SSICR) +#define SSISR_3 (SSIF3.SSISR) +#define SSIFCR_3 (SSIF3.SSIFCR) +#define SSIFSR_3 (SSIF3.SSIFSR) +#define SSIFTDR_3 (SSIF3.SSIFTDR) +#define SSIFRDR_3 (SSIF3.SSIFRDR) +#define SSITDMR_3 (SSIF3.SSITDMR) +#define SSIFCCR_3 (SSIF3.SSIFCCR) +#define SSIFCMR_3 (SSIF3.SSIFCMR) +#define SSIFCSR_3 (SSIF3.SSIFCSR) +#define SSICR_4 (SSIF4.SSICR) +#define SSISR_4 (SSIF4.SSISR) +#define SSIFCR_4 (SSIF4.SSIFCR) +#define SSIFSR_4 (SSIF4.SSIFSR) +#define SSIFTDR_4 (SSIF4.SSIFTDR) +#define SSIFRDR_4 (SSIF4.SSIFRDR) +#define SSITDMR_4 (SSIF4.SSITDMR) +#define SSIFCCR_4 (SSIF4.SSIFCCR) +#define SSIFCMR_4 (SSIF4.SSIFCMR) +#define SSIFCSR_4 (SSIF4.SSIFCSR) +#define SSICR_5 (SSIF5.SSICR) +#define SSISR_5 (SSIF5.SSISR) +#define SSIFCR_5 (SSIF5.SSIFCR) +#define SSIFSR_5 (SSIF5.SSIFSR) +#define SSIFTDR_5 (SSIF5.SSIFTDR) +#define SSIFRDR_5 (SSIF5.SSIFRDR) +#define SSITDMR_5 (SSIF5.SSITDMR) +#define SSIFCCR_5 (SSIF5.SSIFCCR) +#define SSIFCMR_5 (SSIF5.SSIFCMR) +#define SSIFCSR_5 (SSIF5.SSIFCSR) + + +typedef struct st_ssif +{ + /* SSIF */ volatile uint32_t SSICR; /* SSICR */ volatile uint32_t SSISR; /* SSISR */ volatile uint8_t dummy1[8]; /* */ @@ -43,89 +130,21 @@ struct st_ssif volatile uint32_t SSIFCCR; /* SSIFCCR */ volatile uint32_t SSIFCMR; /* SSIFCMR */ volatile uint32_t SSIFCSR; /* SSIFCSR */ -}; +} r_io_ssif_t; -#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ -#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ -#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ -#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ -#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ -#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ +/* Channel array defines of SSIF (2)*/ +#ifdef DECLARE_SSIF_CHANNELS +volatile struct st_ssif* SSIF[ SSIF_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + SSIF_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_SSIF_CHANNELS */ +/* End of channel array defines of SSIF (2)*/ -/* Start of channnel array defines of SSIF */ - -/* Channnel array defines of SSIF */ -/*(Sample) value = SSIF[ channel ]->SSICR; */ -#define SSIF_COUNT 6 -#define SSIF_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - -/* End of channnel array defines of SSIF */ - - -#define SSICR_0 SSIF0.SSICR -#define SSISR_0 SSIF0.SSISR -#define SSIFCR_0 SSIF0.SSIFCR -#define SSIFSR_0 SSIF0.SSIFSR -#define SSIFTDR_0 SSIF0.SSIFTDR -#define SSIFRDR_0 SSIF0.SSIFRDR -#define SSITDMR_0 SSIF0.SSITDMR -#define SSIFCCR_0 SSIF0.SSIFCCR -#define SSIFCMR_0 SSIF0.SSIFCMR -#define SSIFCSR_0 SSIF0.SSIFCSR -#define SSICR_1 SSIF1.SSICR -#define SSISR_1 SSIF1.SSISR -#define SSIFCR_1 SSIF1.SSIFCR -#define SSIFSR_1 SSIF1.SSIFSR -#define SSIFTDR_1 SSIF1.SSIFTDR -#define SSIFRDR_1 SSIF1.SSIFRDR -#define SSITDMR_1 SSIF1.SSITDMR -#define SSIFCCR_1 SSIF1.SSIFCCR -#define SSIFCMR_1 SSIF1.SSIFCMR -#define SSIFCSR_1 SSIF1.SSIFCSR -#define SSICR_2 SSIF2.SSICR -#define SSISR_2 SSIF2.SSISR -#define SSIFCR_2 SSIF2.SSIFCR -#define SSIFSR_2 SSIF2.SSIFSR -#define SSIFTDR_2 SSIF2.SSIFTDR -#define SSIFRDR_2 SSIF2.SSIFRDR -#define SSITDMR_2 SSIF2.SSITDMR -#define SSIFCCR_2 SSIF2.SSIFCCR -#define SSIFCMR_2 SSIF2.SSIFCMR -#define SSIFCSR_2 SSIF2.SSIFCSR -#define SSICR_3 SSIF3.SSICR -#define SSISR_3 SSIF3.SSISR -#define SSIFCR_3 SSIF3.SSIFCR -#define SSIFSR_3 SSIF3.SSIFSR -#define SSIFTDR_3 SSIF3.SSIFTDR -#define SSIFRDR_3 SSIF3.SSIFRDR -#define SSITDMR_3 SSIF3.SSITDMR -#define SSIFCCR_3 SSIF3.SSIFCCR -#define SSIFCMR_3 SSIF3.SSIFCMR -#define SSIFCSR_3 SSIF3.SSIFCSR -#define SSICR_4 SSIF4.SSICR -#define SSISR_4 SSIF4.SSISR -#define SSIFCR_4 SSIF4.SSIFCR -#define SSIFSR_4 SSIF4.SSIFSR -#define SSIFTDR_4 SSIF4.SSIFTDR -#define SSIFRDR_4 SSIF4.SSIFRDR -#define SSITDMR_4 SSIF4.SSITDMR -#define SSIFCCR_4 SSIF4.SSIFCCR -#define SSIFCMR_4 SSIF4.SSIFCMR -#define SSIFCSR_4 SSIF4.SSIFCSR -#define SSICR_5 SSIF5.SSICR -#define SSISR_5 SSIF5.SSISR -#define SSIFCR_5 SSIF5.SSIFCR -#define SSIFSR_5 SSIF5.SSIFSR -#define SSIFTDR_5 SSIF5.SSIFTDR -#define SSIFRDR_5 SSIF5.SSIFRDR -#define SSITDMR_5 SSIF5.SSITDMR -#define SSIFCCR_5 SSIF5.SSIFCCR -#define SSIFCMR_5 SSIF5.SSIFCMR -#define SSIFCSR_5 SSIF5.SSIFCSR /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h index 97e15c8455..a8e60a2647 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h @@ -18,20 +18,365 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : usb20_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef USB20_IODEFINE_H #define USB20_IODEFINE_H +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_usb20 -{ /* USB20 */ +#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ +#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ + + +/* Start of channel array defines of USB20 */ + +/* Channel array defines of USB20 */ +/*(Sample) value = USB20[ channel ]->SYSCFG0; */ +#define USB20_COUNT (2) +#define USB20_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &USB200, &USB201 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of USB20_FROM_D0FIFOB0 */ +/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ +#define USB20_FROM_D0FIFOB0_COUNT (2) +#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ + &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ +#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ +#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ +#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ + + + + +/* Channel array defines of USB20_FROM_PIPE1ATRE */ +/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ +#define USB20_FROM_PIPE1ATRE_COUNT (5) +#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ + &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ +#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ +#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ +#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ +#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ +#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ +#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ +#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ +#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ +#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ + + + + +/* Channel array defines of USB20_FROM_D0FIFOSEL */ +/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ +#define USB20_FROM_D0FIFOSEL_COUNT (2) +#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ + &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ +#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ +#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ +#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ + + +/* End of channel array defines of USB20 */ + + +#define SYSCFG0_0 (USB200.SYSCFG0) +#define BUSWAIT_0 (USB200.BUSWAIT) +#define SYSSTS0_0 (USB200.SYSSTS0) +#define DVSTCTR0_0 (USB200.DVSTCTR0) +#define TESTMODE_0 (USB200.TESTMODE) +#define D0FBCFG_0 (USB200.D0FBCFG) +#define D1FBCFG_0 (USB200.D1FBCFG) +#define CFIFO_0 (USB200.CFIFO.UINT32) +#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L]) +#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H]) +#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_0 (USB200.D0FIFO.UINT32) +#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_0 (USB200.D1FIFO.UINT32) +#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_0 (USB200.CFIFOSEL) +#define CFIFOCTR_0 (USB200.CFIFOCTR) +#define D0FIFOSEL_0 (USB200.D0FIFOSEL) +#define D0FIFOCTR_0 (USB200.D0FIFOCTR) +#define D1FIFOSEL_0 (USB200.D1FIFOSEL) +#define D1FIFOCTR_0 (USB200.D1FIFOCTR) +#define INTENB0_0 (USB200.INTENB0) +#define INTENB1_0 (USB200.INTENB1) +#define BRDYENB_0 (USB200.BRDYENB) +#define NRDYENB_0 (USB200.NRDYENB) +#define BEMPENB_0 (USB200.BEMPENB) +#define SOFCFG_0 (USB200.SOFCFG) +#define INTSTS0_0 (USB200.INTSTS0) +#define INTSTS1_0 (USB200.INTSTS1) +#define BRDYSTS_0 (USB200.BRDYSTS) +#define NRDYSTS_0 (USB200.NRDYSTS) +#define BEMPSTS_0 (USB200.BEMPSTS) +#define FRMNUM_0 (USB200.FRMNUM) +#define UFRMNUM_0 (USB200.UFRMNUM) +#define USBADDR_0 (USB200.USBADDR) +#define USBREQ_0 (USB200.USBREQ) +#define USBVAL_0 (USB200.USBVAL) +#define USBINDX_0 (USB200.USBINDX) +#define USBLENG_0 (USB200.USBLENG) +#define DCPCFG_0 (USB200.DCPCFG) +#define DCPMAXP_0 (USB200.DCPMAXP) +#define DCPCTR_0 (USB200.DCPCTR) +#define PIPESEL_0 (USB200.PIPESEL) +#define PIPECFG_0 (USB200.PIPECFG) +#define PIPEBUF_0 (USB200.PIPEBUF) +#define PIPEMAXP_0 (USB200.PIPEMAXP) +#define PIPEPERI_0 (USB200.PIPEPERI) +#define PIPE1CTR_0 (USB200.PIPE1CTR) +#define PIPE2CTR_0 (USB200.PIPE2CTR) +#define PIPE3CTR_0 (USB200.PIPE3CTR) +#define PIPE4CTR_0 (USB200.PIPE4CTR) +#define PIPE5CTR_0 (USB200.PIPE5CTR) +#define PIPE6CTR_0 (USB200.PIPE6CTR) +#define PIPE7CTR_0 (USB200.PIPE7CTR) +#define PIPE8CTR_0 (USB200.PIPE8CTR) +#define PIPE9CTR_0 (USB200.PIPE9CTR) +#define PIPEACTR_0 (USB200.PIPEACTR) +#define PIPEBCTR_0 (USB200.PIPEBCTR) +#define PIPECCTR_0 (USB200.PIPECCTR) +#define PIPEDCTR_0 (USB200.PIPEDCTR) +#define PIPEECTR_0 (USB200.PIPEECTR) +#define PIPEFCTR_0 (USB200.PIPEFCTR) +#define PIPE1TRE_0 (USB200.PIPE1TRE) +#define PIPE1TRN_0 (USB200.PIPE1TRN) +#define PIPE2TRE_0 (USB200.PIPE2TRE) +#define PIPE2TRN_0 (USB200.PIPE2TRN) +#define PIPE3TRE_0 (USB200.PIPE3TRE) +#define PIPE3TRN_0 (USB200.PIPE3TRN) +#define PIPE4TRE_0 (USB200.PIPE4TRE) +#define PIPE4TRN_0 (USB200.PIPE4TRN) +#define PIPE5TRE_0 (USB200.PIPE5TRE) +#define PIPE5TRN_0 (USB200.PIPE5TRN) +#define PIPEBTRE_0 (USB200.PIPEBTRE) +#define PIPEBTRN_0 (USB200.PIPEBTRN) +#define PIPECTRE_0 (USB200.PIPECTRE) +#define PIPECTRN_0 (USB200.PIPECTRN) +#define PIPEDTRE_0 (USB200.PIPEDTRE) +#define PIPEDTRN_0 (USB200.PIPEDTRN) +#define PIPEETRE_0 (USB200.PIPEETRE) +#define PIPEETRN_0 (USB200.PIPEETRN) +#define PIPEFTRE_0 (USB200.PIPEFTRE) +#define PIPEFTRN_0 (USB200.PIPEFTRN) +#define PIPE9TRE_0 (USB200.PIPE9TRE) +#define PIPE9TRN_0 (USB200.PIPE9TRN) +#define PIPEATRE_0 (USB200.PIPEATRE) +#define PIPEATRN_0 (USB200.PIPEATRN) +#define DEVADD0_0 (USB200.DEVADD0) +#define DEVADD1_0 (USB200.DEVADD1) +#define DEVADD2_0 (USB200.DEVADD2) +#define DEVADD3_0 (USB200.DEVADD3) +#define DEVADD4_0 (USB200.DEVADD4) +#define DEVADD5_0 (USB200.DEVADD5) +#define DEVADD6_0 (USB200.DEVADD6) +#define DEVADD7_0 (USB200.DEVADD7) +#define DEVADD8_0 (USB200.DEVADD8) +#define DEVADD9_0 (USB200.DEVADD9) +#define DEVADDA_0 (USB200.DEVADDA) +#define SUSPMODE_0 (USB200.SUSPMODE) +#define D0FIFOB0_0 (USB200.D0FIFOB0) +#define D0FIFOB1_0 (USB200.D0FIFOB1) +#define D0FIFOB2_0 (USB200.D0FIFOB2) +#define D0FIFOB3_0 (USB200.D0FIFOB3) +#define D0FIFOB4_0 (USB200.D0FIFOB4) +#define D0FIFOB5_0 (USB200.D0FIFOB5) +#define D0FIFOB6_0 (USB200.D0FIFOB6) +#define D0FIFOB7_0 (USB200.D0FIFOB7) +#define D1FIFOB0_0 (USB200.D1FIFOB0) +#define D1FIFOB1_0 (USB200.D1FIFOB1) +#define D1FIFOB2_0 (USB200.D1FIFOB2) +#define D1FIFOB3_0 (USB200.D1FIFOB3) +#define D1FIFOB4_0 (USB200.D1FIFOB4) +#define D1FIFOB5_0 (USB200.D1FIFOB5) +#define D1FIFOB6_0 (USB200.D1FIFOB6) +#define D1FIFOB7_0 (USB200.D1FIFOB7) +#define SYSCFG0_1 (USB201.SYSCFG0) +#define BUSWAIT_1 (USB201.BUSWAIT) +#define SYSSTS0_1 (USB201.SYSSTS0) +#define DVSTCTR0_1 (USB201.DVSTCTR0) +#define TESTMODE_1 (USB201.TESTMODE) +#define D0FBCFG_1 (USB201.D0FBCFG) +#define D1FBCFG_1 (USB201.D1FBCFG) +#define CFIFO_1 (USB201.CFIFO.UINT32) +#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L]) +#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H]) +#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL]) +#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH]) +#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL]) +#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH]) +#define D0FIFO_1 (USB201.D0FIFO.UINT32) +#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L]) +#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H]) +#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL]) +#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH]) +#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL]) +#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH]) +#define D1FIFO_1 (USB201.D1FIFO.UINT32) +#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L]) +#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H]) +#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL]) +#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH]) +#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL]) +#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH]) +#define CFIFOSEL_1 (USB201.CFIFOSEL) +#define CFIFOCTR_1 (USB201.CFIFOCTR) +#define D0FIFOSEL_1 (USB201.D0FIFOSEL) +#define D0FIFOCTR_1 (USB201.D0FIFOCTR) +#define D1FIFOSEL_1 (USB201.D1FIFOSEL) +#define D1FIFOCTR_1 (USB201.D1FIFOCTR) +#define INTENB0_1 (USB201.INTENB0) +#define INTENB1_1 (USB201.INTENB1) +#define BRDYENB_1 (USB201.BRDYENB) +#define NRDYENB_1 (USB201.NRDYENB) +#define BEMPENB_1 (USB201.BEMPENB) +#define SOFCFG_1 (USB201.SOFCFG) +#define INTSTS0_1 (USB201.INTSTS0) +#define INTSTS1_1 (USB201.INTSTS1) +#define BRDYSTS_1 (USB201.BRDYSTS) +#define NRDYSTS_1 (USB201.NRDYSTS) +#define BEMPSTS_1 (USB201.BEMPSTS) +#define FRMNUM_1 (USB201.FRMNUM) +#define UFRMNUM_1 (USB201.UFRMNUM) +#define USBADDR_1 (USB201.USBADDR) +#define USBREQ_1 (USB201.USBREQ) +#define USBVAL_1 (USB201.USBVAL) +#define USBINDX_1 (USB201.USBINDX) +#define USBLENG_1 (USB201.USBLENG) +#define DCPCFG_1 (USB201.DCPCFG) +#define DCPMAXP_1 (USB201.DCPMAXP) +#define DCPCTR_1 (USB201.DCPCTR) +#define PIPESEL_1 (USB201.PIPESEL) +#define PIPECFG_1 (USB201.PIPECFG) +#define PIPEBUF_1 (USB201.PIPEBUF) +#define PIPEMAXP_1 (USB201.PIPEMAXP) +#define PIPEPERI_1 (USB201.PIPEPERI) +#define PIPE1CTR_1 (USB201.PIPE1CTR) +#define PIPE2CTR_1 (USB201.PIPE2CTR) +#define PIPE3CTR_1 (USB201.PIPE3CTR) +#define PIPE4CTR_1 (USB201.PIPE4CTR) +#define PIPE5CTR_1 (USB201.PIPE5CTR) +#define PIPE6CTR_1 (USB201.PIPE6CTR) +#define PIPE7CTR_1 (USB201.PIPE7CTR) +#define PIPE8CTR_1 (USB201.PIPE8CTR) +#define PIPE9CTR_1 (USB201.PIPE9CTR) +#define PIPEACTR_1 (USB201.PIPEACTR) +#define PIPEBCTR_1 (USB201.PIPEBCTR) +#define PIPECCTR_1 (USB201.PIPECCTR) +#define PIPEDCTR_1 (USB201.PIPEDCTR) +#define PIPEECTR_1 (USB201.PIPEECTR) +#define PIPEFCTR_1 (USB201.PIPEFCTR) +#define PIPE1TRE_1 (USB201.PIPE1TRE) +#define PIPE1TRN_1 (USB201.PIPE1TRN) +#define PIPE2TRE_1 (USB201.PIPE2TRE) +#define PIPE2TRN_1 (USB201.PIPE2TRN) +#define PIPE3TRE_1 (USB201.PIPE3TRE) +#define PIPE3TRN_1 (USB201.PIPE3TRN) +#define PIPE4TRE_1 (USB201.PIPE4TRE) +#define PIPE4TRN_1 (USB201.PIPE4TRN) +#define PIPE5TRE_1 (USB201.PIPE5TRE) +#define PIPE5TRN_1 (USB201.PIPE5TRN) +#define PIPEBTRE_1 (USB201.PIPEBTRE) +#define PIPEBTRN_1 (USB201.PIPEBTRN) +#define PIPECTRE_1 (USB201.PIPECTRE) +#define PIPECTRN_1 (USB201.PIPECTRN) +#define PIPEDTRE_1 (USB201.PIPEDTRE) +#define PIPEDTRN_1 (USB201.PIPEDTRN) +#define PIPEETRE_1 (USB201.PIPEETRE) +#define PIPEETRN_1 (USB201.PIPEETRN) +#define PIPEFTRE_1 (USB201.PIPEFTRE) +#define PIPEFTRN_1 (USB201.PIPEFTRN) +#define PIPE9TRE_1 (USB201.PIPE9TRE) +#define PIPE9TRN_1 (USB201.PIPE9TRN) +#define PIPEATRE_1 (USB201.PIPEATRE) +#define PIPEATRN_1 (USB201.PIPEATRN) +#define DEVADD0_1 (USB201.DEVADD0) +#define DEVADD1_1 (USB201.DEVADD1) +#define DEVADD2_1 (USB201.DEVADD2) +#define DEVADD3_1 (USB201.DEVADD3) +#define DEVADD4_1 (USB201.DEVADD4) +#define DEVADD5_1 (USB201.DEVADD5) +#define DEVADD6_1 (USB201.DEVADD6) +#define DEVADD7_1 (USB201.DEVADD7) +#define DEVADD8_1 (USB201.DEVADD8) +#define DEVADD9_1 (USB201.DEVADD9) +#define DEVADDA_1 (USB201.DEVADDA) +#define SUSPMODE_1 (USB201.SUSPMODE) +#define D0FIFOB0_1 (USB201.D0FIFOB0) +#define D0FIFOB1_1 (USB201.D0FIFOB1) +#define D0FIFOB2_1 (USB201.D0FIFOB2) +#define D0FIFOB3_1 (USB201.D0FIFOB3) +#define D0FIFOB4_1 (USB201.D0FIFOB4) +#define D0FIFOB5_1 (USB201.D0FIFOB5) +#define D0FIFOB6_1 (USB201.D0FIFOB6) +#define D0FIFOB7_1 (USB201.D0FIFOB7) +#define D1FIFOB0_1 (USB201.D1FIFOB0) +#define D1FIFOB1_1 (USB201.D1FIFOB1) +#define D1FIFOB2_1 (USB201.D1FIFOB2) +#define D1FIFOB3_1 (USB201.D1FIFOB3) +#define D1FIFOB4_1 (USB201.D1FIFOB4) +#define D1FIFOB5_1 (USB201.D1FIFOB5) +#define D1FIFOB6_1 (USB201.D1FIFOB6) +#define D1FIFOB7_1 (USB201.D1FIFOB7) + +#define USB20_D0FBCFG_COUNT (2) +#define USB20_D0FIFO_COUNT (2) +#define USB20_INTENB0_COUNT (2) +#define USB20_INTSTS0_COUNT (2) +#define USB20_PIPE1CTR_COUNT (0xF) +#define USB20_DEVADD0_COUNT (0xB) +#define USB20_D0FIFOB0_COUNT (0x8) + + +typedef struct st_usb20 +{ + /* USB20 */ volatile uint16_t SYSCFG0; /* SYSCFG0 */ volatile uint16_t BUSWAIT; /* BUSWAIT */ volatile uint16_t SYSSTS0; /* SYSSTS0 */ @@ -40,26 +385,33 @@ struct st_usb20 volatile uint8_t dummy2[2]; /* */ volatile uint16_t TESTMODE; /* TESTMODE */ volatile uint8_t dummy3[2]; /* */ -#define USB20_D0FBCFG_COUNT 2 + +/* #define USB20_D0FBCFG_COUNT (2) */ volatile uint16_t D0FBCFG; /* D0FBCFG */ volatile uint16_t D1FBCFG; /* D1FBCFG */ union iodefine_reg32_t CFIFO; /* CFIFO */ -#define USB20_D0FIFO_COUNT 2 + +/* #define USB20_D0FIFO_COUNT (2) */ union iodefine_reg32_t D0FIFO; /* D0FIFO */ union iodefine_reg32_t D1FIFO; /* D1FIFO */ volatile uint16_t CFIFOSEL; /* CFIFOSEL */ volatile uint16_t CFIFOCTR; /* CFIFOCTR */ volatile uint8_t dummy4[4]; /* */ + /* start of struct st_usb20_from_d0fifosel */ volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ + /* end of struct st_usb20_from_d0fifosel */ + /* start of struct st_usb20_from_d0fifosel */ volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */ volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */ + /* end of struct st_usb20_from_d0fifosel */ -#define USB20_INTENB0_COUNT 2 + +/* #define USB20_INTENB0_COUNT (2) */ volatile uint16_t INTENB0; /* INTENB0 */ volatile uint16_t INTENB1; /* INTENB1 */ volatile uint8_t dummy5[2]; /* */ @@ -68,7 +420,8 @@ struct st_usb20 volatile uint16_t BEMPENB; /* BEMPENB */ volatile uint16_t SOFCFG; /* SOFCFG */ volatile uint8_t dummy6[2]; /* */ -#define USB20_INTSTS0_COUNT 2 + +/* #define USB20_INTSTS0_COUNT (2) */ volatile uint16_t INTSTS0; /* INTSTS0 */ volatile uint16_t INTSTS1; /* INTSTS1 */ volatile uint8_t dummy7[2]; /* */ @@ -93,7 +446,8 @@ struct st_usb20 volatile uint16_t PIPEBUF; /* PIPEBUF */ volatile uint16_t PIPEMAXP; /* PIPEMAXP */ volatile uint16_t PIPEPERI; /* PIPEPERI */ -#define USB20_PIPE1CTR_COUNT 0xF + +/* #define USB20_PIPE1CTR_COUNT (0xF) */ volatile uint16_t PIPE1CTR; /* PIPE1CTR */ volatile uint16_t PIPE2CTR; /* PIPE2CTR */ volatile uint16_t PIPE3CTR; /* PIPE3CTR */ @@ -110,25 +464,35 @@ struct st_usb20 volatile uint16_t PIPEECTR; /* PIPEECTR */ volatile uint16_t PIPEFCTR; /* PIPEFCTR */ volatile uint8_t dummy11[2]; /* */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE1TRE; /* PIPE1TRE */ volatile uint16_t PIPE1TRN; /* PIPE1TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE2TRE; /* PIPE2TRE */ volatile uint16_t PIPE2TRN; /* PIPE2TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE3TRE; /* PIPE3TRE */ volatile uint16_t PIPE3TRN; /* PIPE3TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE4TRE; /* PIPE4TRE */ volatile uint16_t PIPE4TRN; /* PIPE4TRN */ + /* end of struct st_usb20_from_pipe1tre */ + /* start of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPE5TRE; /* PIPE5TRE */ volatile uint16_t PIPE5TRN; /* PIPE5TRN */ + /* end of struct st_usb20_from_pipe1tre */ volatile uint16_t PIPEBTRE; /* PIPEBTRE */ volatile uint16_t PIPEBTRN; /* PIPEBTRN */ @@ -145,7 +509,8 @@ struct st_usb20 volatile uint16_t PIPEATRE; /* PIPEATRE */ volatile uint16_t PIPEATRN; /* PIPEATRN */ volatile uint8_t dummy12[16]; /* */ -#define USB20_DEVADD0_COUNT 0xB + +/* #define USB20_DEVADD0_COUNT (0xB) */ volatile uint16_t DEVADD0; /* DEVADD0 */ volatile uint16_t DEVADD1; /* DEVADD1 */ volatile uint16_t DEVADD2; /* DEVADD2 */ @@ -160,6 +525,7 @@ struct st_usb20 volatile uint8_t dummy13[28]; /* */ volatile uint16_t SUSPMODE; /* SUSPMODE */ volatile uint8_t dummy14[92]; /* */ + /* start of struct st_usb20_from_dmfifob0 */ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ @@ -169,7 +535,9 @@ struct st_usb20 volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ + /* end of struct st_usb20_from_dmfifob0 */ + /* start of struct st_usb20_from_dmfifob0 */ volatile uint32_t D1FIFOB0; /* D1FIFOB0 */ volatile uint32_t D1FIFOB1; /* D1FIFOB1 */ @@ -179,27 +547,32 @@ struct st_usb20 volatile uint32_t D1FIFOB5; /* D1FIFOB5 */ volatile uint32_t D1FIFOB6; /* D1FIFOB6 */ volatile uint32_t D1FIFOB7; /* D1FIFOB7 */ + /* end of struct st_usb20_from_dmfifob0 */ -}; +} r_io_usb20_t; -struct st_usb20_from_d0fifosel +typedef struct st_usb20_from_d0fifosel { + volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */ volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */ -}; +} r_io_usb20_from_d0fifosel_t; -struct st_usb20_from_pipe1tre +typedef struct st_usb20_from_pipe1tre { + volatile uint16_t PIPE1TRE; /* PIPE1TRE */ volatile uint16_t PIPE1TRN; /* PIPE1TRN */ -}; +} r_io_usb20_from_pipe1tre_t; -struct st_usb20_from_dmfifob0 +typedef struct st_usb20_from_dmfifob0 { -#define USB20_D0FIFOB0_COUNT 0x8 + + +/* #define USB20_D0FIFOB0_COUNT (0x8) */ volatile uint32_t D0FIFOB0; /* D0FIFOB0 */ volatile uint32_t D0FIFOB1; /* D0FIFOB1 */ volatile uint32_t D0FIFOB2; /* D0FIFOB2 */ @@ -208,339 +581,42 @@ struct st_usb20_from_dmfifob0 volatile uint32_t D0FIFOB5; /* D0FIFOB5 */ volatile uint32_t D0FIFOB6; /* D0FIFOB6 */ volatile uint32_t D0FIFOB7; /* D0FIFOB7 */ -}; +} r_io_usb20_from_dmfifob0_t; -#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */ -#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */ +/* Channel array defines of USB20 (2)*/ +#ifdef DECLARE_USB20_CHANNELS +volatile struct st_usb20* USB20[ USB20_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS +volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOB0_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS +volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_PIPE1ATRE_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */ + +#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS +volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + USB20_FROM_D0FIFOSEL_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */ +/* End of channel array defines of USB20 (2)*/ -/* Start of channnel array defines of USB20 */ - -/* Channnel array defines of USB20 */ -/*(Sample) value = USB20[ channel ]->SYSCFG0; */ -#define USB20_COUNT 2 -#define USB20_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &USB200, &USB201 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channnel array defines of USB20_FROM_D0FIFOB0 */ -/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */ -#define USB20_FROM_D0FIFOB0_COUNT 2 -#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \ - &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */ -#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */ -#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */ -#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */ - - - - -/* Channnel array defines of USB20_FROM_PIPE1ATRE */ -/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */ -#define USB20_FROM_PIPE1ATRE_COUNT 5 -#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \ - &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */ -#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */ -#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */ -#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */ -#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */ -#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */ -#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */ -#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */ -#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */ -#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */ - - - - -/* Channnel array defines of USB20_FROM_D0FIFOSEL */ -/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */ -#define USB20_FROM_D0FIFOSEL_COUNT 2 -#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \ - &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */ -#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */ -#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */ -#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */ - - -/* End of channnel array defines of USB20 */ - - -#define SYSCFG0_0 USB200.SYSCFG0 -#define BUSWAIT_0 USB200.BUSWAIT -#define SYSSTS0_0 USB200.SYSSTS0 -#define DVSTCTR0_0 USB200.DVSTCTR0 -#define TESTMODE_0 USB200.TESTMODE -#define D0FBCFG_0 USB200.D0FBCFG -#define D1FBCFG_0 USB200.D1FBCFG -#define CFIFO_0 USB200.CFIFO.UINT32 -#define CFIFO_0L USB200.CFIFO.UINT16[L] -#define CFIFO_0H USB200.CFIFO.UINT16[H] -#define CFIFO_0LL USB200.CFIFO.UINT8[LL] -#define CFIFO_0LH USB200.CFIFO.UINT8[LH] -#define CFIFO_0HL USB200.CFIFO.UINT8[HL] -#define CFIFO_0HH USB200.CFIFO.UINT8[HH] -#define D0FIFO_0 USB200.D0FIFO.UINT32 -#define D0FIFO_0L USB200.D0FIFO.UINT16[L] -#define D0FIFO_0H USB200.D0FIFO.UINT16[H] -#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL] -#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH] -#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL] -#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH] -#define D1FIFO_0 USB200.D1FIFO.UINT32 -#define D1FIFO_0L USB200.D1FIFO.UINT16[L] -#define D1FIFO_0H USB200.D1FIFO.UINT16[H] -#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL] -#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH] -#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL] -#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH] -#define CFIFOSEL_0 USB200.CFIFOSEL -#define CFIFOCTR_0 USB200.CFIFOCTR -#define D0FIFOSEL_0 USB200.D0FIFOSEL -#define D0FIFOCTR_0 USB200.D0FIFOCTR -#define D1FIFOSEL_0 USB200.D1FIFOSEL -#define D1FIFOCTR_0 USB200.D1FIFOCTR -#define INTENB0_0 USB200.INTENB0 -#define INTENB1_0 USB200.INTENB1 -#define BRDYENB_0 USB200.BRDYENB -#define NRDYENB_0 USB200.NRDYENB -#define BEMPENB_0 USB200.BEMPENB -#define SOFCFG_0 USB200.SOFCFG -#define INTSTS0_0 USB200.INTSTS0 -#define INTSTS1_0 USB200.INTSTS1 -#define BRDYSTS_0 USB200.BRDYSTS -#define NRDYSTS_0 USB200.NRDYSTS -#define BEMPSTS_0 USB200.BEMPSTS -#define FRMNUM_0 USB200.FRMNUM -#define UFRMNUM_0 USB200.UFRMNUM -#define USBADDR_0 USB200.USBADDR -#define USBREQ_0 USB200.USBREQ -#define USBVAL_0 USB200.USBVAL -#define USBINDX_0 USB200.USBINDX -#define USBLENG_0 USB200.USBLENG -#define DCPCFG_0 USB200.DCPCFG -#define DCPMAXP_0 USB200.DCPMAXP -#define DCPCTR_0 USB200.DCPCTR -#define PIPESEL_0 USB200.PIPESEL -#define PIPECFG_0 USB200.PIPECFG -#define PIPEBUF_0 USB200.PIPEBUF -#define PIPEMAXP_0 USB200.PIPEMAXP -#define PIPEPERI_0 USB200.PIPEPERI -#define PIPE1CTR_0 USB200.PIPE1CTR -#define PIPE2CTR_0 USB200.PIPE2CTR -#define PIPE3CTR_0 USB200.PIPE3CTR -#define PIPE4CTR_0 USB200.PIPE4CTR -#define PIPE5CTR_0 USB200.PIPE5CTR -#define PIPE6CTR_0 USB200.PIPE6CTR -#define PIPE7CTR_0 USB200.PIPE7CTR -#define PIPE8CTR_0 USB200.PIPE8CTR -#define PIPE9CTR_0 USB200.PIPE9CTR -#define PIPEACTR_0 USB200.PIPEACTR -#define PIPEBCTR_0 USB200.PIPEBCTR -#define PIPECCTR_0 USB200.PIPECCTR -#define PIPEDCTR_0 USB200.PIPEDCTR -#define PIPEECTR_0 USB200.PIPEECTR -#define PIPEFCTR_0 USB200.PIPEFCTR -#define PIPE1TRE_0 USB200.PIPE1TRE -#define PIPE1TRN_0 USB200.PIPE1TRN -#define PIPE2TRE_0 USB200.PIPE2TRE -#define PIPE2TRN_0 USB200.PIPE2TRN -#define PIPE3TRE_0 USB200.PIPE3TRE -#define PIPE3TRN_0 USB200.PIPE3TRN -#define PIPE4TRE_0 USB200.PIPE4TRE -#define PIPE4TRN_0 USB200.PIPE4TRN -#define PIPE5TRE_0 USB200.PIPE5TRE -#define PIPE5TRN_0 USB200.PIPE5TRN -#define PIPEBTRE_0 USB200.PIPEBTRE -#define PIPEBTRN_0 USB200.PIPEBTRN -#define PIPECTRE_0 USB200.PIPECTRE -#define PIPECTRN_0 USB200.PIPECTRN -#define PIPEDTRE_0 USB200.PIPEDTRE -#define PIPEDTRN_0 USB200.PIPEDTRN -#define PIPEETRE_0 USB200.PIPEETRE -#define PIPEETRN_0 USB200.PIPEETRN -#define PIPEFTRE_0 USB200.PIPEFTRE -#define PIPEFTRN_0 USB200.PIPEFTRN -#define PIPE9TRE_0 USB200.PIPE9TRE -#define PIPE9TRN_0 USB200.PIPE9TRN -#define PIPEATRE_0 USB200.PIPEATRE -#define PIPEATRN_0 USB200.PIPEATRN -#define DEVADD0_0 USB200.DEVADD0 -#define DEVADD1_0 USB200.DEVADD1 -#define DEVADD2_0 USB200.DEVADD2 -#define DEVADD3_0 USB200.DEVADD3 -#define DEVADD4_0 USB200.DEVADD4 -#define DEVADD5_0 USB200.DEVADD5 -#define DEVADD6_0 USB200.DEVADD6 -#define DEVADD7_0 USB200.DEVADD7 -#define DEVADD8_0 USB200.DEVADD8 -#define DEVADD9_0 USB200.DEVADD9 -#define DEVADDA_0 USB200.DEVADDA -#define SUSPMODE_0 USB200.SUSPMODE -#define D0FIFOB0_0 USB200.D0FIFOB0 -#define D0FIFOB1_0 USB200.D0FIFOB1 -#define D0FIFOB2_0 USB200.D0FIFOB2 -#define D0FIFOB3_0 USB200.D0FIFOB3 -#define D0FIFOB4_0 USB200.D0FIFOB4 -#define D0FIFOB5_0 USB200.D0FIFOB5 -#define D0FIFOB6_0 USB200.D0FIFOB6 -#define D0FIFOB7_0 USB200.D0FIFOB7 -#define D1FIFOB0_0 USB200.D1FIFOB0 -#define D1FIFOB1_0 USB200.D1FIFOB1 -#define D1FIFOB2_0 USB200.D1FIFOB2 -#define D1FIFOB3_0 USB200.D1FIFOB3 -#define D1FIFOB4_0 USB200.D1FIFOB4 -#define D1FIFOB5_0 USB200.D1FIFOB5 -#define D1FIFOB6_0 USB200.D1FIFOB6 -#define D1FIFOB7_0 USB200.D1FIFOB7 -#define SYSCFG0_1 USB201.SYSCFG0 -#define BUSWAIT_1 USB201.BUSWAIT -#define SYSSTS0_1 USB201.SYSSTS0 -#define DVSTCTR0_1 USB201.DVSTCTR0 -#define TESTMODE_1 USB201.TESTMODE -#define D0FBCFG_1 USB201.D0FBCFG -#define D1FBCFG_1 USB201.D1FBCFG -#define CFIFO_1 USB201.CFIFO.UINT32 -#define CFIFO_1L USB201.CFIFO.UINT16[L] -#define CFIFO_1H USB201.CFIFO.UINT16[H] -#define CFIFO_1LL USB201.CFIFO.UINT8[LL] -#define CFIFO_1LH USB201.CFIFO.UINT8[LH] -#define CFIFO_1HL USB201.CFIFO.UINT8[HL] -#define CFIFO_1HH USB201.CFIFO.UINT8[HH] -#define D0FIFO_1 USB201.D0FIFO.UINT32 -#define D0FIFO_1L USB201.D0FIFO.UINT16[L] -#define D0FIFO_1H USB201.D0FIFO.UINT16[H] -#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL] -#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH] -#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL] -#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH] -#define D1FIFO_1 USB201.D1FIFO.UINT32 -#define D1FIFO_1L USB201.D1FIFO.UINT16[L] -#define D1FIFO_1H USB201.D1FIFO.UINT16[H] -#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL] -#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH] -#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL] -#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH] -#define CFIFOSEL_1 USB201.CFIFOSEL -#define CFIFOCTR_1 USB201.CFIFOCTR -#define D0FIFOSEL_1 USB201.D0FIFOSEL -#define D0FIFOCTR_1 USB201.D0FIFOCTR -#define D1FIFOSEL_1 USB201.D1FIFOSEL -#define D1FIFOCTR_1 USB201.D1FIFOCTR -#define INTENB0_1 USB201.INTENB0 -#define INTENB1_1 USB201.INTENB1 -#define BRDYENB_1 USB201.BRDYENB -#define NRDYENB_1 USB201.NRDYENB -#define BEMPENB_1 USB201.BEMPENB -#define SOFCFG_1 USB201.SOFCFG -#define INTSTS0_1 USB201.INTSTS0 -#define INTSTS1_1 USB201.INTSTS1 -#define BRDYSTS_1 USB201.BRDYSTS -#define NRDYSTS_1 USB201.NRDYSTS -#define BEMPSTS_1 USB201.BEMPSTS -#define FRMNUM_1 USB201.FRMNUM -#define UFRMNUM_1 USB201.UFRMNUM -#define USBADDR_1 USB201.USBADDR -#define USBREQ_1 USB201.USBREQ -#define USBVAL_1 USB201.USBVAL -#define USBINDX_1 USB201.USBINDX -#define USBLENG_1 USB201.USBLENG -#define DCPCFG_1 USB201.DCPCFG -#define DCPMAXP_1 USB201.DCPMAXP -#define DCPCTR_1 USB201.DCPCTR -#define PIPESEL_1 USB201.PIPESEL -#define PIPECFG_1 USB201.PIPECFG -#define PIPEBUF_1 USB201.PIPEBUF -#define PIPEMAXP_1 USB201.PIPEMAXP -#define PIPEPERI_1 USB201.PIPEPERI -#define PIPE1CTR_1 USB201.PIPE1CTR -#define PIPE2CTR_1 USB201.PIPE2CTR -#define PIPE3CTR_1 USB201.PIPE3CTR -#define PIPE4CTR_1 USB201.PIPE4CTR -#define PIPE5CTR_1 USB201.PIPE5CTR -#define PIPE6CTR_1 USB201.PIPE6CTR -#define PIPE7CTR_1 USB201.PIPE7CTR -#define PIPE8CTR_1 USB201.PIPE8CTR -#define PIPE9CTR_1 USB201.PIPE9CTR -#define PIPEACTR_1 USB201.PIPEACTR -#define PIPEBCTR_1 USB201.PIPEBCTR -#define PIPECCTR_1 USB201.PIPECCTR -#define PIPEDCTR_1 USB201.PIPEDCTR -#define PIPEECTR_1 USB201.PIPEECTR -#define PIPEFCTR_1 USB201.PIPEFCTR -#define PIPE1TRE_1 USB201.PIPE1TRE -#define PIPE1TRN_1 USB201.PIPE1TRN -#define PIPE2TRE_1 USB201.PIPE2TRE -#define PIPE2TRN_1 USB201.PIPE2TRN -#define PIPE3TRE_1 USB201.PIPE3TRE -#define PIPE3TRN_1 USB201.PIPE3TRN -#define PIPE4TRE_1 USB201.PIPE4TRE -#define PIPE4TRN_1 USB201.PIPE4TRN -#define PIPE5TRE_1 USB201.PIPE5TRE -#define PIPE5TRN_1 USB201.PIPE5TRN -#define PIPEBTRE_1 USB201.PIPEBTRE -#define PIPEBTRN_1 USB201.PIPEBTRN -#define PIPECTRE_1 USB201.PIPECTRE -#define PIPECTRN_1 USB201.PIPECTRN -#define PIPEDTRE_1 USB201.PIPEDTRE -#define PIPEDTRN_1 USB201.PIPEDTRN -#define PIPEETRE_1 USB201.PIPEETRE -#define PIPEETRN_1 USB201.PIPEETRN -#define PIPEFTRE_1 USB201.PIPEFTRE -#define PIPEFTRN_1 USB201.PIPEFTRN -#define PIPE9TRE_1 USB201.PIPE9TRE -#define PIPE9TRN_1 USB201.PIPE9TRN -#define PIPEATRE_1 USB201.PIPEATRE -#define PIPEATRN_1 USB201.PIPEATRN -#define DEVADD0_1 USB201.DEVADD0 -#define DEVADD1_1 USB201.DEVADD1 -#define DEVADD2_1 USB201.DEVADD2 -#define DEVADD3_1 USB201.DEVADD3 -#define DEVADD4_1 USB201.DEVADD4 -#define DEVADD5_1 USB201.DEVADD5 -#define DEVADD6_1 USB201.DEVADD6 -#define DEVADD7_1 USB201.DEVADD7 -#define DEVADD8_1 USB201.DEVADD8 -#define DEVADD9_1 USB201.DEVADD9 -#define DEVADDA_1 USB201.DEVADDA -#define SUSPMODE_1 USB201.SUSPMODE -#define D0FIFOB0_1 USB201.D0FIFOB0 -#define D0FIFOB1_1 USB201.D0FIFOB1 -#define D0FIFOB2_1 USB201.D0FIFOB2 -#define D0FIFOB3_1 USB201.D0FIFOB3 -#define D0FIFOB4_1 USB201.D0FIFOB4 -#define D0FIFOB5_1 USB201.D0FIFOB5 -#define D0FIFOB6_1 USB201.D0FIFOB6 -#define D0FIFOB7_1 USB201.D0FIFOB7 -#define D1FIFOB0_1 USB201.D1FIFOB0 -#define D1FIFOB1_1 USB201.D1FIFOB1 -#define D1FIFOB2_1 USB201.D1FIFOB2 -#define D1FIFOB3_1 USB201.D1FIFOB3 -#define D1FIFOB4_1 USB201.D1FIFOB4 -#define D1FIFOB5_1 USB201.D1FIFOB5 -#define D1FIFOB6_1 USB201.D1FIFOB6 -#define D1FIFOB7_1 USB201.D1FIFOB7 /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h index d20922524e..3c962342e5 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h @@ -18,21 +18,1004 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : vdc5_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef VDC5_IODEFINE_H #define VDC5_IODEFINE_H /* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ /* ->SEC M1.10.1 : Not magic number */ -struct st_vdc5 -{ /* VDC5 */ +#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ +#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ + + +/* Start of channel array defines of VDC5 */ + +/* Channel array defines of VDC5 */ +/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ +#define VDC5_COUNT (2) +#define VDC5_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ + &VDC50, &VDC51 \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ + + + +/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR2_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ + &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ +#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ +#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ +#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ + &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ +#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ +#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ +#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */ +/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ +#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT (2) +#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ + &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ +#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ +#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ +#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ + + + + +/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ +#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ + &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ +#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ +#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ +#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ +#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ + &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ +#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ +#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ +#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ + + + + +/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ +#define VDC50_FROM_GR0_AB7_ARRAY_COUNT (2) +#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ + &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ +#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ +#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ +#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ + + + + +/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */ +/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ +#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT (2) +#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ +{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ +{ \ + &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ + &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ +} \ +} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ +#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ +#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ +#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ +#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ + + +/* End of channel array defines of VDC5 */ + + +#define VDC50INP_UPDATE (VDC50.INP_UPDATE) +#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT) +#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT) +#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ) +#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ) +#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE) +#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0) +#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1) +#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE) +#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0) +#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1) +#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0) +#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1) +#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0) +#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1) +#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG) +#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE) +#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1) +#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2) +#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3) +#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4) +#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5) +#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6) +#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7) +#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9) +#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0) +#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT) +#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1) +#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2) +#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3) +#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4) +#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5) +#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6) +#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7) +#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1) +#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2) +#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3) +#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4) +#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5) +#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6) +#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7) +#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8) +#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1) +#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE) +#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1) +#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2) +#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3) +#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4) +#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5) +#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6) +#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7) +#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8) +#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9) +#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10) +#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11) +#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1) +#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0) +#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1) +#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2) +#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3) +#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD) +#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT) +#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE) +#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD) +#define VDC50GR0_FLM1 (VDC50.GR0_FLM1) +#define VDC50GR0_FLM2 (VDC50.GR0_FLM2) +#define VDC50GR0_FLM3 (VDC50.GR0_FLM3) +#define VDC50GR0_FLM4 (VDC50.GR0_FLM4) +#define VDC50GR0_FLM5 (VDC50.GR0_FLM5) +#define VDC50GR0_FLM6 (VDC50.GR0_FLM6) +#define VDC50GR0_AB1 (VDC50.GR0_AB1) +#define VDC50GR0_AB2 (VDC50.GR0_AB2) +#define VDC50GR0_AB3 (VDC50.GR0_AB3) +#define VDC50GR0_AB7 (VDC50.GR0_AB7) +#define VDC50GR0_AB8 (VDC50.GR0_AB8) +#define VDC50GR0_AB9 (VDC50.GR0_AB9) +#define VDC50GR0_AB10 (VDC50.GR0_AB10) +#define VDC50GR0_AB11 (VDC50.GR0_AB11) +#define VDC50GR0_BASE (VDC50.GR0_BASE) +#define VDC50GR0_CLUT (VDC50.GR0_CLUT) +#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE) +#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET) +#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1) +#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2) +#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3) +#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1) +#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2) +#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3) +#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4) +#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5) +#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6) +#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1) +#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2) +#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE) +#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0) +#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1) +#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0) +#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1) +#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0) +#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1) +#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE) +#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD) +#define VDC50GR2_FLM1 (VDC50.GR2_FLM1) +#define VDC50GR2_FLM2 (VDC50.GR2_FLM2) +#define VDC50GR2_FLM3 (VDC50.GR2_FLM3) +#define VDC50GR2_FLM4 (VDC50.GR2_FLM4) +#define VDC50GR2_FLM5 (VDC50.GR2_FLM5) +#define VDC50GR2_FLM6 (VDC50.GR2_FLM6) +#define VDC50GR2_AB1 (VDC50.GR2_AB1) +#define VDC50GR2_AB2 (VDC50.GR2_AB2) +#define VDC50GR2_AB3 (VDC50.GR2_AB3) +#define VDC50GR2_AB4 (VDC50.GR2_AB4) +#define VDC50GR2_AB5 (VDC50.GR2_AB5) +#define VDC50GR2_AB6 (VDC50.GR2_AB6) +#define VDC50GR2_AB7 (VDC50.GR2_AB7) +#define VDC50GR2_AB8 (VDC50.GR2_AB8) +#define VDC50GR2_AB9 (VDC50.GR2_AB9) +#define VDC50GR2_AB10 (VDC50.GR2_AB10) +#define VDC50GR2_AB11 (VDC50.GR2_AB11) +#define VDC50GR2_BASE (VDC50.GR2_BASE) +#define VDC50GR2_CLUT (VDC50.GR2_CLUT) +#define VDC50GR2_MON (VDC50.GR2_MON) +#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE) +#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD) +#define VDC50GR3_FLM1 (VDC50.GR3_FLM1) +#define VDC50GR3_FLM2 (VDC50.GR3_FLM2) +#define VDC50GR3_FLM3 (VDC50.GR3_FLM3) +#define VDC50GR3_FLM4 (VDC50.GR3_FLM4) +#define VDC50GR3_FLM5 (VDC50.GR3_FLM5) +#define VDC50GR3_FLM6 (VDC50.GR3_FLM6) +#define VDC50GR3_AB1 (VDC50.GR3_AB1) +#define VDC50GR3_AB2 (VDC50.GR3_AB2) +#define VDC50GR3_AB3 (VDC50.GR3_AB3) +#define VDC50GR3_AB4 (VDC50.GR3_AB4) +#define VDC50GR3_AB5 (VDC50.GR3_AB5) +#define VDC50GR3_AB6 (VDC50.GR3_AB6) +#define VDC50GR3_AB7 (VDC50.GR3_AB7) +#define VDC50GR3_AB8 (VDC50.GR3_AB8) +#define VDC50GR3_AB9 (VDC50.GR3_AB9) +#define VDC50GR3_AB10 (VDC50.GR3_AB10) +#define VDC50GR3_AB11 (VDC50.GR3_AB11) +#define VDC50GR3_BASE (VDC50.GR3_BASE) +#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT) +#define VDC50GR3_MON (VDC50.GR3_MON) +#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE) +#define VDC50GAM_SW (VDC50.GAM_SW) +#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1) +#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2) +#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3) +#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4) +#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5) +#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6) +#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7) +#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8) +#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9) +#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10) +#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11) +#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12) +#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13) +#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14) +#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15) +#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16) +#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1) +#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2) +#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3) +#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4) +#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5) +#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6) +#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7) +#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8) +#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE) +#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1) +#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2) +#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3) +#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4) +#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5) +#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6) +#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7) +#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8) +#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9) +#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10) +#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11) +#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12) +#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13) +#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14) +#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15) +#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16) +#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1) +#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2) +#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3) +#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4) +#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5) +#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6) +#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7) +#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8) +#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE) +#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1) +#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2) +#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3) +#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4) +#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5) +#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6) +#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7) +#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8) +#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9) +#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10) +#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11) +#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12) +#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13) +#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14) +#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15) +#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16) +#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1) +#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2) +#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3) +#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4) +#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5) +#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6) +#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7) +#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8) +#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE) +#define VDC50TCON_TIM (VDC50.TCON_TIM) +#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1) +#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2) +#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1) +#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2) +#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1) +#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2) +#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1) +#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2) +#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1) +#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2) +#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1) +#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2) +#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1) +#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2) +#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE) +#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE) +#define VDC50OUT_SET (VDC50.OUT_SET) +#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1) +#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2) +#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST) +#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA) +#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE) +#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1) +#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2) +#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3) +#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4) +#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5) +#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6) +#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK) +#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT) +#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE) +#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1) +#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2) +#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3) +#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4) +#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5) +#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6) +#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7) +#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9) +#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0) +#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT) +#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1) +#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2) +#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3) +#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4) +#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5) +#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6) +#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7) +#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1) +#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2) +#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3) +#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4) +#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5) +#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6) +#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7) +#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8) +#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1) +#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE) +#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1) +#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2) +#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3) +#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4) +#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5) +#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6) +#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7) +#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8) +#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9) +#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10) +#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11) +#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1) +#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0) +#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1) +#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2) +#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3) +#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD) +#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT) +#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE) +#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD) +#define VDC50GR1_FLM1 (VDC50.GR1_FLM1) +#define VDC50GR1_FLM2 (VDC50.GR1_FLM2) +#define VDC50GR1_FLM3 (VDC50.GR1_FLM3) +#define VDC50GR1_FLM4 (VDC50.GR1_FLM4) +#define VDC50GR1_FLM5 (VDC50.GR1_FLM5) +#define VDC50GR1_FLM6 (VDC50.GR1_FLM6) +#define VDC50GR1_AB1 (VDC50.GR1_AB1) +#define VDC50GR1_AB2 (VDC50.GR1_AB2) +#define VDC50GR1_AB3 (VDC50.GR1_AB3) +#define VDC50GR1_AB4 (VDC50.GR1_AB4) +#define VDC50GR1_AB5 (VDC50.GR1_AB5) +#define VDC50GR1_AB6 (VDC50.GR1_AB6) +#define VDC50GR1_AB7 (VDC50.GR1_AB7) +#define VDC50GR1_AB8 (VDC50.GR1_AB8) +#define VDC50GR1_AB9 (VDC50.GR1_AB9) +#define VDC50GR1_AB10 (VDC50.GR1_AB10) +#define VDC50GR1_AB11 (VDC50.GR1_AB11) +#define VDC50GR1_BASE (VDC50.GR1_BASE) +#define VDC50GR1_CLUT (VDC50.GR1_CLUT) +#define VDC50GR1_MON (VDC50.GR1_MON) +#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE) +#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET) +#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1) +#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2) +#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3) +#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1) +#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2) +#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3) +#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4) +#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5) +#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6) +#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1) +#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2) +#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE) +#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0) +#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1) +#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0) +#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1) +#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0) +#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1) +#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE) +#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1) +#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2) +#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3) +#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4) +#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5) +#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6) +#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7) +#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE) +#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON) +#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE) +#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1) +#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2) +#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3) +#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4) +#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5) +#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6) +#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7) +#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1) +#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2) +#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3) +#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7) +#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1) +#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2) +#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3) +#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8) +#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1) +#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE) +#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1) +#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2) +#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3) +#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4) +#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5) +#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6) +#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7) +#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE) +#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD) +#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1) +#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2) +#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3) +#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4) +#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5) +#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6) +#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1) +#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2) +#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3) +#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7) +#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8) +#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9) +#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10) +#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11) +#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE) +#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT) +#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON) +#define VDC51INP_UPDATE (VDC51.INP_UPDATE) +#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT) +#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT) +#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ) +#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ) +#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE) +#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0) +#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1) +#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE) +#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0) +#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1) +#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0) +#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1) +#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0) +#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1) +#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG) +#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE) +#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1) +#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2) +#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3) +#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4) +#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5) +#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6) +#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7) +#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9) +#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0) +#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT) +#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1) +#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2) +#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3) +#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4) +#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5) +#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6) +#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7) +#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1) +#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2) +#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3) +#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4) +#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5) +#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6) +#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7) +#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8) +#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1) +#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE) +#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1) +#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2) +#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3) +#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4) +#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5) +#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6) +#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7) +#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8) +#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9) +#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10) +#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11) +#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1) +#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0) +#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1) +#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2) +#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3) +#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD) +#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT) +#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE) +#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD) +#define VDC51GR0_FLM1 (VDC51.GR0_FLM1) +#define VDC51GR0_FLM2 (VDC51.GR0_FLM2) +#define VDC51GR0_FLM3 (VDC51.GR0_FLM3) +#define VDC51GR0_FLM4 (VDC51.GR0_FLM4) +#define VDC51GR0_FLM5 (VDC51.GR0_FLM5) +#define VDC51GR0_FLM6 (VDC51.GR0_FLM6) +#define VDC51GR0_AB1 (VDC51.GR0_AB1) +#define VDC51GR0_AB2 (VDC51.GR0_AB2) +#define VDC51GR0_AB3 (VDC51.GR0_AB3) +#define VDC51GR0_AB7 (VDC51.GR0_AB7) +#define VDC51GR0_AB8 (VDC51.GR0_AB8) +#define VDC51GR0_AB9 (VDC51.GR0_AB9) +#define VDC51GR0_AB10 (VDC51.GR0_AB10) +#define VDC51GR0_AB11 (VDC51.GR0_AB11) +#define VDC51GR0_BASE (VDC51.GR0_BASE) +#define VDC51GR0_CLUT (VDC51.GR0_CLUT) +#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE) +#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET) +#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1) +#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2) +#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3) +#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1) +#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2) +#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3) +#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4) +#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5) +#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6) +#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1) +#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2) +#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE) +#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0) +#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1) +#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0) +#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1) +#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0) +#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1) +#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE) +#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD) +#define VDC51GR2_FLM1 (VDC51.GR2_FLM1) +#define VDC51GR2_FLM2 (VDC51.GR2_FLM2) +#define VDC51GR2_FLM3 (VDC51.GR2_FLM3) +#define VDC51GR2_FLM4 (VDC51.GR2_FLM4) +#define VDC51GR2_FLM5 (VDC51.GR2_FLM5) +#define VDC51GR2_FLM6 (VDC51.GR2_FLM6) +#define VDC51GR2_AB1 (VDC51.GR2_AB1) +#define VDC51GR2_AB2 (VDC51.GR2_AB2) +#define VDC51GR2_AB3 (VDC51.GR2_AB3) +#define VDC51GR2_AB4 (VDC51.GR2_AB4) +#define VDC51GR2_AB5 (VDC51.GR2_AB5) +#define VDC51GR2_AB6 (VDC51.GR2_AB6) +#define VDC51GR2_AB7 (VDC51.GR2_AB7) +#define VDC51GR2_AB8 (VDC51.GR2_AB8) +#define VDC51GR2_AB9 (VDC51.GR2_AB9) +#define VDC51GR2_AB10 (VDC51.GR2_AB10) +#define VDC51GR2_AB11 (VDC51.GR2_AB11) +#define VDC51GR2_BASE (VDC51.GR2_BASE) +#define VDC51GR2_CLUT (VDC51.GR2_CLUT) +#define VDC51GR2_MON (VDC51.GR2_MON) +#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE) +#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD) +#define VDC51GR3_FLM1 (VDC51.GR3_FLM1) +#define VDC51GR3_FLM2 (VDC51.GR3_FLM2) +#define VDC51GR3_FLM3 (VDC51.GR3_FLM3) +#define VDC51GR3_FLM4 (VDC51.GR3_FLM4) +#define VDC51GR3_FLM5 (VDC51.GR3_FLM5) +#define VDC51GR3_FLM6 (VDC51.GR3_FLM6) +#define VDC51GR3_AB1 (VDC51.GR3_AB1) +#define VDC51GR3_AB2 (VDC51.GR3_AB2) +#define VDC51GR3_AB3 (VDC51.GR3_AB3) +#define VDC51GR3_AB4 (VDC51.GR3_AB4) +#define VDC51GR3_AB5 (VDC51.GR3_AB5) +#define VDC51GR3_AB6 (VDC51.GR3_AB6) +#define VDC51GR3_AB7 (VDC51.GR3_AB7) +#define VDC51GR3_AB8 (VDC51.GR3_AB8) +#define VDC51GR3_AB9 (VDC51.GR3_AB9) +#define VDC51GR3_AB10 (VDC51.GR3_AB10) +#define VDC51GR3_AB11 (VDC51.GR3_AB11) +#define VDC51GR3_BASE (VDC51.GR3_BASE) +#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT) +#define VDC51GR3_MON (VDC51.GR3_MON) +#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE) +#define VDC51GAM_SW (VDC51.GAM_SW) +#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1) +#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2) +#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3) +#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4) +#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5) +#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6) +#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7) +#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8) +#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9) +#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10) +#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11) +#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12) +#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13) +#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14) +#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15) +#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16) +#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1) +#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2) +#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3) +#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4) +#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5) +#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6) +#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7) +#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8) +#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE) +#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1) +#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2) +#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3) +#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4) +#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5) +#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6) +#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7) +#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8) +#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9) +#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10) +#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11) +#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12) +#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13) +#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14) +#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15) +#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16) +#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1) +#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2) +#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3) +#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4) +#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5) +#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6) +#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7) +#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8) +#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE) +#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1) +#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2) +#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3) +#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4) +#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5) +#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6) +#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7) +#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8) +#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9) +#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10) +#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11) +#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12) +#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13) +#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14) +#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15) +#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16) +#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1) +#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2) +#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3) +#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4) +#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5) +#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6) +#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7) +#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8) +#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE) +#define VDC51TCON_TIM (VDC51.TCON_TIM) +#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1) +#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2) +#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1) +#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2) +#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1) +#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2) +#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1) +#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2) +#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1) +#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2) +#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1) +#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2) +#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1) +#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2) +#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE) +#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE) +#define VDC51OUT_SET (VDC51.OUT_SET) +#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1) +#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2) +#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST) +#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA) +#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE) +#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1) +#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2) +#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3) +#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4) +#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5) +#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6) +#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK) +#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT) +#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE) +#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1) +#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2) +#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3) +#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4) +#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5) +#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6) +#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7) +#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9) +#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0) +#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT) +#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1) +#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2) +#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3) +#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4) +#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5) +#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6) +#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7) +#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1) +#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2) +#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3) +#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4) +#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5) +#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6) +#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7) +#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8) +#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1) +#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE) +#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1) +#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2) +#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3) +#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4) +#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5) +#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6) +#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7) +#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8) +#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9) +#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10) +#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11) +#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1) +#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0) +#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1) +#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2) +#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3) +#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD) +#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT) +#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE) +#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD) +#define VDC51GR1_FLM1 (VDC51.GR1_FLM1) +#define VDC51GR1_FLM2 (VDC51.GR1_FLM2) +#define VDC51GR1_FLM3 (VDC51.GR1_FLM3) +#define VDC51GR1_FLM4 (VDC51.GR1_FLM4) +#define VDC51GR1_FLM5 (VDC51.GR1_FLM5) +#define VDC51GR1_FLM6 (VDC51.GR1_FLM6) +#define VDC51GR1_AB1 (VDC51.GR1_AB1) +#define VDC51GR1_AB2 (VDC51.GR1_AB2) +#define VDC51GR1_AB3 (VDC51.GR1_AB3) +#define VDC51GR1_AB4 (VDC51.GR1_AB4) +#define VDC51GR1_AB5 (VDC51.GR1_AB5) +#define VDC51GR1_AB6 (VDC51.GR1_AB6) +#define VDC51GR1_AB7 (VDC51.GR1_AB7) +#define VDC51GR1_AB8 (VDC51.GR1_AB8) +#define VDC51GR1_AB9 (VDC51.GR1_AB9) +#define VDC51GR1_AB10 (VDC51.GR1_AB10) +#define VDC51GR1_AB11 (VDC51.GR1_AB11) +#define VDC51GR1_BASE (VDC51.GR1_BASE) +#define VDC51GR1_CLUT (VDC51.GR1_CLUT) +#define VDC51GR1_MON (VDC51.GR1_MON) +#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE) +#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET) +#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1) +#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2) +#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3) +#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1) +#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2) +#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3) +#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4) +#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5) +#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6) +#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1) +#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2) +#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE) +#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0) +#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1) +#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0) +#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1) +#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0) +#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1) +#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE) +#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1) +#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2) +#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3) +#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4) +#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5) +#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6) +#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7) +#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE) +#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON) +#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE) +#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1) +#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2) +#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3) +#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4) +#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5) +#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6) +#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7) +#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1) +#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2) +#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3) +#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7) +#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1) +#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2) +#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3) +#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8) +#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1) +#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE) +#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1) +#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2) +#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3) +#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4) +#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5) +#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6) +#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7) +#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE) +#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD) +#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1) +#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2) +#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3) +#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4) +#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5) +#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6) +#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1) +#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2) +#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3) +#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7) +#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8) +#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9) +#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10) +#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11) +#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE) +#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT) +#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON) + +#define VDC5_IMGCNT_NR_CNT0_COUNT (2) +#define VDC5_SC0_SCL0_FRC1_COUNT (7) +#define VDC5_SC0_SCL0_DS1_COUNT (7) +#define VDC5_SC0_SCL0_US1_COUNT (8) +#define VDC5_SC0_SCL1_WR1_COUNT (4) +#define VDC5_SC0_SCL1_PBUF0_COUNT (4) +#define VDC5_GR0_FLM1_COUNT (6) +#define VDC5_GR0_AB1_COUNT (3) +#define VDC5_ADJ0_ENH_TIM1_COUNT (3) +#define VDC5_ADJ0_ENH_SHP1_COUNT (6) +#define VDC5_ADJ0_ENH_LTI1_COUNT (2) +#define VDC5_GR2_FLM1_COUNT (6) +#define VDC5_GR2_AB1_COUNT (3) +#define VDC5_GR3_FLM1_COUNT (6) +#define VDC5_GR3_AB1_COUNT (3) +#define VDC5_GAM_G_LUT1_COUNT (16) +#define VDC5_GAM_G_AREA1_COUNT (8) +#define VDC5_GAM_B_LUT1_COUNT (16) +#define VDC5_GAM_B_AREA1_COUNT (8) +#define VDC5_GAM_R_LUT1_COUNT (16) +#define VDC5_GAM_R_AREA1_COUNT (8) +#define VDC5_TCON_TIM_STVA1_COUNT (2) +#define VDC5_TCON_TIM_STVB1_COUNT (2) +#define VDC5_TCON_TIM_STH1_COUNT (2) +#define VDC5_TCON_TIM_STB1_COUNT (2) +#define VDC5_TCON_TIM_CPV1_COUNT (2) +#define VDC5_TCON_TIM_POLA1_COUNT (2) +#define VDC5_TCON_TIM_POLB1_COUNT (2) +#define VDC5_OUT_BRIGHT1_COUNT (2) +#define VDC5_SYSCNT_INT1_COUNT (6) +#define VDC5_SC1_SCL0_FRC1_COUNT (7) +#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) +#define VDC5_SC1_SC1_SCL0_US1_COUNT (8) +#define VDC5_SC1_SCL1_WR1_COUNT (4) +#define VDC5_SC1_SCL1_PBUF0_COUNT (4) +#define VDC5_GR1_FLM1_COUNT (6) +#define VDC5_GR1_AB1_COUNT (3) +#define VDC5_ADJ1_ENH_TIM1_COUNT (3) +#define VDC5_ADJ1_ENH_SHP1_COUNT (6) +#define VDC5_ADJ1_ENH_LTI1_COUNT (2) +#define VDC5_GR_VIN_AB1_COUNT (7) +#define VDC5_OIR_SCL0_FRC1_COUNT (7) +#define VDC5_OIR_SCL0_DS1_COUNT (3) +#define VDC5_OIR_SCL1_WR1_COUNT (4) +#define VDC5_GR_OIR_FLM1_COUNT (6) +#define VDC5_GR_OIR_AB1_COUNT (3) + + +typedef struct st_vdc5 +{ + /* VDC5 */ volatile uint32_t INP_UPDATE; /* INP_UPDATE */ volatile uint32_t INP_SEL_CNT; /* INP_SEL_CNT */ volatile uint32_t INP_EXT_SYNC_CNT; /* INP_EXT_SYNC_CNT */ @@ -40,7 +1023,8 @@ struct st_vdc5 volatile uint32_t INP_DLY_ADJ; /* INP_DLY_ADJ */ volatile uint8_t dummy1[108]; /* */ volatile uint32_t IMGCNT_UPDATE; /* IMGCNT_UPDATE */ -#define VDC5_IMGCNT_NR_CNT0_COUNT 2 + +/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */ volatile uint32_t IMGCNT_NR_CNT0; /* IMGCNT_NR_CNT0 */ volatile uint32_t IMGCNT_NR_CNT1; /* IMGCNT_NR_CNT1 */ volatile uint8_t dummy2[20]; /* */ @@ -54,9 +1038,11 @@ struct st_vdc5 volatile uint8_t dummy3[4]; /* */ volatile uint32_t IMGCNT_DRC_REG; /* IMGCNT_DRC_REG */ volatile uint8_t dummy4[60]; /* */ + /* start of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ -#define VDC5_SC0_SCL0_FRC1_COUNT 7 + +/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ volatile uint32_t SC0_SCL0_FRC3; /* SC0_SCL0_FRC3 */ @@ -68,7 +1054,8 @@ struct st_vdc5 volatile uint32_t SC0_SCL0_FRC9; /* SC0_SCL0_FRC9 */ volatile uint16_t SC0_SCL0_MON0; /* SC0_SCL0_MON0 */ volatile uint16_t SC0_SCL0_INT; /* SC0_SCL0_INT */ -#define VDC5_SC0_SCL0_DS1_COUNT 7 + +/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */ volatile uint32_t SC0_SCL0_DS1; /* SC0_SCL0_DS1 */ volatile uint32_t SC0_SCL0_DS2; /* SC0_SCL0_DS2 */ volatile uint32_t SC0_SCL0_DS3; /* SC0_SCL0_DS3 */ @@ -76,7 +1063,8 @@ struct st_vdc5 volatile uint32_t SC0_SCL0_DS5; /* SC0_SCL0_DS5 */ volatile uint32_t SC0_SCL0_DS6; /* SC0_SCL0_DS6 */ volatile uint32_t SC0_SCL0_DS7; /* SC0_SCL0_DS7 */ -#define VDC5_SC0_SCL0_US1_COUNT 8 + +/* #define VDC5_SC0_SCL0_US1_COUNT (8) */ volatile uint32_t SC0_SCL0_US1; /* SC0_SCL0_US1 */ volatile uint32_t SC0_SCL0_US2; /* SC0_SCL0_US2 */ volatile uint32_t SC0_SCL0_US3; /* SC0_SCL0_US3 */ @@ -90,7 +1078,8 @@ struct st_vdc5 volatile uint8_t dummy7[16]; /* */ volatile uint32_t SC0_SCL1_UPDATE; /* SC0_SCL1_UPDATE */ volatile uint8_t dummy8[4]; /* */ -#define VDC5_SC0_SCL1_WR1_COUNT 4 + +/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */ volatile uint32_t SC0_SCL1_WR1; /* SC0_SCL1_WR1 */ volatile uint32_t SC0_SCL1_WR2; /* SC0_SCL1_WR2 */ volatile uint32_t SC0_SCL1_WR3; /* SC0_SCL1_WR3 */ @@ -102,35 +1091,44 @@ struct st_vdc5 volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ + /* end of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC0_SCL1_WR11; /* SC0_SCL1_WR11 */ volatile uint32_t SC0_SCL1_MON1; /* SC0_SCL1_MON1 */ + /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ -#define VDC5_SC0_SCL1_PBUF0_COUNT 4 + +/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */ volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ + /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ volatile uint8_t dummy10[44]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ -#define VDC5_GR0_FLM1_COUNT 6 + +/* #define VDC5_GR0_FLM1_COUNT (6) */ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ volatile uint32_t GR0_FLM2; /* GR0_FLM2 */ volatile uint32_t GR0_FLM3; /* GR0_FLM3 */ volatile uint32_t GR0_FLM4; /* GR0_FLM4 */ volatile uint32_t GR0_FLM5; /* GR0_FLM5 */ volatile uint32_t GR0_FLM6; /* GR0_FLM6 */ -#define VDC5_GR0_AB1_COUNT 3 + +/* #define VDC5_GR0_AB1_COUNT (3) */ volatile uint32_t GR0_AB1; /* GR0_AB1 */ volatile uint32_t GR0_AB2; /* GR0_AB2 */ volatile uint32_t GR0_AB3; /* GR0_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint8_t dummy11[12]; /* */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR0_AB7; /* GR0_AB7 */ volatile uint32_t GR0_AB8; /* GR0_AB8 */ @@ -138,24 +1136,29 @@ struct st_vdc5 volatile uint32_t GR0_AB10; /* GR0_AB10 */ volatile uint32_t GR0_AB11; /* GR0_AB11 */ volatile uint32_t GR0_BASE; /* GR0_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR0_CLUT; /* GR0_CLUT */ volatile uint8_t dummy12[44]; /* */ + /* start of struct st_vdc5_from_adj0_update */ volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ -#define VDC5_ADJ0_ENH_TIM1_COUNT 3 + +/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ volatile uint32_t ADJ0_ENH_TIM2; /* ADJ0_ENH_TIM2 */ volatile uint32_t ADJ0_ENH_TIM3; /* ADJ0_ENH_TIM3 */ -#define VDC5_ADJ0_ENH_SHP1_COUNT 6 + +/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */ volatile uint32_t ADJ0_ENH_SHP1; /* ADJ0_ENH_SHP1 */ volatile uint32_t ADJ0_ENH_SHP2; /* ADJ0_ENH_SHP2 */ volatile uint32_t ADJ0_ENH_SHP3; /* ADJ0_ENH_SHP3 */ volatile uint32_t ADJ0_ENH_SHP4; /* ADJ0_ENH_SHP4 */ volatile uint32_t ADJ0_ENH_SHP5; /* ADJ0_ENH_SHP5 */ volatile uint32_t ADJ0_ENH_SHP6; /* ADJ0_ENH_SHP6 */ -#define VDC5_ADJ0_ENH_LTI1_COUNT 2 + +/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */ volatile uint32_t ADJ0_ENH_LTI1; /* ADJ0_ENH_LTI1 */ volatile uint32_t ADJ0_ENH_LTI2; /* ADJ0_ENH_LTI2 */ volatile uint32_t ADJ0_MTX_MODE; /* ADJ0_MTX_MODE */ @@ -165,26 +1168,32 @@ struct st_vdc5 volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ + /* end of struct st_vdc5_from_adj0_update */ volatile uint8_t dummy13[48]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR2_UPDATE; /* GR2_UPDATE */ volatile uint32_t GR2_FLM_RD; /* GR2_FLM_RD */ -#define VDC5_GR2_FLM1_COUNT 6 + +/* #define VDC5_GR2_FLM1_COUNT (6) */ volatile uint32_t GR2_FLM1; /* GR2_FLM1 */ volatile uint32_t GR2_FLM2; /* GR2_FLM2 */ volatile uint32_t GR2_FLM3; /* GR2_FLM3 */ volatile uint32_t GR2_FLM4; /* GR2_FLM4 */ volatile uint32_t GR2_FLM5; /* GR2_FLM5 */ volatile uint32_t GR2_FLM6; /* GR2_FLM6 */ -#define VDC5_GR2_AB1_COUNT 3 + +/* #define VDC5_GR2_AB1_COUNT (3) */ volatile uint32_t GR2_AB1; /* GR2_AB1 */ volatile uint32_t GR2_AB2; /* GR2_AB2 */ volatile uint32_t GR2_AB3; /* GR2_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR2_AB4; /* GR2_AB4 */ volatile uint32_t GR2_AB5; /* GR2_AB5 */ volatile uint32_t GR2_AB6; /* GR2_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR2_AB7; /* GR2_AB7 */ volatile uint32_t GR2_AB8; /* GR2_AB8 */ @@ -192,28 +1201,34 @@ struct st_vdc5 volatile uint32_t GR2_AB10; /* GR2_AB10 */ volatile uint32_t GR2_AB11; /* GR2_AB11 */ volatile uint32_t GR2_BASE; /* GR2_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR2_CLUT; /* GR2_CLUT */ volatile uint32_t GR2_MON; /* GR2_MON */ volatile uint8_t dummy14[40]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR3_UPDATE; /* GR3_UPDATE */ volatile uint32_t GR3_FLM_RD; /* GR3_FLM_RD */ -#define VDC5_GR3_FLM1_COUNT 6 + +/* #define VDC5_GR3_FLM1_COUNT (6) */ volatile uint32_t GR3_FLM1; /* GR3_FLM1 */ volatile uint32_t GR3_FLM2; /* GR3_FLM2 */ volatile uint32_t GR3_FLM3; /* GR3_FLM3 */ volatile uint32_t GR3_FLM4; /* GR3_FLM4 */ volatile uint32_t GR3_FLM5; /* GR3_FLM5 */ volatile uint32_t GR3_FLM6; /* GR3_FLM6 */ -#define VDC5_GR3_AB1_COUNT 3 + +/* #define VDC5_GR3_AB1_COUNT (3) */ volatile uint32_t GR3_AB1; /* GR3_AB1 */ volatile uint32_t GR3_AB2; /* GR3_AB2 */ volatile uint32_t GR3_AB3; /* GR3_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR3_AB4; /* GR3_AB4 */ volatile uint32_t GR3_AB5; /* GR3_AB5 */ volatile uint32_t GR3_AB6; /* GR3_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR3_AB7; /* GR3_AB7 */ volatile uint32_t GR3_AB8; /* GR3_AB8 */ @@ -221,13 +1236,15 @@ struct st_vdc5 volatile uint32_t GR3_AB10; /* GR3_AB10 */ volatile uint32_t GR3_AB11; /* GR3_AB11 */ volatile uint32_t GR3_BASE; /* GR3_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR3_CLUT_INT; /* GR3_CLUT_INT */ volatile uint32_t GR3_MON; /* GR3_MON */ volatile uint8_t dummy15[40]; /* */ volatile uint32_t GAM_G_UPDATE; /* GAM_G_UPDATE */ volatile uint32_t GAM_SW; /* GAM_SW */ -#define VDC5_GAM_G_LUT1_COUNT 16 + +/* #define VDC5_GAM_G_LUT1_COUNT (16) */ volatile uint32_t GAM_G_LUT1; /* GAM_G_LUT1 */ volatile uint32_t GAM_G_LUT2; /* GAM_G_LUT2 */ volatile uint32_t GAM_G_LUT3; /* GAM_G_LUT3 */ @@ -244,7 +1261,8 @@ struct st_vdc5 volatile uint32_t GAM_G_LUT14; /* GAM_G_LUT14 */ volatile uint32_t GAM_G_LUT15; /* GAM_G_LUT15 */ volatile uint32_t GAM_G_LUT16; /* GAM_G_LUT16 */ -#define VDC5_GAM_G_AREA1_COUNT 8 + +/* #define VDC5_GAM_G_AREA1_COUNT (8) */ volatile uint32_t GAM_G_AREA1; /* GAM_G_AREA1 */ volatile uint32_t GAM_G_AREA2; /* GAM_G_AREA2 */ volatile uint32_t GAM_G_AREA3; /* GAM_G_AREA3 */ @@ -256,7 +1274,8 @@ struct st_vdc5 volatile uint8_t dummy16[24]; /* */ volatile uint32_t GAM_B_UPDATE; /* GAM_B_UPDATE */ volatile uint8_t dummy17[4]; /* */ -#define VDC5_GAM_B_LUT1_COUNT 16 + +/* #define VDC5_GAM_B_LUT1_COUNT (16) */ volatile uint32_t GAM_B_LUT1; /* GAM_B_LUT1 */ volatile uint32_t GAM_B_LUT2; /* GAM_B_LUT2 */ volatile uint32_t GAM_B_LUT3; /* GAM_B_LUT3 */ @@ -273,7 +1292,8 @@ struct st_vdc5 volatile uint32_t GAM_B_LUT14; /* GAM_B_LUT14 */ volatile uint32_t GAM_B_LUT15; /* GAM_B_LUT15 */ volatile uint32_t GAM_B_LUT16; /* GAM_B_LUT16 */ -#define VDC5_GAM_B_AREA1_COUNT 8 + +/* #define VDC5_GAM_B_AREA1_COUNT (8) */ volatile uint32_t GAM_B_AREA1; /* GAM_B_AREA1 */ volatile uint32_t GAM_B_AREA2; /* GAM_B_AREA2 */ volatile uint32_t GAM_B_AREA3; /* GAM_B_AREA3 */ @@ -285,7 +1305,8 @@ struct st_vdc5 volatile uint8_t dummy18[24]; /* */ volatile uint32_t GAM_R_UPDATE; /* GAM_R_UPDATE */ volatile uint8_t dummy19[4]; /* */ -#define VDC5_GAM_R_LUT1_COUNT 16 + +/* #define VDC5_GAM_R_LUT1_COUNT (16) */ volatile uint32_t GAM_R_LUT1; /* GAM_R_LUT1 */ volatile uint32_t GAM_R_LUT2; /* GAM_R_LUT2 */ volatile uint32_t GAM_R_LUT3; /* GAM_R_LUT3 */ @@ -302,7 +1323,8 @@ struct st_vdc5 volatile uint32_t GAM_R_LUT14; /* GAM_R_LUT14 */ volatile uint32_t GAM_R_LUT15; /* GAM_R_LUT15 */ volatile uint32_t GAM_R_LUT16; /* GAM_R_LUT16 */ -#define VDC5_GAM_R_AREA1_COUNT 8 + +/* #define VDC5_GAM_R_AREA1_COUNT (8) */ volatile uint32_t GAM_R_AREA1; /* GAM_R_AREA1 */ volatile uint32_t GAM_R_AREA2; /* GAM_R_AREA2 */ volatile uint32_t GAM_R_AREA3; /* GAM_R_AREA3 */ @@ -314,32 +1336,40 @@ struct st_vdc5 volatile uint8_t dummy20[24]; /* */ volatile uint32_t TCON_UPDATE; /* TCON_UPDATE */ volatile uint32_t TCON_TIM; /* TCON_TIM */ -#define VDC5_TCON_TIM_STVA1_COUNT 2 + +/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */ volatile uint32_t TCON_TIM_STVA1; /* TCON_TIM_STVA1 */ volatile uint32_t TCON_TIM_STVA2; /* TCON_TIM_STVA2 */ -#define VDC5_TCON_TIM_STVB1_COUNT 2 + +/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */ volatile uint32_t TCON_TIM_STVB1; /* TCON_TIM_STVB1 */ volatile uint32_t TCON_TIM_STVB2; /* TCON_TIM_STVB2 */ -#define VDC5_TCON_TIM_STH1_COUNT 2 + +/* #define VDC5_TCON_TIM_STH1_COUNT (2) */ volatile uint32_t TCON_TIM_STH1; /* TCON_TIM_STH1 */ volatile uint32_t TCON_TIM_STH2; /* TCON_TIM_STH2 */ -#define VDC5_TCON_TIM_STB1_COUNT 2 + +/* #define VDC5_TCON_TIM_STB1_COUNT (2) */ volatile uint32_t TCON_TIM_STB1; /* TCON_TIM_STB1 */ volatile uint32_t TCON_TIM_STB2; /* TCON_TIM_STB2 */ -#define VDC5_TCON_TIM_CPV1_COUNT 2 + +/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */ volatile uint32_t TCON_TIM_CPV1; /* TCON_TIM_CPV1 */ volatile uint32_t TCON_TIM_CPV2; /* TCON_TIM_CPV2 */ -#define VDC5_TCON_TIM_POLA1_COUNT 2 + +/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */ volatile uint32_t TCON_TIM_POLA1; /* TCON_TIM_POLA1 */ volatile uint32_t TCON_TIM_POLA2; /* TCON_TIM_POLA2 */ -#define VDC5_TCON_TIM_POLB1_COUNT 2 + +/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */ volatile uint32_t TCON_TIM_POLB1; /* TCON_TIM_POLB1 */ volatile uint32_t TCON_TIM_POLB2; /* TCON_TIM_POLB2 */ volatile uint32_t TCON_TIM_DE; /* TCON_TIM_DE */ volatile uint8_t dummy21[60]; /* */ volatile uint32_t OUT_UPDATE; /* OUT_UPDATE */ volatile uint32_t OUT_SET; /* OUT_SET */ -#define VDC5_OUT_BRIGHT1_COUNT 2 + +/* #define VDC5_OUT_BRIGHT1_COUNT (2) */ volatile uint32_t OUT_BRIGHT1; /* OUT_BRIGHT1 */ volatile uint32_t OUT_BRIGHT2; /* OUT_BRIGHT2 */ volatile uint32_t OUT_CONTRAST; /* OUT_CONTRAST */ @@ -347,7 +1377,8 @@ struct st_vdc5 volatile uint8_t dummy22[12]; /* */ volatile uint32_t OUT_CLK_PHASE; /* OUT_CLK_PHASE */ volatile uint8_t dummy23[88]; /* */ -#define VDC5_SYSCNT_INT1_COUNT 6 + +/* #define VDC5_SYSCNT_INT1_COUNT (6) */ volatile uint32_t SYSCNT_INT1; /* SYSCNT_INT1 */ volatile uint32_t SYSCNT_INT2; /* SYSCNT_INT2 */ volatile uint32_t SYSCNT_INT3; /* SYSCNT_INT3 */ @@ -357,9 +1388,11 @@ struct st_vdc5 volatile uint16_t SYSCNT_PANEL_CLK; /* SYSCNT_PANEL_CLK */ volatile uint16_t SYSCNT_CLUT; /* SYSCNT_CLUT */ volatile uint8_t dummy24[356]; /* */ + /* start of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC1_SCL0_UPDATE; /* SC1_SCL0_UPDATE */ -#define VDC5_SC1_SCL0_FRC1_COUNT 7 + +/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */ volatile uint32_t SC1_SCL0_FRC1; /* SC1_SCL0_FRC1 */ volatile uint32_t SC1_SCL0_FRC2; /* SC1_SCL0_FRC2 */ volatile uint32_t SC1_SCL0_FRC3; /* SC1_SCL0_FRC3 */ @@ -371,7 +1404,8 @@ struct st_vdc5 volatile uint32_t SC1_SCL0_FRC9; /* SC1_SCL0_FRC9 */ volatile uint16_t SC1_SCL0_MON0; /* SC1_SCL0_MON0 */ volatile uint16_t SC1_SCL0_INT; /* SC1_SCL0_INT */ -#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7 + +/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */ volatile uint32_t SC1_SCL0_DS1; /* SC1_SCL0_DS1 */ volatile uint32_t SC1_SCL0_DS2; /* SC1_SCL0_DS2 */ volatile uint32_t SC1_SCL0_DS3; /* SC1_SCL0_DS3 */ @@ -379,7 +1413,8 @@ struct st_vdc5 volatile uint32_t SC1_SCL0_DS5; /* SC1_SCL0_DS5 */ volatile uint32_t SC1_SCL0_DS6; /* SC1_SCL0_DS6 */ volatile uint32_t SC1_SCL0_DS7; /* SC1_SCL0_DS7 */ -#define VDC5_SC1_SC1_SCL0_US1_COUNT 8 + +/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */ volatile uint32_t SC1_SCL0_US1; /* SC1_SCL0_US1 */ volatile uint32_t SC1_SCL0_US2; /* SC1_SCL0_US2 */ volatile uint32_t SC1_SCL0_US3; /* SC1_SCL0_US3 */ @@ -393,7 +1428,8 @@ struct st_vdc5 volatile uint8_t dummy27[16]; /* */ volatile uint32_t SC1_SCL1_UPDATE; /* SC1_SCL1_UPDATE */ volatile uint8_t dummy28[4]; /* */ -#define VDC5_SC1_SCL1_WR1_COUNT 4 + +/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */ volatile uint32_t SC1_SCL1_WR1; /* SC1_SCL1_WR1 */ volatile uint32_t SC1_SCL1_WR2; /* SC1_SCL1_WR2 */ volatile uint32_t SC1_SCL1_WR3; /* SC1_SCL1_WR3 */ @@ -405,37 +1441,46 @@ struct st_vdc5 volatile uint32_t SC1_SCL1_WR8; /* SC1_SCL1_WR8 */ volatile uint32_t SC1_SCL1_WR9; /* SC1_SCL1_WR9 */ volatile uint32_t SC1_SCL1_WR10; /* SC1_SCL1_WR10 */ + /* end of struct st_vdc5_from_sc0_scl0_update */ volatile uint32_t SC1_SCL1_WR11; /* SC1_SCL1_WR11 */ volatile uint32_t SC1_SCL1_MON1; /* SC1_SCL1_MON1 */ + /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */ -#define VDC5_SC1_SCL1_PBUF0_COUNT 4 + +/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */ volatile uint32_t SC1_SCL1_PBUF0; /* SC1_SCL1_PBUF0 */ volatile uint32_t SC1_SCL1_PBUF1; /* SC1_SCL1_PBUF1 */ volatile uint32_t SC1_SCL1_PBUF2; /* SC1_SCL1_PBUF2 */ volatile uint32_t SC1_SCL1_PBUF3; /* SC1_SCL1_PBUF3 */ volatile uint32_t SC1_SCL1_PBUF_FLD; /* SC1_SCL1_PBUF_FLD */ volatile uint32_t SC1_SCL1_PBUF_CNT; /* SC1_SCL1_PBUF_CNT */ + /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */ volatile uint8_t dummy30[44]; /* */ + /* start of struct st_vdc5_from_gr0_update */ volatile uint32_t GR1_UPDATE; /* GR1_UPDATE */ volatile uint32_t GR1_FLM_RD; /* GR1_FLM_RD */ -#define VDC5_GR1_FLM1_COUNT 6 + +/* #define VDC5_GR1_FLM1_COUNT (6) */ volatile uint32_t GR1_FLM1; /* GR1_FLM1 */ volatile uint32_t GR1_FLM2; /* GR1_FLM2 */ volatile uint32_t GR1_FLM3; /* GR1_FLM3 */ volatile uint32_t GR1_FLM4; /* GR1_FLM4 */ volatile uint32_t GR1_FLM5; /* GR1_FLM5 */ volatile uint32_t GR1_FLM6; /* GR1_FLM6 */ -#define VDC5_GR1_AB1_COUNT 3 + +/* #define VDC5_GR1_AB1_COUNT (3) */ volatile uint32_t GR1_AB1; /* GR1_AB1 */ volatile uint32_t GR1_AB2; /* GR1_AB2 */ volatile uint32_t GR1_AB3; /* GR1_AB3 */ + /* end of struct st_vdc5_from_gr0_update */ volatile uint32_t GR1_AB4; /* GR1_AB4 */ volatile uint32_t GR1_AB5; /* GR1_AB5 */ volatile uint32_t GR1_AB6; /* GR1_AB6 */ + /* start of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR1_AB7; /* GR1_AB7 */ volatile uint32_t GR1_AB8; /* GR1_AB8 */ @@ -443,25 +1488,30 @@ struct st_vdc5 volatile uint32_t GR1_AB10; /* GR1_AB10 */ volatile uint32_t GR1_AB11; /* GR1_AB11 */ volatile uint32_t GR1_BASE; /* GR1_BASE */ + /* end of struct st_vdc5_from_gr0_ab7 */ volatile uint32_t GR1_CLUT; /* GR1_CLUT */ volatile uint32_t GR1_MON; /* GR1_MON */ volatile uint8_t dummy31[40]; /* */ + /* start of struct st_vdc5_from_adj0_update */ volatile uint32_t ADJ1_UPDATE; /* ADJ1_UPDATE */ volatile uint32_t ADJ1_BKSTR_SET; /* ADJ1_BKSTR_SET */ -#define VDC5_ADJ1_ENH_TIM1_COUNT 3 + +/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */ volatile uint32_t ADJ1_ENH_TIM1; /* ADJ1_ENH_TIM1 */ volatile uint32_t ADJ1_ENH_TIM2; /* ADJ1_ENH_TIM2 */ volatile uint32_t ADJ1_ENH_TIM3; /* ADJ1_ENH_TIM3 */ -#define VDC5_ADJ1_ENH_SHP1_COUNT 6 + +/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */ volatile uint32_t ADJ1_ENH_SHP1; /* ADJ1_ENH_SHP1 */ volatile uint32_t ADJ1_ENH_SHP2; /* ADJ1_ENH_SHP2 */ volatile uint32_t ADJ1_ENH_SHP3; /* ADJ1_ENH_SHP3 */ volatile uint32_t ADJ1_ENH_SHP4; /* ADJ1_ENH_SHP4 */ volatile uint32_t ADJ1_ENH_SHP5; /* ADJ1_ENH_SHP5 */ volatile uint32_t ADJ1_ENH_SHP6; /* ADJ1_ENH_SHP6 */ -#define VDC5_ADJ1_ENH_LTI1_COUNT 2 + +/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */ volatile uint32_t ADJ1_ENH_LTI1; /* ADJ1_ENH_LTI1 */ volatile uint32_t ADJ1_ENH_LTI2; /* ADJ1_ENH_LTI2 */ volatile uint32_t ADJ1_MTX_MODE; /* ADJ1_MTX_MODE */ @@ -471,11 +1521,13 @@ struct st_vdc5 volatile uint32_t ADJ1_MTX_CBB_ADJ1; /* ADJ1_MTX_CBB_ADJ1 */ volatile uint32_t ADJ1_MTX_CRR_ADJ0; /* ADJ1_MTX_CRR_ADJ0 */ volatile uint32_t ADJ1_MTX_CRR_ADJ1; /* ADJ1_MTX_CRR_ADJ1 */ + /* end of struct st_vdc5_from_adj0_update */ volatile uint8_t dummy32[48]; /* */ volatile uint32_t GR_VIN_UPDATE; /* GR_VIN_UPDATE */ volatile uint8_t dummy33[28]; /* */ -#define VDC5_GR_VIN_AB1_COUNT 7 + +/* #define VDC5_GR_VIN_AB1_COUNT (7) */ volatile uint32_t GR_VIN_AB1; /* GR_VIN_AB1 */ volatile uint32_t GR_VIN_AB2; /* GR_VIN_AB2 */ volatile uint32_t GR_VIN_AB3; /* GR_VIN_AB3 */ @@ -489,7 +1541,8 @@ struct st_vdc5 volatile uint32_t GR_VIN_MON; /* GR_VIN_MON */ volatile uint8_t dummy36[40]; /* */ volatile uint32_t OIR_SCL0_UPDATE; /* OIR_SCL0_UPDATE */ -#define VDC5_OIR_SCL0_FRC1_COUNT 7 + +/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */ volatile uint32_t OIR_SCL0_FRC1; /* OIR_SCL0_FRC1 */ volatile uint32_t OIR_SCL0_FRC2; /* OIR_SCL0_FRC2 */ volatile uint32_t OIR_SCL0_FRC3; /* OIR_SCL0_FRC3 */ @@ -498,7 +1551,8 @@ struct st_vdc5 volatile uint32_t OIR_SCL0_FRC6; /* OIR_SCL0_FRC6 */ volatile uint32_t OIR_SCL0_FRC7; /* OIR_SCL0_FRC7 */ volatile uint8_t dummy37[12]; /* */ -#define VDC5_OIR_SCL0_DS1_COUNT 3 + +/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */ volatile uint32_t OIR_SCL0_DS1; /* OIR_SCL0_DS1 */ volatile uint32_t OIR_SCL0_DS2; /* OIR_SCL0_DS2 */ volatile uint32_t OIR_SCL0_DS3; /* OIR_SCL0_DS3 */ @@ -514,7 +1568,8 @@ struct st_vdc5 volatile uint8_t dummy41[16]; /* */ volatile uint32_t OIR_SCL1_UPDATE; /* OIR_SCL1_UPDATE */ volatile uint8_t dummy42[4]; /* */ -#define VDC5_OIR_SCL1_WR1_COUNT 4 + +/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */ volatile uint32_t OIR_SCL1_WR1; /* OIR_SCL1_WR1 */ volatile uint32_t OIR_SCL1_WR2; /* OIR_SCL1_WR2 */ volatile uint32_t OIR_SCL1_WR3; /* OIR_SCL1_WR3 */ @@ -526,14 +1581,16 @@ struct st_vdc5 volatile uint8_t dummy44[88]; /* */ volatile uint32_t GR_OIR_UPDATE; /* GR_OIR_UPDATE */ volatile uint32_t GR_OIR_FLM_RD; /* GR_OIR_FLM_RD */ -#define VDC5_GR_OIR_FLM1_COUNT 6 + +/* #define VDC5_GR_OIR_FLM1_COUNT (6) */ volatile uint32_t GR_OIR_FLM1; /* GR_OIR_FLM1 */ volatile uint32_t GR_OIR_FLM2; /* GR_OIR_FLM2 */ volatile uint32_t GR_OIR_FLM3; /* GR_OIR_FLM3 */ volatile uint32_t GR_OIR_FLM4; /* GR_OIR_FLM4 */ volatile uint32_t GR_OIR_FLM5; /* GR_OIR_FLM5 */ volatile uint32_t GR_OIR_FLM6; /* GR_OIR_FLM6 */ -#define VDC5_GR_OIR_AB1_COUNT 3 + +/* #define VDC5_GR_OIR_AB1_COUNT (3) */ volatile uint32_t GR_OIR_AB1; /* GR_OIR_AB1 */ volatile uint32_t GR_OIR_AB2; /* GR_OIR_AB2 */ volatile uint32_t GR_OIR_AB3; /* GR_OIR_AB3 */ @@ -546,11 +1603,12 @@ struct st_vdc5 volatile uint32_t GR_OIR_BASE; /* GR_OIR_BASE */ volatile uint32_t GR_OIR_CLUT; /* GR_OIR_CLUT */ volatile uint32_t GR_OIR_MON; /* GR_OIR_MON */ -}; +} r_io_vdc5_t; -struct st_vdc5_from_gr0_update +typedef struct st_vdc5_from_gr0_update { + volatile uint32_t GR0_UPDATE; /* GR0_UPDATE */ volatile uint32_t GR0_FLM_RD; /* GR0_FLM_RD */ volatile uint32_t GR0_FLM1; /* GR0_FLM1 */ @@ -562,22 +1620,24 @@ struct st_vdc5_from_gr0_update volatile uint32_t GR0_AB1; /* GR0_AB1 */ volatile uint32_t GR0_AB2; /* GR0_AB2 */ volatile uint32_t GR0_AB3; /* GR0_AB3 */ -}; +} r_io_vdc5_from_gr0_update_t; -struct st_vdc5_from_gr0_ab7 +typedef struct st_vdc5_from_gr0_ab7 { + volatile uint32_t GR0_AB7; /* GR0_AB7 */ volatile uint32_t GR0_AB8; /* GR0_AB8 */ volatile uint32_t GR0_AB9; /* GR0_AB9 */ volatile uint32_t GR0_AB10; /* GR0_AB10 */ volatile uint32_t GR0_AB11; /* GR0_AB11 */ volatile uint32_t GR0_BASE; /* GR0_BASE */ -}; +} r_io_vdc5_from_gr0_ab7_t; -struct st_vdc5_from_adj0_update +typedef struct st_vdc5_from_adj0_update { + volatile uint32_t ADJ0_UPDATE; /* ADJ0_UPDATE */ volatile uint32_t ADJ0_BKSTR_SET; /* ADJ0_BKSTR_SET */ volatile uint32_t ADJ0_ENH_TIM1; /* ADJ0_ENH_TIM1 */ @@ -598,11 +1658,12 @@ struct st_vdc5_from_adj0_update volatile uint32_t ADJ0_MTX_CBB_ADJ1; /* ADJ0_MTX_CBB_ADJ1 */ volatile uint32_t ADJ0_MTX_CRR_ADJ0; /* ADJ0_MTX_CRR_ADJ0 */ volatile uint32_t ADJ0_MTX_CRR_ADJ1; /* ADJ0_MTX_CRR_ADJ1 */ -}; +} r_io_vdc5_from_adj0_update_t; -struct st_vdc5_from_sc0_scl0_update +typedef struct st_vdc5_from_sc0_scl0_update { + volatile uint32_t SC0_SCL0_UPDATE; /* SC0_SCL0_UPDATE */ volatile uint32_t SC0_SCL0_FRC1; /* SC0_SCL0_FRC1 */ volatile uint32_t SC0_SCL0_FRC2; /* SC0_SCL0_FRC2 */ @@ -646,951 +1707,82 @@ struct st_vdc5_from_sc0_scl0_update volatile uint32_t SC0_SCL1_WR8; /* SC0_SCL1_WR8 */ volatile uint32_t SC0_SCL1_WR9; /* SC0_SCL1_WR9 */ volatile uint32_t SC0_SCL1_WR10; /* SC0_SCL1_WR10 */ -}; +} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */; -struct st_vdc5_from_sc0_scl1_pbuf0 +typedef struct st_vdc5_from_sc0_scl1_pbuf0 { + volatile uint32_t SC0_SCL1_PBUF0; /* SC0_SCL1_PBUF0 */ volatile uint32_t SC0_SCL1_PBUF1; /* SC0_SCL1_PBUF1 */ volatile uint32_t SC0_SCL1_PBUF2; /* SC0_SCL1_PBUF2 */ volatile uint32_t SC0_SCL1_PBUF3; /* SC0_SCL1_PBUF3 */ volatile uint32_t SC0_SCL1_PBUF_FLD; /* SC0_SCL1_PBUF_FLD */ volatile uint32_t SC0_SCL1_PBUF_CNT; /* SC0_SCL1_PBUF_CNT */ -}; +} r_io_vdc5_from_sc0_scl1_pbuf0_t; -#define VDC50 (*(struct st_vdc5 *)0xFCFF7400uL) /* VDC50 */ -#define VDC51 (*(struct st_vdc5 *)0xFCFF9400uL) /* VDC51 */ +/* Channel array defines of VDC5 (2)*/ +#ifdef DECLARE_VDC5_CHANNELS +volatile struct st_vdc5* VDC5[ VDC5_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC5_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC5_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS +volatile struct st_vdc5_from_sc0_scl1_pbuf0* VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_sc0_scl0_update* VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_adj0_update* VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_ab7* VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */ + +#ifdef DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS +volatile struct st_vdc5_from_gr0_update* VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] = + /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ + VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST; + /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ +#endif /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */ +/* End of channel array defines of VDC5 (2)*/ -/* Start of channnel array defines of VDC5 */ - -/* Channnel array defines of VDC5 */ -/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */ -#define VDC5_COUNT 2 -#define VDC5_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ - &VDC50, &VDC51 \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ - - - -/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT 2 -#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \ - &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */ -#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */ -#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */ -#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */ - - - - -/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \ - &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */ -#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */ -#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */ -#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */ -/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */ -#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT 2 -#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \ - &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */ -#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */ -#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */ -#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */ - - - - -/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */ -#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \ - &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */ -#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */ -#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */ -#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */ -#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \ - &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */ -#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */ -#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */ -#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */ - - - - -/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */ -#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT 2 -#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \ - &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */ -#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */ -#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */ -#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */ - - - - -/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */ -/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */ -#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT 2 -#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \ -{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ -{ \ - &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \ - &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \ -} \ -} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ -#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */ -#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */ -#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */ -#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */ - - -/* End of channnel array defines of VDC5 */ - - -#define VDC50INP_UPDATE VDC50.INP_UPDATE -#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT -#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT -#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ -#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ -#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE -#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0 -#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1 -#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE -#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0 -#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1 -#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0 -#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1 -#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0 -#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1 -#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG -#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE -#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1 -#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2 -#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3 -#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4 -#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5 -#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6 -#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7 -#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9 -#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0 -#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT -#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1 -#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2 -#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3 -#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4 -#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5 -#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6 -#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7 -#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1 -#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2 -#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3 -#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4 -#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5 -#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6 -#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7 -#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8 -#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1 -#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE -#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1 -#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2 -#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3 -#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4 -#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5 -#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6 -#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7 -#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8 -#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9 -#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10 -#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11 -#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1 -#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0 -#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1 -#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2 -#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3 -#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD -#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT -#define VDC50GR0_UPDATE VDC50.GR0_UPDATE -#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD -#define VDC50GR0_FLM1 VDC50.GR0_FLM1 -#define VDC50GR0_FLM2 VDC50.GR0_FLM2 -#define VDC50GR0_FLM3 VDC50.GR0_FLM3 -#define VDC50GR0_FLM4 VDC50.GR0_FLM4 -#define VDC50GR0_FLM5 VDC50.GR0_FLM5 -#define VDC50GR0_FLM6 VDC50.GR0_FLM6 -#define VDC50GR0_AB1 VDC50.GR0_AB1 -#define VDC50GR0_AB2 VDC50.GR0_AB2 -#define VDC50GR0_AB3 VDC50.GR0_AB3 -#define VDC50GR0_AB7 VDC50.GR0_AB7 -#define VDC50GR0_AB8 VDC50.GR0_AB8 -#define VDC50GR0_AB9 VDC50.GR0_AB9 -#define VDC50GR0_AB10 VDC50.GR0_AB10 -#define VDC50GR0_AB11 VDC50.GR0_AB11 -#define VDC50GR0_BASE VDC50.GR0_BASE -#define VDC50GR0_CLUT VDC50.GR0_CLUT -#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE -#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET -#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1 -#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2 -#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3 -#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1 -#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2 -#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3 -#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4 -#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5 -#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6 -#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1 -#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2 -#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE -#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0 -#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1 -#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0 -#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1 -#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0 -#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1 -#define VDC50GR2_UPDATE VDC50.GR2_UPDATE -#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD -#define VDC50GR2_FLM1 VDC50.GR2_FLM1 -#define VDC50GR2_FLM2 VDC50.GR2_FLM2 -#define VDC50GR2_FLM3 VDC50.GR2_FLM3 -#define VDC50GR2_FLM4 VDC50.GR2_FLM4 -#define VDC50GR2_FLM5 VDC50.GR2_FLM5 -#define VDC50GR2_FLM6 VDC50.GR2_FLM6 -#define VDC50GR2_AB1 VDC50.GR2_AB1 -#define VDC50GR2_AB2 VDC50.GR2_AB2 -#define VDC50GR2_AB3 VDC50.GR2_AB3 -#define VDC50GR2_AB4 VDC50.GR2_AB4 -#define VDC50GR2_AB5 VDC50.GR2_AB5 -#define VDC50GR2_AB6 VDC50.GR2_AB6 -#define VDC50GR2_AB7 VDC50.GR2_AB7 -#define VDC50GR2_AB8 VDC50.GR2_AB8 -#define VDC50GR2_AB9 VDC50.GR2_AB9 -#define VDC50GR2_AB10 VDC50.GR2_AB10 -#define VDC50GR2_AB11 VDC50.GR2_AB11 -#define VDC50GR2_BASE VDC50.GR2_BASE -#define VDC50GR2_CLUT VDC50.GR2_CLUT -#define VDC50GR2_MON VDC50.GR2_MON -#define VDC50GR3_UPDATE VDC50.GR3_UPDATE -#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD -#define VDC50GR3_FLM1 VDC50.GR3_FLM1 -#define VDC50GR3_FLM2 VDC50.GR3_FLM2 -#define VDC50GR3_FLM3 VDC50.GR3_FLM3 -#define VDC50GR3_FLM4 VDC50.GR3_FLM4 -#define VDC50GR3_FLM5 VDC50.GR3_FLM5 -#define VDC50GR3_FLM6 VDC50.GR3_FLM6 -#define VDC50GR3_AB1 VDC50.GR3_AB1 -#define VDC50GR3_AB2 VDC50.GR3_AB2 -#define VDC50GR3_AB3 VDC50.GR3_AB3 -#define VDC50GR3_AB4 VDC50.GR3_AB4 -#define VDC50GR3_AB5 VDC50.GR3_AB5 -#define VDC50GR3_AB6 VDC50.GR3_AB6 -#define VDC50GR3_AB7 VDC50.GR3_AB7 -#define VDC50GR3_AB8 VDC50.GR3_AB8 -#define VDC50GR3_AB9 VDC50.GR3_AB9 -#define VDC50GR3_AB10 VDC50.GR3_AB10 -#define VDC50GR3_AB11 VDC50.GR3_AB11 -#define VDC50GR3_BASE VDC50.GR3_BASE -#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT -#define VDC50GR3_MON VDC50.GR3_MON -#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE -#define VDC50GAM_SW VDC50.GAM_SW -#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1 -#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2 -#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3 -#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4 -#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5 -#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6 -#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7 -#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8 -#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9 -#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10 -#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11 -#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12 -#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13 -#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14 -#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15 -#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16 -#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1 -#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2 -#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3 -#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4 -#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5 -#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6 -#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7 -#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8 -#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE -#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1 -#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2 -#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3 -#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4 -#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5 -#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6 -#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7 -#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8 -#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9 -#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10 -#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11 -#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12 -#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13 -#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14 -#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15 -#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16 -#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1 -#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2 -#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3 -#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4 -#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5 -#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6 -#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7 -#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8 -#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE -#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1 -#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2 -#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3 -#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4 -#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5 -#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6 -#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7 -#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8 -#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9 -#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10 -#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11 -#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12 -#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13 -#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14 -#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15 -#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16 -#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1 -#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2 -#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3 -#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4 -#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5 -#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6 -#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7 -#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8 -#define VDC50TCON_UPDATE VDC50.TCON_UPDATE -#define VDC50TCON_TIM VDC50.TCON_TIM -#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1 -#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2 -#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1 -#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2 -#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1 -#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2 -#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1 -#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2 -#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1 -#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2 -#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1 -#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2 -#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1 -#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2 -#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE -#define VDC50OUT_UPDATE VDC50.OUT_UPDATE -#define VDC50OUT_SET VDC50.OUT_SET -#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1 -#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2 -#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST -#define VDC50OUT_PDTHA VDC50.OUT_PDTHA -#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE -#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1 -#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2 -#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3 -#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4 -#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5 -#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6 -#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK -#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT -#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE -#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1 -#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2 -#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3 -#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4 -#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5 -#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6 -#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7 -#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9 -#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0 -#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT -#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1 -#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2 -#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3 -#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4 -#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5 -#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6 -#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7 -#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1 -#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2 -#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3 -#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4 -#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5 -#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6 -#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7 -#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8 -#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1 -#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE -#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1 -#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2 -#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3 -#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4 -#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5 -#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6 -#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7 -#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8 -#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9 -#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10 -#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11 -#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1 -#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0 -#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1 -#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2 -#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3 -#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD -#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT -#define VDC50GR1_UPDATE VDC50.GR1_UPDATE -#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD -#define VDC50GR1_FLM1 VDC50.GR1_FLM1 -#define VDC50GR1_FLM2 VDC50.GR1_FLM2 -#define VDC50GR1_FLM3 VDC50.GR1_FLM3 -#define VDC50GR1_FLM4 VDC50.GR1_FLM4 -#define VDC50GR1_FLM5 VDC50.GR1_FLM5 -#define VDC50GR1_FLM6 VDC50.GR1_FLM6 -#define VDC50GR1_AB1 VDC50.GR1_AB1 -#define VDC50GR1_AB2 VDC50.GR1_AB2 -#define VDC50GR1_AB3 VDC50.GR1_AB3 -#define VDC50GR1_AB4 VDC50.GR1_AB4 -#define VDC50GR1_AB5 VDC50.GR1_AB5 -#define VDC50GR1_AB6 VDC50.GR1_AB6 -#define VDC50GR1_AB7 VDC50.GR1_AB7 -#define VDC50GR1_AB8 VDC50.GR1_AB8 -#define VDC50GR1_AB9 VDC50.GR1_AB9 -#define VDC50GR1_AB10 VDC50.GR1_AB10 -#define VDC50GR1_AB11 VDC50.GR1_AB11 -#define VDC50GR1_BASE VDC50.GR1_BASE -#define VDC50GR1_CLUT VDC50.GR1_CLUT -#define VDC50GR1_MON VDC50.GR1_MON -#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE -#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET -#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1 -#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2 -#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3 -#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1 -#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2 -#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3 -#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4 -#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5 -#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6 -#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1 -#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2 -#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE -#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0 -#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1 -#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0 -#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1 -#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0 -#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1 -#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE -#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1 -#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2 -#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3 -#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4 -#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5 -#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6 -#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7 -#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE -#define VDC50GR_VIN_MON VDC50.GR_VIN_MON -#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE -#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1 -#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2 -#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3 -#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4 -#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5 -#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6 -#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7 -#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1 -#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2 -#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3 -#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7 -#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1 -#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2 -#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3 -#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8 -#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1 -#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE -#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1 -#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2 -#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3 -#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4 -#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5 -#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6 -#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7 -#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE -#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD -#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1 -#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2 -#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3 -#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4 -#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5 -#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6 -#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1 -#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2 -#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3 -#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7 -#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8 -#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9 -#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10 -#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11 -#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE -#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT -#define VDC50GR_OIR_MON VDC50.GR_OIR_MON -#define VDC51INP_UPDATE VDC51.INP_UPDATE -#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT -#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT -#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ -#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ -#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE -#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0 -#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1 -#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE -#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0 -#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1 -#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0 -#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1 -#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0 -#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1 -#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG -#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE -#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1 -#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2 -#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3 -#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4 -#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5 -#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6 -#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7 -#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9 -#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0 -#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT -#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1 -#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2 -#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3 -#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4 -#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5 -#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6 -#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7 -#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1 -#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2 -#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3 -#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4 -#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5 -#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6 -#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7 -#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8 -#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1 -#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE -#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1 -#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2 -#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3 -#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4 -#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5 -#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6 -#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7 -#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8 -#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9 -#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10 -#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11 -#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1 -#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0 -#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1 -#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2 -#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3 -#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD -#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT -#define VDC51GR0_UPDATE VDC51.GR0_UPDATE -#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD -#define VDC51GR0_FLM1 VDC51.GR0_FLM1 -#define VDC51GR0_FLM2 VDC51.GR0_FLM2 -#define VDC51GR0_FLM3 VDC51.GR0_FLM3 -#define VDC51GR0_FLM4 VDC51.GR0_FLM4 -#define VDC51GR0_FLM5 VDC51.GR0_FLM5 -#define VDC51GR0_FLM6 VDC51.GR0_FLM6 -#define VDC51GR0_AB1 VDC51.GR0_AB1 -#define VDC51GR0_AB2 VDC51.GR0_AB2 -#define VDC51GR0_AB3 VDC51.GR0_AB3 -#define VDC51GR0_AB7 VDC51.GR0_AB7 -#define VDC51GR0_AB8 VDC51.GR0_AB8 -#define VDC51GR0_AB9 VDC51.GR0_AB9 -#define VDC51GR0_AB10 VDC51.GR0_AB10 -#define VDC51GR0_AB11 VDC51.GR0_AB11 -#define VDC51GR0_BASE VDC51.GR0_BASE -#define VDC51GR0_CLUT VDC51.GR0_CLUT -#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE -#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET -#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1 -#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2 -#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3 -#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1 -#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2 -#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3 -#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4 -#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5 -#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6 -#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1 -#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2 -#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE -#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0 -#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1 -#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0 -#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1 -#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0 -#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1 -#define VDC51GR2_UPDATE VDC51.GR2_UPDATE -#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD -#define VDC51GR2_FLM1 VDC51.GR2_FLM1 -#define VDC51GR2_FLM2 VDC51.GR2_FLM2 -#define VDC51GR2_FLM3 VDC51.GR2_FLM3 -#define VDC51GR2_FLM4 VDC51.GR2_FLM4 -#define VDC51GR2_FLM5 VDC51.GR2_FLM5 -#define VDC51GR2_FLM6 VDC51.GR2_FLM6 -#define VDC51GR2_AB1 VDC51.GR2_AB1 -#define VDC51GR2_AB2 VDC51.GR2_AB2 -#define VDC51GR2_AB3 VDC51.GR2_AB3 -#define VDC51GR2_AB4 VDC51.GR2_AB4 -#define VDC51GR2_AB5 VDC51.GR2_AB5 -#define VDC51GR2_AB6 VDC51.GR2_AB6 -#define VDC51GR2_AB7 VDC51.GR2_AB7 -#define VDC51GR2_AB8 VDC51.GR2_AB8 -#define VDC51GR2_AB9 VDC51.GR2_AB9 -#define VDC51GR2_AB10 VDC51.GR2_AB10 -#define VDC51GR2_AB11 VDC51.GR2_AB11 -#define VDC51GR2_BASE VDC51.GR2_BASE -#define VDC51GR2_CLUT VDC51.GR2_CLUT -#define VDC51GR2_MON VDC51.GR2_MON -#define VDC51GR3_UPDATE VDC51.GR3_UPDATE -#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD -#define VDC51GR3_FLM1 VDC51.GR3_FLM1 -#define VDC51GR3_FLM2 VDC51.GR3_FLM2 -#define VDC51GR3_FLM3 VDC51.GR3_FLM3 -#define VDC51GR3_FLM4 VDC51.GR3_FLM4 -#define VDC51GR3_FLM5 VDC51.GR3_FLM5 -#define VDC51GR3_FLM6 VDC51.GR3_FLM6 -#define VDC51GR3_AB1 VDC51.GR3_AB1 -#define VDC51GR3_AB2 VDC51.GR3_AB2 -#define VDC51GR3_AB3 VDC51.GR3_AB3 -#define VDC51GR3_AB4 VDC51.GR3_AB4 -#define VDC51GR3_AB5 VDC51.GR3_AB5 -#define VDC51GR3_AB6 VDC51.GR3_AB6 -#define VDC51GR3_AB7 VDC51.GR3_AB7 -#define VDC51GR3_AB8 VDC51.GR3_AB8 -#define VDC51GR3_AB9 VDC51.GR3_AB9 -#define VDC51GR3_AB10 VDC51.GR3_AB10 -#define VDC51GR3_AB11 VDC51.GR3_AB11 -#define VDC51GR3_BASE VDC51.GR3_BASE -#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT -#define VDC51GR3_MON VDC51.GR3_MON -#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE -#define VDC51GAM_SW VDC51.GAM_SW -#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1 -#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2 -#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3 -#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4 -#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5 -#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6 -#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7 -#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8 -#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9 -#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10 -#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11 -#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12 -#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13 -#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14 -#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15 -#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16 -#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1 -#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2 -#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3 -#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4 -#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5 -#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6 -#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7 -#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8 -#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE -#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1 -#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2 -#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3 -#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4 -#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5 -#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6 -#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7 -#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8 -#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9 -#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10 -#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11 -#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12 -#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13 -#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14 -#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15 -#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16 -#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1 -#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2 -#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3 -#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4 -#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5 -#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6 -#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7 -#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8 -#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE -#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1 -#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2 -#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3 -#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4 -#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5 -#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6 -#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7 -#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8 -#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9 -#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10 -#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11 -#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12 -#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13 -#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14 -#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15 -#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16 -#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1 -#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2 -#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3 -#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4 -#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5 -#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6 -#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7 -#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8 -#define VDC51TCON_UPDATE VDC51.TCON_UPDATE -#define VDC51TCON_TIM VDC51.TCON_TIM -#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1 -#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2 -#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1 -#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2 -#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1 -#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2 -#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1 -#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2 -#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1 -#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2 -#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1 -#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2 -#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1 -#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2 -#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE -#define VDC51OUT_UPDATE VDC51.OUT_UPDATE -#define VDC51OUT_SET VDC51.OUT_SET -#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1 -#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2 -#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST -#define VDC51OUT_PDTHA VDC51.OUT_PDTHA -#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE -#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1 -#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2 -#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3 -#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4 -#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5 -#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6 -#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK -#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT -#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE -#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1 -#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2 -#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3 -#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4 -#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5 -#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6 -#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7 -#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9 -#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0 -#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT -#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1 -#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2 -#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3 -#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4 -#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5 -#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6 -#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7 -#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1 -#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2 -#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3 -#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4 -#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5 -#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6 -#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7 -#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8 -#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1 -#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE -#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1 -#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2 -#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3 -#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4 -#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5 -#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6 -#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7 -#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8 -#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9 -#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10 -#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11 -#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1 -#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0 -#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1 -#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2 -#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3 -#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD -#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT -#define VDC51GR1_UPDATE VDC51.GR1_UPDATE -#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD -#define VDC51GR1_FLM1 VDC51.GR1_FLM1 -#define VDC51GR1_FLM2 VDC51.GR1_FLM2 -#define VDC51GR1_FLM3 VDC51.GR1_FLM3 -#define VDC51GR1_FLM4 VDC51.GR1_FLM4 -#define VDC51GR1_FLM5 VDC51.GR1_FLM5 -#define VDC51GR1_FLM6 VDC51.GR1_FLM6 -#define VDC51GR1_AB1 VDC51.GR1_AB1 -#define VDC51GR1_AB2 VDC51.GR1_AB2 -#define VDC51GR1_AB3 VDC51.GR1_AB3 -#define VDC51GR1_AB4 VDC51.GR1_AB4 -#define VDC51GR1_AB5 VDC51.GR1_AB5 -#define VDC51GR1_AB6 VDC51.GR1_AB6 -#define VDC51GR1_AB7 VDC51.GR1_AB7 -#define VDC51GR1_AB8 VDC51.GR1_AB8 -#define VDC51GR1_AB9 VDC51.GR1_AB9 -#define VDC51GR1_AB10 VDC51.GR1_AB10 -#define VDC51GR1_AB11 VDC51.GR1_AB11 -#define VDC51GR1_BASE VDC51.GR1_BASE -#define VDC51GR1_CLUT VDC51.GR1_CLUT -#define VDC51GR1_MON VDC51.GR1_MON -#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE -#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET -#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1 -#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2 -#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3 -#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1 -#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2 -#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3 -#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4 -#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5 -#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6 -#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1 -#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2 -#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE -#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0 -#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1 -#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0 -#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1 -#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0 -#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1 -#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE -#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1 -#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2 -#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3 -#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4 -#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5 -#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6 -#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7 -#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE -#define VDC51GR_VIN_MON VDC51.GR_VIN_MON -#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE -#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1 -#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2 -#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3 -#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4 -#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5 -#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6 -#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7 -#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1 -#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2 -#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3 -#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7 -#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1 -#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2 -#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3 -#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8 -#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1 -#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE -#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1 -#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2 -#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3 -#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4 -#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5 -#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6 -#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7 -#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE -#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD -#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1 -#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2 -#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3 -#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4 -#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5 -#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6 -#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1 -#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2 -#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3 -#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7 -#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8 -#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9 -#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10 -#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11 -#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE -#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT -#define VDC51GR_OIR_MON VDC51.GR_OIR_MON /* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ /* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h index 0ee2a53210..82b448e56c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h @@ -18,29 +18,40 @@ * you agree to the additional terms and conditions found by accessing the * following link: * http://www.renesas.com/disclaimer* -* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. +* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved. *******************************************************************************/ /******************************************************************************* * File Name : wdt_iodefine.h * $Rev: $ * $Date:: $ -* Description : Definition of I/O Register (V1.00a) +* Description : Definition of I/O Register for RZ/A1H,M (V2.00h) ******************************************************************************/ #ifndef WDT_IODEFINE_H #define WDT_IODEFINE_H - -struct st_wdt -{ /* WDT */ - volatile uint16_t WTCSR; /* WTCSR */ - volatile uint16_t WTCNT; /* WTCNT */ - volatile uint16_t WRCSR; /* WRCSR */ -}; - +/* ->QAC 0639 : Over 127 members (C90) */ +/* ->QAC 0857 : Over 1024 #define (C90) */ +/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */ +/* ->SEC M1.10.1 : Not magic number */ #define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */ -#define WDTWTCSR WDT.WTCSR -#define WDTWTCNT WDT.WTCNT -#define WDTWRCSR WDT.WRCSR +#define WDTWTCSR (WDT.WTCSR) +#define WDTWTCNT (WDT.WTCNT) +#define WDTWRCSR (WDT.WRCSR) + + +typedef struct st_wdt +{ + /* WDT */ + volatile uint16_t WTCSR; /* WTCSR */ + volatile uint16_t WTCNT; /* WTCNT */ + volatile uint16_t WRCSR; /* WRCSR */ +} r_io_wdt_t; + + +/* <-SEC M1.10.1 */ +/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */ +/* <-QAC 0857 */ +/* <-QAC 0639 */ #endif diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c deleted file mode 100644 index ed05e4c50d..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c +++ /dev/null @@ -1,243 +0,0 @@ -/**************************************************************************//** - * @file mmu_Renesas_RZ_A1.c - * @brief MMU Startup File for - * mmu_Renesas_RZ_A1 Device Series - * @version V1.01 - * @date 2 Aug 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */ -#define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */ -#define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */ -// L1 Cache info and restrictions about architecture of the caches (CCSIR register): -// Write-Through support *not* available -// Write-Back support available. -// Read allocation support available. -// Write allocation support available. - -//Note: You should use the Shareable attribute carefully. -//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings. -//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. -//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. - -//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. -//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. -//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. - - -//Following MMU configuration is expected -//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) -//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) -//Domain 0 is always the Client domain -//Descriptors place all memory in domain 0 -//There are no restrictions by privilege level (PL0 can access all memory) - -#include -#include "VKRZA1H.h" - -//Import symbols from linker -extern uint32_t Image$$VECTORS$$Base; -extern uint32_t Image$$RO_DATA$$Base; -extern uint32_t Image$$RW_DATA$$Base; -extern uint32_t Image$$ZI_DATA$$Base; -#if !defined ( __ICCARM__ ) -extern uint32_t Image$$TTB$$ZI$$Base; -#endif - -#if defined( __CC_ARM ) -#elif defined( __ICCARM__ ) -#else -extern uint32_t Image$$RW_DATA_NC$$Base; -extern uint32_t Image$$ZI_DATA_NC$$Base; -#endif - -extern uint32_t Image$$VECTORS$$Limit; -extern uint32_t Image$$RO_DATA$$Limit; -extern uint32_t Image$$RW_DATA$$Limit; -extern uint32_t Image$$ZI_DATA$$Limit; -#if defined( __CC_ARM ) -#else -extern uint32_t Image$$RW_DATA_NC$$Limit; -extern uint32_t Image$$ZI_DATA_NC$$Limit; -#endif - -#if defined( __ICCARM__ ) -#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) -#define ZI_DATA_SIZE (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1) -#else -#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) -#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) -#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) -#define ZI_DATA_SIZE (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1) -#endif - -#if defined( __CC_ARM ) -#else -#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) -#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) -#endif - -static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 -static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 -static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable -static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable -static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 -static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable - -/* Define global descriptors */ -static uint32_t Page_L1_4k = 0x0; //generic -static uint32_t Page_L1_64k = 0x0; //generic -static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 -static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 - -#if defined ( __ICCARM__ ) -__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; -uint32_t Image$$VECTORS$$Base; -uint32_t Image$$RO_DATA$$Base; -uint32_t Image$$RW_DATA$$Base; -uint32_t Image$$ZI_DATA$$Base; - -uint32_t Image$$VECTORS$$Limit; -uint32_t Image$$RO_DATA$$Limit; -uint32_t Image$$RW_DATA$$Limit; -uint32_t Image$$ZI_DATA$$Limit; -#endif - -void create_translation_table(void) -{ - mmu_region_attributes_Type region; -#if defined ( __ICCARM__ ) -#pragma section=".intvec" -#pragma section=".rodata" -#pragma section=".rwdata" -#pragma section=".bss" - - Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); - Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); - Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); - Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); - Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); - Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); - Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss"); - Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); -#endif - /* - * Generate descriptors. Refer to VKRZA1H.h to get information about attributes - * - */ - //Create descriptors for Vectors, RO, RW, ZI sections - section_normal(Sect_Normal, region); - section_normal_cod(Sect_Normal_Cod, region); - section_normal_ro(Sect_Normal_RO, region); - section_normal_rw(Sect_Normal_RW, region); - //Create descriptors for peripherals - section_device_ro(Sect_Device_RO, region); - section_device_rw(Sect_Device_RW, region); - section_normal_nc(Sect_Normal_NC, region); - //Create descriptors for 64k pages - page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); - //Create descriptors for 4k pages - page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); - - /* - * Define MMU flat-map regions and attributes - * - */ - - //Create 4GB of faulting entries - __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); - - // R7S72100 memory map. - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE , 1, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); - -#if defined( __ICCARM__ ) - //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); -#else - //Define Image - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW); -#endif - -#if defined( __CC_ARM ) - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); -#elif defined ( __ICCARM__ ) - __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE, 10, Sect_Normal_NC); - -#else - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); - __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); -#endif - - /* Set location of level 1 page table - ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) - ; 13:7 - 0x0 - ; 6 - IRGN[0] 0x0 (Inner WB WA) - ; 5 - NOS 0x0 (Non-shared) - ; 4:3 - RGN 0x1 (Outer WB WA) - ; 2 - IMP 0x0 (Implementation Defined) - ; 1 - S 0x0 (Non-shared) - ; 0 - IRGN[1] 0x1 (Inner WB WA) */ - __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); - - /* Set up domain access control register - ; We set domain 0 to Client and all other domains to No Access. - ; All translation table entries specify domain 0 */ - __set_DACR(1); -} - - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c new file mode 100644 index 0000000000..f97edff22f --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c @@ -0,0 +1,281 @@ +/**************************************************************************//** + * @file mmu_VK_RZ_A1H.c + * @brief MMU Configuration for RZ_A1H Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf + + Memory Type +0xffffffff |--------------------------| ------------ + | Peripherals | Device +0xfcf00000 |--------------------------| ------------ + | Page Fault | Fault +0xe8300000 |--------------------------| ------------ + | Peripherals | Device +0xe8000000 |--------------------------| ------------ + | Page Fault | Fault +0x60A00000 |--------------------------| ------------ + | On Chip RAM (10M) Mirror | Fault +0x60000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x5c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | Fault +0x58000000 |--------------------------| ------------ + | CS5 Mirror | Fault +0x54000000 |--------------------------| ------------ + | CS4 Mirror | Fault +0x50000000 |--------------------------| ------------ + | CS3 Mirror | Fault +0x4c000000 |--------------------------| ------------ + | CS2 Mirror | Fault +0x48000000 |--------------------------| ------------ + | CS1 Mirror | Fault +0x44000000 |--------------------------| ------------ + | CS0 Mirror | Fault +0x40000000 |--------------------------| ------------ + | BSC | RW +0x3ff00000 |--------------------------| ------------ + | SPI_MIO_BASE | RW +0x3fe00000 |--------------------------| ------------ + | Page Fault | Fault +0x20A00000 |--------------------------| ------------ + | On Chip RAM (10M) | RW +0x20000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x1c000000 |--------------------------| ------------ + | SPI multi I/O 64MB | RO +0x18000000 |--------------------------| ------------ + | CS5 User Area 64MB | RW +0x14000000 |--------------------------| ------------ + | CS4 User Area 64MB | RW +0x10000000 |--------------------------| ------------ + | CS3 SDRAM 64MB | RW +0x0c000000 |--------------------------| ------------ + | CS2 SDRAM 64MB | RW +0x08000000 |--------------------------| ------------ + | CS1 NOR Flash 64MB | RO +0x04000000 |--------------------------| ------------ + | CS0 NOR Flash 64MB | RO +0x00000000 |--------------------------| ------------ +*/ + +// L1 Cache info and restrictions about architecture of the caches (CCSIR register): +// Write-Through support *not* available +// Write-Back support available. +// Read allocation support available. +// Write allocation support available. + +//Note: You should use the Shareable attribute carefully. +//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings. +//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor. +//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail. + +//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable. +//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable. +//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable. + + +//Following MMU configuration is expected +//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag) +//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor) +//Domain 0 is always the Client domain +//Descriptors should place all memory in domain 0 +//There are no restrictions by privilege level (PL0 can access all memory) + + +#include "VK_RZ_A1H.h" + +//Import symbols from linker +extern uint32_t Image$$VECTORS$$Base; +extern uint32_t Image$$RO_DATA$$Base; +extern uint32_t Image$$RW_DATA$$Base; +extern uint32_t Image$$RW_IRAM1$$Base; +#if !defined ( __ICCARM__ ) +extern uint32_t Image$$TTB$$ZI$$Base; +#endif + +#if defined( __CC_ARM ) +#elif defined( __ICCARM__ ) +#else +extern uint32_t Image$$RW_DATA_NC$$Base; +extern uint32_t Image$$ZI_DATA_NC$$Base; +#endif + +extern uint32_t Image$$VECTORS$$Limit; +extern uint32_t Image$$RO_DATA$$Limit; +extern uint32_t Image$$RW_DATA$$Limit; +extern uint32_t Image$$RW_IRAM1$$Limit; +#if defined( __CC_ARM ) +#else +extern uint32_t Image$$RW_DATA_NC$$Limit; +extern uint32_t Image$$ZI_DATA_NC$$Limit; +#endif + +#if defined( __ICCARM__ ) +#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1) +#else +#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1) +#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1) +#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1) +#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1) +#endif + +#if defined( __CC_ARM ) +#else +#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1) +#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1) +#endif + +static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0 +static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 +static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable +static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable +static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0 +static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable + +/* Define global descriptors */ +static uint32_t Page_L1_4k = 0x0; //generic +static uint32_t Page_L1_64k = 0x0; //generic +static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0 +static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0 + +#if defined ( __ICCARM__ ) +__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram"; +uint32_t Image$$VECTORS$$Base; +uint32_t Image$$RO_DATA$$Base; +uint32_t Image$$RW_DATA$$Base; +uint32_t Image$$RW_IRAM1$$Base; + +uint32_t Image$$VECTORS$$Limit; +uint32_t Image$$RO_DATA$$Limit; +uint32_t Image$$RW_DATA$$Limit; +uint32_t Image$$RW_IRAM1$$Limit; +#endif + +void MMU_CreateTranslationTable(void) +{ + mmu_region_attributes_Type region; +#if defined ( __ICCARM__ ) +#pragma section=".intvec" +#pragma section=".rodata" +#pragma section=".rwdata" +#pragma section=".bss" + + Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec"); + Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec")); + Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata"); + Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata")); + Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); + Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata")); + Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss"); + Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss")); +#endif + /* + * Generate descriptors. Refer to core_ca.h to get information about attributes + * + */ + //Create descriptors for Vectors, RO, RW, ZI sections + section_normal(Sect_Normal, region); + section_normal_cod(Sect_Normal_Cod, region); + section_normal_ro(Sect_Normal_RO, region); + section_normal_rw(Sect_Normal_RW, region); + //Create descriptors for peripherals + section_device_ro(Sect_Device_RO, region); + section_device_rw(Sect_Device_RW, region); + section_normal_nc(Sect_Normal_NC, region); + //Create descriptors for 64k pages + page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region); + //Create descriptors for 4k pages + page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region); + + /* + * Define MMU flat-map regions and attributes + * + */ + + //Create 4GB of faulting entries + MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT); + + // R7S72100 memory map. + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW); + +#if defined( __ICCARM__ ) + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#else + //Define Image + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW); +#endif + +#if defined( __CC_ARM ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); +#elif defined ( __ICCARM__ ) + MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC); + +#else + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC); + MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC); +#endif + + /* Set location of level 1 page table + ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset) + ; 13:7 - 0x0 + ; 6 - IRGN[0] 0x0 (Inner WB WA) + ; 5 - NOS 0x0 (Non-shared) + ; 4:3 - RGN 0x1 (Outer WB WA) + ; 2 - IMP 0x0 (Implementation Defined) + ; 1 - S 0x0 (Non-shared) + ; 0 - IRGN[1] 0x1 (Inner WB WA) */ + __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9); + __ISB(); + + /* Set up domain access control register + ; We set domain 0 to Client and all other domains to No Access. + ; All translation table entries specify domain 0 */ + __set_DACR(1); + __ISB(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c index 13f0eb250f..d04267618c 100644 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c @@ -33,7 +33,6 @@ Includes , "Project Includes" #include "VKRZA1H.h" #include "wdt_iodefine.h" #include "nvic_wrapper.h" -#include "gic.h" /****************************************************************************** Typedef definitions @@ -71,7 +70,7 @@ void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) uint32_t NVIC_GetPriorityGrouping(void) { - return GIC_GetBinaryPoint(0); + return GIC_GetBinaryPoint(); } @@ -214,14 +213,16 @@ uint32_t ITM_SendChar (uint32_t ch) } -int32_t ITM_ReceiveChar (void) { +int32_t ITM_ReceiveChar (void) +{ /* Not support this function */ /* Use mbed Serial */ return (-1); /* no character available */ } -int32_t ITM_CheckChar (void) { +int32_t ITM_CheckChar (void) +{ /* Not support this function */ /* Use mbed Serial */ return (0); /* no character available */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c new file mode 100644 index 0000000000..e5b259184a --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file os_tick_ostm.c + * @brief CMSIS OS Tick implementation for OS Timer + * @version V1.0.1 + * @date 19. September 2017 + ******************************************************************************/ +/* + * Copyright (c) 2017-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifdef MBED_CONF_RTOS_PRESENT + +#include "os_tick.h" +#include "irq_ctrl.h" + +#include + +#include + + +// Define OS TImer interrupt priority +#ifndef OSTM_IRQ_PRIORITY +#define OSTM_IRQ_PRIORITY 0xFFU +#endif + +// Define OS Timer channel and interrupt number +#define OSTM (OSTM0) +#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn) + + +static uint32_t OSTM_Clock; // Timer tick frequency +static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag + + +// Setup OS Tick. +int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler) +{ + uint32_t clock; + uint32_t prio; + uint32_t bits; + + if (freq == 0U) { + return (-1); + } + + OSTM_PendIRQ = 0U; + + // Get CPG.FRQCR[IFC] bits + clock = (CPG.FRQCR >> 8) & 0x03; + + // Determine Divider 2 output clock by using SystemCoreClock + if (clock == 0x03U) { + clock = (SystemCoreClock * 3U); + } + else if (clock == 0x01U) { + clock = (SystemCoreClock * 3U)/2U; + } + else { + clock = SystemCoreClock; + } + + // Determine tick frequency + clock = clock / freq; + + // Save frequency for later + OSTM_Clock = clock; + + // Enable OSTM clock + CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + // Set interval timer mode and disable interrupts when counting starts + OSTM.OSTMnCTL = 0x00U; + + // Set compare value + OSTM.OSTMnCMP = clock - 1U; + + // Disable corresponding IRQ + IRQ_Disable (OSTM_IRQn); + IRQ_ClearPending(OSTM_IRQn); + + // Determine number of implemented priority bits + IRQ_SetPriority (OSTM_IRQn, 0xFFU); + + prio = IRQ_GetPriority (OSTM_IRQn); + + // At least bits [7:4] must be implemented + if ((prio & 0xF0U) == 0U) { + return (-1); + } + + for (bits = 0; bits < 4; bits++) { + if ((prio & 0x01) != 0) { + break; + } + prio >>= 1; + } + + // Adjust configured priority to the number of implemented priority bits + prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL; + + // Set OSTM interrupt priority + IRQ_SetPriority(OSTM_IRQn, prio-1U); + + // Set edge-triggered, non-secure, single CPU targeted IRQ + IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE); + + // Register tick interrupt handler function + IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler); + + // Enable corresponding IRQ + IRQ_Enable (OSTM_IRQn); + + return (0); +} + +/// Enable OS Tick. +int32_t OS_Tick_Enable (void) +{ + + if (OSTM_PendIRQ != 0U) { + OSTM_PendIRQ = 0U; + IRQ_SetPending (OSTM_IRQn); + } + + // Start the OSTM counter + OSTM.OSTMnTS = 0x01U; + + return (0); +} + +/// Disable OS Tick. +int32_t OS_Tick_Disable (void) +{ + + // Stop the OSTM counter + OSTM.OSTMnTT = 0x01U; + + if (IRQ_GetPending(OSTM_IRQn) != 0) { + IRQ_ClearPending (OSTM_IRQn); + OSTM_PendIRQ = 1U; + } + + return (0); +} + +// Acknowledge OS Tick IRQ. +int32_t OS_Tick_AcknowledgeIRQ (void) +{ + return (IRQ_ClearPending (OSTM_IRQn)); +} + +// Get OS Tick IRQ number. +int32_t OS_Tick_GetIRQn (void) +{ + return (OSTM_IRQn); +} + +// Get OS Tick clock. +uint32_t OS_Tick_GetClock (void) +{ + return (OSTM_Clock); +} + +// Get OS Tick interval. +uint32_t OS_Tick_GetInterval (void) +{ + return (OSTM.OSTMnCMP + 1U); +} + +// Get OS Tick count value. +uint32_t OS_Tick_GetCount (void) +{ + uint32_t cmp = OSTM.OSTMnCMP; + return (cmp - OSTM.OSTMnCNT); +} + +// Get OS Tick overflow status. +uint32_t OS_Tick_GetOverflow (void) +{ + return (IRQ_GetPending(OSTM_IRQn)); +} + +#endif + diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c deleted file mode 100644 index eb6d80a8e2..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************//** - * @file pl310.c - * @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions - * @version - * @date 3 December 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ -#include "VKRZA1H.h" - -//Cache Sync operation -void PL310_Sync(void) -{ - PL310->CACHE_SYNC = 0x0; -} - -//return Cache controller cache ID -int PL310_GetID (void) -{ - return PL310->CACHE_ID; -} - -//return Cache controller cache Type -int PL310_GetType (void) -{ - return PL310->CACHE_TYPE; -} - -//Invalidate all cache by way -void PL310_InvAllByWay (void) -{ - unsigned int assoc; - - if (PL310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - PL310->INV_WAY = (1 << assoc) - 1; - while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate - - PL310_Sync(); -} - -//Clean and Invalidate all cache by way -void PL310_CleanInvAllByWay (void) -{ - unsigned int assoc; - - if (PL310->AUX_CNT & (1<<16)) - assoc = 16; - else - assoc = 8; - - PL310->CLEAN_INV_WAY = (1 << assoc) - 1; - while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate - - PL310_Sync(); -} - -//Enable Cache -void PL310_Enable(void) -{ - PL310->CONTROL = 0; - PL310->INTERRUPT_CLEAR = 0x000001FFuL; - PL310->DEBUG_CONTROL = 0; - PL310->DATA_LOCK_0_WAY = 0; - PL310->CACHE_SYNC = 0; - - PL310->CONTROL = 0x01; - PL310_Sync(); -} -//Disable Cache -void PL310_Disable(void) -{ - PL310->CONTROL = 0x00; - PL310_Sync(); -} - -//Invalidate cache by physical address -void PL310_InvPa (void *pa) -{ - PL310->INV_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - -//Clean cache by physical address -void PL310_CleanPa (void *pa) -{ - PL310->CLEAN_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - -//Clean and invalidate cache by physical address -void PL310_CleanInvPa (void *pa) -{ - PL310->CLEAN_INV_LINE_PA = (unsigned int)pa; - PL310_Sync(); -} - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h deleted file mode 100644 index 0960a4d1f3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************//** - * @file pl310.h - * @brief Implementation of pl310 functions - * @version - * @date 11 June 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -#ifndef __PL310 -#define __PL310 - -typedef struct -{ - __I uint32_t CACHE_ID; /*!< Offset: 0x0000 Cache ID Register */ - __I uint32_t CACHE_TYPE; /*!< Offset: 0x0004 Cache Type Register */ - uint32_t RESERVED0[0x3e]; - __IO uint32_t CONTROL; /*!< Offset: 0x0100 Control Register */ - __IO uint32_t AUX_CNT; /*!< Offset: 0x0104 Auxiliary Control */ - uint32_t RESERVED1[0x3e]; - __IO uint32_t EVENT_CONTROL; /*!< Offset: 0x0200 Event Counter Control */ - __IO uint32_t EVENT_COUNTER1_CONF; /*!< Offset: 0x0204 Event Counter 1 Configuration */ - __IO uint32_t EVENT_COUNTER0_CONF; /*!< Offset: 0x0208 Event Counter 1 Configuration */ - uint32_t RESERVED2[0x2]; - __IO uint32_t INTERRUPT_MASK; /*!< Offset: 0x0214 Interrupt Mask */ - __I uint32_t MASKED_INT_STATUS; /*!< Offset: 0x0218 Masked Interrupt Status */ - __I uint32_t RAW_INT_STATUS; /*!< Offset: 0x021c Raw Interrupt Status */ - __O uint32_t INTERRUPT_CLEAR; /*!< Offset: 0x0220 Interrupt Clear */ - uint32_t RESERVED3[0x143]; - __IO uint32_t CACHE_SYNC; /*!< Offset: 0x0730 Cache Sync */ - uint32_t RESERVED4[0xf]; - __IO uint32_t INV_LINE_PA; /*!< Offset: 0x0770 Invalidate Line By PA */ - uint32_t RESERVED6[2]; - __IO uint32_t INV_WAY; /*!< Offset: 0x077c Invalidate by Way */ - uint32_t RESERVED5[0xc]; - __IO uint32_t CLEAN_LINE_PA; /*!< Offset: 0x07b0 Clean Line by PA */ - uint32_t RESERVED7[1]; - __IO uint32_t CLEAN_LINE_INDEX_WAY; /*!< Offset: 0x07b8 Clean Line by Index/Way */ - __IO uint32_t CLEAN_WAY; /*!< Offset: 0x07bc Clean by Way */ - uint32_t RESERVED8[0xc]; - __IO uint32_t CLEAN_INV_LINE_PA; /*!< Offset: 0x07f0 Clean and Invalidate Line by PA */ - uint32_t RESERVED9[1]; - __IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /*!< Offset: 0x07f8 Clean and Invalidate Line by Index/Way */ - __IO uint32_t CLEAN_INV_WAY; /*!< Offset: 0x07fc Clean and Invalidate by Way */ - uint32_t RESERVED10[0x40]; - __IO uint32_t DATA_LOCK_0_WAY; /*!< Offset: 0x0900 Data Lockdown 0 by Way */ - __IO uint32_t INST_LOCK_0_WAY; /*!< Offset: 0x0904 Instruction Lockdown 0 by Way */ - __IO uint32_t DATA_LOCK_1_WAY; /*!< Offset: 0x0908 Data Lockdown 1 by Way */ - __IO uint32_t INST_LOCK_1_WAY; /*!< Offset: 0x090c Instruction Lockdown 1 by Way */ - __IO uint32_t DATA_LOCK_2_WAY; /*!< Offset: 0x0910 Data Lockdown 2 by Way */ - __IO uint32_t INST_LOCK_2_WAY; /*!< Offset: 0x0914 Instruction Lockdown 2 by Way */ - __IO uint32_t DATA_LOCK_3_WAY; /*!< Offset: 0x0918 Data Lockdown 3 by Way */ - __IO uint32_t INST_LOCK_3_WAY; /*!< Offset: 0x091c Instruction Lockdown 3 by Way */ - __IO uint32_t DATA_LOCK_4_WAY; /*!< Offset: 0x0920 Data Lockdown 4 by Way */ - __IO uint32_t INST_LOCK_4_WAY; /*!< Offset: 0x0924 Instruction Lockdown 4 by Way */ - __IO uint32_t DATA_LOCK_5_WAY; /*!< Offset: 0x0928 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_5_WAY; /*!< Offset: 0x092c Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_6_WAY; /*!< Offset: 0x0930 Data Lockdown 5 by Way */ - __IO uint32_t INST_LOCK_6_WAY; /*!< Offset: 0x0934 Instruction Lockdown 5 by Way */ - __IO uint32_t DATA_LOCK_7_WAY; /*!< Offset: 0x0938 Data Lockdown 6 by Way */ - __IO uint32_t INST_LOCK_7_WAY; /*!< Offset: 0x093c Instruction Lockdown 6 by Way */ - uint32_t RESERVED11[0x4]; - __IO uint32_t LOCK_LINE_EN; /*!< Offset: 0x0950 Lockdown by Line Enable */ - __IO uint32_t UNLOCK_ALL_BY_WAY; /*!< Offset: 0x0954 Unlock All Lines by Way */ - uint32_t RESERVED12[0xaa]; - __IO uint32_t ADDRESS_FILTER_START; /*!< Offset: 0x0c00 Address Filtering Start */ - __IO uint32_t ADDRESS_FILTER_END; /*!< Offset: 0x0c04 Address Filtering End */ - uint32_t RESERVED13[0xce]; - __IO uint32_t DEBUG_CONTROL; /*!< Offset: 0x0f40 Debug Control Register */ - -} PL310_TypeDef; - -#define PL310 ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */ - -extern int PL310_GetID (void); -extern int PL310_GetType (void); -extern void PL310_InvAllByWay (void); -extern void PL310_CleanInvAllByWay(void); -extern void PL310_Enable(void); -extern void PL310_Disable(void); -extern void PL310_InvPa (void *); -extern void PL310_CleanPa (void *); -extern void PL310_CleanInvPa (void *); - -#endif - - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c deleted file mode 100644 index 8017e372a3..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c +++ /dev/null @@ -1,521 +0,0 @@ -/**************************************************************************//** - * @file system_VKRZA1H.c - * @brief CMSIS Device System Source File for - * ARM Cortex-A9 Device Series - * @version V1.00 - * @date 09 January 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#include -#include "VKRZA1H.h" -#include "RZ_A1_Init.h" - - -#if defined(__ARMCC_VERSION) -extern void $Super$$main(void); -__asm void FPUEnable(void); -#else -void FPUEnable(void); - -#endif - -#define FRQCR_IFC_MSK (0x0030) -#define FRQCR_IFC_SHFT (8) -#define FRQCR_IFC_1P1 (0) /* x1/1 */ -#define FRQCR_IFC_2P3 (1) /* x2/3 */ -#define FRQCR_IFC_1P3 (3) /* x1/3 */ - -uint32_t IRQNestLevel; -unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075 -uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the cache. - * - * @param none - * @return none - * - * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode. - */ -#if defined(__ARMCC_VERSION) -#pragma push -#pragma arm - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#pragma pop - -#elif defined(__GNUC__) - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#elif defined ( __ICCARM__ ) - -void InitMemorySubsystem(void) { - - /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before - * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. - * You are not required to invalidate the main TLB, even though it is recommended for safety - * reasons. This ensures compatibility with future revisions of the processor. */ - - unsigned int l2_id; - - /* Invalidate undefined data */ - __ca9u_inv_tlb_all(); - __v7_inv_icache_all(); - __v7_inv_dcache_all(); - __v7_inv_btac(); - - /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and - * invalidate in order to flush the valid data to the next level cache. - */ - __enable_mmu(); - - /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ - __enable_caches(); - __enable_btac(); - - /* If present, you may also need to Invalidate and Enable L2 cache here */ - l2_id = PL310_GetID(); - if (l2_id) - { - PL310_InvAllByWay(); - PL310_Enable(); - } -} -#else - -#endif - - -IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1]; - -uint32_t IRQCount = sizeof IRQTable / 4; - -uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) -{ - if (irq < IRQCount) { - IRQTable[irq] = handler; - return 0; - } - else { - return 1; - } -} - -uint32_t InterruptHandlerUnregister (IRQn_Type irq) -{ - if (irq < IRQCount) { - IRQTable[irq] = 0; - return 0; - } - else { - return 1; - } -} - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock. - */ -void SystemCoreClockUpdate (void) -{ - uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT; - - switch (frqcr_ifc) { - case FRQCR_IFC_1P1: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; - break; - case FRQCR_IFC_2P3: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3; - break; - case FRQCR_IFC_1P3: - SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3; - break; - default: - /* do nothing */ - break; - } -} - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) -{ - IRQNestLevel = 0; -/* do not use global variables because this function is called before - reaching pre-main. RW section maybe overwritten afterwards. */ - RZ_A1_InitClock(); - RZ_A1_InitBus(); - - //Configure GIC ICDICFR GIC_SetICDICFR() - GIC_Enable(); - __enable_irq(); - -} - - -//Fault Status Register (IFSR/DFSR) definitions -#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup -#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external -#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external -#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external -#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external -#define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external -#define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal -#define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal -#define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal -#define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal -#define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal -#define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal -#define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal -#define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal -#define FSR_DEBUG_EVENT 0x02 //internal -#define FSR_SYNC_EXT_ABORT 0x08 //sync/external -#define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external -#define FSR_LOCKDOWN 0x14 //internal -#define FSR_COPROCESSOR_ABORT 0x1a //internal -#define FSR_SYNC_PARITY_ERROR 0x19 //sync/external -#define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external -#define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external - -void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) { - uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status - - switch(FS) { - //Synchronous parity errors - retry - case FSR_SYNC_PARITY_ERROR: - case FSR_SYNC_PARITY_TTB_WALK_FIRST: - case FSR_SYNC_PARITY_TTB_WALK_SECOND: - return; - - //Your code here. Value in DFAR is invalid for some fault statuses. - case FSR_ALIGNMENT_FAULT: - case FSR_INSTRUCTION_CACHE_MAINTENANCE: - case FSR_SYNC_EXT_TTB_WALK_FIRST: - case FSR_SYNC_EXT_TTB_WALK_SECOND: - case FSR_TRANSLATION_FAULT_FIRST: - case FSR_TRANSLATION_FAULT_SECOND: - case FSR_ACCESS_FLAG_FAULT_FIRST: - case FSR_ACCESS_FLAG_FAULT_SECOND: - case FSR_DOMAIN_FAULT_FIRST: - case FSR_DOMAIN_FAULT_SECOND: - case FSR_PERMISION_FAULT_FIRST: - case FSR_PERMISION_FAULT_SECOND: - case FSR_DEBUG_EVENT: - case FSR_SYNC_EXT_ABORT: - case FSR_TLB_CONFLICT_ABORT: - case FSR_LOCKDOWN: - case FSR_COPROCESSOR_ABORT: - case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid - case FSR_ASYNC_PARITY_ERROR: //DFAR invalid - default: - while(1); - } -} - -void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) { - uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status - - switch(FS) { - //Synchronous parity errors - retry - case FSR_SYNC_PARITY_ERROR: - case FSR_SYNC_PARITY_TTB_WALK_FIRST: - case FSR_SYNC_PARITY_TTB_WALK_SECOND: - return; - - //Your code here. Value in IFAR is invalid for some fault statuses. - case FSR_SYNC_EXT_TTB_WALK_FIRST: - case FSR_SYNC_EXT_TTB_WALK_SECOND: - case FSR_TRANSLATION_FAULT_FIRST: - case FSR_TRANSLATION_FAULT_SECOND: - case FSR_ACCESS_FLAG_FAULT_FIRST: - case FSR_ACCESS_FLAG_FAULT_SECOND: - case FSR_DOMAIN_FAULT_FIRST: - case FSR_DOMAIN_FAULT_SECOND: - case FSR_PERMISION_FAULT_FIRST: - case FSR_PERMISION_FAULT_SECOND: - case FSR_DEBUG_EVENT: //IFAR invalid - case FSR_SYNC_EXT_ABORT: - case FSR_TLB_CONFLICT_ABORT: - case FSR_LOCKDOWN: - case FSR_COPROCESSOR_ABORT: - default: - while(1); - } -} - -//returns amount to decrement lr by -//this will be 0 when we have emulated the instruction and want to execute the next instruction -//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2) -//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4) -uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) { - const unsigned int THUMB = 2; - const unsigned int ARM = 4; - //Lazy VFP/NEON initialisation and switching - - // (ARM ARM section A7.5) VFP data processing instruction? - // (ARM ARM section A7.6) VFP/NEON register load/store instruction? - // (ARM ARM section A7.8) VFP/NEON register data transfer instruction? - // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction? - if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) || - (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) { - if (((opcode & 0x00000E00) >> 9) == 5) { - FPUEnable(); - return state; - } - } - - // (ARM ARM section A7.4) NEON data processing instruction? - if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) || - (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) || - // (ARM ARM section A7.7) NEON load/store instruction? - (state == ARM && ((opcode >> 24) == 0xF4)) || - (state == THUMB && ((opcode >> 24) == 0xF9))) { - FPUEnable(); - return state; - } - - //Add code here for other Undef cases - while(1); -} - -#if defined(__ARMCC_VERSION) -#pragma push -#pragma arm -//Critical section, called from undef handler, so systick is disabled -__asm void FPUEnable(void) { - ARM - - //Permit access to VFP/NEON, registers by modifying CPACR - MRC p15,0,R1,c1,c0,2 - ORR R1,R1,#0x00F00000 - MCR p15,0,R1,c1,c0,2 - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - ISB - - //Enable VFP/NEON - VMRS R1,FPEXC - ORR R1,R1,#0x40000000 - VMSR FPEXC,R1 - - //Initialise VFP/NEON registers to 0 - MOV R2,#0 - //Initialise D16 registers to 0 - VMOV D0, R2,R2 - VMOV D1, R2,R2 - VMOV D2, R2,R2 - VMOV D3, R2,R2 - VMOV D4, R2,R2 - VMOV D5, R2,R2 - VMOV D6, R2,R2 - VMOV D7, R2,R2 - VMOV D8, R2,R2 - VMOV D9, R2,R2 - VMOV D10,R2,R2 - VMOV D11,R2,R2 - VMOV D12,R2,R2 - VMOV D13,R2,R2 - VMOV D14,R2,R2 - VMOV D15,R2,R2 - //Initialise D32 registers to 0 - VMOV D16,R2,R2 - VMOV D17,R2,R2 - VMOV D18,R2,R2 - VMOV D19,R2,R2 - VMOV D20,R2,R2 - VMOV D21,R2,R2 - VMOV D22,R2,R2 - VMOV D23,R2,R2 - VMOV D24,R2,R2 - VMOV D25,R2,R2 - VMOV D26,R2,R2 - VMOV D27,R2,R2 - VMOV D28,R2,R2 - VMOV D29,R2,R2 - VMOV D30,R2,R2 - VMOV D31,R2,R2 - //Initialise FPSCR to a known state - VMRS R2,FPSCR - LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - AND R2,R2,R3 - VMSR FPSCR,R2 - - BX LR -} -#pragma pop - -#elif defined(__GNUC__) -void FPUEnable(void) { - __asm__ ( - ".ARM;" - - //Permit access to VFP/NEON, registers by modifying CPACR - "MRC p15,0,R1,c1,c0,2;" - "ORR R1,R1,#0x00F00000;" - "MCR p15,0,R1,c1,c0,2;" - - //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted - "ISB;" - - //Enable VFP/NEON - "VMRS R1,FPEXC;" - "ORR R1,R1,#0x40000000;" - "VMSR FPEXC,R1;" - - //Initialise VFP/NEON registers to 0 - "MOV R2,#0;" - //Initialise D16 registers to 0 - "VMOV D0, R2,R2;" - "VMOV D1, R2,R2;" - "VMOV D2, R2,R2;" - "VMOV D3, R2,R2;" - "VMOV D4, R2,R2;" - "VMOV D5, R2,R2;" - "VMOV D6, R2,R2;" - "VMOV D7, R2,R2;" - "VMOV D8, R2,R2;" - "VMOV D9, R2,R2;" - "VMOV D10,R2,R2;" - "VMOV D11,R2,R2;" - "VMOV D12,R2,R2;" - "VMOV D13,R2,R2;" - "VMOV D14,R2,R2;" - "VMOV D15,R2,R2;" - //Initialise D32 registers to 0 - "VMOV D16,R2,R2;" - "VMOV D17,R2,R2;" - "VMOV D18,R2,R2;" - "VMOV D19,R2,R2;" - "VMOV D20,R2,R2;" - "VMOV D21,R2,R2;" - "VMOV D22,R2,R2;" - "VMOV D23,R2,R2;" - "VMOV D24,R2,R2;" - "VMOV D25,R2,R2;" - "VMOV D26,R2,R2;" - "VMOV D27,R2,R2;" - "VMOV D28,R2,R2;" - "VMOV D29,R2,R2;" - "VMOV D30,R2,R2;" - "VMOV D31,R2,R2;" - - //Initialise FPSCR to a known state - "VMRS R2,FPSCR;" - "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. - "AND R2,R2,R3;" - "VMSR FPSCR,R2;" - - //"BX LR;" - : - : - :"r1", "r2", "r3"); - return; -} -#else -#endif - diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h deleted file mode 100644 index f04b37b8a4..0000000000 --- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************//** - * @file system_VKRZA1H.h - * @brief CMSIS Device System Header File for - * ARMCA9 Device Series - * @version V1.00 - * @date 11 June 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2011 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __SYSTEM_VKRZA1H -#define __SYSTEM_VKRZA1H - -#ifdef __cplusplus -extern "C" { -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -typedef void(*IRQHandler)(); -uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); -uint32_t InterruptHandlerUnregister(IRQn_Type); - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the Systd short int16_t;emCoreClock variable. - */ -extern void SystemInit (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_VKRZA1H */ diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c new file mode 100644 index 0000000000..dc7ac712b0 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * @file system_VK_RZ_A1H_H.c + * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "RZ_A1_Init.h" +#include "irq_ctrl.h" + +#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040) +#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040) +#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu) + +/* + Port 0 (P0) MD pin assignment + P0_0: MD_BOOT0 + P0_1: MD_BOOT1 + P0_2: MD_CLK + P0_3: MD_CLKS + */ + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) + { + uint32_t freq; + uint16_t mode; + uint16_t ifc; + + mode = (GPIO.PPR0 >> 2U) & 0x01U; + + if (mode == 0) { + /* Clock Mode 0 */ + /* CLKIN is between 10MHz and 13.33MHz */ + /* Divider 1 uses 1/1 ratio, PLL x30 is ON */ + freq = CM0_RENESAS_RZ_A1_CLKIN * 30U; + } else { + /* Clock Mode 1 */ + /* CLKIN is 48MHz */ + /* Divider 1 uses 1/4 ratio, PLL x32 is ON */ + freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U; +} + + /* Get CPG.FRQCR[IFC] bits */ + ifc = (CPG.FRQCR >> 8U) & 0x03U; + + /* Determine Divider 2 output clock */ + if (ifc == 0x03U) { + /* Division ratio is 1/3 */ + freq = (freq / 3U); + } + else { + if (ifc == 0x01U) { + /* Division ratio is 2/3 */ + freq = (freq * 2U) / 3U; + } +} + + SystemCoreClock = freq; +} + +/*---------------------------------------------------------------------------- + IRQ Handler Register/Unregister + *----------------------------------------------------------------------------*/ +uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler) +{ + return IRQ_SetHandler(irq, handler); +} + +uint32_t InterruptHandlerUnregister (IRQn_Type irq) +{ + return IRQ_SetHandler(irq, (IRQHandler_t)NULL); +} + +/*---------------------------------------------------------------------------- + System Initialization + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +/* do not use global variables because this function is called before + reaching pre-main. RW section maybe overwritten afterwards. */ + + // Enable SRAM write access + CPG.SYSCR3 = 0x0F; + + RZ_A1_InitClock(); + RZ_A1_InitBus(); + + // Invalidate entire Unified TLB + __set_TLBIALL(0); + + // Invalidate entire branch predictor array + __set_BPIALL(0); + __DSB(); + __ISB(); + + // Invalidate instruction cache and flush branch target cache + __set_ICIALLU(0); + __DSB(); + __ISB(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + + // Create Translation Table + MMU_CreateTranslationTable(); + + // Enable MMU + MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + L2C_InvAllByWay(); + // Enable L2C + L2C_Enable(); +#endif + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // IRQ Initialize + IRQ_Initialize(); +} diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h new file mode 100644 index 0000000000..ef8754d873 --- /dev/null +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * @file system_VK_RZ_A1H.h + * @brief CMSIS Device System Header File for ARM Cortex-A Device Series + * @version V1.00 + * @date 10 Mar 2017 + * + * @note + * + ******************************************************************************/ +/* + * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_VK_RZ_A1H_H +#define __SYSTEM_VK_RZ_A1H_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */ + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +/** + \brief Interrupt Handler Register. + + Registers an Interrupt Handler into the IRQ Table. + */ +extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler); + +/** + \brief Interrupt Handler Unregister. + + Unregisters an Interrupt Handler from the IRQ Table. + */ +extern uint32_t InterruptHandlerUnregister(IRQn_Type); + +/** + \brief Create Translation Table. + + Creates Memory Management Unit Translation Table. + */ +extern void MMU_CreateTranslationTable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_VK_RZ_A1H_H */ diff --git a/targets/TARGET_RENESAS/mbed_rtx.h b/targets/TARGET_RENESAS/mbed_rtx.h index 08f4a53bc5..f7c91c6a21 100644 --- a/targets/TARGET_RENESAS/mbed_rtx.h +++ b/targets/TARGET_RENESAS/mbed_rtx.h @@ -18,7 +18,7 @@ #include -#if defined(TARGET_RZ_A1H) || defined(TARGET_GR_LYCHEE) +#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE) #define OS_IDLE_THREAD_STACK_SIZE 512 #if defined(__CC_ARM) diff --git a/targets/targets.json b/targets/targets.json index 2e93c15b00..9a65e9a113 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2679,8 +2679,8 @@ }, "VK_RZ_A1H": { "inherits": ["RZ_A1XX"], - "extra_labels": ["RZA1H", "VKRZA1H"], - "release_versions": [] + "extra_labels_add": ["RZA1H", "VKRZA1H"], + "release_versions": ["2", "5"] }, "GR_LYCHEE": { "inherits": ["RZ_A1XX"],