Commit Graph

40 Commits (e2048b06b2c4aeddc36be4353855f523a43427d6)

Author SHA1 Message Date
Kevin Bracey fb6aa3ef4f Clean up ARM toolchain heap+stack setup in targets
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.

Looking into this, a number of other issues were highlighted

* Almost all targets had `__initial_sp` hardcoded in assembler,
  rather than getting it from the scatter file. This was behind
  issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
  file layout, in some cases meaning they were overlapping heap
  space. They now all use the area reserved in the scatter file.
  If any problems are seen, then there is an error in the
  scatter file.
* A number of targets were reserving unneeded space for heap and
  stack in their startup assembler, on top of the space reserved in
  the scatter file, so wasting a few K. A couple were using that
  space for the stack, rather than the space in the scatter file.

To clarify expected behaviour:

* Each scatter file contains empty regions `ARM_LIB_HEAP` and
  `ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
  by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
  `ARM_LIB_HEAP` is generally the space left over after static
  RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
  vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
  for the ARM library. The ARM library calls this during startup, and
  it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
  modify SP, so we remain on the boot stack, and the heap is set to
  the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
  exist, then the heap is the space from the end of the used data in
  `RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
  Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
  Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
  itself.
2019-10-23 14:53:49 +03:00
jeromecoutant 96a773a0e6 STM32L4: update drivers version to CUBE V1.14.0 2019-07-19 13:15:07 +02:00
jeromecoutant d919498745 STM32: common cmsis.h and device.h 2019-05-27 16:27:41 +02:00
Martin Kojtal 1de0712272
Merge pull request #9944 from deepikabhavnani/stm32_splitheap
GCC - Add support to split heap across 2-RAM banks
2019-04-30 11:02:51 +01:00
Martin Kojtal 2cd7aa1148
Merge pull request #10303 from juhoeskeli/mem_changes
STM32L4xx: IAR memory maps updated
2019-04-29 13:46:46 +01:00
Anna Bridge 536da479dc
Merge pull request #10018 from deepikabhavnani/stm32_heap_armc6
STM: Update linker script for using SRAM1 and SRAM2 in ARM
2019-04-26 13:30:42 +01:00
Juho Eskeli 443974b864 STM32L4xx: IAR linker file updated to better use available memory 2019-04-23 12:53:53 +03:00
Deepika feba293673 Update linker script for using SRAM1 and SRAM2 in ARM
To have the flexibilty in application; to use any of the section
    (data/bss/heap) without updating linker script in every use case,
    following decisions are made:
    1. Fixed size and small sections moved to SRAM2 (32K)
        Vectors
        Crash data
        Remaining section - RW / ZI
    2. Large memory space should be used for variable sections
       RW/ZI
       Heap - (Minimum - 0x12000)
       Stack - At bottom
2019-04-09 13:41:09 -05:00
Deepika 1a52587c2d Update the linker file to support single and multiple heap banks 2019-04-09 12:08:49 -05:00
Deepika 719d0fb94e Update linker script for split heap support
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:

1. Fixed size and small sections moved to SRAM2 (32K)
    Vectors
    Crash data
    Stack
    Remaining section - Heap memory
2. Large memory space should be used for variable sections
   Data
   BSS
   Heap - Remaining section

Heap is moved to the end of both sections as GCC allocates till 4K boundary,
if end of heap is not aligned to 4K, that chunk of memory will go unutilized
2019-04-09 12:08:49 -05:00
Marcus Chang 7c0714132c Expand sbrk to allocate memory from two regions 2019-04-09 12:08:49 -05:00
Deepika 36c7b2de86 uARM - Move heap region after IRAM1
ARM_LIB_HEAP start is aligned to IRAM1 end, hence should be placed next to
RW_IRAM1 i.e. no other region in between.
2019-04-09 12:01:01 -05:00
Deepika 122549910e Add Crash report section to all uARM files 2019-02-28 19:54:38 -06:00
deepikabhavnani 0dc5561991 Guard RAM start and size defines 2019-02-28 19:54:38 -06:00
deepikabhavnani b598dc1f46 Target_STM: Add ARM_LIB_STACK and ARM_LIB_HEAP section
Instead of user defined symbols in assembly files or C files,
use linker scripts to add heap and stack - this is inconsistent
with ARM std linker scripts
2019-02-28 19:54:28 -06:00
Lin Gao 837e86df28 Updated linker script for IAR and ARM to increase heap size by moving BSS to the 32K ram 2019-02-01 16:03:20 -06:00
Lin Gao aa2d49ae0c Move BSS to SRAM2 to increase heap size on ST475 IOT board 2019-02-01 15:32:43 -06:00
Przemyslaw Stekiel 58f6bf7292 [STM] Support boot stack size configuration option 2019-01-08 15:32:06 +01:00
Senthil Ramakrishnan ef8c1c3cb6 Linker script modifications for crash data region 2018-11-16 13:59:59 -06:00
Deepika bf1a2c8485 [ST]: Fix alignment of execute region to 8-byte boundary in ARM linker files
--legacyalign, --no_legacyalign are deprecated from ARMC6 compiler, in order to
remove deprecated flags all linker files should strictly align to 8-byte boundary
2018-10-09 14:47:14 -05:00
bcostm 7097e07b62 stm32 ticker: typo corrections 2018-07-11 14:43:36 +02:00
bcostm d8e839a789 stm32 ticker: change license 2018-07-11 14:43:16 +02:00
bcostm 32031cbab3 stm32 ticker: rename hal_tick.h in us_ticker_data.h 2018-07-11 14:42:44 +02:00
bcostm fbd7a97e19 stm32 ticker: rename macro and update ST HAL Tick functions
- rename TIM_MST_16BIT in TIM_MST_BIT_WIDTH in order to use it directly in ticker info structure
- change HAL_InitTick() and HAL_GetTick()
2018-07-11 14:39:42 +02:00
bcostm b087390a1a Remove HAL_TICK_DELAY (no more used) 2018-06-05 16:53:40 +02:00
adustm 02b2b01a83 Change STM32L475/76/86 GCC_ARM linker files to have HEAP in SRAM1 and stack in SRAM2 (after the interrupt vector) 2018-02-22 17:36:27 +01:00
jeromecoutant 7979f4d255 SMT32L4 : add missing ST HAL LPUART functions
To enable/disable UART Clock in Stop Mode
2018-01-26 16:24:54 +01:00
Cruz Monrreal f1cf77fa44
Merge pull request #5844 from adustm/DiscoIot_L475_iarlink
ST-DISCO_L475VG_IOT01A: Improve SRAM use for IAR toolchain
2018-01-23 16:23:08 -06:00
adustm 5104f2d1cc Improve SRAM use for IAR toolchain
Use the entire SRAM2 with NVIC buffer + stack
  Increase HEAP size to 0x10000 in SRAM1
  Increase the available SRAM1 by 0x2000
2018-01-12 15:49:27 +01:00
bcostm 84577f9634 L4 ST CUBE V1.11.0
Update to STM32CubeL4 V1.11.0

Conflicts solved:
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/device/stm32l433xx.h
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/stm32l4xx.h
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l496xx.h
	targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/device/stm32l4xx.h
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_conf.h
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_i2c.c
	targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_spi.h
2018-01-12 11:11:31 +01:00
bcostm 9f86a32baf Add freeze timer on debug for all STM32 devices
This is a continuation of the work done on the STM32F401xE devices only.
2017-09-18 13:31:46 +02:00
Jimmy Brisson 15a9a0382b Enable Compiling with ARMC6 across all targets
remove duplicate sys.cpp
2017-09-11 13:20:32 -05:00
jeromecoutant b654af2d80 STM32L4 : json clock source configuration
- default value is the same as before patch
- system_stm32l4xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- nvic_addr.h file is now in TARGET_STM level
2017-07-19 16:39:26 +02:00
bcostm 03930b88f6 DISCO_L475VG_IOT01A: Add missing nvic_addr.h file 2017-06-26 20:14:08 +02:00
bcostm bd6d7382a3 DISCO_L475VG_IOT01A: Update toolchain files for cmsis5 2017-06-26 19:02:52 +02:00
bcostm 8ede14dac1 DISCO_L475VG_IOT01A: Add include of LL timer file 2017-06-12 17:12:57 +02:00
bcostm 66cbc8b452 DISCO_L475VG_IOT01A: Update device files after CubeL4 update 2017-06-12 17:03:12 +02:00
bcostm af2078f38d DISCO_L475VG_IOT01A: Update cmsis_nvic files 2017-06-12 17:03:12 +02:00
bcostm 2ed207efd4 DISCO_L475VG_IOT01A: change comment for 8-byte aligned adress for IAR .icf file 2017-06-12 17:03:12 +02:00
bcostm a8ab839e2c DISCO_L475VG_IOT: Re-organize folder
- Move TARGET_DISCO_L475VG_IOT01A/ in TARGET_STM32L475xG/
- Add STM32L475xG extra label in targets.json
2017-06-12 17:03:12 +02:00