mirror of https://github.com/ARMmbed/mbed-os.git
STM32L4 : json clock source configuration
- default value is the same as before patch - system_stm32l4xx.c file is copied to family level with all other ST cube files - specific clock configuration is now in a new file: system_clock.c (target level) - nvic_addr.h file is now in TARGET_STM levelpull/4740/head
jeromecoutant
parent
912c0de938
commit
b654af2d80
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@ -0,0 +1,374 @@
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/**
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******************************************************************************
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* @file system_stm32l4xx.c
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* @author MCD Application Team
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* @version V1.3.1
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* @date 21-April-2017
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32l4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the MSI (4 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
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* | (external 8 MHz clock) | (internal 16 MHz)
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* | 2- PLL_HSE_XTAL | or PLL_MSI
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* | (external 8 MHz xtal) | (internal 4 MHz)
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 48 | 80
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*-----------------------------------------------------------------------------
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* AHBCLK (MHz) | 48 | 80
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*-----------------------------------------------------------------------------
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* APB1CLK (MHz) | 48 | 80
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*-----------------------------------------------------------------------------
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* APB2CLK (MHz) | 48 | 80
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*-----------------------------------------------------------------------------
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* USB capable (48 MHz precise clock) | YES | NO
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*-----------------------------------------------------------------------------
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**/
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#include "stm32l4xx.h"
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#include "nvic_addr.h"
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#include "mbed_assert.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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// clock source is selected with CLOCK_SOURCE in json config
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#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
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#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
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#define USE_PLL_HSI 0x2 // Use HSI internal clock
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#define USE_PLL_MSI 0x1 // Use MSI internal clock
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#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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uint8_t SetSysClock_PLL_HSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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#if ((CLOCK_SOURCE) & USE_PLL_MSI)
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uint8_t SetSysClock_PLL_MSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR |= RCC_CR_MSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON , HSION, and PLLON bits */
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RCC->CR &= (uint32_t)0xEAF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x00001000;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
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/* 1- Try to start with HSE and external clock */
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if (SetSysClock_PLL_HSE(1) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI()==0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_MSI)
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/* 4- If fail start with MSI clock */
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if (SetSysClock_PLL_MSI() == 0)
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#endif
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{
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while(1) {
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MBED_ASSERT(1);
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}
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}
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}
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}
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}
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 1
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
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#endif
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}
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
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// Used to gain time after DeepSleep in case HSI is used
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if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
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return 0;
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}
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// Select MSI as system clock source to allow modification of the PLL configuration
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
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// Enable HSE oscillator and activate PLL with HSE as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
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if (bypass == 0) {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
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}
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
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RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
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RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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return 0; // FAIL
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}
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
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RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
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return 0; // FAIL
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}
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// Disable MSI Oscillator
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 2
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if (bypass == 0)
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
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else
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
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#endif
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
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// Select MSI as system clock source to allow modification of the PLL configuration
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
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// Enable HSI oscillator and activate PLL with HSI as source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
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RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
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RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
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RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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return 0; // FAIL
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}
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RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
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RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
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RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
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return 0; // FAIL
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}
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// Disable MSI Oscillator
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
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RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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// Output clock on MCO1 pin(PA8) for debugging purpose
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#if DEBUG_MCO == 3
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
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#endif
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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#if ((CLOCK_SOURCE) & USE_PLL_MSI)
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/******************************************************************************/
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/* PLL (clocked by MSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_MSI(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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// Enable LSE Oscillator to automatically calibrate the MSI clock
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
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RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
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RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
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}
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HAL_RCCEx_DisableLSECSS();
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/* Enable MSI Oscillator and activate PLL with MSI as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.MSIState = RCC_MSI_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
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RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
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RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
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RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
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RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
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RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
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RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/* Enable MSI Auto-calibration through LSE */
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HAL_RCCEx_EnableMSIPLLMode();
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/* Select MSI output as USB clock source */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
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return 0; // FAIL
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}
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// Output clock on MCO1 pin(PA8) for debugging purpose
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||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
|
@ -0,0 +1,361 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
#include "mbed_assert.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI()==0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1) {
|
||||
MBED_ASSERT(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
|
@ -1,587 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32l4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32l4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
|
||||
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | YES | NO | YES
|
||||
*---------------------------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
|
||||
#define USE_PLL_HSE_EXTC (0) // Use external clock
|
||||
#define USE_PLL_HSE_XTAL (0) // Use external xtal
|
||||
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
|
||||
4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
|
||||
{ /* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
|
||||
}
|
||||
else
|
||||
{ /* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
|
||||
}
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = (msirange / pllm);
|
||||
break;
|
||||
}
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI or MSI clock */
|
||||
#if (USE_PLL_HSI != 0)
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#else
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0)
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
|
||||
// Non-USB configuration : sysclock = 80MHz
|
||||
//RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
//RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
//RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
//RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
// USB configuration : sysclock = 48 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2017-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef NVIC_ADDR_H
|
||||
#define NVIC_ADDR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma section=".intvec"
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
|
||||
#elif defined(__CC_ARM)
|
||||
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t g_pfnVectors[];
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
|
||||
#else
|
||||
#error "Flash vector address not set for this toolchain"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,361 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
#include "mbed_assert.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI()==0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1) {
|
||||
MBED_ASSERT(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
|
@ -1,587 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32l4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32l4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
|
||||
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | YES | NO | YES
|
||||
*---------------------------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
|
||||
#define USE_PLL_HSE_EXTC (0) // Use external clock
|
||||
#define USE_PLL_HSE_XTAL (0) // Use external xtal
|
||||
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
|
||||
4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
|
||||
{ /* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
|
||||
}
|
||||
else
|
||||
{ /* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
|
||||
}
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = (msirange / pllm);
|
||||
break;
|
||||
}
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI or MSI clock */
|
||||
#if (USE_PLL_HSI != 0)
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#else
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0)
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
|
||||
// Non-USB configuration : sysclock = 80MHz
|
||||
//RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
//RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
//RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
//RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
// USB configuration : sysclock = 48 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,361 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
#include "mbed_assert.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI()==0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1) {
|
||||
MBED_ASSERT(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
|
@ -1,587 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32l4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32l4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
|
||||
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | YES | NO | YES
|
||||
*---------------------------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
|
||||
#define USE_PLL_HSE_EXTC (0) // Use external clock
|
||||
#define USE_PLL_HSE_XTAL (0) // Use external xtal
|
||||
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
|
||||
4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS;; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
|
||||
{ /* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
|
||||
}
|
||||
else
|
||||
{ /* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
|
||||
}
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = (msirange / pllm);
|
||||
break;
|
||||
}
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI or MSI clock */
|
||||
#if (USE_PLL_HSI != 0)
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#else
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0)
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
|
||||
// Non-USB configuration : sysclock = 80MHz
|
||||
//RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
//RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
//RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
//RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
// USB configuration : sysclock = 48 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2017-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef NVIC_ADDR_H
|
||||
#define NVIC_ADDR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma section=".intvec"
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
|
||||
#elif defined(__CC_ARM)
|
||||
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t g_pfnVectors[];
|
||||
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
|
||||
#else
|
||||
#error "Flash vector address not set for this toolchain"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,361 @@
|
|||
/* mbed Microcontroller Library
|
||||
* Copyright (c) 2006-2017 ARM Limited
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* This file configures the system clock as follows:
|
||||
*-----------------------------------------------------------------------------
|
||||
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
|
||||
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
|
||||
* | 3- USE_PLL_HSI (internal 16 MHz)
|
||||
* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 80
|
||||
* AHBCLK (MHz) | 80
|
||||
* APB1CLK (MHz) | 80
|
||||
* APB2CLK (MHz) | 80
|
||||
* USB capable | YES
|
||||
*-----------------------------------------------------------------------------
|
||||
**/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
#include "nvic_addr.h"
|
||||
#include "mbed_assert.h"
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
|
||||
|
||||
// clock source is selected with CLOCK_SOURCE in json config
|
||||
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
|
||||
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
|
||||
#define USE_PLL_HSI 0x2 // Use HSI internal clock
|
||||
#define USE_PLL_MSI 0x1 // Use MSI internal clock
|
||||
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SetSysClock(void)
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/* 3- If fail start with HSI clock */
|
||||
if (SetSysClock_PLL_HSI()==0)
|
||||
#endif
|
||||
{
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/* 4- If fail start with MSI clock */
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1) {
|
||||
MBED_ASSERT(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0) {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
} else {
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
|
||||
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
|
||||
|
||||
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
|
||||
|
|
@ -1,586 +0,0 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32l4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.1
|
||||
* @date 21-April-2017
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
|
||||
*
|
||||
* This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32l4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* After each device reset the MSI (4 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
|
||||
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 48 | 80 | 80
|
||||
*---------------------------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | YES | NO | YES
|
||||
*---------------------------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32l4xx.h"
|
||||
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (MSI_VALUE)
|
||||
#define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* MSI_VALUE */
|
||||
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
|
||||
#define USE_PLL_HSE_EXTC (0) // Use external clock
|
||||
#define USE_PLL_HSE_XTAL (0) // Use external xtal
|
||||
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
uint32_t SystemCoreClock = 4000000;
|
||||
|
||||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
|
||||
const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
|
||||
4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set MSION bit */
|
||||
RCC->CR |= RCC_CR_MSION;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON , HSION, and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEAF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x00001000;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIER = 0x00000000;
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
|
||||
* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 4 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get MSI Range frequency--------------------------------------------------*/
|
||||
if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
|
||||
{ /* MSISRANGE from RCC_CSR applies */
|
||||
msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
|
||||
}
|
||||
else
|
||||
{ /* MSIRANGE from RCC_CR applies */
|
||||
msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
|
||||
}
|
||||
/*MSI frequency range in HZ*/
|
||||
msirange = MSIRangeTable[msirange];
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
switch (RCC->CFGR & RCC_CFGR_SWS)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock source */
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
|
||||
case 0x04: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x0C: /* PLL used as system clock source */
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
|
||||
SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
|
||||
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
|
||||
|
||||
switch (pllsource)
|
||||
{
|
||||
case 0x02: /* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm);
|
||||
break;
|
||||
|
||||
case 0x03: /* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm);
|
||||
break;
|
||||
|
||||
default: /* MSI used as PLL clock source */
|
||||
pllvco = (msirange / pllm);
|
||||
break;
|
||||
}
|
||||
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
|
||||
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
|
||||
SystemCoreClock = pllvco/pllr;
|
||||
break;
|
||||
|
||||
default:
|
||||
SystemCoreClock = msirange;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI or MSI clock */
|
||||
#if (USE_PLL_HSI != 0)
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#else
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0)
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
|
||||
// Non-USB configuration : sysclock = 80MHz
|
||||
//RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
//RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
//RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
//RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
// USB configuration : sysclock = 48 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
HAL_RCCEx_DisableLSECSS();
|
||||
/* Enable MSI Oscillator and activate PLL with MSI as source */
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
||||
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
/* Enable MSI Auto-calibration through LSE */
|
||||
HAL_RCCEx_EnableMSIPLLMode();
|
||||
/* Select MSI output as USB clock source */
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
|
||||
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
|
||||
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -26,20 +26,43 @@
|
|||
*
|
||||
* This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
|
||||
* | (external 8 MHz clock) | (internal 16 MHz)
|
||||
* | 2- PLL_HSE_XTAL | or PLL_MSI
|
||||
* | (external 8 MHz xtal) | (internal 4 MHz)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(MHz) | 48 | 80
|
||||
* System Clock source | MSI
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHBCLK (MHz) | 48 | 80
|
||||
* SYSCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1CLK (MHz) | 48 | 80
|
||||
* HCLK(Hz) | 4000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2CLK (MHz) | 48 | 80
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* USB capable (48 MHz precise clock) | YES | NO
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 8
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_R | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI1_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI2_P | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI2_Q | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLSAI2_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
|
|
@ -129,11 +152,6 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
|
||||
#define USE_PLL_HSE_EXTC (0) // Use external clock
|
||||
#define USE_PLL_HSE_XTAL (0) // Use external xtal
|
||||
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
|
||||
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -163,16 +181,6 @@
|
|||
* @{
|
||||
*/
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
uint8_t SetSysClock_PLL_HSI(void);
|
||||
#endif
|
||||
|
||||
uint8_t SetSysClock_PLL_MSI(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -181,6 +189,10 @@ uint8_t SetSysClock_PLL_MSI(void);
|
|||
* @{
|
||||
*/
|
||||
|
||||
/*+ MBED */
|
||||
#if 0
|
||||
/*- MBED */
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* @param None
|
||||
|
|
@ -218,9 +230,12 @@ void SystemInit(void)
|
|||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*+ MBED */
|
||||
#endif
|
||||
/*- MBED */
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
|
|
@ -331,239 +346,6 @@ void SystemCoreClockUpdate(void)
|
|||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SetSysClock(void)
|
||||
{
|
||||
/* 1- Try to start with HSE and external clock */
|
||||
#if USE_PLL_HSE_EXTC != 0
|
||||
if (SetSysClock_PLL_HSE(1) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 2- If fail try to start with HSE and external xtal */
|
||||
#if USE_PLL_HSE_XTAL != 0
|
||||
if (SetSysClock_PLL_HSE(0) == 0)
|
||||
#endif
|
||||
{
|
||||
/* 3- If fail start with HSI or MSI clock */
|
||||
#if (USE_PLL_HSI != 0)
|
||||
if (SetSysClock_PLL_HSI() == 0)
|
||||
#else
|
||||
if (SetSysClock_PLL_MSI() == 0)
|
||||
#endif
|
||||
{
|
||||
while(1)
|
||||
{
|
||||
// [TODO] Put something here to tell the user that a problem occured...
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 1
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Used to gain time after DeepSleep in case HSI is used
|
||||
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSE oscillator and activate PLL with HSE as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
|
||||
if (bypass == 0)
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
|
||||
}
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
|
||||
// Non-USB configuration : sysclock = 80MHz
|
||||
//RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
//RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
//RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
//RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
//RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
|
||||
// USB configuration : sysclock = 48 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 24; // VCO output clock = 192 MHz (8 MHz * 24)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 27.4 MHz (192 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 48 MHz (192 MHz / 4) --> OK for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 4; // PLL clock = 48 MHz (192 MHz / 4)
|
||||
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz or 48 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 2
|
||||
if (bypass == 0)
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
|
||||
else
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (USE_PLL_HSI != 0)
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_HSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Select MSI as system clock source to allow modification of the PLL configuration
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
|
||||
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
|
||||
|
||||
// Enable HSI oscillator and activate PLL with HSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||||
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2)
|
||||
RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Disable MSI Oscillator
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
HAL_RCC_OscConfig(&RCC_OscInitStruct);
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 3
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by MSI) used as System clock source */
|
||||
/******************************************************************************/
|
||||
uint8_t SetSysClock_PLL_MSI(void)
|
||||
{
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
|
||||
// Enable LSE Oscillator to automatically calibrate the MSI clock
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
|
||||
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
|
||||
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
|
||||
}
|
||||
|
||||
// Enable MSI oscillator and activate PLL with MSI as source
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
||||
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
|
||||
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
|
||||
RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
|
||||
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
|
||||
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
|
||||
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
|
||||
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
||||
{
|
||||
return 0; // FAIL
|
||||
}
|
||||
|
||||
// Output clock on MCO1 pin(PA8) for debugging purpose
|
||||
#if DEBUG_MCO == 4
|
||||
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
|
||||
#endif
|
||||
|
||||
return 1; // OK
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
|
|
@ -1304,6 +1304,13 @@
|
|||
"supported_form_factors": ["ARDUINO"],
|
||||
"core": "Cortex-M4F",
|
||||
"extra_labels_add": ["STM32L4", "STM32L432xC", "STM32L432KC"],
|
||||
"config": {
|
||||
"clock_source": {
|
||||
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
|
||||
"value": "USE_PLL_MSI",
|
||||
"macro_name": "CLOCK_SOURCE"
|
||||
}
|
||||
},
|
||||
"detect_code": ["0770"],
|
||||
"device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_FC", "CAN", "TRNG", "FLASH"],
|
||||
"release_versions": ["2", "5"],
|
||||
|
|
@ -1316,7 +1323,7 @@
|
|||
"extra_labels_add": ["STM32L4", "STM32L476RG", "STM32L476xG"],
|
||||
"config": {
|
||||
"clock_source": {
|
||||
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI (L4)",
|
||||
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
|
||||
"value": "USE_PLL_MSI",
|
||||
"macro_name": "CLOCK_SOURCE"
|
||||
}
|
||||
|
|
@ -1333,6 +1340,13 @@
|
|||
"supported_form_factors": ["ARDUINO", "MORPHO"],
|
||||
"core": "Cortex-M4F",
|
||||
"extra_labels_add": ["STM32L4", "STM32L486RG", "STM32L486xG"],
|
||||
"config": {
|
||||
"clock_source": {
|
||||
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
|
||||
"value": "USE_PLL_MSI",
|
||||
"macro_name": "CLOCK_SOURCE"
|
||||
}
|
||||
},
|
||||
"detect_code": ["0827"],
|
||||
"macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
|
||||
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
|
||||
|
|
@ -1523,6 +1537,13 @@
|
|||
"inherits": ["FAMILY_STM32"],
|
||||
"core": "Cortex-M4F",
|
||||
"extra_labels_add": ["STM32L4", "STM32L475xG", "STM32L475VG"],
|
||||
"config": {
|
||||
"clock_source": {
|
||||
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
|
||||
"value": "USE_PLL_MSI",
|
||||
"macro_name": "CLOCK_SOURCE"
|
||||
}
|
||||
},
|
||||
"supported_form_factors": ["ARDUINO"],
|
||||
"detect_code": ["0764"],
|
||||
"macros_add": ["USBHOST_OTHER"],
|
||||
|
|
@ -1534,6 +1555,13 @@
|
|||
"inherits": ["FAMILY_STM32"],
|
||||
"core": "Cortex-M4F",
|
||||
"extra_labels_add": ["STM32L4", "STM32L476xG", "STM32L476VG"],
|
||||
"config": {
|
||||
"clock_source": {
|
||||
"help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
|
||||
"value": "USE_PLL_MSI",
|
||||
"macro_name": "CLOCK_SOURCE"
|
||||
}
|
||||
},
|
||||
"detect_code": ["0820"],
|
||||
"macros_add": ["USBHOST_OTHER"],
|
||||
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
|
||||
|
|
|
|||
Loading…
Reference in New Issue