Commit Graph

4829 Commits (d810b85094fecb582005c4dad43dfb05655b2cb5)

Author SHA1 Message Date
Shrikant Tudavekar 4b182b92f1 enable crash capture for NUMAKER_PFM_NUC472 2019-04-08 15:36:28 -05:00
Shrikant Tudavekar 197b85e2fe create a region instead of a block for crash data 2019-04-08 15:22:59 -05:00
Martin Kojtal c2ebb79723
Merge pull request #9814 from LMESTM/dev_NUCLEO_WB55RG
Adding NUCLEO_WB55RG support
2019-04-04 15:30:07 +02:00
Ganesh Ramachandran 0b84c30d7c Fixed support for DigitalOut(NC) instantiation 2019-04-04 15:16:29 +05:30
Martin Kojtal 6081727cbf
Merge pull request #10115 from enebular/raven
Uhuru RAVEN: Adding platform HAL
2019-04-04 11:05:23 +02:00
Martin Kojtal 25371d47c5
Merge pull request #10288 from bridadan/allow_armc5_for_renesas_targets
Revert limiting Renesas targets to ARMC6
2019-04-04 10:30:46 +02:00
Martin Kojtal 0066ba9b0d
Merge pull request #10267 from cy-vivekp/pr/psoc_32_bit_lp_ticker
PSOC6: Modify lp_ticker to 32 bit
2019-04-03 11:13:25 +02:00
Martin Kojtal 1d26dbb068
Merge pull request #10291 from lrusinowicz/sequana_psa_deepsleep
FUTURE_SEQUANA: Fixed LP ticker for M0 core
2019-04-03 08:59:20 +02:00
Cruz Monrreal d8dc981fd1
Merge pull request #10289 from cydriftcloud/pr/wiced-lib-rebuild-03
PSOC6: Rebuild WICED libraries
2019-04-02 09:14:28 -05:00
Leszek Rusinowicz f0e0e9f5cd FUTURE_SEQUANA: Fixed LP ticker for M0 core
Fixed interrupt vector settings on M0 core. Wrong vector settings prevented
LP_TICKER from working, resulting in deep sleep tests failing on M0
or PSA variant.
2019-04-02 13:33:33 +02:00
Martin Kojtal 2a694cf1d9
Merge pull request #10143 from jeromecoutant/PR_ADC_RESETINTERNAL
STM32 ADC INTERNAL CHANNEL reset after read
2019-04-02 13:02:14 +02:00
Cruz Monrreal 4950178db5
Merge pull request #10246 from NXPmicro/Fix_LPC55S69_Flash_ClockSpeed
LPC55S69: Update Flash driver to set clock frequency
2019-04-01 21:53:18 -05:00
Lei Zhang d6f70065bb PSOC6: Rebuild WICED libraries
- Modify WICED to RTOS priority mapping
2019-04-01 15:46:50 -07:00
Cruz Monrreal cdc2579b7b
Merge pull request #10248 from VVESTM/issue_9934
TARGET_STM32F7: Refresh cache when erasing or programming flash
2019-04-01 17:04:26 -05:00
Cruz Monrreal 4dd55d2db6
Merge pull request #10281 from ashok-rao/S2_LP
Adding support for S2_LP (WiSUN) as a new MTB target
2019-04-01 17:03:37 -05:00
Brian Daniels 57cfa0bfa2 Revert "Only enable ARMC6 for a few targets"
These targets appear to run fine with ARMC5.

This reverts commit 2b75dfda0f.
2019-04-01 15:20:29 -05:00
Mahesh Mahadevan 1b9531d1af LPC55S69: Update Flash driver to set clock frequency
This is to ensure the flash access time is set correctly

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2019-04-01 12:10:24 -05:00
Ashok Rao 1f572f987e SPDX license identifier changed to Apache-2.0 2019-04-01 15:17:06 +01:00
Ashok Rao 5cb1c64d59 Adding SPDX identifier 2019-04-01 11:21:45 +01:00
Ashok Rao 479bcfdbfe Incorporating review comments
Removing USBDEVICE since USB pins are NOT brought out on the MTB/MCB.
2019-04-01 11:16:16 +01:00
Ashok Rao d2af702ed9 Incorporating review comments 2019-04-01 10:06:30 +01:00
Ashok Rao 83ad921196 Resolving merge conflicts from my remote 2019-04-01 07:49:37 +01:00
Ashok Rao d4c83fc056 Adding STM32_F429 + S2_LP (WiSUN) as a new MTB target 2019-04-01 07:31:01 +01:00
Laurent Meunier b0f4815261 STM32WB: ADC INTERNAL CHANNEL reset after read
Internal channels use is enabling ADC "internal path" which needs
to be disabled after measurement.

Same applied here for WB family as was done for others in #10143.
2019-03-29 16:21:46 +01:00
Laurent Meunier c6277988c6 STM32WB: Only configure default peripherals in SetSysClock
Typically the RTC clock is configured by RTC driver itself.

RNG on the other hand is shared with M0+ core and it is expected that
M4 turns it on at boot time.
2019-03-29 16:21:46 +01:00
Laurent Meunier a744343931 STM32WB: disable debug lines when not needed
When doing so, do not disbale GPIO clocks as they may be used by other
drivers !

As a result, debug will be disabled by default, but can be enabled by
either modifying code or selecting MBED debug profile.
2019-03-29 16:21:46 +01:00
Laurent Meunier 718b16545c STM32WB: update deep sleep sequence
Review HSE clock initialization to match with latest CUBE firmware.
Also there is no need to set the full clock tree again after deep sleep exit.

With this change we get a stable deep sleep mode (when allowed by CORDIO stack).
2019-03-29 16:21:45 +01:00
Laurent Meunier b21110d6b8 STM32WB: Add FLASH HW Semaphore
Because FLASH is a shared resource between the 2 STM32WB cores, SW needs
to acquire HW Semaphore before using the resource.
2019-03-29 16:21:45 +01:00
Laurent Meunier 14ee4a1c7b STM32WB: Add TRNG HW Semaphore
Because TRNG is a shared resource between the 2 STM32WB cores, SW needs
to acquire HW Semaphore before using the resource.
2019-03-29 16:21:45 +01:00
Laurent Meunier 71c396cab1 STM32WB: update GCC linker script to match with master 2019-03-29 16:21:45 +01:00
Laurent Meunier 6caa4d487f STM32WB: Add SPDX identifier to new files
also update the copyright year when needed
2019-03-29 16:21:44 +01:00
Laurent Meunier c53021b77f STM32WB: Update headers 2019-03-29 16:21:43 +01:00
Laurent Meunier 536c37f58b STM32WB55RG: temporarily remove device_name property in targets.json
Until the CMSIS pack device name is officially deployed.

then we'll the name as can be found in Keil CMSIS pack

       <!-- *************************  Device 'STM32WB55RG'  ***************************** -->
        <device Dname="STM32WB55RGVx">
          <memory id="IROM1"                           start="0x08000000" size="0x001000000" startup="1" default="1" />
          <memory id="IRAM1"                           start="0x20000000" size="0x000040000" init="0"    default="1" />
          <algorithm name="CMSIS/Flash/STM32WB_M4.FLM" start="0x08000000" size="0x001000000"             default="1" />

          <feature type="QFP" n="68"/>
        </device>
2019-03-29 16:21:42 +01:00
Laurent Meunier 002f40dd3a STM32WB: ARM linker script update
There is no need to add FIRST attribute to MAPPING_TABLE as the default
ordering is alphabetical order.

With this change, we don't have any warning with MBED2 and the sections
are properly ordered anyway in BLE cases.
2019-03-29 16:21:42 +01:00
Laurent Meunier f2580c1c4a STM32WB: Fix ARM link error in mbed2
In case of mbed2, BLE feature is not built.

As there is a MAPPING_TABLE in BLE feature which is not compiled in case
of mbed2, the linker reported the below error

[ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/
.link_script.sct", line 65 (column 6): Error: L6236E:
No section matches selector - no section to be FIRST/LAST.

Solution is to check whether BLE is enabled.
2019-03-29 16:21:41 +01:00
Laurent Meunier f9b4f11507 STM32WB: Adapt I2C timings
for now based on L4+ cubeMX inputs
2019-03-29 16:21:41 +01:00
Laurent Meunier bb2aea41f8 fixup! NUCLEO_WB55RG: add SDK files 2019-03-29 16:21:41 +01:00
Laurent Meunier e2cdb19e7f STM32WB: Add missing analogin_pinmap
This is required since PR #9449
commit
"Add HAL API for analog in pinmap"
2019-03-29 16:21:41 +01:00
Laurent Meunier d9c17addd7 Add WB support and CUBE FW version in readme.md 2019-03-29 16:21:40 +01:00
Laurent Meunier 5aa609b4db STM: fix minor warnings 2019-03-29 16:21:40 +01:00
Laurent Meunier 22f9ac6624 STM32WB: FIX LL RTC warning 2019-03-29 16:21:40 +01:00
Laurent Meunier 5871a712dc STM32WB: Move STM32WB utilies from FEATURE_BLE to targets folder
These files are not BLE specific, but also needed for some clock setting
for instance.

In order to compile an MBED2 application, we need to move the files.
2019-03-29 16:21:40 +01:00
Laurent Meunier 27e7e4d9df NUCLEO_WB55RG: Rework Clock and sleep support
- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as
this is used also out of BLE feature.
- create a dedicated hal_deepsleep function as the behavior in WB is a lot
different from other existing STM32 targets
- update clock tree configuration to directly clock the entire tree @ 32MHz
out of HSE. This is needed as we want to let the M0 core running without
any change on M0-side of clocks when M4 enters /exits deep sleep.
2019-03-29 16:21:40 +01:00
bcostm 96ecd48a40 NUCLEO_WB55RG: update targets.json 2019-03-29 16:21:39 +01:00
jeromecoutant ea86e8ef34 NUCLEO_WB55RG: HAL API updates to get SLEEP, RTC and LPTICKER OK
- astyle OK
- file alignment with other families
- HSE, MSI, HSI clock support
- LPTICKER with RTC and LPTIM tested
2019-03-29 16:21:38 +01:00
bcostm beab69704a NUCLEO_WB55RG: update STM common files
- Include RTC ll file from hal as in other families
- STM32WB: update Flash API driver
2019-03-29 16:21:38 +01:00
Laurent Meunier baf7a121bb NUCLEO_WB55RG: IAR, ARM and GCC linker files alignment
Align all scatter BLE shared memory declarations.
2019-03-29 16:21:38 +01:00
bcostm 4547fa34f7 NUCLEO_WB55RG: update mbed_rtx.h 2019-03-29 16:21:38 +01:00
bcostm 81f985433f NUCLEO_WB55RG: add SDK files
- Contains files from STM32Cube_FW_WB_V1.0.0
2019-03-29 16:21:37 +01:00
jeromecoutant ec00ea5655 STM32 ADC INTERNAL CHANNEL reset after read
Internal channels use is enabling ADC "internal path"
which needs to be disabled after measurement
2019-03-29 14:30:49 +01:00