Kernel::get_ms_count is documented as not working from IRQ.
In RTOS builds it can return misleading answers - see
https://github.com/ARM-software/CMSIS_5/issues/625
In non-RTOS builds, it can trigger an assert, as it upsets the
sleep logic.
Modified code is still not ideal - could be improved further if
there was a fast path for "post now" that didn't bother looking
at timers (both at post time and dispatch time).
Revert back to older behaviour where we hold deep sleep lock only while
timing a sleep. Previous version was a speed optimisation, but broke
some tests.
Provide partial RTOS API for bare metal builds - things that
can be done in a single threaded environment.
Allows more code to work in both RTOS and bare metal builds without
change, and in particular gives easy access to the ability to
efficiently wait for something occurring in interrupt.
Available in bare-metal:
* ThisThread
* osThreadFlagsSet to set flags on main thread (can be set from IRQ)
* EventFlags (can be set from IRQ)
* Semaphores (can be released from IRQ)
* Mutex (dummy implementation)
Not useful:
* ConditionVariable (could only be signalled from 2nd thread)
* RtosTimer (calls in a second thread context)
* Thread
Unimplemented:
* Mail, Queue, MemoryPool
Possible future work:
* ConditionVariableCS to act as IRQ signalled ConditionVariable
- Add the no confidentiality & no replay protection flags
- Add actual size parameter in PS/ITS get APIs
- Change a few size parameters from uint32_t to size_t
This test requires total latency (tot = h/w + s/w) (wakeup from deepsleep) be
under 1ms. To check the issue, measure total latency on Nuvoton targets:
TARGET EXP(us) EXP+TOL(us) ACT(us)
NANO130 42000 43000 42939
NUC472 42000 43000 42236
M453 42000 43000 43274
M487 42000 43000 42877
M2351 42000 43000 43213
Checking h/w spec, h/w latency (wakeup time from normal power-down mode) on
M487/M2351 is just 1us (n/a on other targets). S/W latency plays the major
part here.
S/W latency relies on system performance. On Nuvoton targets, 'LPTICKER_DELAY_TICKS'
possibly complicates the test. Anyway, to pass the test, add extra 1ms latency
(deep-sleep-latency) in targets.json for Nuvoton targets.
Fix warnings due to unused variables, comparison between signed and
unsigned. This patch also re-enables I2C asserts that were disabled
during early development.
Since QSPi is not yet supported by base TARGET_PSOC6,
there is no need to remove the device label from
FUTURE targets that inherit from TARGET_PSOC6.
This will need to be reverted back once the QSPI support
is implemented for Cypress PSOC6 targets.
During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Voltage rail differences between target and FPGA
Extension of lesser-resolution ADC's to 16-bit results
An extra start signal was observed on the bus which was
discovered by the FPGA test shield.
This is because the hardware sends out a transaction as soon
as a write to the START bit. Hence the write to the START
bit is delayed by using a flag.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Kevin Bracey
Martin Kojtal
David Saada
Yuan Cao
Evelyne Donnaes
Jaeden Amero
Filip Jagodzinski
Chun-Chieh Li
Russ Butler
Volodymyr Medvid
Arto Kinnunen
Volodymyr Medvid
jeromecoutant
Steven Cooreman
Tymoteusz Bloch
Mahesh Mahadevan