Increase ADC test tolerance to 5%

During the SiP workshop, we discovered that 3% is too narrow due to a combination of:
Voltage rail differences between target and FPGA
Extension of lesser-resolution ADC's to 16-bit results

TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp

@@ -36,8 +36,8 @@ using namespace utest::v1;
 
 #define analogin_debug_printf(...)
 
-#define DELTA_FLOAT                     0.03f    // 3%
-#define DELTA_U16                       1965     // 3%
+#define DELTA_FLOAT                     0.05f    // 5%
+#define DELTA_U16                       3277     // 5%
 
 const PinList *form_factor = pinmap_ff_default_pins();
 const PinList *restricted = pinmap_restricted_pins();