From f6a70b20281ac790e4644a5afa41eca2e2de6a10 Mon Sep 17 00:00:00 2001 From: Steven Cooreman Date: Wed, 10 Jul 2019 11:35:05 +0100 Subject: [PATCH] Increase ADC test tolerance to 5% During the SiP workshop, we discovered that 3% is too narrow due to a combination of: Voltage rail differences between target and FPGA Extension of lesser-resolution ADC's to 16-bit results --- TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp index 0add62b502..981ffff4d0 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/analogin/main.cpp @@ -36,8 +36,8 @@ using namespace utest::v1; #define analogin_debug_printf(...) -#define DELTA_FLOAT 0.03f // 3% -#define DELTA_U16 1965 // 3% +#define DELTA_FLOAT 0.05f // 5% +#define DELTA_U16 3277 // 5% const PinList *form_factor = pinmap_ff_default_pins(); const PinList *restricted = pinmap_restricted_pins();