mirror of https://github.com/ARMmbed/mbed-os.git
PSOC6: cleanup DEVICE_QSPI mappings
Note: device_has: "QSPI" is still disabled for TARGET_PSOC6 (QSPI HAL implementation is incomplete).pull/10692/head
Volodymyr Medvid
parent
2524a67c38
commit
bab34cb467
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@ -24,7 +24,7 @@
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#include "PeripheralNames.h"
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// //*** I2C ***
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//*** I2C ***
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#if DEVICE_I2C
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extern const PinMap PinMap_I2C_SDA[];
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extern const PinMap PinMap_I2C_SCL[];
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@ -51,13 +51,6 @@ extern const PinMap PinMap_SPI_SCLK[];
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extern const PinMap PinMap_SPI_SSEL[];
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#endif
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//*** QSPI ***
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#if DEVICE_QSPI
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extern const PinMap PinMap_QSPI_SCLK[];
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extern const PinMap PinMap_QSPI_DATA[];
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extern const PinMap PinMap_QSPI_SSEL[];
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#endif
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//*** ADC ***
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#if DEVICE_ANALOGIN
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extern const PinMap PinMap_ADC[];
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@ -68,6 +61,7 @@ extern const PinMap PinMap_ADC[];
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extern const PinMap PinMap_DAC[];
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#endif
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//*** QSPI ***
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#if DEVICE_QSPI
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extern const PinMap PinMap_QSPI_SCLK[];
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extern const PinMap PinMap_QSPI_SSEL[];
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@ -108,8 +108,8 @@ typedef enum {
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} DACName;
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typedef enum {
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SMIF_0 = (int)SMIF0_BASE,
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} SMIFName;
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QSPI_0,
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} QSPIName;
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#ifdef __cplusplus
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}
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@ -366,30 +366,28 @@ const PinMap PinMap_DAC[] = {
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#endif // DEVICE_ANALOGIN
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#if DEVICE_QSPI
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const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
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{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
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{NC, NC, 0}
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const PinMap PinMap_QSPI_SCLK[] = {
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{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
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{NC, NC, 0},
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};
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// Ensure that the spi_data pins are defined in the order 0 to 7
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const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
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{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
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{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
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{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
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{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
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{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
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{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
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{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
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{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
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{NC, NC, 0}
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};
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// Ensure that the spi_select pins are defined in the order 0 to 3
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const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
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{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
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{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
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{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
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{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
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{NC, NC, 0}
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const PinMap PinMap_QSPI_SSEL[] = {
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{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA0[] = {
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{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA1[] = {
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{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA2[] = {
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{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA3[] = {
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{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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#endif // DEVICE_QSPI
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@ -114,8 +114,8 @@ typedef enum {
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} ADCName;
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typedef enum {
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SMIF_0 = (int)SMIF0_BASE,
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} SMIFName;
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QSPI_0,
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} QSPIName;
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#ifdef __cplusplus
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}
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@ -464,31 +464,28 @@ const PinMap PinMap_ADC[] = {
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#endif // DEVICE_ANALOGIN
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#if DEVICE_QSPI
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const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
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{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
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{NC, NC, 0}
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const PinMap PinMap_QSPI_SCLK[] = {
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{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
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{NC, NC, 0},
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};
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// Ensure that the spi_data pins are defined in the order 0 to 7
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const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
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{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
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{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
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{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
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{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
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{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
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{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
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{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
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{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
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{NC, NC, 0}
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};
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// Ensure that the spi_select pins are defined in the order 0 to 3
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const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
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{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
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{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
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{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
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{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
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{NC, NC, 0}
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const PinMap PinMap_QSPI_SSEL[] = {
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{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA0[] = {
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{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA1[] = {
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{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA2[] = {
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{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA3[] = {
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{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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#endif // DEVICE_QSPI
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@ -108,8 +108,8 @@ typedef enum {
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} DACName;
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typedef enum {
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SMIF_0 = (int)SMIF0_BASE,
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} SMIFName;
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QSPI_0,
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} QSPIName;
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#ifdef __cplusplus
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}
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@ -436,30 +436,28 @@ const PinMap PinMap_DAC[] = {
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#endif // DEVICE_ANALOGIN
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#if DEVICE_QSPI
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const PinMap PinMap_QSPI_SCLK[] = { // does not use PERI clock, uses HFCLK2
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{P11_7, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_7_SMIF_SPI_CLK, 0)},
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{NC, NC, 0}
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const PinMap PinMap_QSPI_SCLK[] = {
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{P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
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{NC, NC, 0},
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};
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// Ensure that the spi_data pins are defined in the order 0 to 7
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const PinMap PinMap_QSPI_DATA[] = { // does not use PERI clock, uses HFCLK2
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{P11_6, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_6_SMIF_SPI_DATA0, 0)}, // spi_data0
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{P11_5, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_5_SMIF_SPI_DATA1, 0)}, // spi_data1
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{P11_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_4_SMIF_SPI_DATA2, 0)}, // spi_data2
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{P11_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_3_SMIF_SPI_DATA3, 0)}, // spi_data3
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{P12_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_0_SMIF_SPI_DATA4, 0)}, // spi_data4
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{P12_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_1_SMIF_SPI_DATA5, 0)}, // spi_data5
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{P12_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_2_SMIF_SPI_DATA6, 0)}, // spi_data6
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{P12_3, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_3_SMIF_SPI_DATA7, 0)}, // spi_data7
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{NC, NC, 0}
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};
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// Ensure that the spi_select pins are defined in the order 0 to 3
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const PinMap PinMap_QSPI_SSEL[] = { // does not use PERI clock, uses HFCLK2
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{P11_2, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0, 0)}, // spi_select0
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{P11_1, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1, 0)}, // spi_select1
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{P11_0, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2, 0)}, // spi_select2
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{P12_4, SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3, 0)}, // spi_select3
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{NC, NC, 0}
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const PinMap PinMap_QSPI_SSEL[] = {
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{P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA0[] = {
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{P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA1[] = {
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{P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA2[] = {
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{P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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const PinMap PinMap_QSPI_DATA3[] = {
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{P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
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{NC, NC, 0},
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};
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#endif // DEVICE_QSPI
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