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49 Commits (d0dba1a533eb97d8fbb70b36acdaf5ca20f117cc)

Author SHA1 Message Date
Wang Xu cd37bf47d5
Adding NUCLEO-U545RE-Q and NUCLEO-U5A5ZJ-Q support, with some changes to stm_dma_utils (#273) 
* added an option "QSPI_OSPIM_IOPORT_HIGH=1" to allow using the high IO ports (IO 4~7) of an OSPI peripheral to drive a QSPI device
updated STM32U5 firmware package to support STM32U5F/G devices
STM DMA Utils: added stm_get_dma_instance, stm_set_dma_link, stm_get_dma_link for working with DMA code in external libraries

* added NUCLEO-U545RE-Q and NUCLEO-U5A5ZJ-Q
USB is not supported yet

* added missing USART6 handlers for STM32U5

* changed PA_2_ALT0/PA_3_ALT0 in UART pinmap back to PA_2/PA_3 for NUCLEO-U545RE-Q

* renamed stm_get_dma_link to stm_get_dma_handle_for_link
renamed stm_set_dma_link to stm_set_dma_handle_for_link
added option "qspi_ospim_ioport_high" for MCU_STM32U5
implemented SetSysClock_PLL_HSI for NUCLEO-U545RE-Q and NUCLEO-U5A5ZJ-Q
made PLL_HSI the default clock source for NUCLEO-U545RE-Q and NUCLEO-U5A5ZJ-Q

* changed clock sources of NUCLEO-U545RE-Q and NUCLEO-U5A5ZJ-Q back to PLL+MSI
embedded LICENSE file into every source file in the STM32U5 firmware package
 2024-05-03 00:39:59 -07:00
jeromecoutant 21dcebb58d STM32 OSPI/QSPI : correct GPIO free 2021-03-18 14:53:00 +01:00
jeromecoutant 806417853d STM32WB: enable QSPI for custom boards 2021-03-08 16:51:53 +01:00
reme 5a2835c18c STM32WL : ADDING STM32 SUPPORT 
Add code concerning all STM32 platforms
 2021-02-05 08:04:31 +00:00
Martino Facchin c2aa453387 STM32: QSPI: allow setting SAMPLE_SHIFTING mode 2020-12-11 10:11:51 +01:00
Lingkai Dong 8f50b03a38 Reduce ST QSPI/OSPI trace verbosity to debug 2020-11-19 16:22:12 +00:00
jeromecoutant 3c6ba98823 STM32L4: STM32Cube_FW_L4_V1.16.0 
source: https://github.com/STMicroelectronics/STM32CubeL4
 2020-10-20 08:51:37 +02:00
rogeryou de9b283abe modify the div value when calling octo controller. 
For ST OSPI controller driver(stm32l4xx_hal_ospi.c), the frequency it has be subtracted 1, so "div = div - 1;" should be removed.
 2020-05-25 12:07:24 +08:00
jeromecoutant 9977ace2c9 STM32 : enable MBED trace for QSPI 2020-02-20 12:20:24 +01:00
jeromecoutant f0969022b8 STM32L5 : add QSPI support 2020-02-14 17:49:33 +01:00
Martin Kojtal 7177d8fefe
Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS 
DISCO_H747I: add support of MBED_TICKLESS
 2019-11-29 09:48:09 +01:00
Przemyslaw Stekiel 2e793842d8 STM QSPI driver: return init status, fix pin function setting 2019-11-28 12:41:40 +01:00
Przemyslaw Stekiel b2dad08387 Change explicit pinmap to static pinmap 2019-11-28 08:32:12 +01:00
Przemyslaw Stekiel 31f99416ae STM QSPI driver: Add explicit pinmap support 2019-11-28 08:32:04 +01:00
Alexandre Bourdiol affe7113ef TARGET_STM: Remove timeout on HSEM. 
With tickless mechanism hsem can be used for quite a long time
(time to set up PLL clock).
Also, if hsem is held to long, then this is not the current core which is faulty,
but probably the other (the one which hold the HSEM)
 2019-11-27 14:25:43 +01:00
Laurent Meunier 28c908fdef STM32 QSPI: Use defines for setting address size 2019-10-28 15:38:53 +01:00
Kyle Kearney 8e9877c212 Update STM driver changes for clarity 
- Use a switch statement rather than shifting and masking to compute
  the AlternateBytes value.
- Rename rounded_size to alt_bytes to clarify its purpose.
 2019-10-16 09:37:27 -07:00
Alexandre Bourdiol adcf0e2fa5 DISCO_H747I Dualcore support 
Add 2 targets for DISCO_H747I dualcore:
* DISCO_H747I      -> for CM7 core
* DISCO_H747I_CM4  -> for CM4 core

Current restrictions:
* TICKLESS deactivated
* DeepSleep not supported (DeepSleep wrapped to sleep)

Warning: use of the same IP (example I2C1) by both core at the same time is not prevented,
but is strongly not recommended.
Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC.

Warning: Drag and drop of binary to DISCO_H747I will flash CM7.
         In order to flash CM4, one can use STM32 CubeProgrammer tool.
 2019-10-14 18:02:57 +02:00
Kyle Kearney 9b32c0f316 Fix possible negative QSPI alt count on STM 
Remove an extraneous decrement operation in cases where the alt
bits size is a multiple of 8.
 2019-09-30 16:00:24 -07:00
Matthew Macovsky baf375f8cb Allow for arbitrary QSPI alt sizes 
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
 2019-09-30 14:45:08 -07:00
Laurent Meunier 8401c2ea31 STM32: Few fixes and tidy-up in qspi_api 2019-08-29 11:17:46 +02:00
jeromecoutant 8cd00b3468 STM32L4: Add OSPI IP support in fallback QSPI mode 
For STM32 platforms that embed an OSPI IP, we're offering
a QSPI fallback support with this commit.

When OSPI is supported in mbed, we can consider adding full
OSPI support
 2019-08-23 15:18:48 +02:00
Russ Butler 2ed1dc2bfa Add HAL API for qspi pinmap 
Add the functions qspi_master_sclk_pinmap, qspi_master_ssel_pinmap and
qspi_master_data0_pinmap-qspi_master_data3_pinmap to all targets with
qspi support.
 2019-02-08 09:10:25 -06:00
Russ Butler 82b131aa59 Use dedicated PinMap for each QSPI data line 
Split PinMap_QSPI_DATA into PinMap_QSPI_DATA0 - PinMap_QSPI_DATA3.
This allows pins to be selected more accurately.
 2019-01-22 12:11:15 -06:00
Martin Kojtal fd6ceda960
Merge pull request #9323 from jeromecoutant/PR_AST 
STM32: astyle check
 2019-01-11 14:06:05 +00:00
jeromecoutant b1a284a876 STM32: astyle check 2019-01-10 10:22:21 +01:00
jeromecoutant cc447e9b27 STM32 : typo error in QSPI 2019-01-10 10:06:17 +01:00
jeromecoutant dfa902ec6c STM32 QSPI: frequency calculation update 2018-12-13 10:56:33 +01:00
adustm 6095ccf1b4 Add reset internal state before call to HAL_QspiInit function 2018-08-22 15:02:11 +02:00
adustm 7dda4e4fc6 Implement qspi_free function 2018-08-22 15:02:10 +02:00
adustm 5c26e15cd3 Fix support of max flash size 2018-08-22 15:02:09 +02:00
Maciej Bocianski 42935bbdc0 STM qspi: temporary fix for qspi_free return value 2018-08-22 15:02:03 +02:00
adustm 9b4b28fc3f Support maximum flash size : 4Gbytes 2018-08-22 15:00:22 +02:00
adustm c57a47e4b5 Change default FlashSize to 64Mbit = 8Mbytes = 0x800000 2018-08-22 15:00:20 +02:00
adustm 8e08740237 Fix Instruction with no data command 
Adding QSPI_DATA_NONE activates the transfer
of the command inside HAL_QSPI_COMMAND function
 2018-08-22 15:00:19 +02:00
adustm 05899e9c70 Fix Address.Size and AlternateByes.Size by shifting them 
The ST HAL code is waiting for the correctly shifted vlue
(for a direct write into the HW register)
 2018-08-22 15:00:18 +02:00
Martin Kojtal d282c81e86 QSPI: add STM32L4 support 
Disco IoT board support for QSPI. As it does not have dual flash support in QSPI,
we need to fix qspi hal implementation.
 2018-08-22 15:00:17 +02:00
Martin Kojtal c778c90184 QSPI STM32: fix default fifo and cycle 
As example for DISCO F469NI defines them
 2018-08-22 15:00:15 +02:00
Martin Kojtal 8783956a77 QSPI STM32: fix prepare comman - alt/address 2018-08-22 15:00:14 +02:00
Martin Kojtal fff20729be QSPI STM32: fix command transfer 
use write/read from STM32 driver
 2018-08-22 15:00:14 +02:00
Martin Kojtal 5038b38622 QSPI STM32: fix pin merging 
hw name as input
 2018-08-22 15:00:13 +02:00
Martin Kojtal 16ca742d87 QSPI STM32: fix disabled format phase 2018-08-22 15:00:12 +02:00
Martin Kojtal 2766672f64 QSPI STM32: add QSPI_x support to pinnames 2018-08-22 15:00:12 +02:00
Martin Kojtal 660d250e0d QSPI STM32: init returns error if failed to init 2018-08-22 15:00:11 +02:00
Martin Kojtal 551f044e77 QSPI STM32: add qspi_command_transfer implementation 2018-08-22 15:00:11 +02:00
Martin Kojtal 6e5b889e52 QSPI STM32: remove polling from write/read 
This will be part of custom instruction transfer, the flow will be:

1. write data
2. wait for transfer to complete (poll status register from the memory device)
 2018-08-22 15:00:10 +02:00
Martin Kojtal 8da072d8af QSPI STM32: set default command values to none 2018-08-22 15:00:10 +02:00
Martin Kojtal 11ae100d80 QSPI STM32: fix return value in frequency 2018-08-22 15:00:09 +02:00
Martin Kojtal 7da0ac2516 QSPI: add STM32 implementation 2018-08-22 15:00:08 +02:00