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TARGET_STM: Remove timeout on HSEM. 

With tickless mechanism hsem can be used for quite a long time
(time to set up PLL clock).
Also, if hsem is held to long, then this is not the current core which is faulty,
but probably the other (the one which hold the HSEM)
pull/11950/head
Alexandre Bourdiol 2019-11-19 16:16:17 +01:00
parent 41b038a028
commit affe7113ef
17 changed files with 33 additions and 65 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c
View File

@ -93,8 +93,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
return;
}
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
/* Force the CRYP Periheral Clock Reset */

3
targets/TARGET_STM/TARGET_STM32H7/analogin_device.c
View File

@ -89,8 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
PeriphClkInitStruct.PLL2.PLL2P = 4;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

9
targets/TARGET_STM/TARGET_STM32H7/flash_api.c
View File

@ -28,8 +28,7 @@ static uint32_t GetSectorBase(uint32_t SectorId, uint32_t BanksId);
int32_t flash_init(flash_t *obj)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* DUAL_CORE */
/* Clear pending flags (if any) */
@ -58,8 +57,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
}
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_FLASH_Unlock() != HAL_OK) {
@ -121,8 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_FLASH_Unlock() != HAL_OK) {

6
targets/TARGET_STM/TARGET_STM32H7/pin_device.h
View File

@ -45,8 +45,7 @@ static inline void stm_pin_DisconnectDebug(PinName pin)
static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */
@ -72,8 +71,7 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

9
targets/TARGET_STM/can_api.c
View File

@ -91,8 +91,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80)
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
@ -190,8 +189,7 @@ void can_irq_free(can_t *obj)
void can_free(can_t *obj)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
__HAL_RCC_FDCAN_FORCE_RESET();
@ -638,8 +636,7 @@ void can_free(can_t *obj)
{
CANName can = (CANName) obj->CanHandle.Instance;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
// Reset CAN and disable clock

3
targets/TARGET_STM/gpio_api.c
View File

@ -156,8 +156,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
inline void gpio_dir(gpio_t *obj, PinDirection direction)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

3
targets/TARGET_STM/gpio_object.h
View File

@ -58,8 +58,7 @@ typedef struct {
static inline void gpio_write(gpio_t *obj, int value)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

6
targets/TARGET_STM/i2c_api.c
View File

@ -215,8 +215,7 @@ void i2c_hw_reset(i2c_t *obj)
timeout = BYTE_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
#if defined(DUAL_CORE)
timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined I2C1_BASE
@ -422,8 +421,7 @@ void i2c_frequency(i2c_t *obj, int hz)
/*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
#if defined(DUAL_CORE)
timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)

3
targets/TARGET_STM/lp_ticker.c
View File

@ -205,8 +205,7 @@ void lp_ticker_init(void)
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {

8
targets/TARGET_STM/pinmap.c
View File

@ -81,8 +81,7 @@ void pin_function(PinName pin, int data)
if (mode == STM_PIN_OUTPUT) {
#endif
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */
switch (speed) {
@ -126,7 +125,7 @@ void pin_function(PinName pin, int data)
}
#if defined(DUAL_CORE)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */
@ -172,8 +171,7 @@ void pin_mode(PinName pin, PinMode mode)
GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

6
targets/TARGET_STM/qspi_api.c
View File

@ -499,8 +499,7 @@ qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinN
// Reset QSPI
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
__HAL_RCC_QSPI_FORCE_RESET();
@ -607,8 +606,7 @@ qspi_status_t qspi_free(qspi_t *obj)
// Reset QSPI
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
__HAL_RCC_QSPI_FORCE_RESET();

3
targets/TARGET_STM/rtc_api.c
View File

@ -59,8 +59,7 @@ void rtc_init(void)
HAL_PWR_EnableBkUpAccess();
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if MBED_CONF_TARGET_LSE_AVAILABLE

18
targets/TARGET_STM/serial_api.c
View File

@ -211,8 +211,7 @@ void serial_free(serial_t *obj)
// Reset UART and disable clock
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined(USART1_BASE)
@ -365,8 +364,7 @@ void serial_baud(serial_t *obj, int baudrate)
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCC_OscConfig(&RCC_OscInitStruct);
@ -377,8 +375,7 @@ void serial_baud(serial_t *obj, int baudrate)
// Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout
if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
@ -408,8 +405,7 @@ void serial_baud(serial_t *obj, int baudrate)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCC_OscConfig(&RCC_OscInitStruct);
@ -421,8 +417,7 @@ void serial_baud(serial_t *obj, int baudrate)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) {
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
@ -437,8 +432,7 @@ void serial_baud(serial_t *obj, int baudrate)
// Last chance using SYSCLK
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

6
targets/TARGET_STM/sleep.c
View File

@ -58,8 +58,7 @@ static void ForcePeriphOutofDeepSleep(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
/* Get the Clocks configuration according to the internal RCC registers */
@ -100,8 +99,7 @@ static void ForceOscOutofDeepSleep(void)
__HAL_RCC_PWR_CLK_ENABLE();
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
/* Get the Oscillators configuration according to the internal RCC registers */

3
targets/TARGET_STM/stm_spi_api.c
View File

@ -236,8 +236,7 @@ void spi_free(spi_t *obj)
HAL_SPI_DeInit(handle);
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined SPI1_BASE

3
targets/TARGET_STM/trng_api.c
View File

@ -54,8 +54,7 @@ void trng_init(trng_t *obj)
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {

6
targets/TARGET_STM/us_ticker.c
View File

@ -76,8 +76,7 @@ void init_16bit_timer(void)
// Reset timer
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
TIM_MST_RESET_ON;
@ -170,8 +169,7 @@ void init_32bit_timer(void)
// Reset timer
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
TIM_MST_RESET_ON;