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Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS 

DISCO_H747I: add support of MBED_TICKLESS
pull/11984/head
Martin Kojtal 2019-11-29 09:48:09 +01:00 committed by GitHub
parent 9f34b255be 42a0407a56
commit 7177d8fefe
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
33 changed files with 157 additions and 116 deletions
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3
features/mbedtls/targets/TARGET_STM/TARGET_STM32L4/aes_alt.c
View File

@ -93,8 +93,7 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
return;
}
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
/* Force the CRYP Periheral Clock Reset */

8
targets/TARGET_STM/TARGET_STM32F0/common_objects.h
View File

@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32f0xx_ll_usart.h"
#include "stm32f0xx_ll_tim.h"
#include "stm32f0xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {
@ -119,6 +120,13 @@ struct analogin_s {
uint8_t channel;
};
#ifdef CRC_PROG_POLYNOMIAL_SUPPORT
#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 7 || (width) == 8 || (width) == 16 || (width) == 32)
#else
#define HAL_CRC_IS_SUPPORTED(polynomial, width) ((width) == 32 && (polynomial) == 0x04C11DB7)
#endif
#include "gpio_object.h"
#if DEVICE_ANALOGOUT

1
targets/TARGET_STM/TARGET_STM32F1/common_objects.h
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@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32f1xx_ll_usart.h"
#include "stm32f1xx_ll_tim.h"
#include "stm32f1xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32F2/objects.h
View File

@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32f2xx_ll_usart.h"
#include "stm32f2xx_ll_tim.h"
#include "stm32f2xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32F3/common_objects.h
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@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32f3xx_ll_usart.h"
#include "stm32f3xx_ll_tim.h"
#include "stm32f3xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32F4/common_objects.h
View File

@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32f4xx_ll_usart.h"
#include "stm32f4xx_ll_tim.h"
#include "stm32f4xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32F7/common_objects.h
View File

@ -38,6 +38,7 @@
#include "stm32f7xx_ll_tim.h"
#include "stm32f7xx_ll_adc.h"
#include "stm32f7xx_ll_rtc.h"
#include "stm32f7xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

23
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/h747i_sleep.c
View File

@ -1,23 +0,0 @@
/* mbed Microcontroller Library
*******************************************************************************
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
* SPDX-License-Identifier: BSD-3-Clause
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*******************************************************************************
*/
#if DEVICE_SLEEP
/* Deepsleep temporarily not supported on STM32H747I
* wrap it to sleep
*/
void hal_deepsleep(void)
{
hal_sleep();
}
#endif

3
targets/TARGET_STM/TARGET_STM32H7/analogin_device.c
View File

@ -89,8 +89,7 @@ void analogin_init(analogin_t *obj, PinName pin)
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
PeriphClkInitStruct.PLL2.PLL2P = 4;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

14
targets/TARGET_STM/TARGET_STM32H7/device/stm32h7xx_hal_rcc.c
View File

@ -803,7 +803,19 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
}
else
{
return HAL_ERROR;
/* Do not return HAL_ERROR if request repeats the current configuration */
uint32_t temp1_pllckcfg = RCC->PLLCKSELR;
uint32_t temp2_pllckcfg = RCC->PLL1DIVR;
if(((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
{
return HAL_ERROR;
}
}
}
return HAL_OK;

9
targets/TARGET_STM/TARGET_STM32H7/flash_api.c
View File

@ -28,8 +28,7 @@ static uint32_t GetSectorBase(uint32_t SectorId, uint32_t BanksId);
int32_t flash_init(flash_t *obj)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* DUAL_CORE */
/* Clear pending flags (if any) */
@ -58,8 +57,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
}
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_FLASH_Unlock() != HAL_OK) {
@ -121,8 +119,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data,
}
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_FLASH_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_FLASH_Unlock() != HAL_OK) {

6
targets/TARGET_STM/TARGET_STM32H7/objects.h
View File

@ -40,9 +40,9 @@
#if defined(DUAL_CORE)
#include "stm32h7xx_ll_hsem.h"
#include "stm32h7xx_ll_rcc.h"
#include "stm32h7xx_ll_pwr.h"
#include "stm32h7xx_ll_cortex.h"
#endif /* CONFIG_STM32H7_DUAL_CORE */
#include "stm32h7xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {
@ -151,8 +151,8 @@ struct analogin_s {
#if defined(DUAL_CORE)
/* HW semaphore Complement ID list defined in hw_conf.h from STM32WB */
/* Index of the semaphore used to manage the entry Stop Mode procedure */
#define CFG_HW_ENTRY_STOP_MODE_SEMID 4
#define CFG_HW_ENTRY_STOP_MODE_MASK_SEMID (1 << CFG_HW_ENTRY_STOP_MODE_SEMID)
#define CFG_HW_STOP_MODE_SEMID 4
#define CFG_HW_STOP_MODE_MASK_SEMID (1 << CFG_HW_STOP_MODE_SEMID)
/* Index of the semaphore used to access the RCC */
#define CFG_HW_RCC_SEMID 3

6
targets/TARGET_STM/TARGET_STM32H7/pin_device.h
View File

@ -45,8 +45,7 @@ static inline void stm_pin_DisconnectDebug(PinName pin)
static inline void stm_pin_PullConfig(GPIO_TypeDef *gpio, uint32_t ll_pin, uint32_t pull_config)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */
@ -72,8 +71,7 @@ static inline void stm_pin_SetAFPin(GPIO_TypeDef *gpio, PinName pin, uint32_t af
uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)];
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

1
targets/TARGET_STM/TARGET_STM32L0/common_objects.h
View File

@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32l0xx_ll_usart.h"
#include "stm32l0xx_ll_tim.h"
#include "stm32l0xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32L1/common_objects.h
View File

@ -36,6 +36,7 @@
#include "PinNames.h"
#include "stm32l1xx_ll_usart.h"
#include "stm32l1xx_ll_tim.h"
#include "stm32l1xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32L4/common_objects.h
View File

@ -38,6 +38,7 @@
#include "stm32l4xx_ll_lpuart.h"
#include "stm32l4xx_ll_tim.h"
#include "stm32l4xx_ll_rtc.h"
#include "stm32l4xx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

1
targets/TARGET_STM/TARGET_STM32WB/common_objects.h
View File

@ -38,6 +38,7 @@
#include "PinNames.h"
#include "stm32wbxx_ll_usart.h"
#include "stm32wbxx_ll_tim.h"
#include "stm32wbxx_ll_pwr.h"
#ifdef __cplusplus
extern "C" {

9
targets/TARGET_STM/can_api.c
View File

@ -87,8 +87,7 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
RCC_PeriphClkInit.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; // 10 MHz (RCC_OscInitStruct.PLL.PLLQ = 80)
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
@ -229,8 +228,7 @@ void can_irq_free(can_t *obj)
void can_free(can_t *obj)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
__HAL_RCC_FDCAN_FORCE_RESET();
@ -716,8 +714,7 @@ void can_free(can_t *obj)
{
CANName can = (CANName) obj->CanHandle.Instance;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
// Reset CAN and disable clock

3
targets/TARGET_STM/gpio_api.c
View File

@ -156,8 +156,7 @@ void gpio_mode(gpio_t *obj, PinMode mode)
inline void gpio_dir(gpio_t *obj, PinDirection direction)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

3
targets/TARGET_STM/gpio_object.h
View File

@ -58,8 +58,7 @@ typedef struct {
static inline void gpio_write(gpio_t *obj, int value)
{
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

6
targets/TARGET_STM/i2c_api.c
View File

@ -215,8 +215,7 @@ void i2c_hw_reset(i2c_t *obj)
timeout = BYTE_TIMEOUT;
while ((__HAL_I2C_GET_FLAG(handle, I2C_FLAG_BUSY)) && (--timeout != 0));
#if defined(DUAL_CORE)
timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined I2C1_BASE
@ -452,8 +451,7 @@ void i2c_frequency(i2c_t *obj, int hz)
/*##-1- Configure the I2C clock source. The clock is derived from the SYSCLK #*/
#if defined(DUAL_CORE)
timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined(I2C1_BASE) && defined (__HAL_RCC_I2C1_CONFIG)

21
targets/TARGET_STM/lp_ticker.c
View File

@ -67,6 +67,13 @@
#define LPTIM_MST_IRQ LPTIM4_IRQn
#define LPTIM_MST_RCC __HAL_RCC_LPTIM4_CLK_ENABLE
#define LPTIM_MST_RCC_CLKAM __HAL_RCC_LPTIM4_CLKAM_ENABLE
/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG() {\
HAL_EXTI_D1_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, ENABLE);\
HAL_EXTI_D2_EventInputConfig(EXTI_LINE52, EXTI_MODE_IT, DISABLE);\
}
#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM4_FORCE_RESET
#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM4_RELEASE_RESET
@ -85,6 +92,13 @@
#define LPTIM_MST_IRQ LPTIM5_IRQn
#define LPTIM_MST_RCC __HAL_RCC_LPTIM5_CLK_ENABLE
#define LPTIM_MST_RCC_CLKAM __HAL_RCC_LPTIM5_CLKAM_ENABLE
/* Enable LPTIM wakeup source but only for current core, and disable it for the other core */
#define LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG() {\
HAL_EXTI_D2_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, ENABLE);\
HAL_EXTI_D1_EventInputConfig(EXTI_LINE53, EXTI_MODE_IT, DISABLE);\
}
#define LPTIM_MST_RESET_ON __HAL_RCC_LPTIM5_FORCE_RESET
#define LPTIM_MST_RESET_OFF __HAL_RCC_LPTIM5_RELEASE_RESET
#else
@ -191,8 +205,7 @@ void lp_ticker_init(void)
#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
@ -209,6 +222,10 @@ void lp_ticker_init(void)
LPTIM_MST_RESET_ON();
LPTIM_MST_RESET_OFF();
#if defined(DUAL_CORE)
/* Configure EXTI wakeup and configure autonomous mode */
LPTIM_MST_RCC_CLKAM();
LPTIM_MST_EXTI_LPTIM_WAKEUP_CONFIG();
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */

9
targets/TARGET_STM/mbed_overrides.c
View File

@ -60,7 +60,7 @@ void mbed_sdk_init()
/* CM4 boots at the same time than CM7. It is necessary to synchronize with CM7, by mean of HSEM, that CM7 finishes its initialization. */
/* Activate HSEM notification for Cortex-M4*/
LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID);
LL_HSEM_EnableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
/*
* Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
@ -89,7 +89,8 @@ void mbed_sdk_init()
LL_LPM_EnableSleep();
/* Clear HSEM flag */
LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_ENTRY_STOP_MODE_MASK_SEMID);
LL_HSEM_DisableIT_C2IER(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
LL_HSEM_ClearFlag_C2ICR(HSEM, CFG_HW_STOP_MODE_MASK_SEMID);
}
// Update the SystemCoreClock variable.
@ -109,9 +110,9 @@ void mbed_sdk_init()
/* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization.
otherwise CM7 should wakeup CM4 when system clocks initialization is done. */
if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) {
LL_HSEM_1StepLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID);
LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID);
/*Release HSEM in order to notify the CPU2(CM4)*/
LL_HSEM_ReleaseLock(HSEM, CFG_HW_ENTRY_STOP_MODE_SEMID, 0);
LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, 0);
} else {
LL_RCC_ForceCM4Boot();
}

8
targets/TARGET_STM/pinmap.c
View File

@ -81,8 +81,7 @@ void pin_function(PinName pin, int data)
if (mode == STM_PIN_OUTPUT) {
#endif
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */
switch (speed) {
@ -126,7 +125,7 @@ void pin_function(PinName pin, int data)
}
#if defined(DUAL_CORE)
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */
@ -172,8 +171,7 @@ void pin_mode(PinName pin, PinMode mode)
GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index);
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_GPIO_SEMID)) {
}
#endif /* DUAL_CORE */

6
targets/TARGET_STM/qspi_api.c
View File

@ -531,8 +531,7 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap,
// Reset QSPI
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
__HAL_RCC_QSPI_FORCE_RESET();
@ -661,8 +660,7 @@ qspi_status_t qspi_free(qspi_t *obj)
// Reset QSPI
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
__HAL_RCC_QSPI_FORCE_RESET();

3
targets/TARGET_STM/rtc_api.c
View File

@ -59,8 +59,7 @@ void rtc_init(void)
HAL_PWR_EnableBkUpAccess();
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if MBED_CONF_TARGET_LSE_AVAILABLE

18
targets/TARGET_STM/serial_api.c
View File

@ -229,8 +229,7 @@ void serial_free(serial_t *obj)
// Reset UART and disable clock
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined(USART1_BASE)
@ -383,8 +382,7 @@ void serial_baud(serial_t *obj, int baudrate)
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCC_OscConfig(&RCC_OscInitStruct);
@ -395,8 +393,7 @@ void serial_baud(serial_t *obj, int baudrate)
// Keep it to verify if HAL_RCC_OscConfig didn't exit with a timeout
if (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
@ -426,8 +423,7 @@ void serial_baud(serial_t *obj, int baudrate)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCC_OscConfig(&RCC_OscInitStruct);
@ -439,8 +435,7 @@ void serial_baud(serial_t *obj, int baudrate)
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY)) {
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
@ -455,8 +450,7 @@ void serial_baud(serial_t *obj, int baudrate)
// Last chance using SYSCLK
PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);

80
targets/TARGET_STM/sleep.c
View File

@ -57,11 +57,6 @@ static void ForcePeriphOutofDeepSleep(void)
uint32_t pFLatency = 0;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
}
#endif /* DUAL_CORE */
/* Get the Clocks configuration according to the internal RCC registers */
HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
@ -86,9 +81,6 @@ static void ForcePeriphOutofDeepSleep(void)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
error("ForcePeriphOutofDeepSleep clock issue\r\n");
}
#if defined(DUAL_CORE)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */
}
@ -99,11 +91,6 @@ static void ForceOscOutofDeepSleep(void)
/* Enable Power Control clock */
__HAL_RCC_PWR_CLK_ENABLE();
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
}
#endif /* DUAL_CORE */
/* Get the Oscillators configuration according to the internal RCC registers */
HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
@ -123,9 +110,7 @@ static void ForceOscOutofDeepSleep(void)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
error("ForceOscOutofDeepSleep clock issue\r\n");
}
#if defined(DUAL_CORE)
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
#endif /* DUAL_CORE */
}
@ -135,7 +120,7 @@ void hal_sleep(void)
core_util_critical_section_enter();
// Request to enter SLEEP mode
#ifdef PWR_CR1_LPR
#if defined(PWR_CR1_LPR)
// State Transitions (see 5.3 Low-power modes, Fig. 13):
// * (opt): Low Power Run (LPR) Mode -> Run Mode
// * Run Mode -> Sleep
@ -145,7 +130,14 @@ void hal_sleep(void)
// [5.4.1 Power control register 1 (PWR_CR1)]
// LPR: When this bit is set, the regulator is switched from main mode (MR) to low-power mode (LPR).
int lowPowerMode = PWR->CR1 & PWR_CR1_LPR;
uint32_t lowPowerMode = LL_PWR_IsEnabledLowPowerRunMode();
if (lowPowerMode) {
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
} else {
HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
}
#elif defined(PWR_CR_LPDS) || defined(PWR_CR1_LPDS)
uint32_t lowPowerMode = LL_PWR_GetRegulModeDS();
if (lowPowerMode) {
HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFI);
} else {
@ -204,6 +196,25 @@ __WEAK void hal_deepsleep(void)
if (!pwrClockEnabled) {
__HAL_RCC_PWR_CLK_DISABLE();
}
#elif defined(DUAL_CORE)
int lowPowerModeEnabled = LL_PWR_GetRegulModeDS();
#if defined(CORE_CM7)
HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN);
HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D1_DOMAIN);
#elif defined(CORE_CM4)
HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D3_DOMAIN);
HAL_PWREx_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI, PWR_D2_DOMAIN);
#else
#error "Wrong Core selection"
#endif /* CORE_CM7 */
if (lowPowerModeEnabled) {
LL_PWR_SetRegulModeDS(lowPowerModeEnabled);
}
#else /* PWR_CR1_LPMS_STOP2 */
HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
#endif /* PWR_CR1_LPMS_STOP2 */
@ -212,6 +223,36 @@ __WEAK void hal_deepsleep(void)
* us_ticker timestamp until the us_ticker context is restored. */
mbed_sdk_inited = 0;
/* After wake-up from STOP reconfigure the PLL */
#if defined(DUAL_CORE)
/* CFG_HW_STOP_MODE_SEMID is used to protect read access to STOP flag, and this avoid both core to configure clocks if both exit from stop at the same time */
while (LL_HSEM_1StepLock(HSEM, CFG_HW_STOP_MODE_SEMID)) {
}
/* Clocks need to be reconfigured only if system has been in stop mode */
if (LL_PWR_CPU_IsActiveFlag_STOP() && LL_PWR_CPU2_IsActiveFlag_STOP()) {
/* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered
* So we need to force clock init out of Deep Sleep.
* This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel.
* This will reduce the maximum stack usage in case on non-optimized / debug compilers settings
*/
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
ForceOscOutofDeepSleep();
ForcePeriphOutofDeepSleep();
SetSysClock();
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
}
#if defined(CORE_CM7)
LL_PWR_ClearFlag_CPU();
#elif defined(CORE_CM4)
LL_PWR_ClearFlag_CPU2();
#else
#error "Core not supported"
#endif
LL_HSEM_ReleaseLock(HSEM, CFG_HW_STOP_MODE_SEMID, HSEM_CR_COREID_CURRENT);
#else
/* We've seen unstable PLL CLK configuration when DEEP SLEEP exits just few µs after being entered
* So we need to force clock init out of Deep Sleep.
* This init has been split into 2 separate functions so that the involved structures are not allocated on the stack in parallel.
@ -219,9 +260,8 @@ __WEAK void hal_deepsleep(void)
*/
ForceOscOutofDeepSleep();
ForcePeriphOutofDeepSleep();
// After wake-up from STOP reconfigure the PLL
SetSysClock();
#endif
/* Wait for clock to be stabilized.
* TO DO: a better way of doing this, would be to rely on

3
targets/TARGET_STM/stm_spi_api.c
View File

@ -260,8 +260,7 @@ void spi_free(spi_t *obj)
HAL_SPI_DeInit(handle);
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
#if defined SPI1_BASE

3
targets/TARGET_STM/trng_api.c
View File

@ -54,8 +54,7 @@ void trng_init(trng_t *obj)
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {

6
targets/TARGET_STM/us_ticker.c
View File

@ -76,8 +76,7 @@ void init_16bit_timer(void)
// Reset timer
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
TIM_MST_RESET_ON;
@ -170,8 +169,7 @@ void init_32bit_timer(void)
// Reset timer
#if defined(DUAL_CORE)
uint32_t timeout = HSEM_TIMEOUT;
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
}
#endif /* DUAL_CORE */
TIM_MST_RESET_ON;

12
targets/targets.json
View File

@ -3301,7 +3301,8 @@
"macros_add": [
"STM32H747xx",
"CORE_CM7",
"EXTRA_IDLE_STACK_REQUIRED"
"EXTRA_IDLE_STACK_REQUIRED",
"MBED_TICKLESS"
],
"overrides": { "lpticker_delay_ticks": 0 },
"supported_form_factors": [
@ -3336,6 +3337,11 @@
"mbed_ram_start": "0x10000000",
"mbed_ram_size" : "0x48000",
"config": {
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC",
"macro_name": "CLOCK_SOURCE"
},
"lpticker_lptim": {
"help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
"value": 1
@ -3344,7 +3350,8 @@
"macros_add": [
"STM32H747xx",
"CORE_CM4",
"EXTRA_IDLE_STACK_REQUIRED"
"EXTRA_IDLE_STACK_REQUIRED",
"MBED_TICKLESS"
],
"overrides": { "lpticker_delay_ticks": 0 },
"supported_form_factors": [
@ -3360,7 +3367,6 @@
"FLASH",
"MPU"
],
"device_name": "STM32H747XIHx",
"bootloader_supported": true
},
"DISCO_H747I_CM7": {

2
tools/export/iar/iar_definitions.json
View File

@ -371,7 +371,7 @@
"STM32H743ZI": {
"OGChipSelectEditMenu": "STM32H743ZI\tST STM32H743ZI"
},
"DISCO_H747I": {
"STM32H747XIHx": {
"OGChipSelectEditMenu": "STM32H747XI_CM7\tST STM32H747XI_CM7"
},
"DISCO_H747I_CM4": {