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3380 Commits (c1c5d89bdfdc068a4ba4ff19529b0948307d2007)

Author SHA1 Message Date
Cruz Monrreal 218811024f
Merge pull request #7479 from SiliconLabs/feature/crc 
Silicon Labs: Add support for hardware CRC
 2018-07-19 13:06:42 -05:00
Cruz Monrreal dd6482b955
Merge pull request #7504 from TacoGrandeTX/feature_itm_fix 
Feature itm fix
 2018-07-18 09:01:13 -05:00
Cruz Monrreal db9a0e8b72
Merge pull request #7533 from marcuschangarm/fix-nrf52832-iar 
Fix linker script for NRF52832/IAR
 2018-07-18 08:56:44 -05:00
Cruz Monrreal e9e1ff997d
Merge pull request #7302 from OpenNuvoton/nuvoton_m2351_v1.1 
Support Nuvoton's NUMAKER_PFM_M2351 target
 2018-07-18 08:49:55 -05:00
Marcus Chang 9a073c0ae4 Fix linker script for NRF52832/IAR 
IAR linker script was using memory settings from the NRF52840 and
not the NRF52832.
 2018-07-17 12:43:23 -07:00
Steven Cooreman 86491627bf Add implementation for CRC API 2018-07-16 11:08:45 +02:00
Deepika 455f1fd440 [M2351] Support only ARMC6 toolchain 
Support for GCC_ARM/IAR toolchains are TODO.
 2018-07-16 10:15:36 +08:00
Cruz Monrreal 38744b9e68
Merge pull request #7498 from bcostm/fix_hsi_lse_lpuart 
STM32: enable HSI/LSE clocks for LPUART
 2018-07-14 13:33:35 -05:00
Cruz Monrreal 671b3c875e
Merge pull request #7507 from jeromecoutant/PR_LPTIM 
STM32 LPTICKER with LPTIM minor update
 2018-07-14 06:29:36 -05:00
Cruz Monrreal 602b0cea09
Merge pull request #7079 from SiliconLabs/feature/EFM32GG11-OS5.9 
Add support for EFM32GG11
 2018-07-13 17:33:34 -05:00
Cruz Monrreal cc8651e45c
Merge pull request #7505 from naveenkaje/pushbranch 
Fix linker script for NRF52840/ARM
 2018-07-13 13:30:25 -05:00
Cruz Monrreal 531ee3c5d4
Merge pull request #7461 from 0xc0170/fix_raytac_removal 
Raytac: target removal
 2018-07-13 11:46:58 -05:00
Deepika 2bbe043793 [M2351] Adding missing ENDP for ARM 2018-07-13 10:56:45 -05:00
Cruz Monrreal 1145d6bb3c
Merge pull request #7489 from mirelachirica/wise_1570_hsi_source_clock 
Cellular: HSI set to be source clock for WISE_1570
 2018-07-13 09:12:22 -05:00
jeromecoutant 8a0b83233a STM32 LPTICKER with LPTIM minor update 
Code cleaning (L0 Cube update, comment precision)
 2018-07-13 10:03:31 +02:00
Naveen Kaje ed251020b6 NRF52832 linker script: formatting fix 2018-07-12 15:19:13 -05:00
Naveen Kaje 192eb28814 Fix linker script for NRF52840/ARM 2018-07-12 15:19:13 -05:00
RFulchiero 0198481f8f Improved formatting for preprocessor conditionals. 2018-07-12 13:30:36 -05:00
Marcus Chang 10b90edea3 Fix ITM on NRF52 series 
The ITM must be initialized before the SoftDevice, but due to the
lazy initialization in C++ on (at least) GCC the ITM init call
might happen too late.

This commit moves the initialization code into the NRF52 system
startup file.
 2018-07-12 13:29:24 -05:00
Cruz Monrreal f4c936f455
Merge pull request #7486 from marcuschangarm/fix-nrf52-iar 
Fix linker script for NRF52840/IAR
 2018-07-12 10:09:12 -05:00
Cruz Monrreal 6300d8b5e4
Merge pull request #7487 from marcuschangarm/fix-nrf52-serial 
Allow STDIO pins to be NC in NRF52 series
 2018-07-12 10:05:08 -05:00
bcostm 665de33cc6 stm32 lpuart: enable lse and hsi if not done 2018-07-12 15:58:02 +02:00
ccli8 e61c5146c6 [M2351] Fix binary-compatible across compilers in secure functions 
1. Rename m2351_stddriver_sup.h/c to stddriver_secure.h/.c for naming consistency
2. Add hal_secure.h to include hal-exported secure functions
3. Change return/argument type in secure functions:
   (1) Change int to int32_t
   (2) Change PinName to int32_t
   (3) Change time_t to int64_t
4. Update secure lib/bin accordingly
 2018-07-12 18:01:41 +08:00
ccli8 6bf8e191af [M2351] Support configurable for partitioning flash/SRAM 2018-07-12 18:01:39 +08:00
ccli8 778aa1e766 [M2351] Place default secure binary/library 2018-07-12 18:01:38 +08:00
ccli8 31bf7bf342 [M2351] Fix include file name error on case-sensitive system 2018-07-12 18:01:36 +08:00
ccli8 d350f45b4b [M2351] Synchronize lp_ticker code to us_ticker 
This is to make us_ticker/lp_ticker code consistent.
 2018-07-12 18:01:35 +08:00
ccli8 688029a511 [M2351] Remove special handling for dummy interrupt in lp_ticker 
It is because dummy interrupt is very rare or pending time caused by it
is very short.
 2018-07-12 18:01:34 +08:00
ccli8 124b4ad557 [M2351] Remove NUMAKER_PFM_M2351_S/_NS targets 2018-07-12 18:01:33 +08:00
ccli8 c382e9642e [M2351] Upgrade chip version to B from A 
There is a reset halt issue with PLL in A version.
To switch back to A version for some reason, define NU_CHIP_MAJOR to 1.
 2018-07-12 17:52:10 +08:00
ccli8 c725f188ec [M2351] Change pinout to meet NuMaker-PFM-M2351 V1.1 2018-07-12 17:52:09 +08:00
ccli8 93ee13adbe [M2351] Change secure flash/SRAM to 256KB/32KB as default 
This is to compilant with CMSIS pack.
 2018-07-12 17:52:08 +08:00
ccli8 c3c661da8d [M2351] Change secure/non-secure stack/heap size 
1. Change RTOS-less main stack/RTOS ISR stack size to 2KiB
2. Change secure/non-secure heap size to 16KiB/32KiB for IAR
 2018-07-12 17:52:07 +08:00
ccli8 04f723755b [M2351] Meet new RTC HAL spec (Mbed OS 5.9) 
1. Power down RTC access from CPU domain in rtc_free. After rtc_free, RTC gets
   inaccessible from CPU domain but keeps counting.
2. Fix RTC cannot cross reset cycle.
 2018-07-12 17:52:06 +08:00
ccli8 6729b65236 [M2351] Meet new lp_ticker HAL spec (Mbed OS 5.9) 
1. Add LPTICKER in device_has option of targets.json file.
2. Disable interrupt in lp_ticker_init
3. Add lp_ticker_free
4. Enable interrupt in lp_ticker_set_interrupt/lp_ticker_fire_interrupt
5. Disable interupt in ISR
 2018-07-12 17:52:05 +08:00
ccli8 9cbc8b21ee [M2351] Meet new us_ticker HAL spec (Mbed OS 5.9) 
1. Add USTICKER in device_has option of targets.json file.
2. Disable interrupt in us_ticker_init
3. Add us_ticker_free
4. Enable interrupt in us_ticker_set_interrupt/us_ticker_fire_interrupt
5. Disable interrupt in ISR
 2018-07-12 17:52:03 +08:00
ccli8 de83cb2892 [M2351] Add secure gateway functions SYS_LockReg_S/SYS_UnlockReg_S 2018-07-12 17:52:02 +08:00
ccli8 990665512d [M2351] Add SD pinmap 2018-07-12 17:52:01 +08:00
ccli8 1b9fa07b6f [M2351] Default MBED_TZ_DEFAULT_ACCESS to 1 to control secure SYS/CLK regions from non-secure threads 
To initialize/uninitialize H/W module, we need to control secure SYS/CLK regions through secure functions.
For a new thread to call these secure functions, we need to allocate secure context for it.
 2018-07-12 17:52:00 +08:00
ccli8 89d32227a0 [M2351] Replace __attribute__((cmse_nonsecure_entry)) with compiler agnostic __NONSECURE_ENTRY 2018-07-12 17:51:59 +08:00
ccli8 767e74b1db [M2351] Support TrustZone and bootloader for IAR 2018-07-12 17:51:58 +08:00
ccli8 8f1623f717 [M2351] Add consistency check for CRYPTO/CRPT's secure attribute and TRNG/Mbed TLS H/W 2018-07-12 17:51:55 +08:00
ccli8 2854b57091 [M2351] Remove dead code with '#if 0' in SPI 2018-07-12 17:51:54 +08:00
ccli8 d3c64785c7 [M2351] Add GPIO debounce configuration in targets.json 2018-07-12 17:51:53 +08:00
ccli8 13e1209c83 [M2351] Support PWM out 2018-07-12 17:51:52 +08:00
ccli8 d05ef693ac [M2351] Support analog-in 2018-07-12 17:51:51 +08:00
ccli8 1da430f1e9 [M2351] Support TRNG 
To change TRNG security state, we need to:
1. Change CRPT/CRYPTO bit in NVIC/SCU in partition_M2351.h
2. Add/remove TRNG in device_has list in targets.json to match partition_M2351.h
 2018-07-12 17:51:50 +08:00
ccli8 dd7fd76758 [M2351] Centralize size configuration for secure flash, secure SRAM, NSC, and bootloader 2018-07-12 17:51:48 +08:00
ccli8 ca63abae73 [M2351] Change NSC location 
NSC location has the following requirements:
1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
 2018-07-12 17:51:48 +08:00
ccli8 42aa7fe0c5 [M2351] Upgrade partition format 
Following BSP, this upgrade makes partitioning flash/SRAM clear.
flash_api.c relies on flash partition, so it is updated accordingly.
 2018-07-12 17:51:47 +08:00