Commit Graph

289 Commits (9d1ae521e8fa32f21a8696d25a0c5f8d2dddc6c8)

Author SHA1 Message Date
jeromecoutant a62736bba2 STM32L0: STM32Cube_FW_L0_V1.11.3
https://github.com/STMicroelectronics/STM32CubeL0
2020-10-19 17:42:38 +02:00
jeromecoutant d9cdd31f21 STM32L0: back to updated files 2020-10-19 17:42:38 +02:00
jeromecoutant a519a2fe6b STM32L0: directory restructuration
+ STM32Cube_FW_L0_V1.10.0 original files
+ targets.json update introducing subfamily level
2020-10-19 17:42:38 +02:00
Harrison Mutai 4fad1112e5 Add SPDX license identifier to Arm files
Add license identifier to files which Arm owns the copyright to,
and contain either BSD-3 or Apache-2.0 licenses. This is to address
license errors raised by scancode analysis.
2020-10-15 10:47:27 +01:00
Andrea Gilardoni b99702094c fixing nvic num 2020-09-22 09:46:48 +02:00
Andrea Gilardoni 1d77cfa08b trying to fix startup file 2020-09-16 08:41:41 +02:00
Andrea Gilardoni 303b3c28b6 making some cleaning 2020-09-15 11:25:47 +02:00
Andrea Gilardoni d5adca141b Edit on Toolchain linker files
Previous one were not working, using nucleol073RZ files
2020-09-15 11:13:03 +02:00
Martin Kojtal a17a481c54
Merge pull request #13583 from jeromecoutant/PR_ARDUINO_PIN
STM32: correct few Arduino pins value
2020-09-10 12:38:02 +01:00
Jaeden Amero 612b148fd4 stack: armc: Workaround config passing bug
Workaround a bug where the boot stack size configuration option is not
passed on to armlink, the Arm Compiler's linker. Prefer
MBED_CONF_TARGET_BOOT_STACK_SIZE if present, as this is what the
configuration system should provide. Fall back to MBED_BOOT_STACK_SIZE
if MBED_CONF_TARGET_BOOT_STACK_SIZE is not defined, as in the case of
buggy tools. If both MBED_CONF_TARGET_BOOT_STACK_SIZE and
MBED_BOOT_STACK_SIZE are not defined, then we fall back to a hard-coded
value provided by the linkerscript. See
https://github.com/ARMmbed/mbed-os/issues/13474 for more information.
2020-09-10 10:08:38 +01:00
Jaeden Amero 39e69d328d Use boot stack size from config system
To allow overriding of the boot stack size from the Mbed configuration
system, consistently use MBED_CONF_TARGET_BOOT_STACK_SIZE rather than
MBED_BOOT_STACK_SIZE.

Fixes #10319
2020-09-10 10:08:38 +01:00
jeromecoutant 5bcb02a013 DISCO_L072CZ_LRWAN1: wrong A1/A3/A4/A5 pin values 2020-09-10 10:05:41 +02:00
Andrea Gilardoni 3c39eeb8dd fixing SPDX identifiers in all files 2020-09-01 10:08:41 +02:00
Andrea Gilardoni 15ca58b9c8 fixing small issues 2020-08-31 14:03:49 +02:00
Andrea Gilardoni 23a3ea06cb fixing the remaining parts after the rename 2020-08-28 19:37:53 +02:00
Andrea Gilardoni c62fc559c9 renaming the mcu to stm32l071xx 2020-08-28 19:24:43 +02:00
Andrea Gilardoni 0c0692a3d1 fixing the issues 2020-08-28 19:12:37 +02:00
Andrea Gilardoni a03f5ff4e6 Adding a new target
Adding STM32L071CXCTX as a generic target to be extended.
This addition required to fix some issues on stml0 library
2020-08-28 19:10:41 +02:00
jeromecoutant b57b12cc9f STM32L0 baremetal support 2020-05-18 17:27:42 +02:00
jeromecoutant c96eb2cd0e STM32 rename TOOLCHAIN_ARM_STD into TOOLCHAIN_ARM 2020-05-15 10:41:28 +02:00
jeromecoutant 303752ad84 STM32 remove all TOOLCHAIN_ARM_MICRO 2020-05-15 09:37:40 +02:00
jeromecoutant cda2538bd2 STM32L0 code cleaning 2020-05-14 13:55:32 +02:00
MarceloSalazar 91607fe9cd Remove MTB_MURATA_ABZ target 2020-04-20 16:55:33 +01:00
Martin Kojtal 7fd5119b89
Merge pull request #12341 from fkjagodzinski/fix-stm-hal_fpga
STM32L4: Fix the UART RX & TX data reg bitmasks
2020-02-10 13:21:31 +00:00
jeromecoutant 2368a07244 STM32: Fix the UART RX & TX data reg bitmasks 2020-02-07 16:23:50 +00:00
Alexandre Bourdiol 315220832f TARGET_STM: L0 CUBE SPI async mode send next byte after previous one read
In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.

So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
2020-02-04 13:26:49 +01:00
Qinghao Shi f7d9850fe7 Disable Analogin D13(PA_5) on some NUCLEO targets
- pins are connected to the LED, can't be used as analogin
2020-02-03 11:39:31 +00:00
Rajkumar Kanagaraj 957dca2082 Enabling small C library option and deprecating uARM toolchain
- By default, Mbed OS build tools use standard C library for all supported toolchains.
   It is possible to use smaller C libraries by overriding the "target.default_lib" option
   with "small". This option is only currently supported for the GCC_ARM toolchain.
   This override config option is now extended in the build tool for ARM toolchain.
 - Add configuration option to specify libraries supported for each toolchain per targets.
 - Move __aeabi_assert function from rtos to retarget code so it’s available for bare metal.
 - Use 2 memory region model for ARM toolchain scatter file for the following targets:
   NUCLEO_F207ZG, STM32F411xE, STM32F429xI, NUCLEO_L073RZ, STM32F303xE
 - Add a warning message in the build tools to deprecate uARM toolchain.
 - NewLib-Nano C library is not supporting floating-point and printf with %hhd,%hhu,%hhX,%lld,%llu,%llX
   format specifier so skipping those green tea test cases.
2019-12-19 10:05:11 -08:00
Kevin Bracey fe22bc023e Update HAL CRC API
* Change "is supported" check to be a macro, so it can be done at
  compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
2019-12-02 14:45:37 +02:00
Martin Kojtal 7177d8fefe
Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS
DISCO_H747I: add support of MBED_TICKLESS
2019-11-29 09:48:09 +01:00
Przemyslaw Stekiel b2dad08387 Change explicit pinmap to static pinmap 2019-11-28 08:32:12 +01:00
Przemyslaw Stekiel e3a34a57e1 Move GPIO_AF_NONE from PeripheralPins.h to PinNamesTypes.h 2019-11-28 08:32:10 +01:00
Przemyslaw Stekiel a2320f2e5c NUCLEO_L073RZ: Add explicit pinmap support 2019-11-28 08:32:05 +01:00
Martin Kojtal a1cddbae5f
Merge pull request #11938 from LMESTM/stm32_serial_clear_rxne
STM32: Update and align serial_clear implementations
2019-11-27 16:30:11 +01:00
Alexandre Bourdiol 41b038a028 TARGET_STM: rework hal_sleep management to be compatible with all STM32 families 2019-11-27 14:25:30 +01:00
Martin Kojtal 5f7ecea00b
Revert "MbedCRC and CRC HAL revisions" 2019-11-26 13:45:37 +00:00
Laurent Meunier f20529f9e6 STM32: Update and align serial_clear implementations
Clear RXNE flag by reading the RX register and align this implementation
on all families.
2019-11-25 14:55:32 +01:00
Martin Kojtal fd22997b60
Merge pull request #11559 from kjbracey-arm/crc
MbedCRC and CRC HAL revisions
2019-11-13 18:24:04 +01:00
Kevin Bracey 1f94428a56 Update HAL CRC API
* Change "is supported" check to be a macro, so it can be done at
  compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
2019-11-13 14:31:49 +02:00
Adam Mitchell 6064979303
Correct PB_6/PB_7 Serial AF mapping 2019-11-12 14:16:21 +00:00
Przemyslaw Stekiel ee519e6a5c NUCLEO_F411RE, NUCLEO_L073RZ, NUCLEO_F303RE: Disable Analogin D13(PA_5) pin.
Analogin test fails on D13(PA_5) pin. When logic one (3.3V) is provided on this pin ADC reads 0.86 value. On other pins we got 0.98.
This is caused because this pin is connected to led2.
2019-10-30 14:34:57 +01:00
Martin Kojtal df79609cc5
Merge pull request #11675 from jeromecoutant/PR_USB_STEP1
STM32 USB update step 1
2019-10-28 14:06:15 +01:00
Kevin Bracey fb6aa3ef4f Clean up ARM toolchain heap+stack setup in targets
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.

Looking into this, a number of other issues were highlighted

* Almost all targets had `__initial_sp` hardcoded in assembler,
  rather than getting it from the scatter file. This was behind
  issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
  file layout, in some cases meaning they were overlapping heap
  space. They now all use the area reserved in the scatter file.
  If any problems are seen, then there is an error in the
  scatter file.
* A number of targets were reserving unneeded space for heap and
  stack in their startup assembler, on top of the space reserved in
  the scatter file, so wasting a few K. A couple were using that
  space for the stack, rather than the space in the scatter file.

To clarify expected behaviour:

* Each scatter file contains empty regions `ARM_LIB_HEAP` and
  `ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
  by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
  `ARM_LIB_HEAP` is generally the space left over after static
  RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
  vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
  for the ARM library. The ARM library calls this during startup, and
  it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
  modify SP, so we remain on the boot stack, and the heap is set to
  the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
  exist, then the heap is the space from the end of the used data in
  `RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
  Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
  Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
  itself.
2019-10-23 14:53:49 +03:00
jeromecoutant 01e798fd6a STM32 clock configuration depending on USB 2019-10-21 17:11:59 +02:00
jeromecoutant a54fdf7585 STM32L0 USB pins addition 2019-10-21 17:11:52 +02:00
Laurent Meunier e862438fad Clearing UART TC Flag prevents deep sleep, so do not clear it
The TC flag is used in function serial_is_tx_ongoing to check if there is
an ongoing serial transmission. So this Flag must not be cleared at the
end of the transmission, otherwise, serial_is_tx_ongoing will notify that
TX is ongoing.

The impact is that it may prevent deep sleep to be entered.

Also there is no need to clear this flag at the end of the transaction
because it will be cleared automatically by HW when a new transmission
starts.
2019-10-15 15:59:51 +02:00
jeromecoutant db7efabfd5 STM license file update
Some code have been copied from ST Cube deliveries.
ST copyright is then needed.
2019-09-10 14:24:48 +02:00
Alexandre Bourdiol 7647b39adc TARGET_STM: I2C sequential communication revert PR #3324 to original cube HAL 2019-08-22 10:44:20 +02:00
Martin Kojtal de84004be1
Merge pull request #11189 from LMESTM/pwmout_cpp_guard
__cplusplus guard fixed pwmout_device.h for STM32 families
2019-08-13 11:19:24 +02:00
Laurent Meunier 319223ac16 __cplusplus guard fixed pwmout_device.h for STM32 families
This bug prevented using this header in cpp code directly.
2019-08-09 09:51:39 +02:00