In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.
So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
- By default, Mbed OS build tools use standard C library for all supported toolchains.
It is possible to use smaller C libraries by overriding the "target.default_lib" option
with "small". This option is only currently supported for the GCC_ARM toolchain.
This override config option is now extended in the build tool for ARM toolchain.
- Add configuration option to specify libraries supported for each toolchain per targets.
- Move __aeabi_assert function from rtos to retarget code so it’s available for bare metal.
- Use 2 memory region model for ARM toolchain scatter file for the following targets:
NUCLEO_F207ZG, STM32F411xE, STM32F429xI, NUCLEO_L073RZ, STM32F303xE
- Add a warning message in the build tools to deprecate uARM toolchain.
- NewLib-Nano C library is not supporting floating-point and printf with %hhd,%hhu,%hhX,%lld,%llu,%llX
format specifier so skipping those green tea test cases.
* Change "is supported" check to be a macro, so it can be done at
compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
* Change "is supported" check to be a macro, so it can be done at
compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
Analogin test fails on D13(PA_5) pin. When logic one (3.3V) is provided on this pin ADC reads 0.86 value. On other pins we got 0.98.
This is caused because this pin is connected to led2.
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.
Looking into this, a number of other issues were highlighted
* Almost all targets had `__initial_sp` hardcoded in assembler,
rather than getting it from the scatter file. This was behind
issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
file layout, in some cases meaning they were overlapping heap
space. They now all use the area reserved in the scatter file.
If any problems are seen, then there is an error in the
scatter file.
* A number of targets were reserving unneeded space for heap and
stack in their startup assembler, on top of the space reserved in
the scatter file, so wasting a few K. A couple were using that
space for the stack, rather than the space in the scatter file.
To clarify expected behaviour:
* Each scatter file contains empty regions `ARM_LIB_HEAP` and
`ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
`ARM_LIB_HEAP` is generally the space left over after static
RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
for the ARM library. The ARM library calls this during startup, and
it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
modify SP, so we remain on the boot stack, and the heap is set to
the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
exist, then the heap is the space from the end of the used data in
`RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
itself.
The TC flag is used in function serial_is_tx_ongoing to check if there is
an ongoing serial transmission. So this Flag must not be cleared at the
end of the transmission, otherwise, serial_is_tx_ongoing will notify that
TX is ongoing.
The impact is that it may prevent deep sleep to be entered.
Also there is no need to clear this flag at the end of the transaction
because it will be cleared automatically by HW when a new transmission
starts.
jeromecoutant
MarceloSalazar
Martin Kojtal
Alexandre Bourdiol
Qinghao Shi
Rajkumar Kanagaraj
Kevin Bracey
Przemyslaw Stekiel
Laurent Meunier
Adam Mitchell
Yuan Cao
Vincent Veron
Filip Jagodzinski
Teijo Kinnunen
Sarah Marsh
deepikabhavnani