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mbed-os
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343 Commits (8f2c717c4c7b3a9e923d700469e3cb3bd4600dd2)

Author SHA1 Message Date
ccli8 8f1623f717 [M2351] Add consistency check for CRYPTO/CRPT's secure attribute and TRNG/Mbed TLS H/W 2018-07-12 17:51:55 +08:00
ccli8 2854b57091 [M2351] Remove dead code with '#if 0' in SPI 2018-07-12 17:51:54 +08:00
ccli8 13e1209c83 [M2351] Support PWM out 2018-07-12 17:51:52 +08:00
ccli8 d05ef693ac [M2351] Support analog-in 2018-07-12 17:51:51 +08:00
ccli8 1da430f1e9 [M2351] Support TRNG 
To change TRNG security state, we need to:
1. Change CRPT/CRYPTO bit in NVIC/SCU in partition_M2351.h
2. Add/remove TRNG in device_has list in targets.json to match partition_M2351.h
 2018-07-12 17:51:50 +08:00
ccli8 dd7fd76758 [M2351] Centralize size configuration for secure flash, secure SRAM, NSC, and bootloader 2018-07-12 17:51:48 +08:00
ccli8 ca63abae73 [M2351] Change NSC location 
NSC location has the following requirements:
1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
 2018-07-12 17:51:48 +08:00
ccli8 42aa7fe0c5 [M2351] Upgrade partition format 
Following BSP, this upgrade makes partitioning flash/SRAM clear.
flash_api.c relies on flash partition, so it is updated accordingly.
 2018-07-12 17:51:47 +08:00
ccli8 805049d80f [M2351] Fix page size in flash IAP 
In Mbed OS, page size is program unit, which is different than FMC definition.
After fixing page size, we can pass NVSTORE test (mbed-os-features-nvstore-tests-nvstore-functionality).
 2018-07-12 17:51:45 +08:00
ccli8 711cb64e95 [M2351] Support flash IAP 2018-07-12 17:51:44 +08:00
ccli8 fa0124ed8d [M2351] Add missing delay in lp_ticker 2018-07-12 17:51:43 +08:00
ccli8 06cb070442 [M2351] Trim HIRC48 to 48M against LXT 2018-07-12 17:51:42 +08:00
ccli8 649389a962 [M2351] Support I2C 2018-07-12 17:51:41 +08:00
ccli8 3ca24b62ff [M2351] Support SPI 2018-07-12 17:51:40 +08:00
ccli8 dcfe1d4283 [M2351] Refine UART code 
1. Replace SYS_ResetModule/CLK_SetModuleClock/CLK_EnableModuleClock/CLK_DisableModuleClock with TrustZone-aware versions.
2. Configure all UART to secure
3. Support asynchronous transfer
4. Remove sleep management code, which has been replaced with Sleep Manager.
 2018-07-12 17:51:38 +08:00
ccli8 ebf53b9f64 [M2351] Support PDMA 2018-07-12 17:51:38 +08:00
cyliangtw 999dd332e6 [M2351] Rework us_ticker and lp_ticker 
The rework includes the following:
1. Remove ticker overflow handling because upper layer (mbed_ticker_api.c) has done with it.
   This makes us_ticker/lp_ticker implementation more succinct and avoids potential error.
2. Refine timer register access with low-power clock source
 2018-07-12 17:51:37 +08:00
ccli8 236bf657b6 [M2351] Remove peripheral sleep management from hal_sleep/hal_deepsleep 
The upper layer has introduced Sleep Manager to handle the task.
 2018-07-12 17:51:36 +08:00
ccli8 6bfc90dc73 [M2351] Rework RTC 
The rework includes the following:
1. Support year range beyond H/W RTC 2000~2099.
2. Refine RTC register access with low-power clock source
 2018-07-12 17:51:34 +08:00
ccli8 f16b971482 [M2351] Fix GPIO to be TrustZone-aware 
1. Revise NU_PORT_BASE to be TrustZone-aware
2. Add TrustZone-aware NU_GET_GPIO_PIN_DATA/NU_SET_GPIO_PIN_DATA to replace GPIO_PIN_DATA
3. Revise pin_function to be TrustZone-aware
 2018-07-12 17:51:33 +08:00
ccli8 2aa2b7eb00 [M2351] Fix SystemCoreClockUpdate isn't called in non-secure domain 2018-07-12 17:51:32 +08:00
ccli8 0cb7633356 [M2351] Fix HCLK clock source 
There is a reset halt issue with PLL in A version.
Work around it by using HIRC48 instead of PLL as HCLK clock source.
 2018-07-12 17:51:31 +08:00
ccli8 135f1279ca [M2351] Add secure BSP driver function 
SYS_ResetModule_S
CLK_SetModuleClock_S
CLK_EnableModuleClock_S
CLK_DisableModuleClock_S
 2018-07-12 17:51:30 +08:00
ccli8 d84a90e29d [M2351] Unify secure/non-secure peripheral base based on partition file 2018-07-12 17:51:29 +08:00
ccli8 77e45d414b [M2351] Configure most modules to non-secure 
All modules are configured to non-secure except:
1. TIMER0/1 hard-wired to secure and TIMER2/3 reserved for non-secure.
2. PDMA0 hard-wired to secure and PDMA1 reserved for non-secure.
3. RTC configured to secure and shared to non-secure through NSC.
4. CRYPTO configured to secure and shared to non-secure through NSC.
 2018-07-12 17:51:28 +08:00
ccli8 2da6bf6301 [M2351] Fix STDIO UART 2018-07-12 17:51:27 +08:00
cyliangtw 0c3f0f7cb7 [M2351] To fulfill _rtc_localtime one more argument 2018-07-12 17:51:24 +08:00
cyliangtw 2b44eeaef5 [M2351] Add gpio_is_connected 2018-07-12 17:51:22 +08:00
cyliangtw ef7f04808d [M2351] Set secure SRAM size as 24KB in SAU & SCU 2018-07-12 17:51:21 +08:00
cyliangtw d99fbcb166 [M2351] Set 48KB SRAM and UART0 as non-secure 2018-07-12 17:51:20 +08:00
cyliangtw 12a7830c9a [M2351] Resolve reset halt issue in MP chip A version 2018-07-12 17:51:19 +08:00
cyliangtw 6163628b1e [M2351] Sync IRQ arrangement to fulfill MP version 2018-07-12 17:51:18 +08:00
cyliangtw 331945fa08 [M2351] Remove redundant GetPC 2018-07-12 17:51:17 +08:00
cyliangtw 90fcc04596 [M2351] Migrate for MP chip version, build sucessfully 2018-07-12 17:51:16 +08:00
Deepika 94d95d34a4 [M2351] Support TrustZone in port_read/port_write 2018-07-12 17:51:14 +08:00
Deepika aec7c5441c [M2351] Add non-secure reset handler address 2018-07-12 17:51:13 +08:00
deepikabhavnani eebc6e38cb [M2351] Corrected Vector table address in scatter file 2018-07-12 17:51:12 +08:00
cyliangtw 46f948aa6f [M2351] Link register base with partition file & correct heap size in linker file 2018-07-12 17:51:11 +08:00
cyliangtw 5985dcd268 [M2351] Support secure loader invoke non-secure Mbed OS 2018-07-12 17:51:10 +08:00
deepikabhavnani 2f01120d93 [M2351] Corrected preprocess define usage in toolchain specific linker files 2018-07-12 17:51:09 +08:00
cyliangtw 18ca9b5e6c [M2351] Fix GCC linker file 'cannot move location counter backwards' issue 2018-07-12 17:51:08 +08:00
cyliangtw ba9e5fdc29 [M2351] IAR linker file support both of secure & non-secure domain 2018-07-12 17:51:07 +08:00
cyliangtw f06644a920 [M2351] Linker files support both of secure & non-secure domain 2018-07-12 17:51:06 +08:00
cyliangtw a2aac528f4 [M2351] Update GCC linker for NSC Veneer 2018-07-12 17:51:05 +08:00
Deepika f7ea847dfe [M2351] ARMC6 compiler related changes 2018-07-12 17:51:04 +08:00
Deepika d46220c7e0 [M2351] Set SAU Region present flag for M2351 device and include security header file. 
As per SAU documents, SAU is always present if the security extension is
available. The functionality differs if the SAU contains SAU regions.
If SAU regions are available it is configured with the macro __SAUREGION_PRESENT
 2018-07-12 17:51:02 +08:00
Deepika 11792f60fa [M2351] Added xx_ticker_fire_interrupt function for M2351 device 2018-07-12 17:51:01 +08:00
Deepika ffcc438b5a [M2351] Use Cortex M23 specific header files and interrupts 
1. Update use of correct header files
2. Added missing entry of M2351 device in IAR defines.
3. Removed support of ARM toolchain in targets.json
 2018-07-12 17:51:00 +08:00
cyliangtw e67ed3f86e [M2351] Revise nu_bitutil.h for M23 2018-07-12 17:50:59 +08:00
cyliangtw 6b85478730 [M2351] Modify Nuvoton common files to avoid conflicting with master 2018-07-12 17:50:58 +08:00