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2271 Commits (70c5797a94b105db9fb6adeb29a4315eb82292a5)

Author SHA1 Message Date
jeromecoutant a1570f936f STM32WB : Add ReadMe file 
Help on FW update procedure
 2020-02-20 09:20:44 +01:00
jeromecoutant 9d016022b6 STM32WB clean SetSysClock 2020-02-20 09:20:44 +01:00
jeromecoutant ebae0e56d4 STM32WB align deepsleep functions with CubeFW 2020-02-20 09:20:43 +01:00
Martin Kojtal 9f5ced30dc
Merge pull request #12415 from jeromecoutant/PR_H7README 
STM32H7 : add readme file for dual core use
 2020-02-19 12:52:10 +00:00
jeromecoutant 065a79e48a STM32H7: add README file for dual core use 2020-02-17 16:21:20 +01:00
jeromecoutant d66b39de18 STM32L5 : Add DISCO-L562E support 2020-02-14 17:49:40 +01:00
jeromecoutant f0969022b8 STM32L5 : add QSPI support 2020-02-14 17:49:33 +01:00
Martin Kojtal 7658681a9e
Merge pull request #12409 from LMESTM/Fix_lpuart_deep_sleep 
FIX: LPUART clock source selection should be left to serial driver
 2020-02-13 09:45:41 +00:00
Laurent Meunier 3fd071404e FIX: LPUART clock source selection should be left to serial driver 
The clock source selection of LPUART depends on System clocks but also on
the serial baudrate. There is a specific computation done in serial driver
targets/target_STM/serial_api.c

At first start-up the LPUART1 clock selected in SetSysClock was anyway
overridden by the serial driver, so this was of no effect. But in case
of deep sleep SetSysClock is called again, while the driver isn't, so
SetSyClock was corrupting the serial clock configuration.

So let's remove these few lines of code which are causing trouble.
 2020-02-11 17:14:45 +01:00
Martin Kojtal c1eaf2c358
Merge pull request #12380 from mprse/DISCO_L475VG_IOT01A_add_gpio_pinmap 
DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing
 2020-02-11 11:58:53 +00:00
Martin Kojtal 7fd5119b89
Merge pull request #12341 from fkjagodzinski/fix-stm-hal_fpga 
STM32L4: Fix the UART RX & TX data reg bitmasks
 2020-02-10 13:21:31 +00:00
jeromecoutant 2368a07244 STM32: Fix the UART RX & TX data reg bitmasks 2020-02-07 16:23:50 +00:00
Przemyslaw Stekiel 3a71f86235 DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing 2020-02-07 11:41:32 +01:00
Filip Jagodzinski ae635d5cd4 STM32L4: Fix the UART RX & TX data reg bitmasks 
The existing logic was insufficient to properly handle odd and even
parity setting, e.g. serial_getc() returned 9-bit data for 8O1
transmission format.
 2020-02-06 14:07:51 +01:00
Martin Kojtal 32675cc6ac
Merge pull request #11874 from fkjagodzinski/armc6_build-enable_lto_for_release 
ARMC6: Add a build profile extension with the link-time optimizer enabled
 2020-02-05 14:42:16 +00:00
Martin Kojtal e3ad1cae55
Merge pull request #12334 from AriParkkila/cell-c030-r412m 
Update cellular drivers/tests for UBLOX_C030_R412M
 2020-02-05 12:50:11 +00:00
Martin Kojtal 841b846b46
Merge pull request #12362 from ABOSTM/L0_CUBE_HAL_REWORK_NO_MORE_OVERRUN 
TARGET_STM: L0 CUBE SPI async mode send next byte after previous one is read
 2020-02-05 10:17:13 +00:00
Martin Kojtal cee2a352a7
Merge pull request #12357 from ABOSTM/F103_ADC3_NOT_SUPPORTING_COMMON_SETTINGS 
TARGET_STM32F1: don't set ADC common register when ADC doesn't support it
 2020-02-04 15:24:51 +00:00
Alexandre Bourdiol 315220832f TARGET_STM: L0 CUBE SPI async mode send next byte after previous one read 
In STM32 Cube HAL, in interrupt mode (async),
2 bytes can be prepared in hardware registers without any read
(1 in regular register, the other in shift register),
but Only 1 RX byte can stored in hardware register, specially when there is no hardware FIFO.
If interrupt handling is fast enough, each read is made in parralele of the write.
But if interrupt handling is too long or is interrupted for too long,
it can happen that one read byte is lost (overrun).
For STM32F4, Tickless has been deactivated to avoid such issue.
For STM32L0, we don't want to deactivate tickless,
because those chips are specially design for lowpower.

So instead of removing SPI async mode,
we propose to change the HAL behavior specially for L0:
each byte is send only when previous read is performed.
Thus only 1 RX byte at a time which is saved in hardware register.
This prevent overrun, but it introduceS some latency between each byte send,
this is why it is not applied to all STM32 families.
 2020-02-04 13:26:49 +01:00
Maciej Bocianski 8db3b40a7b STM: change rtc irq handler name 
Fix for the error caused by lto on armc6 compiler:

L6137E: Symbol RTC_IRQHandler was not preserved by the LTO codegen but is needed by the image.

lto optimization cause that local symbol RTC_IRQHandler(from rtc_api.c)
somehow interferes with global symbol RTC_IRQHandler (from startup_stm32f070xb.S)

Changing local RTC_IRQHandler to _RTC_IRQHandler fixes problem
 2020-02-04 12:29:52 +01:00
Martin Kojtal 250e58134f
Merge pull request #12286 from pea-pod/target-nucleo_l452re-p 
Add new target: NUCLEO_L452RE-P
 2020-02-03 16:34:36 +00:00
Alexandre Bourdiol 03b03feb8d TARGET_STM32F1: don't set ADC common register when ADC doesn't support it 
STM32F103ZE: ADC3 doesn't support common settings.
__LL_ADC_COMMON_INSTANCE(ADC3) returns 0
 2020-02-03 15:56:49 +01:00
Martin Kojtal 0f4a9867be
Merge pull request #12332 from jamesbeyond/analogIn_fix 
FIX: Disable Analogin D13(PA_5) on some NUCLEO targets
 2020-02-03 12:44:07 +00:00
Qinghao Shi f7d9850fe7 Disable Analogin D13(PA_5) on some NUCLEO targets 
- pins are connected to the LED, can't be used as analogin
 2020-02-03 11:39:31 +00:00
Martin Kojtal 02c5e0806f
Merge pull request #12350 from maciejbocianski/fix_fpga_i2c_test 
implements i2c_free for STM
 2020-02-03 09:56:59 +00:00
Maciej Bocianski 0b634e54b4 implement i2c_free for STM family 2020-01-31 14:51:54 +01:00
Maciej Bocianski 95996fb924 disable PA_8 i2c pin on NUCLEO_F411RE 
pin PA_8 by default is connected to MCO
 2020-01-31 14:48:00 +01:00
Kevin Bracey ba5dd4d8c1
Merge pull request #12153 from mprse/spi_fpga_test_extend 
Hackathon: Increase coverage of the SPI master FPGA test
 2020-01-31 15:00:02 +02:00
Kevin Bracey 91464b2729
Merge pull request #12306 from jeromecoutant/PR_STM32L5_NUCLEO 
STM32L5: NUCLEO-L552ZE-Q new target
 2020-01-29 16:07:44 +02:00
Ari Parkkila d6f8fece69 Cellular: Enable IP over PPP on UBLOX_C030_R41XM 2020-01-29 03:03:35 -08:00
pea-pod f7c4693747 Add new target: NUCLEO_L452RE-P 2020-01-27 18:41:18 -06:00
Anna Bridge ceaf562a11
Merge pull request #12283 from jeromecoutant/PR_STM32WB 
STM32WB - Update CubeDriver from v1.0.0 to v1.4.0
 2020-01-25 11:54:29 +00:00
jeromecoutant e4d0629d18 STM32L5 : Introduce NUCLEO_L552ZE_Q board 2020-01-23 17:55:07 +01:00
jeromecoutant c1386cf52d STM32L5 : update generic STM files for L5 2020-01-23 17:54:55 +01:00
jeromecoutant bee5d44a1f STM32L5: add API L5 family files 2020-01-23 17:54:52 +01:00
jeromecoutant 5d59c99b99 STM32L5: TOOLCHAIN automatic updates 2020-01-23 17:54:41 +01:00
jeromecoutant 77e5bb45b9 STM32L5: STM32Cube_FW_L5_V1.0.0 files 2020-01-23 13:30:31 +01:00
jeromecoutant 25da13bc18 STM32WB remove extra file 2020-01-23 10:53:09 +01:00
jeromecoutant 9f42a58d5a STM32H7 correct PWMOUT 2020-01-21 16:03:17 +01:00
jeromecoutant 3657f902d3 STM32Cube_FW_WB_V1.4.0 - STM32WB55xx part 2020-01-20 17:24:46 +01:00
jeromecoutant 7a5da6109f STM32Cube_FW_WB_V1.4.0 - STM32WB50xx part 2020-01-20 17:24:46 +01:00
jeromecoutant c39a13d10c STM32Cube_FW_WB_V1.4.0 - template part 2020-01-20 17:24:45 +01:00
jeromecoutant b4f3b0799d STM32Cube_FW_WB_V1.4.0 - STM32_WPAN part 2020-01-20 17:24:45 +01:00
jeromecoutant 08184d7ac9 STM32Cube_FW_WB_V1.4.0 - HAL_DRIVER part 2020-01-20 17:24:44 +01:00
jeromecoutant d6e4b15c1a STM32Cube_FW_WB_V1.4.0 - CMSIS part 2020-01-20 17:24:43 +01:00
jeromecoutant 339846a1bb STM32WB cleanup 
- BLE feature is mandatory
- remove clock source selection
- license alignment
- startup file from Cube delivery
- linker script alignement
 2020-01-20 17:24:28 +01:00
jeromecoutant 8f6171f8b0 STM32WB - BLE restructure 2020-01-20 16:10:55 +01:00
jeromecoutant 8c76a43d3c STM32WB - New directory structure 2020-01-20 16:10:55 +01:00
Martin Kojtal d6e69ef57b
Merge pull request #12208 from hugueskamba/hk-replace-uartserial-st 
ST targets: Replace UARTSerial references with BufferedSerial
 2020-01-17 08:19:09 +00:00
Martin Kojtal 88f48d240e
Merge pull request #12237 from mprse/stm_serial_free_fix 
STM serial free: Set pin function only if pin is defined (not NC)
 2020-01-15 13:02:20 +01:00