By default, FLASH_SIZE should be read from HW.
In case this is not the case, we define it here, as the size of FLASH
that is available to the application running on M4.
the flash is shared and split between cortex-M4 that
runs (mbed-os) application and the cortex-M0+ that
runs the BLE firmware.
The 512K allocated to the application was a
conservative that can now be updated.
With recent up-to-date BLE firmware flashed @ 0x080CB000,
there should be 812K available to application.
But there are boards out there that don't have an up-to-date
firmware, so we're keeping an intermediate, safer,
application size of 768K.
Reimplement atomic code in inline assembly. This can improve
optimisation, and avoids potential architectural problems with using
LDREX/STREX intrinsics.
API further extended:
* Bitwise operations (fetch_and/fetch_or/fetch_xor)
* fetch_add and fetch_sub (like incr/decr, but returning old value -
aligning with C++11)
* compare_exchange_weak
* Explicit memory order specification
* Basic freestanding template overloads for C++
This gives our existing C implementation essentially all the functionality
needed by C++11.
An actual Atomic<T> template based upon these C functions could follow.
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:
1. Fixed size and small sections moved to SRAM2 (32K)
Vectors
Crash data
Remaining section - RW / ZI
2. Large memory space should be used for variable sections
RW/ZI
Heap - (Minimum - 0x12000)
Stack - At bottom
Please note the heap address of the both the banks must not be contigious else
GCC considers it to be single memory bank and does allocation across the banks,
which might result into hard-fault
To have the flexibilty in application; to use any of the section
(data/bss/heap) without updating linker script in every use case,
following decisions are made:
1. Fixed size and small sections moved to SRAM2 (32K)
Vectors
Crash data
Stack
Remaining section - Heap memory
2. Large memory space should be used for variable sections
Data
BSS
Heap - Remaining section
Heap is moved to the end of both sections as GCC allocates till 4K boundary,
if end of heap is not aligned to 4K, that chunk of memory will go unutilized
Internal channels use is enabling ADC "internal path" which needs
to be disabled after measurement.
Same applied here for WB family as was done for others in #10143.
Typically the RTC clock is configured by RTC driver itself.
RNG on the other hand is shared with M0+ core and it is expected that
M4 turns it on at boot time.
Martin Kojtal
Anna Bridge
jeromecoutant
Laurent Meunier
aqin
M. Rahimi
Guillermo Alonso
mudassar-ublox
Lin Gao
Malavika Sajikumar
Kevin Bracey
Juho Eskeli
Deepika
Marcus Chang
Vincent Veron
Cruz Monrreal
Ashok Rao