This commit includes all sections that are just added to the linker
script. These changes are backwards-compatible, meaning that they will
not affect the existing code.
Targets that do not support uVisor will leave those sections empty.
Freescale KSDK2 gpio_object.h pulled in Freescale libraries to inline
some GPIO operations.
The resulting namespace pollution (status_t) doesn't seem to be worth
the function call overhead. Hopefully making the base address array
non-automatic will offset that loss.
mbed TLS requires an entropy source, and this provides support for one through
the K64F RNG.
The macro MBEDTLS_ENTROPY_HARDWARE_ALT also added to target.json to enable use
of the entropy collector by mbed TLS.
Due to directory structure change, modification in e93878078 was made wrong
after rebasing the code.
This reverts commit e938780788 and updates path
to the correct file.
Note:
Current value of TIM_MST->CNT is read in interrupt context only.
This avoids master timer overflow without SlaveCounter update.
Continuation of patch: 07b841b08f
Change-Id: Iab0341847130f86e16500fd85024b6a87525fe14
Added CAN API support for NUCLEO_L476RG target.
"stm32l476xx.h" file was changed to avoid compilation errors.
Change-Id: Ifadf7048f6c72c0311ec915e47ce2190460ede68
Added CAN API support for DISCO_L476VG target.
*stm32l476xx.h* file was changed to avoid compilation errors.
NOTE: MBED_29 or MBED_30 cannot be tested on this platform because CAN pins are
soldered to USB, GYRO and others.
Change-Id: I2e85bd36dc45872b1ab617f072de98164f2c96f8
With this change, the heap section occupy the whole space from the end of
the bss section to the start of the stack section instead of taking a
fixed size in RAM.
This change allows applications to make a more efficient use of the RAM
available and allows application to be compiled if the space between end
of bss and start of stack is less than 2048 bytes.
Following cube update, there has been changes in cube HAL that impact
the serial_api.c layer. The global state has been moved to separate
global/tx and rx states, so we can now differentiate both.
The NRF51 doesn't have a systick. When the MCU doesn't have a systick, the
HAL has to export several functions which will be use by the kernel to
manage the tick:
* os_tick_init provides the initialization function for the alternative
hardware timer.
* os_tick_val returns the current value of the alternative hardware timer.
* os_tick_ovf returns the overflow flag of the alternative hardware timer.
* os_tick_irqack is an interrupt acknowledge function that is called to
confirm the alternative hardware timer interrupt.
The HAL should also call OS_Tick_Handler needs to be called as the
hardware timer interrupt function.
In the case of the NRF51, two RTCs are available:
* RTC0: reserved for soft device
* RTC1: used by us_ticker.
RTC1 is a 4 channels timers, channel 0 is used for us_ticker, and
in this port channel 1 is used for tick generation.
Implementation notes:
* RTC1_IRQHandler: has to be written in assembly otherwise a stack
overflow will occur because the function OS_Tick_Handler never
returns. This function is called when RTC1 channel IRQ is triggered.
* tick generation has been optimised for a tick with a duration of
1000us.
* us_ticker can still be compiled and used without RTX enabled.
More information about alternative timer as RTX Kernel Timer:
https://www.keil.com/pack/doc/CMSIS/RTX/html/_timer_tick.html
The KSDK2 update restricts static data to the first 64K of RAM.
This breaks some applications which require more than 64K of
static data. This patch moves the static data sections
(bss and data) into the second ram region which is 192K.
Changes taken from similar patches here:
https://github.com/ARMmbed/target-kinetis-k64-gcc/pull/5https://github.com/ARMmbed/target-kinetis-k64-gcc/pull/6
Previous layout
---------------
0x1FFF0000 m_data .interrupts_ram
0x1FFF0400 data, bss
0x1FFFFFFF end of bss
0x20000000 m_data_2 start of heap, end of stack
0x2002ffff end of heap, start of stack
New layout
----------
0x1FFF0000 m_data .interrupts_ram
0x1FFF0400 start of unused ram
0x1FFFFFFF end of unused ram
0x20000000 m_data_2 data, bss
0x200XXXXX end of bss
0x200XXXXX+1 start of heap, end of stack
0x2002ffff end of heap, start of stack
When the function spi_master_write is called a transfer will occur
and set the end of queue flag. This disables further SPI transfers
which causes the next SPI transfer to hang forever.
This patch clears the end of queue flag so SPI does not hang after
the first transfer.
Address passed into the mbed I2C API are expected to be 8 bit and
include the read/write flag. KSDK2 expects a 7 bit address without
this flag. This patch shifts the address passed into the KSDK by 1
so it is in the correct format.
On repeated starts the flag to indicate this is not being set
properly. Because of this the transfer fails. This patch
keeps track of the last transfer to determine if a repeated
start should be sent and sets the KSDK flags appropriately.
- Resetting in LPCXpresso IDE did not reset the LCD controller which
sometimes could cause strange behaviour
- The ROM_LAT bit in the MATRIXARB register must be set in order to
prevent a HardFault when debugging
- The change of compiler in LPCXpresso IDE to ARM launchpad GCC5 was
causing build errors due to multiply defined timeval symbol.
- The exporters for LPCXpresso IDE did not set the FPU_PRESENT define
for assembler, only for c/c++. This caused very strange behaviour
in the RTOS code (e.g. timeouts no longer working, context switches
failing etc.)
In repeating start scenarios, there was a bug in the I2C driver for
various NXP LPCxxxx parts which could allow an extra I/O from the
previous operation to leak through. The scenario I encountered which
triggered this bug went like so:
* The higher level application code would first do an I2C write that
doesn't send a stop bit (use repeating start instead.)
* The higher level application code would then issues an I2C read
operation which begin with a call to i2c_start().
* i2c_start() would clear the SI bit (interrupt flag) at the top of
its implementation.
* i2C_start() would then get interrupted right after clearing the SI
bit.
* While the CPU is off running the ISR code, the I2C peripheral
repeats the last byte written to I2CDAT and then sets the SI bit to
indicate that the write has completed.
* The ISR returns to allow the i2c_start() to continue execution.
* i2c_start() would then set the STA bit but it is too late.
* i2c_start() waits for the SI bit to be set but it is already set
because of the completed byte write and not because of the repeated
start as expected.
For me this bug would cause strange interactions between my ISRs and
the code using I2C to read from the MPU-6050 IMU. I would be getting
valid orientation data and then all of a sudden I would start receiving
what looked like random values but I think it was just reading from the
incorrect offset in the device's FIFO.
It appears that atleast one other person has seen this before but it
was never root caused since it required specific timing to reproduce:
https://developer.mbed.org/forum/bugs-suggestions/topic/4254/
This bug can be found in most of the NXP I2C drivers and this commit
contains a fix for them all. I however only have the LPC1768 and
LPC11U24 for testing.
My fix does the following:
* No longer clears the SI bit in the i2c_conclr() call near the
beginning of the i2c_start() function. It was this clear that
previously caused the problem as described above.
* The second part of the fix was to instead clear the SI bit after
the STA (start) bit has been set with the i2c_conset() call.
* The clearing of the SI bit should be skipped if there isn't an
active interrupt when first entering i2c_start(). If you clear
the SI bit when there isn't an active interrupt then the code
is likely to skip over the interrupt for the start bit which was
just sent and then allow the I2C peripheral to start sending the
slave address before it has even been loaded into the I2CDAT
register.
We need to remove *can_api.c* file accordingly to new directory structure.
Without that we can't compile any CAN mBed test.
Change-Id: I3d4f798ad75ec1b4c4a1d7ed877e71b7db6bf60f
This path fixes issue #816.
Current value of TIM_MST->CNT is read in interrupt context only.
This avoids master timer overflow without SlaveCounter update.
Change-Id: I8e2ec02ce7539a4c044c7e3dfe6bedc9fcdf7736
This path fixes issue #816.
Current value of TIM_MST->CNT is read in interrupt context only.
This avoids master timer overflow without SlaveCounter update.
Change-Id: Iaaf7b9eb33aa8d8992e9354ca5e21bf01ec2413d
This path fixes issue #816.
Current value of TIM_MST->CNT is read in interrupt context only.
This avoids master timer overflow without SlaveCounter update.
Change-Id: Ie7a9bfce76990f85caa84264450d053604af33e5
Both STM32F0xx and STM32F1xx are using a 16-bit timer as a internal ticker
but the mBed ticker needs a 32-bit timer implementation, so the upper part
of that 32-bit timer is being calculated in software.
Software bug has been fixed where continous HIGH/LOW voltage levels
could be observerd for 65ms due to 16-bit timer overflow.
Now current value of TIM_MST->CNT is stored in cnt_val and is
updated in interrupt context only. This avoids master timer
overflow without SlaveCounter update.
This fix is only for platforms which already implements a 16-bit timer:
F103RB, F070RB, F030R8
Change-Id: I205c70ce155b373c6593ead93ade9ec38993f7f9
Alessandro Angelino
Vincent Coubard
bcostm
svastm
tomoyuki yamanaka
Russ Butler
jeromecoutant
Martin Kojtal
Kevin Bracey
Simon Butcher
Rohit Grover
Mahesh Mahadevan
Bartosz Szczepanski
Jimmy Brisson
Michel Jaouen
Erwan GOURIOU
Laurent Meunier
Russ Butler
Jerome COUTANT
adustm
Anders Lindvall
Adam Green
Rafal Kula