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[NUCLEO_F070RB] 16-bit timer register update 

This path fixes issue #816.

Current value of TIM_MST->CNT is read in interrupt context only.
This avoids master timer overflow without SlaveCounter update.

Change-Id: Iaaf7b9eb33aa8d8992e9354ca5e21bf01ec2413d
pull/1763/head
Bartosz Szczepanski 2016-05-23 13:19:03 +02:00
parent e938780788
commit 82d82d0b2a
1 changed files with 3 additions and 2 deletions
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5
hal/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/hal_tick.c
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@ -43,6 +43,7 @@ void set_compare(uint16_t count);
extern volatile uint32_t SlaveCounter;
extern volatile uint32_t oc_int_part;
extern volatile uint16_t oc_rem_part;
extern volatile uint16_t cnt_val;
// Used to increment the slave counter
void timer_update_irq_handler(void)
@ -59,7 +60,7 @@ void timer_update_irq_handler(void)
// Used for mbed timeout (channel 1) and HAL tick (channel 2)
void timer_oc_irq_handler(void)
{
uint16_t cval = TIM_MST->CNT;
cnt_val = TIM_MST->CNT;
TimMasterHandle.Instance = TIM_MST;
// Channel 1 for mbed timeout
@ -71,7 +72,7 @@ void timer_oc_irq_handler(void)
} else {
if (oc_int_part > 0) {
set_compare(0xFFFF);
oc_rem_part = cval; // To finish the counter loop the next time
oc_rem_part = cnt_val; // To finish the counter loop the next time
oc_int_part--;
} else {
us_ticker_irq_handler();