mirror of https://github.com/ARMmbed/mbed-os.git
RTOS port for nrf51.
The NRF51 doesn't have a systick. When the MCU doesn't have a systick, the
HAL has to export several functions which will be use by the kernel to
manage the tick:
* os_tick_init provides the initialization function for the alternative
hardware timer.
* os_tick_val returns the current value of the alternative hardware timer.
* os_tick_ovf returns the overflow flag of the alternative hardware timer.
* os_tick_irqack is an interrupt acknowledge function that is called to
confirm the alternative hardware timer interrupt.
The HAL should also call OS_Tick_Handler needs to be called as the
hardware timer interrupt function.
In the case of the NRF51, two RTCs are available:
* RTC0: reserved for soft device
* RTC1: used by us_ticker.
RTC1 is a 4 channels timers, channel 0 is used for us_ticker, and
in this port channel 1 is used for tick generation.
Implementation notes:
* RTC1_IRQHandler: has to be written in assembly otherwise a stack
overflow will occur because the function OS_Tick_Handler never
returns. This function is called when RTC1 channel IRQ is triggered.
* tick generation has been optimised for a tick with a duration of
1000us.
* us_ticker can still be compiled and used without RTX enabled.
More information about alternative timer as RTX Kernel Timer:
https://www.keil.com/pack/doc/CMSIS/RTX/html/_timer_tick.html
pull/1854/head
Vincent Coubard
parent
b32f7a9aaf
commit
000e04d768
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@ -55,6 +55,34 @@ static bool us_ticker_inited = false;
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static volatile uint32_t overflowCount; /**< The number of times the 24-bit RTC counter has overflowed. */
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static volatile bool us_ticker_callbackPending = false;
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static uint32_t us_ticker_callbackTimestamp;
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static bool os_tick_started = false; /**< flag indicating if the os_tick has started */
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/**
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* The value previously set in the capture compare register of channel 1
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*/
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static uint32_t previous_tick_cc_value = 0;
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/*
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RTX provide the following definitions which are used by the tick code:
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* os_trv: The number (minus 1) of clock cycle between two tick.
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* os_clockrate: Time duration between two ticks (in us).
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* OS_Tick_Handler: The function which handle a tick event.
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This function is special because it never returns.
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Those definitions are used by the code which handle the os tick.
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To allow compilation of us_ticker programs without RTOS, those symbols are
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exported from this module as weak ones.
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*/
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#if defined (__CC_ARM) /* ARMCC Compiler */
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__attribute__((weak)) uint32_t const os_trv;
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__attribute__((weak)) uint32_t const os_clockrate;
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__attribute__((weak)) void OS_Tick_Handler() { }
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#elif defined (__GNUC__) /* GNU Compiler */
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__attribute__((weak)) uint32_t const os_trv = 31;
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__attribute__((weak)) uint32_t const os_clockrate = 1000;
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__attribute__((noreturn, naked, weak)) void OS_Tick_Handler() { }
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#else
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#error Compiler not supported.
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#error Weak definitions of os_trv, os_clockrate and OS_Tick_Handler should be provided.
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#endif
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static inline void rtc1_enableCompareInterrupt(void)
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{
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@ -110,15 +138,22 @@ static void rtc1_start()
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*/
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void rtc1_stop(void)
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{
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NVIC_DisableIRQ(RTC1_IRQn);
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rtc1_disableCompareInterrupt();
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rtc1_disableOverflowInterrupt();
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// If the os tick has been started, RTC1 shouldn't be stopped
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// In that case, us ticker and overflow interrupt are disabled.
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if (os_tick_started) {
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rtc1_disableCompareInterrupt();
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rtc1_disableOverflowInterrupt();
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} else {
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NVIC_DisableIRQ(RTC1_IRQn);
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rtc1_disableCompareInterrupt();
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rtc1_disableOverflowInterrupt();
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NRF_RTC1->TASKS_STOP = 1;
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nrf_delay_us(MAX_RTC_TASKS_DELAY);
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NRF_RTC1->TASKS_STOP = 1;
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nrf_delay_us(MAX_RTC_TASKS_DELAY);
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NRF_RTC1->TASKS_CLEAR = 1;
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nrf_delay_us(MAX_RTC_TASKS_DELAY);
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NRF_RTC1->TASKS_CLEAR = 1;
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nrf_delay_us(MAX_RTC_TASKS_DELAY);
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}
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}
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/**
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@ -148,11 +183,11 @@ static inline uint32_t rtc1_getCounter(void)
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}
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/**
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* @brief Function for handling the RTC1 interrupt.
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* @brief Function for handling the RTC1 interrupt for us ticker (capture compare channel 0 and overflow).
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*
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* @details Checks for timeouts, and executes timeout handlers for expired timers.
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*/
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void RTC1_IRQHandler(void)
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void us_ticker_handler(void)
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{
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if (NRF_RTC1->EVENTS_OVRFLW) {
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overflowCount++;
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@ -271,3 +306,305 @@ void us_ticker_clear_interrupt(void)
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NRF_RTC1->EVENTS_OVRFLW = 0;
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NRF_RTC1->EVENTS_COMPARE[0] = 0;
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}
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#if defined (__CC_ARM) /* ARMCC Compiler */
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__asm void RTC1_IRQHandler(void)
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{
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IMPORT OS_Tick_Handler
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IMPORT us_ticker_handler
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/**
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* Chanel 1 of RTC1 is used by RTX as a systick.
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* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
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* Otherwise, just execute us_ticker_handler.
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* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
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* will never return.
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* A c function would put lr on the stack before calling OS_Tick_Handler and this value
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* would never been dequeued.
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*
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* \code
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* void RTC1_IRQHandler(void) {
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if(NRF_RTC1->EVENTS_COMPARE[1]) {
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// never return...
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OS_Tick_Handler();
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} else {
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us_ticker_handler();
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}
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}
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* \endcode
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*/
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ldr r0,=0x40011144
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ldr r1, [r0, #0]
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cmp r1, #0
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beq US_TICKER_HANDLER
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bl OS_Tick_Handler
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US_TICKER_HANDLER
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push {r3, lr}
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bl us_ticker_handler
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pop {r3, pc}
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nop /* padding */
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}
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#elif defined (__GNUC__) /* GNU Compiler */
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__attribute__((naked)) void RTC1_IRQHandler(void)
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{
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/**
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* Chanel 1 of RTC1 is used by RTX as a systick.
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* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
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* Otherwise, just execute us_ticker_handler.
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* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
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* will never return.
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* A c function would put lr on the stack before calling OS_Tick_Handler and this value
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* would never been dequeued.
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*
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* \code
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* void RTC1_IRQHandler(void) {
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if(NRF_RTC1->EVENTS_COMPARE[1]) {
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// never return...
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OS_Tick_Handler();
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} else {
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us_ticker_handler();
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}
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}
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* \endcode
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*/
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__asm__ (
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"ldr r0,=0x40011144\n"
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"ldr r1, [r0, #0]\n"
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"cmp r1, #0\n"
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"beq US_TICKER_HANDLER\n"
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"bl OS_Tick_Handler\n"
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"US_TICKER_HANDLER:\n"
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"push {r3, lr}\n"
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"bl us_ticker_handler\n"
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"pop {r3, pc}\n"
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"nop"
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);
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}
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#else
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#error Compiler not supported.
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#error Provide a definition of RTC1_IRQHandler.
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/*
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* Chanel 1 of RTC1 is used by RTX as a systick.
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* If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
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* Otherwise, just execute us_ticker_handler.
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* This function has to be written in assembly and tagged as naked because OS_Tick_Handler
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* will never return.
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* A c function would put lr on the stack before calling OS_Tick_Handler and this value
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* will never been dequeued. After a certain time a stack overflow will happen.
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*
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* \code
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* void RTC1_IRQHandler(void) {
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if(NRF_RTC1->EVENTS_COMPARE[1]) {
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// never return...
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OS_Tick_Handler();
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} else {
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us_ticker_handler();
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}
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}
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* \endcode
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*/
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#endif
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/**
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* Return the next number of clock cycle needed for the next tick.
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* @note This function has been carrefuly optimized for a systick occuring every 1000us.
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*/
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static uint32_t get_next_tick_cc_delta() {
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uint32_t delta = 0;
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if (os_clockrate != 1000) {
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// In RTX, by default SYSTICK is is used.
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// A tick event is generated every os_trv + 1 clock cycles of the system timer.
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delta = os_trv + 1;
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} else {
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// If the clockrate is set to 1000us then 1000 tick should happen every second.
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// Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
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// If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
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// generated in 32000 clock cycle instead of 32768 clock cycles.
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// As a result, if a user schedule an OS timer to start in 100s, the timer will start
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// instead after 97.656s
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// The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
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// clock cycles.
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// The strategy is simple, for 1000 ticks:
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// * 768 ticks will occur 33 clock cycles after the previous tick
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// * 232 ticks will occur 32 clock cycles after the previous tick
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// By default every delta is equal to 33.
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// Every five ticks (20%, 200 delta in one second), the delta is equal to 32
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// The remaining (32) deltas equal to 32 are distributed using primes numbers.
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static uint32_t counter = 0;
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if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
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delta = 32;
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} else {
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delta = 33;
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}
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++counter;
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if (counter == 1000) {
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counter = 0;
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}
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}
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return delta;
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}
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static inline void clear_tick_interrupt() {
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NRF_RTC1->EVENTS_COMPARE[1] = 0;
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NRF_RTC1->EVTENCLR = (1 << 17);
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}
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/**
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* Indicate if a value is included in a range which can be wrapped.
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* @param begin start of the range
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* @param end end of the range
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* @param val value to check
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* @return true if the value is included in the range and false otherwise.
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*/
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static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) {
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// regular case, begin < end
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// return true if begin <= val < end
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if (begin < end) {
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if (begin <= val && val < end) {
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return false;
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} else {
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return true;
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}
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} else {
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// In this case end < begin because it has wrap around the limits
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// return false if end < val < begin
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if (end < val && val < begin) {
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return false;
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} else {
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return true;
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}
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}
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}
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/**
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* Register the next tick.
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*/
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static void register_next_tick() {
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previous_tick_cc_value = NRF_RTC1->CC[1];
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uint32_t delta = get_next_tick_cc_delta();
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uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
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// Disable irq directly for few cycles,
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// Validation of the new CC value against the COUNTER,
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// Setting the new CC value and enabling CC IRQ should be an atomic operation
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// Otherwise, there is a possibility to set an invalid CC value because
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// the RTC1 keeps running.
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// This code is very short 20-38 cycles in the worst case, it shouldn't
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// disturb softdevice.
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__disable_irq();
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uint32_t current_counter = NRF_RTC1->COUNTER;
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// If an overflow occur, set the next tick in COUNTER + delta clock cycles
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if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter) == false) {
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new_compare_value = current_counter + delta;
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}
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NRF_RTC1->CC[1] = new_compare_value;
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// set the interrupt of CC channel 1 and reenable IRQs
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NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE1_Msk;
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__enable_irq();
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}
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/**
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* Initialize alternative hardware timer as RTX kernel timer
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* This function is directly called by RTX.
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* @note this function shouldn't be called directly.
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* @return IRQ number of the alternative hardware timer
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*/
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int os_tick_init (void)
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{
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NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
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NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
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NRF_CLOCK->TASKS_LFCLKSTART = 1;
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while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
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// wait for the low frequency clock start
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}
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NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */
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NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI);
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NVIC_ClearPendingIRQ(RTC1_IRQn);
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NVIC_EnableIRQ(RTC1_IRQn);
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NRF_RTC1->TASKS_START = 1;
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nrf_delay_us(MAX_RTC_TASKS_DELAY);
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NRF_RTC1->CC[1] = 0;
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clear_tick_interrupt();
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register_next_tick();
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os_tick_started = true;
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return RTC1_IRQn;
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}
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/**
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* Acknowledge the tick interrupt.
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* This function is called by the function OS_Tick_Handler of RTX.
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* @note this function shouldn't be called directly.
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*/
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void os_tick_irqack(void)
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{
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clear_tick_interrupt();
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register_next_tick();
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}
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/**
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* Returns the overflow flag of the alternative hardware timer.
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* @note This function is exposed by RTX kernel.
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* @return 1 if the timer has overflowed and 0 otherwise.
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*/
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uint32_t os_tick_ovf(void) {
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uint32_t current_counter = NRF_RTC1->COUNTER;
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uint32_t next_tick_cc_value = NRF_RTC1->CC[1];
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return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
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}
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/**
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* Return the value of the alternative hardware timer.
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* @note The documentation is not very clear about what is expected as a result,
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* is it an ascending counter, a descending one ?
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* None of this is specified.
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* The default systick is a descending counter and this function return values in
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* descending order, even if the internal counter used is an ascending one.
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* @return the value of the alternative hardware timer.
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*/
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uint32_t os_tick_val(void) {
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uint32_t current_counter = NRF_RTC1->COUNTER;
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uint32_t next_tick_cc_value = NRF_RTC1->CC[1];
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// do not use os_tick_ovf because its counter value can be different
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if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
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if (next_tick_cc_value > previous_tick_cc_value) {
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return next_tick_cc_value - current_counter;
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} else if(current_counter <= next_tick_cc_value) {
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return next_tick_cc_value - current_counter;
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} else {
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return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
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}
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} else {
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// use (os_trv + 1) has the base step, can be totally inacurate ...
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uint32_t clock_cycles_by_tick = os_trv + 1;
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// if current counter has wrap arround, add the limit to it.
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if (current_counter < next_tick_cc_value) {
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current_counter = current_counter + MAX_RTC_COUNTER_VAL;
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}
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return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
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}
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return 0;
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}
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|
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@ -178,7 +178,7 @@ osMessageQId osMessageQId_osTimerMessageQ;
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#endif
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/* Legacy RTX User Timers not used */
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uint32_t os_tmr = 0U;
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uint32_t os_tmr = 0U;
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uint32_t const *m_tmr = NULL;
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uint16_t const mp_tmr_size = 0U;
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@ -420,6 +420,11 @@ osThreadDef_t os_thread_def_main = {(os_pthread)pre_main, osPriorityNormal, 1U,
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#elif defined(TARGET_STM32L152RC)
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#define INITIAL_SP (0x20008000UL)
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#elif defined(TARGET_MCU_NORDIC_32K)
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#define INITIAL_SP (0x20008000UL)
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#elif defined(TARGET_MCU_NORDIC_16K)
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#define INITIAL_SP (0x20004000UL)
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#else
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#error "no target defined"
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|
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@ -57,7 +57,7 @@
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|| defined(TARGET_LPC812) || defined(TARGET_KL25Z) || defined(TARGET_KL26Z) || defined(TARGET_KL27Z) || defined(TARGET_KL05Z) || defined(TARGET_STM32F100RB) || defined(TARGET_STM32F051R8) \
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|| defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \
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|| defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
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|| defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
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|| defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB) || defined(TARGET_MCU_NRF51822)
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# define OS_TASKCNT 6
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# else
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# error "no target defined"
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@ -91,7 +91,7 @@
|
|||
|| defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
|
||||
|| defined(TARGET_SSCI824) || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB)
|
||||
# define OS_MAINSTKSIZE 128
|
||||
# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ)
|
||||
# elif defined(TARGET_STM32F334R8) || defined(TARGET_STM32F303RE) || defined(TARGET_STM32F303K8) || defined(TARGET_STM32F334C8) || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) || defined(TARGET_MCU_NRF51822)
|
||||
# define OS_MAINSTKSIZE 112
|
||||
# else
|
||||
# error "no target defined"
|
||||
|
|
@ -105,7 +105,7 @@
|
|||
#ifndef OS_PRIVCNT
|
||||
#define OS_PRIVCNT 0
|
||||
#endif
|
||||
|
||||
|
||||
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
|
||||
// <i> Defines the combined stack size for threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
|
|
@ -120,16 +120,16 @@
|
|||
#ifndef OS_STKCHECK
|
||||
#define OS_STKCHECK 1
|
||||
#endif
|
||||
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
|
||||
// <i> Enabling this option increases significantly the execution time of osThreadCreate.
|
||||
#ifndef OS_STKINIT
|
||||
#define OS_STKINIT 0
|
||||
#endif
|
||||
|
||||
// <o>Processor mode for thread execution
|
||||
// <0=> Unprivileged mode
|
||||
|
||||
// <o>Processor mode for thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Privileged mode
|
||||
#ifndef OS_RUNPRIV
|
||||
|
|
@ -137,19 +137,23 @@
|
|||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
|
||||
// <h>RTX Kernel Timer Tick Configuration
|
||||
// ======================================
|
||||
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
|
||||
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
|
||||
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
|
||||
// <i> as time-base for RTX.
|
||||
#ifndef OS_SYSTICK
|
||||
#define OS_SYSTICK 1
|
||||
# if defined(TARGET_MCU_NRF51822)
|
||||
# define OS_SYSTICK 0
|
||||
# else
|
||||
# define OS_SYSTICK 1
|
||||
# endif
|
||||
#endif
|
||||
//
|
||||
// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
|
||||
// <i> Defines the input frequency of the RTOS Kernel Timer.
|
||||
// <i> When the Cortex-M SysTick timer is used, the input clock
|
||||
// <i> Defines the input frequency of the RTOS Kernel Timer.
|
||||
// <i> When the Cortex-M SysTick timer is used, the input clock
|
||||
// <i> is on most systems identical with the core clock.
|
||||
#ifndef OS_CLOCK
|
||||
# if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_TEENSY3_1)
|
||||
|
|
@ -240,11 +244,14 @@
|
|||
#elif defined(TARGET_STM32L152RC)
|
||||
# define OS_CLOCK 24000000
|
||||
|
||||
#elif defined(TARGET_MCU_NRF51822)
|
||||
# define OS_CLOCK 32768
|
||||
|
||||
# else
|
||||
# error "no target defined"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
||||
// <o>RTX Timer tick interval value [us] <1-1000000>
|
||||
// <i> The RTX Timer tick interval value is used to calculate timeout values.
|
||||
// <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
|
||||
|
|
@ -292,14 +299,14 @@
|
|||
#ifndef OS_TIMERPRIO
|
||||
#define OS_TIMERPRIO 5
|
||||
#endif
|
||||
|
||||
|
||||
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_TIMERSTKSZ
|
||||
#define OS_TIMERSTKSZ 200
|
||||
#endif
|
||||
|
||||
|
||||
// <o>Timer Callback Queue size <1-32>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> Default: 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue