Stack should be 8 byte aligned on ARM.
Fix the automatic correction of the alignment in rt_init_stack,
and make sure that all stacks are aligned by the compiler.
Decreasing OS_SCHEDULERSTKSIZE to 112 bytes solves the problem of the
failed test RTOS_3 (Semaphore resource lock).
The test itself was successfull but the final printf failed.
With the reduced stacksize now every test is OK.
There exists an inconsistency between official STM schematic of Nucleo
boards and the existing hardware. Each board should have an 8MHz
external clock source. That is not the case. At some boards the solder
jumper is existing and with that the external clock source. At some
other boards the solder jumper is not available. The Nucleo_F302 should
run with 72MHz but that is only possible with an external clock source.
Because of a missing solder jumper it runs only with the internal clock
source, and that's why only with 64MHz.
In case of off-line compiler, there is no problem about the frequency setting processing.
But in case of online compiler, the frequency setting processing will be error.
So, modify frequency setting processing of SPI to pass in online compiler.
Issue originally reported on mbed site here:
https://developer.mbed.org/questions/5695/FRDM-KL05z-hardfault-when-compiled-with-/
The RAM base address was incorrectly set to the beginning of RAM
instead of at a 0xC0 byte offset to reserve room for the interrupt
vectors. Without this fix, the global variables and the interrupt
vectors were occupying the same space in RAM once the user enabled the
timer interrupt.
The user who originally reported the issue on the mbed site has tested
this fix and verified that it corrected the hard fault issue that they
were encountering.
- Change default setting of CMSIS-RTOS RTX for Cortex-A9 to align with Cortex-M.
- Change the interrupt priority of Ether driver to align with other drivers.
Changes as below.
-I2C
Change communication wait time and Frequency accuracy improvement of I2C.
- Frequency accuracy improvement
- Changed the wait time between one communication completed and the next communication start.
The wait time will be Low clock width by this changing.
-PWM
Modify processing of pulsewidth() of PWM
- Modify processing of pulsewidth() to match the specifications of the RZ_A1H.
-SPI
Fixed a bug that SPI driver is not able to communicate when transfer bit length is 16bit or 32bit.
- Frequency accuracy improvement
- Modify transfer processing when transfer bit length is 16bit or 32bit.
-Serial
Change the reference register macro of Serial
- Change the reference register macro to align with other driver codes.
ohagendorf
Per Kristian Gjermshus
Martin Kojtal
Olivier Martin
albert361
Masao Hamanaka
Toyomasa Watarai
Adam Green
GustavWi
bcostm
Martin Olejar
mazgch
Yihui Xiong