- default value is the same as before patch
- system_stm32l4xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- nvic_addr.h file is now in TARGET_STM level
- default value is the same as before patch
- system_stm32l1xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32l0xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f7xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f3xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f2xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f1xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
- default value is the same as before patch
- system_stm32f0xx.c file is copied to family level with all other ST cube files
- specific clock configuration is now in a new file: system_clock.c (target level)
The FlashIAP is supposed to have access to the full application
memory, so the address scope has been changed to encompass
the entire external flash.
The address translation has also been changed to reflect the memory
layout in the documentation:
Realtek Ameba1 Memory Layout: 5.1 Flash Memory
TXE indicates that a byte can be written to UART register for sending,
while TC indicates that last byte was completely sent. So the TXE flag
can be used in case of interrupt based Serial communication, to allow
faster and efficient application buffer emptying.
Also TXE flag will be erased from the interrupt when writing to register.
In case there is nothing to write in the register, the application is
expected to disable the interrupt.
The RXNE flag is getting cleared when reading Data Register so it should
not be cleared here. Especially in case of high data rate, another byte of
data could have received during irq_handler call and clearing the flag
would read and discard this data which would be lost for application.
Martin Kojtal
Jimmy Brisson
Deepika
jeromecoutant
Mahadevan Mahesh
Russ Butler
Marcus Chang
adustm
Laurent MEUNIER
Yuguo Zou