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3378 Commits (a070e350ecd92a65e102aed05ac4f87edd026161)

Author SHA1 Message Date
ccli8 fa0124ed8d [M2351] Add missing delay in lp_ticker 2018-07-12 17:51:43 +08:00
ccli8 06cb070442 [M2351] Trim HIRC48 to 48M against LXT 2018-07-12 17:51:42 +08:00
ccli8 649389a962 [M2351] Support I2C 2018-07-12 17:51:41 +08:00
ccli8 3ca24b62ff [M2351] Support SPI 2018-07-12 17:51:40 +08:00
ccli8 dcfe1d4283 [M2351] Refine UART code 
1. Replace SYS_ResetModule/CLK_SetModuleClock/CLK_EnableModuleClock/CLK_DisableModuleClock with TrustZone-aware versions.
2. Configure all UART to secure
3. Support asynchronous transfer
4. Remove sleep management code, which has been replaced with Sleep Manager.
 2018-07-12 17:51:38 +08:00
ccli8 ebf53b9f64 [M2351] Support PDMA 2018-07-12 17:51:38 +08:00
cyliangtw 999dd332e6 [M2351] Rework us_ticker and lp_ticker 
The rework includes the following:
1. Remove ticker overflow handling because upper layer (mbed_ticker_api.c) has done with it.
   This makes us_ticker/lp_ticker implementation more succinct and avoids potential error.
2. Refine timer register access with low-power clock source
 2018-07-12 17:51:37 +08:00
ccli8 236bf657b6 [M2351] Remove peripheral sleep management from hal_sleep/hal_deepsleep 
The upper layer has introduced Sleep Manager to handle the task.
 2018-07-12 17:51:36 +08:00
ccli8 6bfc90dc73 [M2351] Rework RTC 
The rework includes the following:
1. Support year range beyond H/W RTC 2000~2099.
2. Refine RTC register access with low-power clock source
 2018-07-12 17:51:34 +08:00
ccli8 f16b971482 [M2351] Fix GPIO to be TrustZone-aware 
1. Revise NU_PORT_BASE to be TrustZone-aware
2. Add TrustZone-aware NU_GET_GPIO_PIN_DATA/NU_SET_GPIO_PIN_DATA to replace GPIO_PIN_DATA
3. Revise pin_function to be TrustZone-aware
 2018-07-12 17:51:33 +08:00
ccli8 2aa2b7eb00 [M2351] Fix SystemCoreClockUpdate isn't called in non-secure domain 2018-07-12 17:51:32 +08:00
ccli8 0cb7633356 [M2351] Fix HCLK clock source 
There is a reset halt issue with PLL in A version.
Work around it by using HIRC48 instead of PLL as HCLK clock source.
 2018-07-12 17:51:31 +08:00
ccli8 135f1279ca [M2351] Add secure BSP driver function 
SYS_ResetModule_S
CLK_SetModuleClock_S
CLK_EnableModuleClock_S
CLK_DisableModuleClock_S
 2018-07-12 17:51:30 +08:00
ccli8 d84a90e29d [M2351] Unify secure/non-secure peripheral base based on partition file 2018-07-12 17:51:29 +08:00
ccli8 77e45d414b [M2351] Configure most modules to non-secure 
All modules are configured to non-secure except:
1. TIMER0/1 hard-wired to secure and TIMER2/3 reserved for non-secure.
2. PDMA0 hard-wired to secure and PDMA1 reserved for non-secure.
3. RTC configured to secure and shared to non-secure through NSC.
4. CRYPTO configured to secure and shared to non-secure through NSC.
 2018-07-12 17:51:28 +08:00
ccli8 2da6bf6301 [M2351] Fix STDIO UART 2018-07-12 17:51:27 +08:00
ccli8 a3846932a6 [M2351] Fix target configuration 
1. NUMAKER_PFM_M2351 defaults to non-secure
2. Add NUMAKER_PFM_M2351_S/NUMAKER_PFM_M2351_NS which are for secure/non-secure build respectively.
3. Change output format to Intel HEX
4. Fix device name to M2351KIAAEES from M2351K1AAEES
5. Add detect_code
 2018-07-12 17:51:25 +08:00
cyliangtw 0c3f0f7cb7 [M2351] To fulfill _rtc_localtime one more argument 2018-07-12 17:51:24 +08:00
deepikabhavnani 21de229047 [M2351] Disabled fault handler support 2018-07-12 17:51:23 +08:00
cyliangtw 2b44eeaef5 [M2351] Add gpio_is_connected 2018-07-12 17:51:22 +08:00
cyliangtw ef7f04808d [M2351] Set secure SRAM size as 24KB in SAU & SCU 2018-07-12 17:51:21 +08:00
cyliangtw d99fbcb166 [M2351] Set 48KB SRAM and UART0 as non-secure 2018-07-12 17:51:20 +08:00
cyliangtw 12a7830c9a [M2351] Resolve reset halt issue in MP chip A version 2018-07-12 17:51:19 +08:00
cyliangtw 6163628b1e [M2351] Sync IRQ arrangement to fulfill MP version 2018-07-12 17:51:18 +08:00
cyliangtw 331945fa08 [M2351] Remove redundant GetPC 2018-07-12 17:51:17 +08:00
cyliangtw 90fcc04596 [M2351] Migrate for MP chip version, build sucessfully 2018-07-12 17:51:16 +08:00
Deepika 94d95d34a4 [M2351] Support TrustZone in port_read/port_write 2018-07-12 17:51:14 +08:00
Deepika aec7c5441c [M2351] Add non-secure reset handler address 2018-07-12 17:51:13 +08:00
deepikabhavnani eebc6e38cb [M2351] Corrected Vector table address in scatter file 2018-07-12 17:51:12 +08:00
cyliangtw 46f948aa6f [M2351] Link register base with partition file & correct heap size in linker file 2018-07-12 17:51:11 +08:00
cyliangtw 5985dcd268 [M2351] Support secure loader invoke non-secure Mbed OS 2018-07-12 17:51:10 +08:00
deepikabhavnani 2f01120d93 [M2351] Corrected preprocess define usage in toolchain specific linker files 2018-07-12 17:51:09 +08:00
cyliangtw 18ca9b5e6c [M2351] Fix GCC linker file 'cannot move location counter backwards' issue 2018-07-12 17:51:08 +08:00
cyliangtw ba9e5fdc29 [M2351] IAR linker file support both of secure & non-secure domain 2018-07-12 17:51:07 +08:00
cyliangtw f06644a920 [M2351] Linker files support both of secure & non-secure domain 2018-07-12 17:51:06 +08:00
cyliangtw a2aac528f4 [M2351] Update GCC linker for NSC Veneer 2018-07-12 17:51:05 +08:00
Deepika f7ea847dfe [M2351] ARMC6 compiler related changes 2018-07-12 17:51:04 +08:00
Deepika 1117e84d9e [M2351] Removed device name, till device patch is added to IAR/Keil 2018-07-12 17:51:03 +08:00
Deepika d46220c7e0 [M2351] Set SAU Region present flag for M2351 device and include security header file. 
As per SAU documents, SAU is always present if the security extension is
available. The functionality differs if the SAU contains SAU regions.
If SAU regions are available it is configured with the macro __SAUREGION_PRESENT
 2018-07-12 17:51:02 +08:00
Deepika 11792f60fa [M2351] Added xx_ticker_fire_interrupt function for M2351 device 2018-07-12 17:51:01 +08:00
Deepika ffcc438b5a [M2351] Use Cortex M23 specific header files and interrupts 
1. Update use of correct header files
2. Added missing entry of M2351 device in IAR defines.
3. Removed support of ARM toolchain in targets.json
 2018-07-12 17:51:00 +08:00
cyliangtw e67ed3f86e [M2351] Revise nu_bitutil.h for M23 2018-07-12 17:50:59 +08:00
cyliangtw 6b85478730 [M2351] Modify Nuvoton common files to avoid conflicting with master 2018-07-12 17:50:58 +08:00
cyliangtw 98c8427a90 [M2351] Add partition header file for CMSE feature 2018-07-12 17:50:57 +08:00
cyliangtw 368f8eef93 [M2351] Remove mbed_sdk_init_forced 
1. mbed_sdk_init is called before C++ global obj constructor in OS 5
2. Refine startup file with GCC_ARM toolchain related to this modification.
 2018-07-12 17:50:56 +08:00
cyliangtw 06910bdea5 [M2351] remove progen, not used any more 2018-07-12 17:50:55 +08:00
cyliangtw c5494eb751 [M2351] Support __vector_table instead of __vector_handlers in IAR 2018-07-12 17:50:54 +08:00
cyliangtw 1f27546480 [M2351] Support GCC & IAR toolchain 2018-07-12 17:50:53 +08:00
cyliangtw dcdd9fb56e [M2351] Sync SDH_CardDetection type to avoid GCC compiler error 2018-07-12 17:50:52 +08:00
cyliangtw 205f8dbab2 [M2351] Add one new target M2351, regard as M0+ with some V8M CPU control at first 2018-07-12 17:50:51 +08:00
Mirela Chirica 72aabc9db4 Cellular: HSI set to be source clock for WISE_1570 2018-07-12 10:12:15 +03:00
Cruz Monrreal e1df16e843
Merge pull request #7365 from jeromecoutant/PR_RTC_SHADOW 
STM32 RTC : bypass shadow registers
 2018-07-11 21:29:02 -05:00
Cruz Monrreal 19c6f3b316
Merge pull request #7290 from bcostm/refactor_us_ticker 
STM32: Refactor us_ticker files
 2018-07-11 21:28:32 -05:00
Marcus Chang fd088d2c4e Allow STDIO pins to be NC in NRF52 series 
Prevent ASSERT from triggering when one of the STDIO pins is not
connected.
 2018-07-11 17:19:18 -07:00
Marcus Chang 6f0bb757f4 Fix linker script for NRF52840/IAR 
Add missing noinit section.
 2018-07-11 15:48:51 -07:00
Cruz Monrreal c669655d86
Merge pull request #7042 from shuoo/feature-cm3ds-flash 
Flash API: Enable Flash api on CM3DS
 2018-07-11 09:28:17 -05:00
Cruz Monrreal 38c5e9c669
Merge pull request #7453 from marcuschangarm/fix-nrf52-swi 
Fix SWI conflict in SoftDevice for NRF52 series
 2018-07-11 08:12:30 -05:00
bcostm 0b133be504 stm32 ticker: change th eplace where timer init in done, fix overflow issue with 16-bit timer 
- Move back the 16/32bit timer initialization in HAL_InitTick() and not in us_ticker_init()
- Use ticker_read_us() and us_ticker_read() in HAL_GetTick() to fix potential overflow issue with the 16bit timer

==> These corrections allow timer, rtc, sleep, tick tests to PASS
 2018-07-11 14:45:48 +02:00
bcostm fc50e28ae6 stm32 ticker: corrections in order to pass tests 2018-07-11 14:44:23 +02:00
bcostm 7097e07b62 stm32 ticker: typo corrections 2018-07-11 14:43:36 +02:00
bcostm d8e839a789 stm32 ticker: change license 2018-07-11 14:43:16 +02:00
bcostm 32031cbab3 stm32 ticker: rename hal_tick.h in us_ticker_data.h 2018-07-11 14:42:44 +02:00
Cruz Monrreal dc946b3c34
Merge pull request #7446 from kivaisan/disable_lse_MTB_USI_WM_BN_BM_22 
Disable LSE for MTB_USI_WM_BN_BM_22
 2018-07-11 07:39:44 -05:00
bcostm fbd7a97e19 stm32 ticker: rename macro and update ST HAL Tick functions 
- rename TIM_MST_16BIT in TIM_MST_BIT_WIDTH in order to use it directly in ticker info structure
- change HAL_InitTick() and HAL_GetTick()
 2018-07-11 14:39:42 +02:00
bcostm b1bbd765b7 stm32 ticker: rename files and move functions 
- rename hal_tick_common.c in hal_tick_overrides.c
- move 16 and 32bits timer functions in us_ticker.c
 2018-07-11 14:36:58 +02:00
Steven Cooreman 001844231b Add EFM32GG11_STK3701 support 2018-07-11 10:45:38 +02:00
jeromecoutant 1052993236 STM32 RTC : bypass shadow registers 
- RTC_SSR for the subseconds
- RTC_TR for the time
- RTC_DR for the date

These registers were accessed through shadow registers which are synchronized with PCLK1 (APB1 clock).
They are now accessed directly in order to avoid waiting for the synchronization duration.
 2018-07-11 10:08:02 +02:00
Martin Kojtal 396c88ac3c Raytac: target removal 
No files to build - should not be in targets
Reverts part of the https://github.com/ARMmbed/mbed-os/pull/6178
 2018-07-10 12:23:34 +01:00
Kimmo Vaisanen a5ac795304 Disable LSE for MTB_USI_WM_BN_BM_22 
Current MTB_USI_WM_BN_BM_22 modules do not have OSC32_IN connected, so
external xtal is not in use.
 2018-07-10 08:49:38 +03:00
Marcus Chang 4bb84fdb71 Change NRF52 series UART to only use one SWI channel 
This fixes conflicts with the SoftDevice.
 2018-07-09 12:54:09 -07:00
Marcus Chang cfb99d689a Fix inconsistent SWI configuration in NRF52 series 
All SWI channels except SWI0 is being used by the SoftDevice and
not only SWI1.
 2018-07-09 12:54:09 -07:00
Marcus Chang 01135e30ce Remove white space in config files for NRF52 series 2018-07-09 12:54:08 -07:00
Cruz Monrreal bcec185754
Merge pull request #7352 from bcostm/fix_rtc_ticker 
STM32: Fix RTC test issue on targets using a 16-bit timer for us_ticker
 2018-07-09 10:20:13 -05:00
Karl Zhang bbb97c803b Flash API: Enable Flash api on CM3DS 
Implement flash_api.c for CM3DS on MPS2+.
Because MPS2+ board has no physical flash chip, the implementation emulates
flash over SRAM.
 2018-07-09 21:07:48 +08:00
Cruz Monrreal 69d8c0bac3
Merge pull request #7429 from codeauroraforum/MXRT_Fix_AnalogIn 
MXRT1050: Ensure the pins are in input mode for analogin
 2018-07-06 11:24:40 -05:00
Cruz Monrreal 59defa29e9
Merge pull request #7406 from OpenNuvoton/nuvoton_fix_wakeup_delay 
NANO130: Change PLL clock source to HIRC instead of HXT
 2018-07-06 11:20:40 -05:00
Mahesh Mahadevan 19b6ef2e87 MXRT1050: Ensure the pins are in input mode for analogin 
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
 2018-07-05 17:23:07 -05:00
Mahesh Mahadevan c24d158fb4 MIMXRT1050_EVK: Move clock enable after check of pin 
Enable clock could return an error if pin is NC

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
 2018-07-05 10:59:00 -05:00
Cruz Monrreal 9f27672f0f
Merge pull request #7420 from codeauroraforum/Fix_MXRT_GPIO_IRQ 
MIMXRT1050_EVK: Fix the GPIO IRQ number assignements
 2018-07-05 10:51:02 -05:00
Cruz Monrreal 4942ec540c
Merge pull request #7413 from mikaleppanen/wiced_removed_def_inst 
Modified Wiced drivers EMAC instance get
 2018-07-05 10:42:41 -05:00
Cruz Monrreal 917dc8394c
Merge pull request #7405 from marcuschangarm/fix-nrf52-target 
Fix target definition for NRF52 series
 2018-07-05 10:41:55 -05:00
Cruz Monrreal 8b6dfc4050
Merge pull request #7401 from marcuschangarm/fix-nrf52-irq 
Fix interrupt initialization for NRF52 series
 2018-07-05 10:41:20 -05:00
Cruz Monrreal 3faedca1cf
Merge pull request #7390 from jeromecoutant/PR_TWO 
DISCO STM32L4 : Add TWO_RAM_REGIONS macro
 2018-07-05 10:39:31 -05:00
Cruz Monrreal 513960f17d
Merge pull request #7386 from evva-sfw/feature/make_clock_src_changeable 
Make clock source changeable over mbed_app.json for EFM32-Targets
 2018-07-05 10:39:11 -05:00
Cruz Monrreal 1941906f72
Merge pull request #7376 from bcostm/dev_leds_disco_L496ag 
DISCO_L496AG: change LED1 and LED2 pins
 2018-07-05 10:37:57 -05:00
Mahesh Mahadevan 9b48f3978a MIMXRT1050_EVK: Fix the GPIO IRQ number assignements 
Use the GPIO_Combined IRQ array

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
 2018-07-04 11:53:47 -05:00
bcostm a838cb21d1 save/restore timer registers before/after deepsleep 2018-07-04 16:44:00 +02:00
bcostm 9523bcf8c9 Use elapsed time only for 16bit timer 2018-07-04 16:43:21 +02:00
bcostm fcdd529f89 Re-enable IT CC1 after deepsleep 2018-07-04 10:16:32 +02:00
bcostm f785c23e89 HAL_GetTick returns elapsed time 2018-07-04 10:16:31 +02:00
bcostm 26cb388d14 Use us_ticker_read while SDK is not ready 2018-07-04 10:15:15 +02:00
Mika Leppänen 83a82d31e0 Modified Wiced drivers EMAC instance get 
Removed EMAC get_default_instance() since WLAN drivers are not default EMAC drivers.
Moved EMAC static declaration inside get_instance().
 2018-07-04 09:44:28 +03:00
ccli8 13fec628d0 [NANO130] Change PLL clock source to HIRC instead of HXT 
This change is to reduce delay of wake-up from power-down to pass Greentea test.
Because HIRC's accuracy is worse than HXT's, we must switch back to HXT for e.g. USBD application.
This can be done through setting NU_CLOCK_PLL to NU_HXT_PLL.
 2018-07-03 15:37:53 +08:00
Marcus Chang 3f28fe2f54 Fix target definition for NRF52 series 
* Removed RTC, NRF52840 doesn't support RTC API.
 * Reorganized DEVICE_HAS order for NRF52832.
 2018-07-02 16:58:33 -07:00
Mahesh Mahadevan 34dab4a4d9 LPC546XX: Fix UART mux setting in the LPCXpresso board 
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
 2018-07-02 15:16:57 -05:00
Marcus Chang a0224ed794 Fix interrupt initialization for NRF52 series 
In some cases the UARTE interrupt would be enabled with pending
interrupts. This commit ensures that interrupts are only enabled
from a known state.
 2018-07-02 11:13:50 -07:00
Martin Kojtal 2353e7b1c6
Merge pull request #7029 from OpenNuvoton/nuvoton_5.9_ticker 
Nuvoton: Adhere to reworked ticker spec to release with Mbed OS 5.9
 2018-07-02 17:28:11 +02:00
Martin Kojtal 44acaf587b
Merge pull request #7369 from marcuschangarm/fix-nrf52-serial 
Fix race condition in serial_api.c for NRF52 series
 2018-07-02 17:24:16 +02:00
jeromecoutant 40da60b959 DISCO STM32L4 : Add TWO_RAM_REGIONS macro 2018-07-02 14:03:05 +02:00
bcostm b6beb74d9d DISCO_L496AG: update LEDs comments in PeripheralPins.c 2018-07-02 10:27:23 +02:00