mbed_config.h is a file that is placed in your project root when you
export. This allows the configuration to be used by your IDE. When this
file already exists (due to a previous export), it changed the compiler
include option on Windows from "-include mbed_config.h" to "-include
.\mbed_config.h". The "\" character was interpreted as an escape
character "\m" and broke the build. This converts all resource paths to
use the Posix path separator "/" before writing project files to avoid
this issue.
The call to encode() was causing the include paths to be placed in the
uvision product file with the prefix "b'" and the postfix "'". This
broke the parsing of this file and broke the build.
The compiler used for the ARM toolchain changes depending on the target.
This changes the front end scripts to do the proper toolchain look up
before checking the system PATH for the compiler executable. The tools
were always checking for the ARMC5 compiler, now it should check for the
right version.
* Replace call with check_call to throw exception on failure
* Check if binaries actually been changes before calling git commit
* Docstrings for all functions
* Small refactor
Fixes#9974
The error was that the Asymmetric CPUs were assumed to have the same
structure as the Symmetric CPUs. This is clearly false.
This PR changes the FPU detection of Asymmetric CPUs to find the correct
core and use it's cpu settings.
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
Added WiFi_Bt CM4 PSA target in mbedos json
Added SPE-NSPE mailbox initialization for CM4 SystemInit
Made similar to FUTURE_SEQUANA configurations
Copied FUTURE_SEQUANA CM0 SPM part for WiFi_Bt smoke test
Added CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Sorted files for new CY8CKIT_062_WIFI_BT_M0 and CY8CKIT_062_WIFI_BT_M0_PSA targets
Copied files for CY8CKIT_062_WIFI_BT_M0_PSA from FUTURE_SEQUANA
Copied and updated cm0p start files
Corrected according to FUTURE_SEQUANA
Changes to M0 startup files to have SPM started
Fixed implicit declaration warning
Commented interrupts enabling according to FUTURE_SEQUANA flow
Updated prebuild spm_smore CM0 hex for CM4 target
Turned on greentea environment
Used special memory region for common CM0/CM4 data
Updated prebuild CM0 SPM hex
Placed shared memory region for flash operations into SPM shared memory region
Updated cyprotection code and configuration
Start address of protected regions is set by a defined number from target.json
Added masters pcMask configuration
Added support for PSA target to WIFI_BT board
Enabled resources protection for SPM
Aligned RAM usage according to Cypress FlashBoot and CyBootloader
alligned protection config
Added CYW943012P6EVB_01_M0 target
Enlarged heap size, remobed nv_seed
Added heap reservation in linker script from mbed-os
Removed heap size definition
turned on nv_seed config
Removed nv_seed macros
Enabled protection for PSoC6 CM0
Added PSoC6 CM0 PSA readme
Enabled mbed_hal-spm test
Enabled nv_seed and removed unneeded ipc config define
Added SPDX string to feature_ble cypress target files
Removed unneeded supported_toolchains lines for Cypress targets
Disabled protection settings
Corrected flash initialization for PSoC6 CM0 PSA
Changed PSoC6 IPC6 protection for flash
Enabled special flash initialization and enabled protection settings
Updated and added new prebuild PSoC6 CM0 PSA hex files
Disabled HW TRNG and CRC for PSoC6 CM4 PSA target
Added missing const to allow types to match
Updated PSoC6 WIFI_BT_PSA prebuilt directory
Moved PSoC6 shared section usage area definition to begin of ld
Added initial ARM_STD linker and startup files for PSoC6 CM0
Added initial IAR linker and startup files for PSoC6 CM0
Added defines to disable some SPM protection settings for PSoC64
Moved Flash function variables into separate memory region
Added defines for new Public area definition
Updated PSoC6 CM0_PSA hex-files
The Makefile is run from the build directory. The source files were
properly prefixed with "../", however the paths provided to the
assmebler were not. This ensures the assembler include paths are
prefixed properly.
Revert latest change to index. Linker scripts follow one RAM region. If index is updated,
requires further changes in the target that should be done separately.
Priously, post-bulid was run before the merge from managed bootloader mode.
This renders many post-build scripts less than useful, as most of them
compute a digest of the ROM image generated in a build.
This reorders the post-build scripts to come after the managed bootloader
mode so that post-build script digests are useful again.
The "hook tools" were capable of hooking into many commands run by the build system.
To my knowlage, the only hook is the "post-build-hook". The post build hook could be
easier to reason about if the implementation is specialized for just post-build
hooking.
This commit make it much easier to point out where post build hooks are called by
making the call explicit.
Reference template file is used from IAR8.32 installation available at path
"Embedded Workbench 8.2\arm\config\template\ConvertToIAR\template_project.ewp"
Also added trustzone configs in iar_definitions.json
Add tests to
1. Verify that a ConfigException is generated if application is placed
within the bootloader region
2. Verify that a ConfigException is generated if bootloader segments
don't fit witin rom.
Support the requirement where bootloader can be in chunks and enable
placing the application at a particular offset specified by config.
With FEATURE_BOOTLOADER support, the bootloader can be placed at a
high address. Add support to the tools so that application can be
placed in the available space before the beginning of the bootloader.
- Move all PSA storage code under psa/storage directory
- Create a global PSA error codes header, eliminating ITS specific ones
- Create a common header file for PSA storage type definitions,
eliminating ITS specific ones
- Create a common implementation for PS & ITS
- Implement protected storage feature
- Change ITS test to be common to PS as well
When the original PSOC6 CM4 hex file contains unalinged text sections
that span through multiple intelhex segments, aligned segments (filled
with zeroes) overlap with the original data segments, resulting in
error thrown by ihex.merge(alignments, overlap='error').
Such hex file can be produced when the ELF is built with ARM MDK Compiler
with --split_sections option:
http://www.keil.com/support/man/docs/armcc/armcc_chr1359124944914.htm
Change the merge strategy to overlap='ignore', so that the overlapping
zero-filled segments are skipped.
The approach for the hex_files subset selection is identical
to makefile exporter: https://github.com/ARMmbed/mbed-os/pull/9466
Single hex file should be passed to srec_cat when hex_filename
is set in targets.json or mbed_app.json.
The templ file names are both all upper case and lower case letters.
The Target Names map is usually all upper case. The match could fail
if the templ file, as we have case-sensitive comparison. Handle such
cases by perorming a case-insensitve check.
mbed export of a project to MCUXpresso could potentially always fail
irrespective of what is passed in -m option since the target names
map entry and the filename may not match. This commit fixes this issue.
Example of the issue that this commit fixes:
$ mbed export -i mcuxpresso -m lpc11u68 -v
<snip>
project.py: error: LPC11U68 not supported by mcuxpresso
<snip>
The command-line argument '--profile' looks for build
profiles provided in mbed-os/tools/profiles/. If a
directory name exists in the root folder with the
same name as one of the profile names provided by
default [e.g debug/develop/release], that directory
is processed instead resulting in incorrect behavior.
Fix this behavior by processing the default profiles first.
Currently, if you were to add a directory that only contained .inc
files, this file would not be passed as an include path to the compiler.
This ensures that .inc files are also considered header files.
Allow to use default intelliSenseEngine in visual studio code.
Add of compilerPath and forcedInclude of mbed_config header in the
created c_cpp_properties.json file.
When building secure targets, we would like compile only files that are in the the mbe-os root folder.
This Fixes an issue when sending multiple --source parameters that are all inside the mbed-os tree
$(file > $@.in, $(filter %.o, $^)) is not supported in GNU Make 3.81.
Create the linker response file with pipe redirect from echo command.
This is tested with Cygwin make and make 3.8.1 shipped with macOS.
Also, change the linker responce file name to .link_options.txt.
This is an internal file, not a build artifact.
As per the IAR Development guide, below options for CPU are valid
1. Cortex-M33
2. Cortex-M33.no_dsp (core without integer DSP extension)
3. Cortex-M33.fp (floating-point unit with support for single precision)
4. Cortex-M33.no_se (core without support for TrustZone)
5. Cortex-M4
6. Cortex-M4F
7. Cortex-M7
8. Cortex-M7.fp.dp (floating-point unit with support for double precision)
9. Cortex-M7.fp.sp (floating-point unit with support for single precision)
DAPLink implementation on Cypress kits cannot handle hex files
with 64 bytes per row: refer to https://github.com/ARMmbed/DAPLink,
source/daplink/drag-n-drop/intelhex.c, hex_line_t struct, data field.
Below are the options read from the toolchains/arm
armclang --target=arm-arm-none-eabi -mcpu=list
The following arguments to option 'mcpu' can be selected:
-mcpu=cortex-m0
-mcpu=cortex-m0plus
-mcpu=cortex-m1
-mcpu=cortex-m3
-mcpu=cortex-m4
-mcpu=cortex-m7
-mcpu=cortex-m23
-mcpu=cortex-m33
...
armlink --cpu=list
The following arguments to option 'cpu' can be selected:
--cpu=Cortex-M0
--cpu=Cortex-M0plus
--cpu=Cortex-M1
--cpu=Cortex-M1.os_extension
--cpu=Cortex-M1.no_os_extension
--cpu=Cortex-M4
--cpu=Cortex-M4.no_fp
--cpu=Cortex-M7
--cpu=Cortex-M7.fp.sp
--cpu=Cortex-M7.no_fp
--cpu=Cortex-M23
--cpu=Cortex-M33
--cpu=Cortex-M33.no_fp
--cpu=Cortex-M33.no_dsp
--cpu=Cortex-M33.no_dsp.no_fp
...
armclang --target=arm-arm-none-eabi -mfpu=list
The following arguments to option 'mfpu' can be selected:
-mfpu=fpv4-sp-d16
-mfpu=fpv5-sp-d16
-mfpu=fpv5-d16
...
Rename the existing PSoC-specific m0_core_img key in targets.json
as a more generic hex_filename key. Update makefile exporter to select
the subset of resources.hex_files matching the hex_filename value.
Without this fix, multiple prebuilt CM0+ hex files are found in the
target resources and erroneously passed to the srec_cat tool.
The fix is generic so other targets that need post-build hex merging
can use this key to pass the correct image to srecord tool.
The fix also removes sub_target key: instead, rely hex_filename json
key to detect if the hex image merging needs to be done.
The sub_target is not used in mbed-os codebase for anything else.
It is possible to override the hex file name in mbed_app.json:
{
"target_overrides": {
"*": {
"target.hex_filename": "my_custom_m0_image.hex"
}
}
Replace hard-coded numeric offsets of PSoC 6 hex file sections
with sensible constants.
Do not attempt to update the checksum and metadata contents
if the sections are not found in the original HEX file.
PSoC 6 hex files contain 4-byte chip ID at virtual offset 0x90500002
added by PSoC Creator or cymcuelftool from .cymeta ELF section.
merge_images compares chip ID in CM0+ and CM4 hex files and raises
an exception in case of mismatch. Chip ID is different for each MPN
(for example, 0xE2072100 for CY8C6347BZI-BLD53 and 0xE2062100 for
CY8C6247BZI-D54). CM0+ prebuilt images target CY8C6347BZI-BLD53
but should be compatible with other PSoC6 MPNs.
Remove the check to enable merging CM0+ images with CM4 applications
built for different MPNs, with empty or absent cymetadata.
printf was called from ISR when sleep tracing was enabled. Issue was
captured only in debug profile.
Printf is not allowed from ISR context and issues like this should be
trapped in case of debug profiles as well.