Merge pull request #9437 from deepikabhavnani/preprocess_asm

FPU_USED to be set based on HW FPU support + Squash commits

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_ARM/TARGET_M33/irq_armv8mml.S

@@ -28,10 +28,13 @@
 DOMAIN_NS     EQU      0
 #endif
 
-#ifndef __FPU_USED
+#ifdef __ARM_FP
+__FPU_USED      EQU      1
+#else
 __FPU_USED      EQU      0
 #endif
 
+
 I_T_RUN_OFS     EQU      20                     ; osRtxInfo.thread.run offset
 TCB_SM_OFS      EQU      48                     ; TCB.stack_mem offset
 TCB_SP_OFS      EQU      56                     ; TCB.SP offset

rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_M33/irq_armv8mml.S

@@ -31,7 +31,9 @@
         .equ     DOMAIN_NS, 0
 #endif
 
-#ifndef  __FPU_USED
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+        .equ     __FPU_USED,  1
+#else
         .equ     __FPU_USED,  0
 #endif
 

tools/importer/cmsis_importer.json

@@ -145,15 +145,13 @@
   ],
    "commit_sha" : [
       "4360b7bbf815c4d812005938c9c27af199803a97",
-      "cc2e0517e1c6440abf88f2815b8e1501a55cdd4d",
       "b88254809eb626689c8aeb41304a308bf4e34a04",
-      "287121ffdc4c9c19f9ce8872e4edd941862daca1",
-      "b228cd9db0b7ed79d99f1d9be15d512791f367cc",
       "1752803626865147dca92f30a39cef8d04581736",
       "6a6e3ac0ebab1a6b6aa08d0928702c79562acee9",
       "fb354752eb69403ad503c8e53da67da6483776d6",
       "d3f7abdb7c109517e6a71daed8bae63ad6436afc",
-      "ba92372b8d754cf65917a560cd27e4088548de0e"
+      "ba92372b8d754cf65917a560cd27e4088548de0e",
+      "094662790a0e100cb11ea2e0c1b94c4d796afb3f"
     ]
 }