Commit Graph

503 Commits (920133e8edab4e77be2dacf414bd193fdba758c7)

Author SHA1 Message Date
jeromecoutant 0a447ac798 STM32L4 baremetal support 2020-06-08 12:05:54 +02:00
jeromecoutant c96eb2cd0e STM32 rename TOOLCHAIN_ARM_STD into TOOLCHAIN_ARM 2020-05-15 10:41:28 +02:00
jeromecoutant 303752ad84 STM32 remove all TOOLCHAIN_ARM_MICRO 2020-05-15 09:37:40 +02:00
Hugues Kamba ce1c51ea51 ST Boards: Remove uARM tooolchain support
For NUCLEO_F401RE, NUCLEO_F411RE, NUCLEO_F303RE, and DISCO_L475VG_IOT01A:
* Ensure the scatter files for the ARM toolchain use 2 region memory model.
  The scatter files changes affects the following boards:
    * NUCLEO_F401RE, STEVAL_3DP001V1 (stm32f401xe.sct)
    * NUCLEO_F411RE, MTS_MDOT_F411RE, MTS_DRAGONFLY_F411RE, MTB_MTS_DRAGONFLY, SAKURAIO_EVB_01 (stm32f411re.sct)
    * NUCLEO_F303RE, NUCLEO_F303ZE (stm32f303xe.sct)
    * DISCO_L475VG_IOT01A, MTB_STM_L475 (stm32l475xx.sct)
* Remove the TOOLCHAIN_ARM_MICRO directories.
* Remove release_version as not necessary and as the targets can also run
  Mbed OS 6.
* Remove uARM support for all FAMILY_STM32 targets.
2020-04-30 14:17:39 +01:00
Marcelo Salazar a7b026bd14 Rename ADV_WISE_1510 target 2020-04-30 09:56:35 +01:00
Marcelo Salazar 92cbd9a734 Rename ADV_WISE_1570 target 2020-04-30 09:56:35 +01:00
MarceloSalazar 4b1ad8ad4c Remove MTB_STM_L475 target 2020-04-20 16:55:33 +01:00
MarceloSalazar 831c475a46 Remove Silica target 2020-04-09 15:32:41 +01:00
jeromecoutant 3e30033822 DISCO_L4R9I correct LED pins 2020-03-03 13:36:57 +01:00
Martin Kojtal 7658681a9e
Merge pull request #12409 from LMESTM/Fix_lpuart_deep_sleep
FIX: LPUART clock source selection should be left to serial driver
2020-02-13 09:45:41 +00:00
Laurent Meunier 3fd071404e FIX: LPUART clock source selection should be left to serial driver
The clock source selection of LPUART depends on System clocks but also on
the serial baudrate. There is a specific computation done in serial driver
targets/target_STM/serial_api.c

At first start-up the LPUART1 clock selected in SetSysClock was anyway
overridden by the serial driver, so this was of no effect. But in case
of deep sleep SetSysClock is called again, while the driver isn't, so
SetSyClock was corrupting the serial clock configuration.

So let's remove these few lines of code which are causing trouble.
2020-02-11 17:14:45 +01:00
Martin Kojtal c1eaf2c358
Merge pull request #12380 from mprse/DISCO_L475VG_IOT01A_add_gpio_pinmap
DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing
2020-02-11 11:58:53 +00:00
Martin Kojtal 7fd5119b89
Merge pull request #12341 from fkjagodzinski/fix-stm-hal_fpga
STM32L4: Fix the UART RX & TX data reg bitmasks
2020-02-10 13:21:31 +00:00
Przemyslaw Stekiel 3a71f86235 DISCO_L475VG_IOT01A: Add a list of restricted GPIO pins for testing 2020-02-07 11:41:32 +01:00
Filip Jagodzinski ae635d5cd4 STM32L4: Fix the UART RX & TX data reg bitmasks
The existing logic was insufficient to properly handle odd and even
parity setting, e.g. serial_getc() returned 9-bit data for 8O1
transmission format.
2020-02-06 14:07:51 +01:00
pea-pod f7c4693747 Add new target: NUCLEO_L452RE-P 2020-01-27 18:41:18 -06:00
Martin Kojtal d6e69ef57b
Merge pull request #12208 from hugueskamba/hk-replace-uartserial-st
ST targets: Replace UARTSerial references with BufferedSerial
2020-01-17 08:19:09 +00:00
Hugues Kamba 03cff0a02c ST targets: Replace UARTSerial references with BufferedSerial
BufferedSerial is UARTSerial renamed to convey the original purpose of
the class. It is the recommended buffered I/O serial class.
2020-01-08 08:34:20 +00:00
Leon Lindenfelser 94ead7adb2 Minor fixes for peripheral pins on Dragonfly Nano
1. PG8 should be labeled I2C3 not I2C1.
2. PC0 is dedicated to measuring system voltage.
2020-01-07 08:52:34 -06:00
Antti Kauppila e29cb193ca Added missing define for Quectel UG96 2019-12-27 16:04:10 +01:00
Antti Kauppila ca7848d854 Refactored away onboard_modem_api because it is not needed at all
All targets must implement soft_- and hard_power_on/off() functions which are practically same what onboard_modem_api offered.
These were seen as a duplicate features and therefore we removed this.
All targets involved have been updated to reflect the changes
2019-12-27 16:04:10 +01:00
Anna Bridge b1b0673622
Merge pull request #12086 from ABOSTM/FLASH_API_64B_ALIGNMENT
TARGET_STM: fix flash api 64bit address alignment on L4 and WB
2019-12-17 16:46:21 +00:00
Alexandre Bourdiol 9e3ad13d5e TARGET_STM: fix flash api 64bit address alignment on L4 and WB 2019-12-11 18:32:42 +01:00
jeromecoutant bea83d02c2 STM32 TARGET_STM astyle corrections 2019-12-10 14:39:47 +01:00
Kevin Bracey fe22bc023e Update HAL CRC API
* Change "is supported" check to be a macro, so it can be done at
  compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
2019-12-02 14:45:37 +02:00
Martin Kojtal 48f544f9e4
Merge pull request #11980 from jeromecoutant/PR_L4R9I
DISCO_L4R9I: update clock configuration for all clock sources
2019-12-02 11:23:51 +01:00
Martin Kojtal 7177d8fefe
Merge pull request #11950 from ABOSTM/DISCO_H747I_TICKLESS
DISCO_H747I: add support of MBED_TICKLESS
2019-11-29 09:48:09 +01:00
jeromecoutant 354913a45e DISCO_L4R9I: correct clock tree for all clock sources 2019-11-28 16:29:11 +01:00
Przemyslaw Stekiel b2dad08387 Change explicit pinmap to static pinmap 2019-11-28 08:32:12 +01:00
Przemyslaw Stekiel e3a34a57e1 Move GPIO_AF_NONE from PeripheralPins.h to PinNamesTypes.h 2019-11-28 08:32:10 +01:00
Przemyslaw Stekiel 6489bb7c99 STM: Add support for internal ADC pins 2019-11-28 08:32:06 +01:00
Przemyslaw Stekiel dc26390d08 DISCO_L475VG_IOT01A: Add explicit pinmap support 2019-11-28 08:32:04 +01:00
Martin Kojtal a1cddbae5f
Merge pull request #11938 from LMESTM/stm32_serial_clear_rxne
STM32: Update and align serial_clear implementations
2019-11-27 16:30:11 +01:00
Alexandre Bourdiol 41b038a028 TARGET_STM: rework hal_sleep management to be compatible with all STM32 families 2019-11-27 14:25:30 +01:00
Martin Kojtal 5f7ecea00b
Revert "MbedCRC and CRC HAL revisions" 2019-11-26 13:45:37 +00:00
Laurent Meunier f20529f9e6 STM32: Update and align serial_clear implementations
Clear RXNE flag by reading the RX register and align this implementation
on all families.
2019-11-25 14:55:32 +01:00
Kevin Bracey 1f94428a56 Update HAL CRC API
* Change "is supported" check to be a macro, so it can be done at
  compile-time.
* Eliminate weird shift on 7-bit CRCs.
* Add support for 32-bit CRCs and reversals to TMPM3HQ.
2019-11-13 14:31:49 +02:00
Martin Kojtal df79609cc5
Merge pull request #11675 from jeromecoutant/PR_USB_STEP1
STM32 USB update step 1
2019-10-28 14:06:15 +01:00
Kevin Bracey fb6aa3ef4f Clean up ARM toolchain heap+stack setup in targets
ARM Compiler 6.13 testing revealed linker errors pointing out
conflicting use of `__user_setup_stackheap` and
`__user_initial_stackheap` in some targets. Remove the unwanted
`__user_initial_stackheap` from the targets - the setup is
centralised in the common platform code.

Looking into this, a number of other issues were highlighted

* Almost all targets had `__initial_sp` hardcoded in assembler,
  rather than getting it from the scatter file. This was behind
  issue #11313. Fix this generally.
* A few targets' `__initial_sp` values did not match the scatter
  file layout, in some cases meaning they were overlapping heap
  space. They now all use the area reserved in the scatter file.
  If any problems are seen, then there is an error in the
  scatter file.
* A number of targets were reserving unneeded space for heap and
  stack in their startup assembler, on top of the space reserved in
  the scatter file, so wasting a few K. A couple were using that
  space for the stack, rather than the space in the scatter file.

To clarify expected behaviour:

* Each scatter file contains empty regions `ARM_LIB_HEAP` and
  `ARM_LIB_STACK` to reserve space. `ARM_LIB_STACK` is sized
  by the macro `MBED_BOOT_STACK_SIZE`, which is set by the tools.
  `ARM_LIB_HEAP` is generally the space left over after static
  RAM and stack.
* The address of the end of `ARM_LIB_STACK` is written into the
  vector table and on reset the CPU sets MSP to that address.
* The common platform code in Mbed OS provides `__user_setup_stackheap`
  for the ARM library. The ARM library calls this during startup, and
  it calls `__mbed_user_setup_stackheap`.
* The default weak definition of `__mbed_user_setup_stackheap` does not
  modify SP, so we remain on the boot stack, and the heap is set to
  the region described by `ARM_LIB_HEAP`. If `ARM_LIB_HEAP` doesn't
  exist, then the heap is the space from the end of the used data in
  `RW_IRAM1` to the start of `ARM_LIB_STACK`.
* Targets can override `__mbed_user_setup_stackheap` if they want.
  Currently only Renesas (ARMv7-A class) devices do.
* If microlib is in use, then it doesn't call `__user_setup_stackheap`.
  Instead it just finds and uses `ARM_LIB_STACK` and `ARM_LIB_HEAP`
  itself.
2019-10-23 14:53:49 +03:00
jeromecoutant 01e798fd6a STM32 clock configuration depending on USB 2019-10-21 17:11:59 +02:00
jeromecoutant 03dd8d3e22 STM32L4 USB pins addition 2019-10-21 17:11:55 +02:00
Laurent Meunier e862438fad Clearing UART TC Flag prevents deep sleep, so do not clear it
The TC flag is used in function serial_is_tx_ongoing to check if there is
an ongoing serial transmission. So this Flag must not be cleared at the
end of the transmission, otherwise, serial_is_tx_ongoing will notify that
TX is ongoing.

The impact is that it may prevent deep sleep to be entered.

Also there is no need to clear this flag at the end of the transaction
because it will be cleared automatically by HW when a new transmission
starts.
2019-10-15 15:59:51 +02:00
jeromecoutant fc5b91a36f DISCO_L4R9I: update default STMOD+ pin 2019-10-07 16:01:16 +02:00
jeromecoutant db7efabfd5 STM license file update
Some code have been copied from ST Cube deliveries.
ST copyright is then needed.
2019-09-10 14:24:48 +02:00
jeromecoutant bb1388be8e NUCLEO_L4R5ZI: add QSPI_x definition 2019-08-29 14:17:33 +02:00
jeromecoutant f13072490c NUCLEO_L4R5ZI : add OSPI pins for QSPI 2019-08-29 12:11:28 +02:00
Martin Kojtal 96d9a8fea9 Merge branch 'MX25LM51245G_QSPI_test_config' of git://github.com/LMESTM/mbed into dev_rollup 2019-08-28 18:37:17 +01:00
Martin Kojtal 104f9281c4 Merge branch 'I2C_SEQUENTIAL_COMMUNICATION_REWORK' of git://github.com/ABOSTM/mbed-os into dev_rollup 2019-08-28 18:36:53 +01:00
Leon Lindenfelser 7063ccee9e Add PA6 to ADC PeripheralPins for MTS_DRAGONFLY_L471QG 2019-08-28 13:12:08 +01:00
jeromecoutant 8cd00b3468 STM32L4: Add OSPI IP support in fallback QSPI mode
For STM32 platforms that embed an OSPI IP, we're offering
a QSPI fallback support with this commit.

When OSPI is supported in mbed, we can consider adding full
OSPI support
2019-08-23 15:18:48 +02:00