Musca-A1 is a Cortex-M33 based target with security extension enabled.
- ARM_MUSCA_A1 is the non-secure target running mbed-os.
- ARM_MUSCA_A1_S is the secure target running TF-M.
- TF-M sources were imported and patched in previous commits.
- TF-M secure bootloader (McuBoot) for MUSCA_A1 is submitted by a pre-built binary.
- A post-build hook concatenates The secure and non-secure binaries,
signs it and then concatenates the bootloader with the signed binary.
Change the heuristic for selection of CMSE in the tools python, so that
a non-TrustZone ARMv8 build can happen.
Ideally we would have more direct flagging in the targets, but this
refines the heuristic so the necessary behaviour can be easily
achieved.
* DOMAIN_NS=1 is based purely on the `-NS` suffix on the core name.
* Enabling CMSE in the compiler and outputting a secure import library
is now enabled when the core doesn't have an `-NS` suffix by either
the target label `TFM` being present or the flag `trustzone` being set.
This covers the existing ARMv8-M behaviour - TF-M builds have the TFM
label, as per its documentation; M2351 secure builds have no explicit
flagging, so we ensure that the M2351_NS target has the trustzone flag
set, and the out-of-tree secure target inherits that.
PSA code generation will be called automatically upon mbed invocation.
The autogenerated files will be created under <mbed-os-root>/PSA_AUTOGEN directory.
The "hook tools" were capable of hooking into many commands run by the build system.
To my knowlage, the only hook is the "post-build-hook". The post build hook could be
easier to reason about if the implementation is specialized for just post-build
hooking.
This commit make it much easier to point out where post build hooks are called by
making the call explicit.
When the original PSOC6 CM4 hex file contains unalinged text sections
that span through multiple intelhex segments, aligned segments (filled
with zeroes) overlap with the original data segments, resulting in
error thrown by ihex.merge(alignments, overlap='error').
Such hex file can be produced when the ELF is built with ARM MDK Compiler
with --split_sections option:
http://www.keil.com/support/man/docs/armcc/armcc_chr1359124944914.htm
Change the merge strategy to overlap='ignore', so that the overlapping
zero-filled segments are skipped.
DAPLink implementation on Cypress kits cannot handle hex files
with 64 bytes per row: refer to https://github.com/ARMmbed/DAPLink,
source/daplink/drag-n-drop/intelhex.c, hex_line_t struct, data field.
Rename the existing PSoC-specific m0_core_img key in targets.json
as a more generic hex_filename key. Update makefile exporter to select
the subset of resources.hex_files matching the hex_filename value.
Without this fix, multiple prebuilt CM0+ hex files are found in the
target resources and erroneously passed to the srec_cat tool.
The fix is generic so other targets that need post-build hex merging
can use this key to pass the correct image to srecord tool.
The fix also removes sub_target key: instead, rely hex_filename json
key to detect if the hex image merging needs to be done.
The sub_target is not used in mbed-os codebase for anything else.
It is possible to override the hex file name in mbed_app.json:
{
"target_overrides": {
"*": {
"target.hex_filename": "my_custom_m0_image.hex"
}
}
Replace hard-coded numeric offsets of PSoC 6 hex file sections
with sensible constants.
Do not attempt to update the checksum and metadata contents
if the sections are not found in the original HEX file.
PSoC 6 hex files contain 4-byte chip ID at virtual offset 0x90500002
added by PSoC Creator or cymcuelftool from .cymeta ELF section.
merge_images compares chip ID in CM0+ and CM4 hex files and raises
an exception in case of mismatch. Chip ID is different for each MPN
(for example, 0xE2072100 for CY8C6347BZI-BLD53 and 0xE2062100 for
CY8C6247BZI-D54). CM0+ prebuilt images target CY8C6347BZI-BLD53
but should be compatible with other PSoC6 MPNs.
Remove the check to enable merging CM0+ images with CM4 applications
built for different MPNs, with empty or absent cymetadata.
The DEVICE_FOO macros are always defined (either 0 or 1).
This patch replaces any instances of a define check on a DEVICE_FOO
macro with value test instead.
Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
* Modify linker scripts to be compatible with bootloader and PSA
* Add memory protection
* Modify original post-build step to allow link with PSA binaries
* Config kvstore for ITS on FUTURE_SEQUANA_PSA
* Enable PSA-Crypto on PSoC6 with NVSeed
This PR modifies the name of the bin file generated for SMCC FOTA feature
Description
Modify name of the bin file from '-payload.bin' to '_update.bin' in REALTEK_RTL8195AM.py file to adapt the manifest tool requirment for the SMCC FOTA feature.
Pull request type
[ ] Fix
[ ] Refactor
[x] Target update
[ ] Functionality change
[ ] Docs update
[ ] Test update
[ ] Breaking change
Exporter hooks removed completely.
Cleanup and improvements to the comments, including removal of the redundant doxygen comments.
Code run through astyle. Additionally:
- changes to drivers/Timer.cpp reverted
- ipcpipe_transport.* files removed as they are not used for now,
- fixed condition in stdio_init.cpp to perform serial initialization only when STDIO is enabled,
- added missing resurce manager call in PWM initialization,
- us_ticker initialization changed to use pre-reserved clock divider (to avoid resource manager call).
Changed reporting level from info to debug in PSOC6.py.
Added missing includes for function declarations in startup files.
Fixed (removed) garbadge text in psoc6_utils.c
Precompiled binaries updated for recent changes in psoc6_utils.c and moved to a separate folder; README and LICENSE files added.
1. In drivers/Timer.cpp make sure that hardware timer is initialized outside of critical section.
This is because on PSoC 6 hardware resources are shared between both cores
and we have to make sure that the other core is not already using a particular resource.
This mechanism is based on interprocessor communication taht cannot be handled iside of
critical section.
2. Added support for post-binary hook function for PSoC 6 targets, so the hex image for M0+ CPU core
can be merged with M4 core image for the final image.
3. Added possibility to use hook function from exportes, so the M0+ hex image could be included
in the generated project.
4. Included hex images in the build dependency list, so the update of image is catched by the
build process.
### Description
Noticed by the online compiler:
When a user has an incomplete target definition, the error is not show
to the user. That's because it's reported as a `KeyError`. This PR adds
an outer `NotSupportedException` so that the outer catch statement knows
that this is not a build system crash, but a user error.
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Breaking change
### Description
The NRF51 post build hook finds it's hex files using the Resources
object. This PR fixes the corner case where the hex files within a
project have a name!=path (This really only happens online).
### Pull request type
[x] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Breaking change
1. move ota region 1 from 0x00b000 to 0x040000
2. move ota region 2 from 0x0c0000 to 0x120000
3. refactor bootloader header as follows:
uint32_t tag;
uint32_t ver;
uint64_t timestamp;
uint32_t size;
uint8_t hash[32];
uint8_t campaign[16];
uint32_t crc32;
where,
a. hash is the sha256 checksum of the payload.
b. crc32 is the crc32 checksum of headers from tag to campaign.
4. Call NVIC_SystemReset for soft reset.
Signed-off-by: Tony Wu <tung7970@gmail.com>
Use TOOLCHAIN_PATHS to locate toolchain binaries for users might set
compiler paths, through mbed_settings.py, env vars, or system path.
Signed-off-by: Tony Wu <tonywu@realtek.com>
When the RTOS is present and the tickless mode is not implemented, it is
expected that the next tick issued by the Systick timer will wake up the MCU.
However nothing prevents an implementation of the ARM architecture to gate the
systick clock signal upon sleep entry.
Therefore on those targets sleep shall be prohibited if the RTOS is present and the
tickless mode is not implemented.
To ease life of porters , a new option has been added in the device add list:
STCLK_OF_DURING_SLEEP. This option expose that the target turn of the systick
clock during sleep.
Targets which exhibit such behavior shall add this define in their device_has list.
Update directory structure to include RTX for only cortex targets, and
for all cortex targets. This patch accomplishes this by moving mbed-os
specific RTX files and RTX itself into rtos/TARGET_CORTEX along with
removing TARGET_CORTEX_M from the RTX5 directory.
The old directory structure:
rtos/rtx5/<mbed-os specific RTX files>
rtos/rtx5/TARGET_CORTEX_M/*
rtos/rtx4/*
rtos/<mbed-os specific RTX files>
Is re-arranged to:
rtos/TARGET_CORTEX/rtx5/*
rtos/TARGET_CORTEX/rtx4/*
rtos/TARGET_CORTEX/<mbed-os specific rtx files>
This both encapsulates RTX code more cleanly and makes it easier to
experiment with non-cortex cmsis-os2 backends, such as a posix
based cmsis-os2 backend.
Note - A potentially better name for the CORTEX_M directory would be
something like FEATURE_RTX5 since this directory only contains RTX5
related files. This cannot be done because there is not an easy way
to turn this feature on, since it cannot be done from mbed_lib.json.
1. Rearrange SDRAM and SRAM layout. Move timing critical code to SRAM,
and the rest to SDRAM.
2. Add bootloader that's capable of FOTA over mbed cloud.
Signed-off-by: Tony Wu <tonywu@realtek.com>
Roman Okhrimenko
jeromecoutant
Alexander Zilberkant
Michael Schwarcz
Anna Bridge
Kevin Bracey
Lin Gao
Alexander Zilberkant
Cruz Monrreal
David Saada
Yossi Levy
Jimmy Brisson
Mahesh Mahadevan
Brian Daniels
Martin Kojtal
Senthil Ramakrishnan
Oren Cohen
Volodymyr Medvid
Aleksi Klasila
deepikabhavnani
Alastair D'Silva
Lu
Leszek Rusinowicz
Russ Butler
Bartek Szatkowski
Cruz Monrreal
drewcassidy
Ashok Rao
chrisyang
Tony Wu
Vincent Coubard
Yuguo Zou
Tony Wu
jacobjohnson-ON