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Add RTL8195AM support for mbed client with IAR 

Move ticker related code to SRAM due to time drift sensitive
pull/4665/head
Yuguo Zou 2017-08-18 19:31:50 +08:00
parent e16c2d2833
commit 1e398cfc60
5 changed files with 189 additions and 86 deletions
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BIN
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/lib_peripheral_mbed_gcc.a
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23
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld
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@ -70,15 +70,16 @@ SECTIONS
*rtl8195a_crypto.o (.text* .rodata*)
*mbedtls*.o (.text* .rodata*)
*libc.a: (.text* .rodata*)
*Ticker.o (.text*)
*Timeout.o (.text*)
*TimerEvent.o (.text*)
*mbed_ticker_api.o (.text*)
*mbed_critical.o (.text*)
*us_ticker.o (.text*)
*lib_peripheral_mbed_gcc.a: (.text*)
*Ticker.o (.text*)
*Timeout.o (.text*)
/* *rtx_timer.o (.text*)*/
*TimerEvent.o (.text*)
*mbed_ticker_api.o (.text*)
*mbed_critical.o (.text*)
*us_ticker.o (.text*)
*lib_peripheral_mbed_gcc.a: (.text*)
} > SRAM1
.text.sram2 :
@ -203,7 +204,7 @@ SECTIONS
__end__ = .;
end = __end__;
*(.heap*)
. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;
. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;
__HeapLimit = .;
} > SRAM1
@ -214,7 +215,7 @@ SECTIONS
{
__StackLimit = .;
*(.stack)
. += StackSize - (. - __StackLimit);
. += StackSize - (. - __StackLimit);
} > SRAM1
/* Set stack top to end of RAM, and stack limit move down by

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targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/lib_peripheral_mbed_iar.a
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250
targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_IAR/rtl8195a.icf
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@ -16,7 +16,7 @@ define symbol __ICFEDIT_region_ROM_USED_RAM_end__ = 0x10005FFF;
//define symbol __ICFEDIT_region_RECY_RAM_start__ = 0x10002090;
//define symbol __ICFEDIT_region_RECY_RAM_end__ = 0x100037FF;
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_start__ ) ) {
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10006000;
define symbol __ICFEDIT_region_BD_RAM_start__ = 0x10007000;
}
if( !isdefinedsymbol( __ICFEDIT_region_BD_RAM_end__ ) ) {
define symbol __ICFEDIT_region_BD_RAM_end__ = 0x1006FFFF;
@ -31,12 +31,12 @@ define symbol __ICFEDIT_size_heap__ = 0x19000;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region TCM_region = mem:[from __ICFEDIT_region_TCM_start__ to __ICFEDIT_region_TCM_end__];
define region ROM_USED_RAM_region = mem:[from __ICFEDIT_region_ROM_USED_RAM_start__ to __ICFEDIT_region_ROM_USED_RAM_end__];
//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
//define region RECY_RAM_region = mem:[from __ICFEDIT_region_RECY_RAM_start__ to __ICFEDIT_region_RECY_RAM_end__];
define region BD_RAM_region = mem:[from __ICFEDIT_region_BD_RAM_start__ to __ICFEDIT_region_BD_RAM_end__];
define region SDRAM_RAM_region = mem:[from __ICFEDIT_region_SDRAM_RAM_start__ to __ICFEDIT_region_SDRAM_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
@ -95,11 +95,11 @@ define block .ram_image1.data with fixed order{ section .image1.validate.rodata*
section .infra.ram.data*,
section .timer.ram.data*,
section .cutb.ram.data*,
section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
section .hal.ram.data* object rom.o, // for standard libaray __impure_data_ptr
section .cutc.ram.data*,
section .hal.ram.data*
};
define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
define block .ram_image1.bss with fixed order{ //section .hal.flash.data*,
section .hal.sdrc.data*
};
@ -113,13 +113,14 @@ define block IMAGE1 with fixed order { section LOADER };
define block IMAGE1_DBG with fixed order { block .ram.start.table, block .ram_image1.data, block .ram_image1.bss, block .ram_image1.text };
place at start of ROM_USED_RAM_region {
block .vector_table,
block .user_vector_table,
block .user_data_table,
block .rom.bss,
block IMAGE1
};
block .vector_table,
block .user_vector_table,
block .user_data_table,
block .rom.bss,
block IMAGE1
};
keep { section .image2.ram.data* };
define block .image2.start.table1 with fixed order{ section .image2.ram.data* };
@ -133,98 +134,197 @@ define block CPP_INIT with alignment = 8, fixed order {
block SHT$$INIT_ARRAY
};
define block FPB_REMAP with alignment = 256,fixed order {
section .fpb.remap*
};
define block .ram_image2.text with fixed order{ section .infra.ram.start*,
section .rodata*,
block CPP_INIT,
section .fpb.remap*
};
define block MBEDTLS_TEXT with alignment = 8, fixed order{
section .text* object aes.o,
section .text* object aesni.o,
section .text* object arc4.o,
section .text* object asn1parse.o,
section .text* object asn1write.o,
section .text* object base64.o,
section .text* object bignum.o,
section .text* object blowfish.o,
section .text* object camellia.o,
section .text* object ccm.o,
section .text* object certs.o,
section .text* object cipher.o,
section .text* object cipher_wrap.o,
section .text* object cmac.o,
section .text* object ctr_drbg.o,
section .text* object debug.o,
section .text* object des.o,
section .text* object dhm.o,
section .text* object ecdh.o,
section .text* object ecdsa.o,
section .text* object ecjpake.o,
section .text* object ecp.o,
section .text* object ecp_curves.o,
section .text* object entropy.o,
section .text* object entropy_poll.o,
section .text* object error.o,
section .text* object gcm.o,
section .text* object havege.o,
section .text* object hmac_drbg.o,
section .text* object md.o,
section .text* object md2.o,
section .text* object md4.o,
section .text* object md5.o,
section .text* object md_wrap.o,
section .text* object memory_buffer_alloc.o,
section .text* object net_sockets.o,
section .text* object oid.o,
section .text* object padlock.o,
section .text* object pem.o,
section .text* object pk.o,
section .text* object pk_wrap.o,
section .text* object pkcs11.o,
section .text* object pkcs12.o,
section .text* object pkcs5.o,
section .text* object pkparse.o,
section .text* object pkwrite.o,
section .text* object platform.o,
section .text* object ripemd160.o,
section .text* object rsa.o,
section .text* object sha1.o,
section .text* object sha256.o,
section .text* object sha512.o,
section .text* object ssl_cache.o,
section .text* object ssl_ciphersuites.o,
section .text* object ssl_cli.o,
section .text* object ssl_cookie.o,
section .text* object ssl_srv.o,
section .text* object ssl_ticket.o,
section .text* object ssl_tls.o,
section .text* object threading.o,
section .text* object timing.o,
section .text* object version.o,
section .text* object version_features.o,
section .text* object x509.o,
section .text* object x509_create.o,
section .text* object x509_crl.o,
section .text* object x509_crt.o,
section .text* object x509_csr.o,
section .text* object x509write_crt.o,
section .text* object x509write_csr.o,
section .text* object xtea.o,
};
define block .sram1.text with fixed order {
block MBEDTLS_TEXT,
section .text* object Ticker.o,
section .text* object Timeout.o,
section .text* object TimerEvent.o,
section .text* object mbed_ticker_api.o,
section .text* object mbed_critical.o,
section .text* object us_ticker.o,
section .text* object lib_peripheral_mbed_iar.a,
};
define block .sram2.text with fixed order {
block .image2.start.table1,
block .image2.start.table2,
section .mon.ram.text*,
section .hal.flash.text*,
section .hal.sdrc.text*,
section .hal.gpio.text*,
section .text* object main.o,
section .wlan.text,
section .wps.text,
section .text*,
section .infra.ram.start*,
section .rodata*,
};
define block .sram2.data with fixed order {
//section .infra.ram.start*,
//section .rodata*,
//section .wlan.text,
//section .wps.text,
section CODE,
section .otg.rom.text,
//section .otg.rom.text,
section Veneer object startup.o,
section __DLIB_PERTHREAD,
section .iar.dynexit*,
block CPP_INIT,
//section .mdns.text
};
};
define block .ram.data with fixed order {
readwrite, readonly,
section .data*,
section .wlan.data,
section .wps.data,
section DATA,
section .ram.otg.data.a,
section .iar.init_table,
//section .mdns.data,
//section .data* object lib_peripheral_mbed_iar.a,
};
define block .ram.data with fixed order{ readwrite, readonly,
section .data*,
section .wlan.data,
section .wps.data,
section DATA,
section .ram.otg.data.a,
section .iar.init_table,
//section .mdns.data
};
define block .ram.bss with fixed order {
section .bss*,
section COMMON,
section .bdsram.data*,
};
define block IMAGE2 with fixed order { block .image2.start.table1, block .image2.start.table2, block .ram_image2.text, block .ram.data };
define block IMAGE2 with fixed order {
block .sram1.text,
block .ram.data,
block .ram.bss
};
define block .ram.bss with fixed order{ section .bss*,
section .ssl_ram_map,
section .hal.flash.data*,
section .hal.gpio.data*,
section COMMON,
section .bdsram.data*,
section .bss* object heap_4.o
};
define block .bf_data with fixed order{ section .bfsram.data* };
define block .heap with fixed order{ section .heap* };
define block .stack_dummy with fixed order { section .stack };
place at start of BD_RAM_region {
place at start of BD_RAM_region {
block IMAGE2,
//block IMAGE1_DBG,
block .ram.bss,
//block .ram.bss,
//block .bf_data,
};
};
//place at address mem:0x10052b00 { readwrite,
place at end of BD_RAM_region {
block .bf_data,
block HEAP,
};
define block SDRAM with fixed order{
section .text*,
section .sdram.text*,
section .sdram.data*,
section .mdns.text*,
section .mdns.data*,
block FPB_REMAP
};
};
define block SDRAM with fixed order {
block .sram2.text,
block .sram2.data,
section .sdram.text*,
section .sdram.data*,
section .mdns.text*,
section .mdns.data*,
block FPB_REMAP
};
define block SDRBSS with fixed order{
section .sdram.bss*
};
section .sdram.bss*
};
place at start of SDRAM_RAM_region {
block SDRAM,
block SDRBSS,
//block IMAGE1_DBG
place at start of SDRAM_RAM_region {
block SDRAM,
block SDRBSS,
//block IMAGE1_DBG
};
/* TCM placement */
define overlay TCM_overlay {
section .tcm.heap,
section .bss object lwip_mem.o,
section .bss object lwip_memp.o,
block .heap,
block .stack_dummy
};
section .tcm.heap,
section .bss object lwip_mem.o,
section .bss object lwip_memp.o,
block .heap,
block .stack_dummy
};
/* dummy code placement */
define overlay TCM_overlay { block IMAGE1_DBG };
place at start of TCM_region { overlay TCM_overlay };
place at end of TCM_region { block CSTACK};
place at start of TCM_region { overlay TCM_overlay };
place at end of TCM_region { block CSTACK};
define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
define exported symbol __rom_bss_start__ = 0x10000300; // use in rom
define exported symbol __rom_bss_end__ = 0x10000bc8; // use in rom
define exported symbol __ram_start_table_start__= 0x10000bc8; // use in rom
define exported symbol __image1_validate_code__= 0x10000bdc; // needed by ram code
define exported symbol _rtl_impure_ptr = 0x10001c60; // for standard library
define exported symbol __sdio_rom_bss_start__ = 0x1006D000;
define exported symbol __sdio_rom_bss_end__ = 0x1006fa10;

2
tools/targets/REALTEK_RTL8195AM.py
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@ -214,6 +214,8 @@ def parse_load_segment_iar(image_elf):
offset = int(segment[2][2:], 16)
addr = int(segment[3][2:], 16)
size = int(segment[5][2:], 16)
if addr < 0x10007000:
continue
if addr != 0 and size != 0:
segment_list.append((offset, addr, size))
return segment_list