Currently, trng_api.c is located in targets/ and AES/DES/SHA alter. are located in mbedtls/.
They have shared crypto code.
If they could locate at same location e.g. mbedtls/, the shared crypto code placement would be more reasonable.
Add counter to track crypto init among crypto sub-modules. It includes:
1. Enable crypto clock
2. Enable crypto interrupt
As counter gets zero, crypto clock is disabled to save power.
which can be called from diferent contexts.
Orginal nordic critical primitives must been called in pairs
from exacly the same function. As mbed hal call it in separate
methods, so they are not suitable here.
As it does not share the codebase with RZ A1H, it needs to be disabled until
bring it up to date with the latest changes to cmsis. There are changes
regarding caches, mmu and others
Merged from the existing TARGET_DISCO_F413ZH code (which has the same MCU)
and TARGET_NUCLEO_F412ZG code (which has the same Nucleo-144 board and
pinout).
Although the extened RTC is supported by #5363 commit ("Add support and tests for extended RTC"), it seems that the changes was overlooked in RZ_A1H_api.c.
So I added the changes with reference to other rtc_api.c.
I changed disable_irq() / enable_irq() to core_util_critical_section_enter() / core_util_critical_section_exit() by utilizing "mbed_critical" function in the below drivers.
- serial_api.c
- us_ticker.c
I added the below definitions for working "Dynamic Stack" and "Dynamic heap" on Mbed OS by referencing with the codes of Cortex-M target board.
"ISR_STACK_START", "ISR_STACK_SIZE", "INITIAL_SP", "HEAP_START" and "HEAP_SIZE"
By updating to the codes of CMSIS5/RTX5, GIC_SetConfigration() function was added for Cortex-A, this function is set the interrupt configuration using GIC's ICFGR register. Therefore, I added this function to satisfy Cortex-A interrupt spec in the below files.
"can_api.c", "ethernet_api.c", "gpio_irq_api.c", "i2c_api.c", "spi_api.c" and "us_ticker.c"
For supporting tp CMSIS5/RTX5, I changed the start-up processing of 3 toolchains(ARMCC, GCC_ARM, IAR) and updated the register definition of PEACH specific.
In addition,
I changed the linker script files to implement the dynamic HEAP the same as Cortex-M targets.Since GR-PEACH's HEAP was a fixed area, I changed the label name(ZI_DATA to RW_IRAM1) and replaced the allocation of STACK/HEAP.
Set buffer for 1 sample in analogin_read_u16. Before it assumes the
buffer is set outside by the higher layer. Now it's temporarily
located on the stack since only the ADC value is returned.
Pending official update from STM, add memory barriers to the Ethernet
HAL code for the STM32F7xx family.
Cortex-M7 has a merging write buffer that is not automatically flushed
by accesses to devices, so without these DMBs, we sometimes lose synch
with the transmitter.
The DMBs are architecturally needed in every version of this HAL, but
adding just to the STM32F7 version for now to clear test, as the
problem has only been observed on Cortex-M7-based devices.
Fixes#5622.
Filter numbers 14 to 27 are reserved for dual CAN configuration.
However, CAN3 operates in single CAN configuration according to the
reference manual).
CAN_2 and CAN_3 are enum and not #define and this causes compilation error with GCC_ARM
Instead put back the test of CAN_NUM (which are defined in can_device.h).
Ensure all instance memory blocks meet 4 byte alignment requirement
without relying on compiler's or liker's optional settings:
- gpioMemory[] for adi_gpio_Init()
- aRtcDevMem0[] for adi_rtc_Open()
- i2c_Mem[] or I2C_Mem[] for adi_i2c_Open()
- spi_Mem0[], spi_Mem1[], spi_Mem2[] or SPI_Mem[] for adi_spi_Open()
Add RSF synchro during init
Set a better WakeUp clock for long wake up period in order to stay in sleep mode
Use rtc_isenabled function before init as rtc_init is called at each set_time call
- Maintain compatible code for ARM 5 and ARM 6 while default alignment
settings differ.
- Instance memory containing memory pointers must be 4 byte aligned for
all compilers regardless compilers' settings.
- uint32_t is recommended to replace uint8_t for instance memory
declaration because uint32_t guarantee 4 byte alignment.
bcostm
ccli8
Jimmy Brisson
Andrzej Puzdrowski
Martin Kojtal
gorazd
Anna Bridge
Adam Heinrich
Cruz Monrreal II
Ashok Rao
jeromecoutant
TomoYamanaka
Dave Wu
Dexter Fryar
Kevin Bracey
Bilal
Prashant Ravi
Maciej Rogozinski
Edmund Hsu
Przemyslaw Stekiel
Steven Cooreman