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5768 Commits (489c30f5692ae5a990635d1a72aab6746d77fabf)

Author SHA1 Message Date
Anna Bridge 489c30f569
Merge pull request #11297 from kyle-cypress/pr/qspi-dummy-cycles 
Differentiate alt and dummy cycles in QSPIF
 2019-10-11 14:34:17 +01:00
Anna Bridge 97e11cc781
Merge pull request #11176 from OpenNuvoton/nuvoton_m252kg 
Support Nuvoton target NUMAKER_M252KG
 2019-10-11 14:33:06 +01:00
Anna Bridge 1798c246cc
Merge pull request #11625 from gpsimenos/gp-revert-tickless-ublox-odin 
Revert tickless on UBLOX_EVK_ODIN_W2
 2019-10-08 10:45:43 +01:00
Anna Bridge f1295b9aa7
Merge pull request #11573 from felser/add_413_dragonfly 
Add 413 dragonfly
 2019-10-07 16:48:07 +01:00
Anna Bridge f987fe0b32
Merge pull request #11542 from morser499/pr/target-update 
Update Cypress targets
 2019-10-07 16:44:59 +01:00
Anna Bridge 7eb8807a76
Merge pull request #11589 from jamesbeyond/fm_psa 
Enable PSA tests for fastmodel
 2019-10-04 12:01:19 +01:00
George Psimenos 508775c240 Revert tickless on UBLOX_EVK_ODIN_W2 2019-10-03 15:57:25 +01:00
Martin Kojtal fda544a14c
Merge pull request #11566 from trowbridgec/add-default-connectivity-config-for-ep-agora 
EP_AGORA: Add config logic to enable BLE, cell, and LoRa by default
 2019-10-01 13:17:59 +02:00
Kyle Kearney 9b32c0f316 Fix possible negative QSPI alt count on STM 
Remove an extraneous decrement operation in cases where the alt
bits size is a multiple of 8.
 2019-09-30 16:00:24 -07:00
Matthew Macovsky baf375f8cb Allow for arbitrary QSPI alt sizes 
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
 2019-09-30 14:45:08 -07:00
Ben Cooke dd778c4126 Add MTS_DRAGONFLY_F413RH platform to mbed-os 2019-09-30 13:50:40 -05:00
Qinghao Shi bdff628a6c FASTMODEL: add a comment for TRNG simulation 2019-09-30 16:43:44 +01:00
Qinghao Shi 5089d9de87 FASTMODEL: update trng based on comments 2019-09-30 16:30:51 +01:00
Martin Kojtal 7e62cafc82
Merge pull request #11585 from marcemmers/nrf_port_api 
NRF52: Fixed missing guard in port_api.c
 2019-09-30 14:46:31 +02:00
Martin Kojtal fa327ea16a
Merge pull request #11583 from jeromecoutant/PULL_REQUEST_CUBE_UPDATE_H7_V1.5.0 
STM32H7 ST CUBE V1.5.0 update
 2019-09-30 13:59:32 +02:00
Marc Emmers a02c50d768 Add newline at end of file 2019-09-30 11:20:56 +02:00
Ryan Morse 54d962a240 Moved TriggerMux initialization out of the HAL and into the BSP since that is what dictates what trigger muxes actually need to be used 2019-09-27 13:01:38 -07:00
Qinghao Shi a3f82738dd FASTMODEL: enable PSA tests for fastmodel 2019-09-27 15:59:42 +01:00
Qinghao Shi 4bbbad3d79 FASTMODEL: add simulated TRNG implementation to fastmodel 2019-09-27 15:58:28 +01:00
Marc Emmers 4c1067b8b8 Fixed missing #if in port_api.c 2019-09-27 14:44:20 +02:00
Chun-Chieh Li f45ca72f11 [M252KG] Remove TRNG support 
Reasons to remove TRNG support:
1.  M252 just has 32KiB SRAM and cannot afford mbedtls application.
2.  Implementing TRNG HAL with PRNG H/W has security concern.
 2019-09-27 17:50:48 +08:00
Chun-Chieh Li 0168304e5b [M252KG] Add BSD-3-Clause license for BSP files 2019-09-27 17:45:57 +08:00
Chun-Chieh Li 967effe59f [M252KG] Free up peripheral pins in peripheral free-up HAL API 
Without free-up of peripheral pins, peripheral pins of the same peripheral may
share by multiple ports after port iteration, and this peripheral may fail with
pin interference.
 2019-09-27 17:45:56 +08:00
Chun-Chieh Li 38aaee0c1a [M252KG] Support GPIO input pull-high/pull-low 
In Nuvoton, only new-design chips support GPIO input pull-high/pull-low modes.
Targets not supporting this feature are listed below:

- NUMAKER_PFM_NANO130
- NUMAKER_PFM_NUC472
- NUMAKER_PFM_M453
 2019-09-27 17:45:56 +08:00
Chun-Chieh Li 1447d9049f [M252KG] Fix redundant call to UART IRQ handler 
Honor RxIrq/TxIrq to avoid redundant call to UART IRQ handler.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-uart.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li d9217ed77a [M252KG] Fix redundant SPI clock generation 
Fix SPI clocks are generated redundantly at the end of transfer.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/
SPI - async mode.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li c68af32a4c [M252KG] Fix I2C NACK error 
Fix logic error on replying NACK at the end of transfer.

This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-i2c/
i2c - test single byte read i2c API.
 2019-09-27 17:45:55 +08:00
Chun-Chieh Li 0917a0d5a6 [M252KG] Fix IP initialization sequence 
Better IP initialization sequence:
1. Configure IP pins
2. Select IP clock source and then enable it
3. Reset the IP (SYS_ResetModule)

NOTE1: IP reset takes effect regardless of IP clock. So it doesn't matter if
       IP clock enable is before IP reset.
NOTE2: Non-configured pins may disturb IP's state, so IP pinout first and then
       IP reset.
NOTE3: IP reset at the end of IP initialization sequence can cover unexpected
       situation.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li 4bb7fde6b5 [M252KG] Exclude USB UART from testing 
USB UART is dedicated to USB COM and so must exclude from FPGA CI testing.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li cd73422345 [M252KG] Force enum PinName to 32-bit 
NU_PINNAME_BIND(...) requires enum PinName to be 32-bit to encode module
binding information in it.
 2019-09-27 17:45:54 +08:00
Chun-Chieh Li a8f0817cdb [M252KG] Enlarge LPTICKER_DELAY_TICKS for safe 
On Nuvoton targets, lp_ticker_set_interrupt(...) needs around 3 lp-ticker
ticks to take effect. It may miss when current tick and match tick are very
close (see hal/LowPowerTickerWrapper.cpp). Enlarge LPTICKER_DELAY_TICKS to
4 from 3 to address this boundary case.
 2019-09-27 17:45:53 +08:00
Chun-Chieh Li a5afcd6115 [M252KG] Enlarge required deep sleep latency 
This configuration is to pass wake-up from deep-sleep test such as mbedmicro-rtos-mbed-systimer.
 2019-09-27 17:45:53 +08:00
Chun-Chieh Li 538f55f9ff [M252KG] Add 'sectors' target configuration parameter 2019-09-27 17:45:53 +08:00
Chun-Chieh Li d0ffd9510f [M252KG] Override mpu-rom-end to 0x1fffffff 
Without this override, mpu hal will require 5 mpu regions which exceed 4 mpu
regions supported by M252 (see hal/mpu/mbed_mpu_v8m.c). In this scenario,
we will hit assert error but we actually meet stack overrun first due to just
0x400 bytes for emitting error message. The issue doesn’t occur on other
targets such as M487 because it has 8 mpu regions.
 2019-09-27 17:45:52 +08:00
Chun-Chieh Li 36278618ad Support Nuvoton's NUMAKER_M252KG target 2019-09-27 17:45:52 +08:00
jeromecoutant fff88617b7 STM32H7 ST CUBE V1.5.0 update 2019-09-27 11:39:06 +02:00
Martin Kojtal fff888b118
Merge pull request #11562 from VVESTM/vve_h7_memmap 
STM32H7: memory relocation
 2019-09-26 14:01:23 +02:00
Martin Kojtal 698e75f336
Merge pull request #11529 from vmedcy/pr/psoc6pdl-1.3.1 
PSOC6: update to PDL 1.3.1
 2019-09-26 12:24:06 +02:00
Chris Trowbridge eb6a474ba8 EP_AGORA: Add config logic to enable BLE, cell, and LoRa by default 2019-09-25 12:28:04 -04:00
Volodymyr Medvid d199fa6bb4 PSOC6: update to PDL 1.3.1.1499 2019-09-24 17:43:23 +03:00
Martin Kojtal 65d5c72cbd
Merge pull request #11404 from lrusinowicz/interrupt_in_fix 
FUTURE_SEQUANA: InterruptIn implementation bug fix
 2019-09-24 13:20:39 +02:00
Martin Kojtal f513bce4a3
Merge pull request #11480 from gpsimenos/gp-enable-tickless-stage2 
Enable tickless mode in additional tested targets
 2019-09-23 11:42:58 +02:00
Martin Kojtal 1f5a124820
Merge pull request #11117 from Terstegge/target_msp432_support 
Target msp432 support
 2019-09-20 15:02:35 +02:00
Martin Kojtal bb1338d07d
Merge pull request #11525 from jeromecoutant/PR_LSI 
STM32WB/STM32H7 : LSI selection when LSE is not available
 2019-09-20 14:19:58 +02:00
Martin Kojtal c225f8f1e7
Merge pull request #11516 from kyle-cypress/pr/hal-update 
Update to latest psoc6csp
 2019-09-20 14:18:13 +02:00
Martin Kojtal 77dd6f02a0
Merge pull request #11463 from gpsimenos/gp-enable-tickless-stage1 
Enable tickless mode in MAX32630FTHR
 2019-09-20 14:13:32 +02:00
Martin Kojtal 6790e64bd8
Merge pull request #11347 from woodsking2/master 
Fix NRF52832 softdevice memory map
 2019-09-20 14:09:42 +02:00
James Wang 876b643a9d remove NRF52840, NRF52832 static_memory_defines set 
static_memory_defines controls the macro MBED_RAM_START AND MBED_RAM_SIZE
when nrf52840 to use softdevice, it need MBED_RAM_START to set the true application ram start

default static_memory_defines is true, so just remove NRF52840 and NRF52832's set
 2019-09-20 11:34:35 +08:00
Kyle Kearney f0fdee4a1c Clean up BSP hardware configuration 
- Improve block naming
- Remove unneeded items
 2019-09-19 12:05:25 -07:00
Kyle Kearney 2831dfde1c Update CY8CPROTO-064-SB linker scripts 
Update linker scripts for the latest PDL to be consistent with other Cypress targets
 2019-09-19 12:03:32 -07:00