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Merge pull request #11542 from morser499/pr/target-update 

Update Cypress targets
pull/11645/head
Anna Bridge 2019-10-07 16:44:59 +01:00 committed by GitHub
parent 5108f9188d f0fdee4a1c
commit f987fe0b32
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
98 changed files with 3930 additions and 3612 deletions
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15
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,6 +24,14 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_UART_CLK_DIV_HW,
.channel_num = CYBSP_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
{
@ -52,6 +60,13 @@
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -35,6 +35,9 @@
extern "C" {
#endif
#define CYBSP_UART_CLK_DIV_ENABLED 1U
#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_UART_CLK_DIV_NUM 0U
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 1U
@ -45,6 +48,9 @@ extern "C" {
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -24,6 +24,20 @@
#include "cycfg_peripherals.h"
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
.epBuffer = NULL,
.epBufferSize = 0U,
.dmaConfig[0] = NULL,
.dmaConfig[1] = NULL,
.dmaConfig[2] = NULL,
.dmaConfig[3] = NULL,
.dmaConfig[4] = NULL,
.dmaConfig[5] = NULL,
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USBUART_obj =
{
.type = CYHAL_RSC_USB,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
@ -163,4 +202,9 @@ void init_cycfg_peripherals(void)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
#endif //defined (CY_USING_HAL)
}

13
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -37,6 +37,7 @@
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
@ -113,6 +114,14 @@ extern "C" {
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

87
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -216,6 +216,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_USB_DP_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_USB_DP_PORT_NUM,
.channel_num = CYBSP_USB_DP_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_USB_DM_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_USB_DM_PORT_NUM,
.channel_num = CYBSP_USB_DM_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
{
.outVal = 1,
@ -408,6 +456,30 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
.intEdge = CY_GPIO_INTR_RISING,
.intMask = 1UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
{
.outVal = 1,
@ -812,6 +884,16 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
#endif //defined (CY_USING_HAL)
@ -851,6 +933,11 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);

84
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -228,6 +228,54 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_USB_DP_ENABLED 1U
#define CYBSP_USB_DP_PORT GPIO_PRT14
#define CYBSP_USB_DP_PORT_NUM 14U
#define CYBSP_USB_DP_PIN 0U
#define CYBSP_USB_DP_NUM 0U
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_0_HSIOM
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_USB_DM_ENABLED 1U
#define CYBSP_USB_DM_PORT GPIO_PRT14
#define CYBSP_USB_DM_PORT_NUM 14U
#define CYBSP_USB_DM_PIN 1U
#define CYBSP_USB_DM_NUM 1U
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_1_HSIOM
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_RX_ENABLED 1U
#define CYBSP_CSD_RX_PORT GPIO_PRT1
#define CYBSP_CSD_RX_PORT_NUM 1U
@ -420,6 +468,30 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT4
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 4U
#define CYBSP_WIFI_HOST_WAKE_PIN 1U
#define CYBSP_WIFI_HOST_WAKE_NUM 1U
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
#ifndef ioss_0_port_4_pin_1_HSIOM
#define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_4_pin_1_HSIOM
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P4_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_RISE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_EZI2C_SCL_ENABLED 1U
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
@ -813,6 +885,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
@ -845,6 +925,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,7 +24,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
&S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,19 +28,19 @@
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -73,7 +73,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.refDiv = 20U,
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
.enableOutputDiv = true,
.lockTolerance = 10U,
.lockTolerance = 4U,
.igain = 9U,
.pgain = 5U,
.settlingCount = 8U,

30
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,34 +1,6 @@
[Device="CY8C624ABZI-D44"]
[Device=CY8C624ABZI-D44]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[11].pin[1]
# CYBSP_USER_LED2
ioss[0].port[1].pin[5]
# CYBSP_USER_LED3
ioss[0].port[1].pin[1]
# CYBSP_USER_LED4
ioss[0].port[0].pin[5]
# CYBSP_USER_LED5
ioss[0].port[7].pin[3]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# CYBSP_USER_BTN2
ioss[0].port[1].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[5]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[1]
# CYBSP_DEBUG_UART_RTS
ioss[0].port[5].pin[2]
# CYBSP_DEBUG_UART_CTS
ioss[0].port[5].pin[3]
# WIFI
# CYBSP_WIFI_SDIO
sdhc[0]

82
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C624ABZI-D44">
@ -124,6 +124,26 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_RX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -204,6 +224,16 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[4].pin[1]" alias="CYBSP_WIFI_HOST_WAKE" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_RISING"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_EZI2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
@ -354,6 +384,11 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_16[0]" alias="CYBSP_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="720"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_16[1]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="78"/>
<Param id="fracDivider" value="0"/>
@ -467,7 +502,7 @@
<Param id="hibernate" value="true"/>
</Block>
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
<Param id="trim" value="0.25"/>
</Block>
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="ilo"/>
@ -525,7 +560,6 @@
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@ -565,6 +599,27 @@
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
<Param id="epMask" value="0"/>
<Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
<Param id="bufSize" value="512"/>
<Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
<Param id="enableLpm" value="false"/>
<Param id="lpmIntr" value="0x0U"/>
<Param id="ArbIntr" value="0x0U"/>
<Param id="ep0CntrIntr" value="0x2U"/>
<Param id="busResetIntr" value="0x2U"/>
<Param id="sofIntr" value="0x1U"/>
<Param id="ep0Intr" value="0x1U"/>
<Param id="ep1Intr" value="0x1U"/>
<Param id="ep2Intr" value="0x1U"/>
<Param id="ep3Intr" value="0x1U"/>
<Param id="ep4Intr" value="0x1U"/>
<Param id="ep5Intr" value="0x1U"/>
<Param id="ep6Intr" value="0x1U"/>
<Param id="ep7Intr" value="0x1U"/>
<Param id="inFlash" value="true"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
@ -639,6 +694,18 @@
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[0].aux[0]"/>
<Port name="usb[0].usb_dp_pad[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[1].aux[0]"/>
<Port name="usb[0].usb_dm_pad[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="usb[0].clock_dev_brs[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[1].clk[0]"/>
<Port name="scb[2].clock[0]"/>
@ -655,6 +722,10 @@
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
<Net>
<Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
<Port name="usb[0].clk_usb_dev[0]"/>
</Net>
<Mux name="sense" location="csd[0].csd[0]">
<Arm>
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
@ -700,9 +771,6 @@
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="bt_sdk" version="1.1"/>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<Libraries/>
<ConfiguratorData/>
</Design>

112
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* \file CY8CKIT-062S2-43012/cybsp.c
* \file cybsp.c
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CKIT-062S2-43012 pioneer kit.
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
@ -32,11 +32,51 @@
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
cy_rslt_t result;
result = cyhal_hwmgr_init();
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
cy_rslt_t result = cyhal_hwmgr_init();
init_cycfg_system();
if (CY_RSLT_SUCCESS == result)
@ -44,57 +84,35 @@ cy_rslt_t cybsp_init(void)
result = cybsp_register_sysclk_pm_callback();
}
#ifndef __MBED__
if (CY_RSLT_SUCCESS == result)
{
/* Initialize User LEDs */
/* Reserves: CYBSP_USER_LED1 */
result |= cybsp_led_init(CYBSP_USER_LED1);
/* Reserves: CYBSP_USER_LED2 */
result |= cybsp_led_init(CYBSP_USER_LED2);
/* Reserves: CYBSP_USER_LED3 */
result |= cybsp_led_init(CYBSP_USER_LED3);
/* Reserves: CYBSP_USER_LED4 */
result |= cybsp_led_init(CYBSP_USER_LED4);
/* Reserves: CYBSP_USER_LED5 */
result |= cybsp_led_init(CYBSP_USER_LED5);
/* Initialize User Buttons */
/* Reserves: CYBSP_USER_BTN1 */
result |= cybsp_btn_init(CYBSP_USER_BTN1);
/* Reserves: CYBSP_USER_BTN2 */
result |= cybsp_btn_init(CYBSP_USER_BTN2);
CY_ASSERT(CY_RSLT_SUCCESS == result);
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RTS, CYBSP_DEBUG_UART_CTS
* corresponding SCB instance and one of available clock dividers */
result = cybsp_retarget_init();
}
}
#endif /* __MBED__ */
#if defined(CYBSP_WIFI_CAPABLE)
/* Initialize SDIO interface.
NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done
when starting up WiFi. */
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */
result = cybsp_wifi_sdio_init();
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both. */
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}
#if defined(__cplusplus)
}
#endif

53
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp.h
View File

@ -1,9 +1,8 @@
/***************************************************************************//**
* \file CY8CKIT-062S2-43012/cybsp.h
* \file cybsp.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CKIT-062S2-43012 pioneer kit.
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
@ -25,22 +24,50 @@
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_core.h"
#if defined(CYBSP_WIFI_CAPABLE)
#include "cybsp_wifi_sdio.h"
#include "cyhal_sdio.h"
#endif
#ifndef __MBED__
#include "cybsp_retarget.h"
#include "cybsp_serial_flash.h"
#include "cybsp_rgb_led.h"
#endif /* __MBED__ */
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
#if defined(__cplusplus)
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */

421
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/cybsp_types.h
View File

@ -25,256 +25,221 @@
#pragma once
#include "cyhal.h"
#include "cyhal_pin_package.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P0_2
/** Arduino D8 */
#define CYBSP_D8 P13_0
/** Arduino D9 */
#define CYBSP_D9 P13_1
/** Arduino D10 */
#define CYBSP_D10 P12_3
/** Arduino D11 */
#define CYBSP_D11 P12_0
/** Arduino D12 */
#define CYBSP_D12 P12_1
/** Arduino D13 */
#define CYBSP_D13 P12_2
/** Arduino D14 */
#define CYBSP_D14 P6_1
/** Arduino D15 */
#define CYBSP_D15 P6_0
/** Pin: WCO input */
#define CYBSP_WCO_IN P0_0
/** Pin: WCO output */
#define CYBSP_WCO_OUT P0_1
/** Pin: WIFI SDIO D0 */
/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: WIFI SDIO D1 */
/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: WIFI SDIO D2 */
/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: WIFI SDIO D3 */
/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: WIFI SDIO CMD */
/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: WIFI SDIO CLK */
/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: WIFI ON */
/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE P4_1
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX P3_0
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX P3_1
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS P3_2
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS P3_3
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE P4_0
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE P3_5
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[2], scb[5] */
#define CYBSP_DEBUG_UART_RTS P5_2
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[3], scb[5] */
#define CYBSP_DEBUG_UART_CTS P5_3
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL P6_0
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA P6_1
/** Pin: SWO */
#define CYBSP_SWO P6_4
/** Pin: SWDIO */
#define CYBSP_SWDIO P6_6
/** Pin: SWDCK */
#define CYBSP_SWDCK P6_7
/** Pin: CapSesnse RX */
#define CYBSP_CSD_RX P1_0
/** Pin: CapSesnse CINA */
#define CYBSP_CINA P7_1
/** Pin: CapSesnse CINB */
#define CYBSP_CINB P7_2
/** Pin: CapSesnse CMOD */
#define CYBSP_CMOD P7_7
/** Pin: CapSesnse Button 0 */
#define CYBSP_CSD_BTN0 P8_1
/** Pin: CapSesnse Button 1 */
#define CYBSP_CSD_BTN1 P8_2
/** Pin: CapSesnse Slider 0 */
#define CYBSP_CSD_SLD0 P8_3
/** Pin: CapSesnse Slider 1 */
#define CYBSP_CSD_SLD1 P8_4
/** Pin: CapSesnse Slider 2 */
#define CYBSP_CSD_SLD2 P8_5
/** Pin: CapSesnse Slider 3 */
#define CYBSP_CSD_SLD3 P8_6
/** Pin: CapSesnse Slider 4 */
#define CYBSP_CSD_SLD4 P8_7
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
/** BSP user LED reference designator to pin mapping */
#define LED9_R P11_1
/** BSP user LED reference designator to pin mapping */
#define LED8_O P1_5
/** BSP user LED reference designator to pin mapping */
#define LED5_RGB_R P1_1
/** BSP user LED reference designator to pin mapping */
#define LED5_RGB_G P0_5
/** BSP user LED reference designator to pin mapping */
#define LED5_RGB_B P7_3
/** BSP LED defines by LED color */
#define CYBSP_LED_RED LED5_RGB_R
/** BSP LED defines by LED color */
#define CYBSP_LED_GREEN LED5_RGB_G
/** BSP LED defines by LED color */
#define CYBSP_LED_BLUE LED5_RGB_B
/** BSP LED defines by LED color */
#define CYBSP_LED_ORANGE LED8
/** BSP user button reference designator to pin mapping */
#define SW2 P0_4
/** BSP user button reference designator to pin mapping */
#define SW4 P1_4
/** \} group_bsp_cy8ckit_pins */
/**
* \addtogroup group_bsp_enums Enumerated Types
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** Enum defining the different states for the LED. */
typedef enum
{
CYBSP_LED_STATE_ON = 0,
CYBSP_LED_STATE_OFF = 1,
} cybsp_led_state_t;
/** LED 8; User LED1 (orange) */
#define CYBSP_LED8 (P1_5)
/** LED 9; User LED2 (red) */
#define CYBSP_LED9 (P11_1)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_LED_RGB_RED (P1_1)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_LED_RGB_GREEN (P0_5)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_LED_RGB_BLUE (P7_3)
/** Enum defining the different states for a button. */
typedef enum
{
CYBSP_BTN_PRESSED = 0,
CYBSP_BTN_OFF = 1,
} cybsp_btn_state_t;
/** LED 8; User LED1 (orange) */
#define CYBSP_USER_LED1 (CYBSP_LED8)
/** LED 9; User LED2 (red) */
#define CYBSP_USER_LED2 (CYBSP_LED9)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
/** LED 8; User LED1 (orange) */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** \} group_bsp_pins_led */
/** Enum defining the different user LEDs available on the board. */
typedef enum
{
CYBSP_LED_RGB_RED = LED5_RGB_R,
CYBSP_LED_RGB_GREEN = LED5_RGB_G,
CYBSP_LED_RGB_BLUE = LED5_RGB_B,
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/* Corresponds to: ioss[0].port[11].pin[1] */
CYBSP_USER_LED1 = LED9_R,
/* Corresponds to: ioss[0].port[1].pin[5] */
CYBSP_USER_LED2 = LED8_O,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[0].pin[5] */
CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[7].pin[3] */
CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
/** Switch 2; User Button 1 */
#define CYBSP_SW2 (P0_4)
/** Switch 4; User Button 2 */
#define CYBSP_SW4 (P1_4)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW2)
/** Switch 4; User Button 2 */
#define CYBSP_USER_BTN2 (CYBSP_SW4)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_pins_btn */
/** Enum defining the different user buttons available on the board. */
typedef enum
{
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = SW2,
/* Corresponds to: ioss[0].port[1].pin[4] */
CYBSP_USER_BTN2 = SW4,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P4_1)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P3_0)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P3_1)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P3_2)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P3_3)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P3_4)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P4_0)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P3_5)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_1)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RTS (P5_2)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_CTS (P5_3)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** \} group_bsp_pins_comm */
/** \} group_bsp_enums */
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 (P5_0)
/** Arduino D1 */
#define CYBSP_D1 (P5_1)
/** Arduino D2 */
#define CYBSP_D2 (P5_2)
/** Arduino D3 */
#define CYBSP_D3 (P5_3)
/** Arduino D4 */
#define CYBSP_D4 (P5_4)
/** Arduino D5 */
#define CYBSP_D5 (P5_5)
/** Arduino D6 */
#define CYBSP_D6 (P5_6)
/** Arduino D7 */
#define CYBSP_D7 (P0_2)
/** Arduino D8 */
#define CYBSP_D8 (P13_0)
/** Arduino D9 */
#define CYBSP_D9 (P13_1)
/** Arduino D10 */
#define CYBSP_D10 (P12_3)
/** Arduino D11 */
#define CYBSP_D11 (P12_0)
/** Arduino D12 */
#define CYBSP_D12 (P12_1)
/** Arduino D13 */
#define CYBSP_D13 (P12_2)
/** Arduino D14 */
#define CYBSP_D14 (P6_1)
/** Arduino D15 */
#define CYBSP_D15 (P6_0)
/** \} group_bsp_pins_arduino */
/** \} group_bsp_pins */
#if defined(__cplusplus)
}

24
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,24 +1,4 @@
[Device="CY8C6347BZI-BLD53"]
[Device=CY8C6347BZI-BLD53]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[1].pin[5]
# CYBSP_USER_LED2
ioss[0].port[13].pin[7]
# CYBSP_USER_LED3
ioss[0].port[0].pin[3]
# CYBSP_USER_LED4
ioss[0].port[1].pin[1]
# CYBSP_USER_LED5
ioss[0].port[11].pin[1]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[5]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[1]
# Nothing needs to be reserved for this device

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -560,8 +560,6 @@
</Netlist>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<Libraries/>
<ConfiguratorData/>
</Design>

102
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.c
View File

@ -1,8 +1,9 @@
/***************************************************************************//**
* \file CY8CKIT-062-BLE/cybsp.c
* \file cybsp.c
*
* Description:
* Provides basic hardware initialization for the CY8CKIT-062-BLE pioneer kit.
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
@ -24,17 +25,58 @@
#include <stdlib.h>
#include "cybsp.h"
#include "cycfg_system.h"
#include "cyhal_utils.h"
#include "cycfg.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
cy_rslt_t result;
result = cyhal_hwmgr_init();
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
cy_rslt_t result = cyhal_hwmgr_init();
init_cycfg_system();
if (CY_RSLT_SUCCESS == result)
@ -42,38 +84,32 @@ cy_rslt_t cybsp_init(void)
result = cybsp_register_sysclk_pm_callback();
}
#ifndef __MBED__
#if defined(CYBSP_WIFI_CAPABLE)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Initialize User LEDs */
/* Reserves: CYBSP_USER_LED1 */
result |= cybsp_led_init(CYBSP_USER_LED1);
/* Reserves: CYBSP_USER_LED2 */
result |= cybsp_led_init(CYBSP_USER_LED2);
/* Reserves: CYBSP_USER_LED3 */
result |= cybsp_led_init(CYBSP_USER_LED3);
/* Reserves: CYBSP_USER_LED4 */
result |= cybsp_led_init(CYBSP_USER_LED4);
/* Reserves: CYBSP_USER_LED5 */
result |= cybsp_led_init(CYBSP_USER_LED5);
/* Initialize User Buttons */
/* Reserves: CYBSP_USER_BTN1 */
result |= cybsp_btn_init(CYBSP_USER_BTN1);
CY_ASSERT(CY_RSLT_SUCCESS == result);
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance and one of available
* clock dividers */
result = cybsp_retarget_init();
}
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* __MBED__ */
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both. */
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}

55
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp.h
View File

@ -1,9 +1,8 @@
/***************************************************************************//**
* \file CY8CKIT-062-BLE/cybsp.h
* \file cybsp.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CKIT-062-BLE pioneer kit.
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
@ -25,18 +24,50 @@
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_core.h"
#ifndef __MBED__
#include "cybsp_retarget.h"
#include "cybsp_serial_flash.h"
#include "cybsp_rgb_led.h"
#endif /* __MBED__ */
#if defined(CYBSP_WIFI_CAPABLE)
#include "cyhal_sdio.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(__cplusplus)
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */

298
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/cybsp_types.h
View File

@ -31,172 +31,168 @@
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P0_2
/** Arduino D8 */
#define CYBSP_D8 P13_0
/** Arduino D9 */
#define CYBSP_D9 P13_1
/** Arduino D10 */
#define CYBSP_D10 P12_3
/** Arduino D11 */
#define CYBSP_D11 P12_0
/** Arduino D12 */
#define CYBSP_D12 P12_1
/** Arduino D13 */
#define CYBSP_D13 P12_2
/** Arduino D14 */
#define CYBSP_D14 P6_1
/** Arduino D15 */
#define CYBSP_D15 P6_0
// Generic signal names
/** Pin: WCO input */
#define CYBSP_WCO_IN P0_0
/** Pin: WCO output */
#define CYBSP_WCO_OUT P0_1
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL P6_0
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA P6_1
/** Pin: SWO */
#define CYBSP_SWO P6_4
/** Pin: SWDIO */
#define CYBSP_SWDIO P6_6
/** Pin: SWDCK */
#define CYBSP_SWDCK P6_7
/** Pin: CapSesnse TX */
#define CYBSP_CSD_TX P1_0
/** Pin: CapSesnse CINA */
#define CYBSP_CINA P7_1
/** Pin: CapSesnse CINB */
#define CYBSP_CINB P7_2
/** Pin: CapSesnse CMOD */
#define CYBSP_CMOD P7_7
/** Pin: CapSesnse Button 0 */
#define CYBSP_CSD_BTN0 P8_1
/** Pin: CapSesnse Button 1 */
#define CYBSP_CSD_BTN1 P8_2
/** Pin: CapSesnse Slider 0 */
#define CYBSP_CSD_SLD0 P8_3
/** Pin: CapSesnse Slider 1 */
#define CYBSP_CSD_SLD1 P8_4
/** Pin: CapSesnse Slider 2 */
#define CYBSP_CSD_SLD2 P8_5
/** Pin: CapSesnse Slider 3 */
#define CYBSP_CSD_SLD3 P8_6
/** Pin: CapSesnse Slider 4 */
#define CYBSP_CSD_SLD4 P8_7
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_enums Enumerated Types
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** Enum defining the different states for the LED. */
typedef enum
{
CYBSP_LED_STATE_ON = 0,
CYBSP_LED_STATE_OFF = 1,
} cybsp_led_state_t;
/** LED 8; User LED1 */
#define CYBSP_LED8 (P1_5)
/** LED 9; User LED2 */
#define CYBSP_LED9 (P13_7)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_LED_RGB_RED (P0_3)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_LED_RGB_GREEN (P1_1)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_LED_RGB_BLUE (P11_1)
/** Enum defining the different states for a button. */
typedef enum
{
CYBSP_BTN_PRESSED = 0,
CYBSP_BTN_OFF = 1,
} cybsp_btn_state_t;
/** LED 8; User LED1 */
#define CYBSP_USER_LED1 (CYBSP_LED8)
/** LED 9; User LED2 */
#define CYBSP_USER_LED2 (CYBSP_LED9)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
/** LED 8; User LED1 */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** Enum defining the different LED pins on the board. */
typedef enum
{
CYBSP_LED9 = P13_7,
CYBSP_LED8 = P1_5,
CYBSP_LED_RGB_RED = P0_3,
CYBSP_LED_RGB_GREEN = P1_1,
CYBSP_LED_RGB_BLUE = P11_1,
/** \} group_bsp_pins_led */
/* Corresponds to: ioss[0].port[1].pin[5] */
CYBSP_USER_LED1 = CYBSP_LED8,
/* Corresponds to: ioss[0].port[13].pin[7] */
CYBSP_USER_LED2 = CYBSP_LED9,
/* Corresponds to: ioss[0].port[0].pin[3] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[11].pin[1] */
CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** Enum defining the different button pins on the board. */
typedef enum
{
CYBSP_SW2 = P0_4,
/** Switch 2; User Button 1 */
#define CYBSP_SW2 (P0_4)
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW2,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW2)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_enums */
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_1)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** \} group_bsp_pins_comm */
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 (P5_0)
/** Arduino D1 */
#define CYBSP_D1 (P5_1)
/** Arduino D2 */
#define CYBSP_D2 (P5_2)
/** Arduino D3 */
#define CYBSP_D3 (P5_3)
/** Arduino D4 */
#define CYBSP_D4 (P5_4)
/** Arduino D5 */
#define CYBSP_D5 (P5_5)
/** Arduino D6 */
#define CYBSP_D6 (P5_6)
/** Arduino D7 */
#define CYBSP_D7 (P0_2)
/** Arduino D8 */
#define CYBSP_D8 (P13_0)
/** Arduino D9 */
#define CYBSP_D9 (P13_1)
/** Arduino D10 */
#define CYBSP_D10 (P12_3)
/** Arduino D11 */
#define CYBSP_D11 (P12_0)
/** Arduino D12 */
#define CYBSP_D12 (P12_1)
/** Arduino D13 */
#define CYBSP_D13 (P12_2)
/** Arduino D14 */
#define CYBSP_D14 (P6_1)
/** Arduino D15 */
#define CYBSP_D15 (P6_0)
/** \} group_bsp_pins_arduino */
/** \} group_bsp_pins */
#if defined(__cplusplus)
}

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -28,7 +28,6 @@ void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_dmas();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -32,7 +32,6 @@ extern "C" {
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"

23
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -32,14 +32,6 @@
.channel_num = CYBSP_USB_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_SDIO_DIV_HW,
.channel_num = CYBSP_SDIO_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
{
@ -57,11 +49,11 @@
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t peri_0_div_8_4_obj =
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_div_8_4_HW,
.channel_num = peri_0_div_8_4_NUM,
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
@ -75,13 +67,6 @@ void init_cycfg_clocks(void)
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
@ -100,6 +85,6 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -38,25 +38,19 @@ extern "C" {
#define CYBSP_USB_CLK_DIV_ENABLED 1U
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_CLK_DIV_NUM 0U
#define CYBSP_SDIO_DIV_ENABLED 1U
#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_SDIO_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 3U
#define peri_0_div_8_4_ENABLED 1U
#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_4_NUM 4U
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 4U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
@ -64,7 +58,7 @@ extern "C" {
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);

230
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
View File

@ -1,230 +0,0 @@
/*******************************************************************************
* File Name: cycfg_dmas.c
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_dmas.h"
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_1D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 1,
.xCount = 6,
.srcYincrement = 0,
.dstYincrement = 0,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
{
.descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
.preemptable = true,
.priority = 1,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_16CYC,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_1D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 1,
.dstXincrement = 0,
.xCount = 5,
.srcYincrement = 0,
.dstYincrement = 0,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
{
.descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
.preemptable = true,
.priority = 1,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_X_LOOP,
.dataSize = CY_DMA_HALFWORD,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_2D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 2,
.dstXincrement = 0,
.xCount = 10,
.srcYincrement = 10,
.dstYincrement = 0,
.yCount = 2,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
{
.descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
.preemptable = false,
.priority = 0,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_X_LOOP,
.dataSize = CY_DMA_HALFWORD,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_2D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 2,
.xCount = 10,
.srcYincrement = 0,
.dstYincrement = 10,
.yCount = 2,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
{
.descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
.preemptable = false,
.priority = 0,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
#endif //defined (CY_USING_HAL)
}

87
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
View File

@ -1,87 +0,0 @@
/*******************************************************************************
* File Name: cycfg_dmas.h
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_DMAS_H)
#define CYCFG_DMAS_H
#include "cycfg_notices.h"
#include "cy_dma.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_DMAS_H */

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -118,7 +118,6 @@ extern "C" {
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_USB_CORE 4U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn

28
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -216,11 +216,11 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
.channel_num = CYBSP_QSPI_SCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = ioss_0_port_14_pin_0_HSIOM,
.hsiom = CYBSP_USB_DP_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
@ -233,18 +233,18 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj =
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = ioss_0_port_14_pin_0_PORT_NUM,
.channel_num = ioss_0_port_14_pin_0_PIN,
.block_num = CYBSP_USB_DP_PORT_NUM,
.channel_num = CYBSP_USB_DP_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = ioss_0_port_14_pin_1_HSIOM,
.hsiom = CYBSP_USB_DM_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
@ -257,11 +257,11 @@ const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config =
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj =
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = ioss_0_port_14_pin_1_PORT_NUM,
.channel_num = ioss_0_port_14_pin_1_PIN,
.block_num = CYBSP_USB_DM_PORT_NUM,
.channel_num = CYBSP_USB_DM_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
@ -884,14 +884,14 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(ioss_0_port_14_pin_0_PORT, ioss_0_port_14_pin_0_PIN, &ioss_0_port_14_pin_0_config);
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&ioss_0_port_14_pin_0_obj);
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(ioss_0_port_14_pin_1_PORT, ioss_0_port_14_pin_1_PIN, &ioss_0_port_14_pin_1_config);
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&ioss_0_port_14_pin_1_obj);
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)

58
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -228,51 +228,53 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define ioss_0_port_14_pin_0_ENABLED 1U
#define ioss_0_port_14_pin_0_PORT GPIO_PRT14
#define ioss_0_port_14_pin_0_PORT_NUM 14U
#define ioss_0_port_14_pin_0_PIN 0U
#define ioss_0_port_14_pin_0_NUM 0U
#define ioss_0_port_14_pin_0_DRIVEMODE CY_GPIO_DM_ANALOG
#define ioss_0_port_14_pin_0_INIT_DRIVESTATE 1
#define CYBSP_USB_DP_ENABLED 1U
#define CYBSP_USB_DP_PORT GPIO_PRT14
#define CYBSP_USB_DP_PORT_NUM 14U
#define CYBSP_USB_DP_PIN 0U
#define CYBSP_USB_DP_NUM 0U
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_0_HSIOM
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_14_pin_0_IRQ ioss_interrupts_gpio_14_IRQn
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_0_HAL_PORT_PIN P14_0
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_0_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define ioss_0_port_14_pin_1_ENABLED 1U
#define ioss_0_port_14_pin_1_PORT GPIO_PRT14
#define ioss_0_port_14_pin_1_PORT_NUM 14U
#define ioss_0_port_14_pin_1_PIN 1U
#define ioss_0_port_14_pin_1_NUM 1U
#define ioss_0_port_14_pin_1_DRIVEMODE CY_GPIO_DM_ANALOG
#define ioss_0_port_14_pin_1_INIT_DRIVESTATE 1
#define CYBSP_USB_DM_ENABLED 1U
#define CYBSP_USB_DM_PORT GPIO_PRT14
#define CYBSP_USB_DM_PORT_NUM 14U
#define CYBSP_USB_DM_PIN 1U
#define CYBSP_USB_DM_NUM 1U
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_1_HSIOM
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_14_pin_1_IRQ ioss_interrupts_gpio_14_IRQn
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_1_HAL_PORT_PIN P14_1
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_1_HAL_DIR CYHAL_GPIO_DIR_INPUT
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define ioss_0_port_14_pin_1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
@ -883,13 +885,13 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_0_config;
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t ioss_0_port_14_pin_0_obj;
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t ioss_0_port_14_pin_1_config;
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t ioss_0_port_14_pin_1_obj;
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
#if defined (CY_USING_HAL)

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,7 +24,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
&S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,19 +28,19 @@
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

48
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,31 +1,14 @@
[Device="CY8C6247BZI-D54"]
[Device=CY8C6247BZI-D54]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[1].pin[5]
# CYBSP_USER_LED2
ioss[0].port[13].pin[7]
# CYBSP_USER_LED3
ioss[0].port[0].pin[3]
# CYBSP_USER_LED4
ioss[0].port[1].pin[1]
# CYBSP_USER_LED5
ioss[0].port[11].pin[1]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[5]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[1]
# WIFI
# CYBSP_WIFI_SDIO
udb[0]
peri[0].div_8[0]
cpuss[0].dw0[0].chan[0]
cpuss[0].dw0[0].chan[1]
cpuss[0].dw1[0].chan[1]
cpuss[0].dw1[0].chan[3]
# CYBSP_WIFI_SDIO_D0
ioss[0].port[2].pin[0]
# CYBSP_WIFI_SDIO_D1
@ -39,4 +22,21 @@ ioss[0].port[2].pin[4]
# CYBSP_WIFI_SDIO_CLK
ioss[0].port[2].pin[5]
# CYBSP_WIFI_WL_REG_ON
ioss[0].port[2].pin[6]
ioss[0].port[2].pin[6]
[RoutingResources]
# CYBSP_WIFI_SDIO
cpuss[0].dw0_tr_in[0]
cpuss[0].dw0_tr_in[1]
cpuss[0].dw1_tr_in[1]
cpuss[0].dw1_tr_in[3]
udb[0].tr_udb[0]
udb[0].tr_udb[1]
udb[0].tr_udb[3]
udb[0].tr_udb[7]
tr_group[0].input[43]
tr_group[0].input[44]
tr_group[0].input[47]
tr_group[0].input[48]

130
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -8,114 +8,6 @@
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="false"/>
</Block>
<Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="1"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="true"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
<Param id="X_SRC_INCREMENT_0" value="0"/>
<Param id="X_DST_INCREMENT_0" value="1"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="1"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="true"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
<Param id="X_SRC_INCREMENT_0" value="1"/>
<Param id="X_DST_INCREMENT_0" value="0"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="0"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="false"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
<Param id="X_SRC_INCREMENT_0" value="2"/>
<Param id="X_DST_INCREMENT_0" value="0"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
<Param id="Y_SRC_INCREMENT_0" value="10"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="0"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="false"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
<Param id="X_SRC_INCREMENT_0" value="0"/>
<Param id="X_DST_INCREMENT_0" value="2"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="10"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CSD" template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
@ -232,7 +124,7 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[0]" alias="" template="mxs40pin" version="1.1">
<Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@ -242,7 +134,7 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[1]" alias="" template="mxs40pin" version="1.1">
<Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
@ -497,11 +389,6 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="8"/>
<Param id="fracDivider" value="0"/>
@ -512,7 +399,7 @@
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[4]" alias="" template="mxs40peripheralclock" version="1.0">
<Block location="peri[0].div_8[4]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
@ -673,7 +560,6 @@
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@ -713,12 +599,10 @@
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
<Param id="configurator" value="0"/>
<Param id="UsbCore" value="4"/>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
<Param id="epMask" value="0"/>
<Param id="bufSize" value="512"/>
<Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
<Param id="bufSize" value="512"/>
<Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
<Param id="enableLpm" value="false"/>
<Param id="lpmIntr" value="0x0U"/>
@ -887,8 +771,6 @@
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<Libraries/>
<ConfiguratorData/>
</Design>

109
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* \file CY8CKIT-062-WIFI-BT/cybsp.c
* \file cybsp.c
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CKIT-062-WIFI-BT pioneer kit.
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
@ -32,11 +32,51 @@
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
cy_rslt_t result;
result = cyhal_hwmgr_init();
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
cy_rslt_t result = cyhal_hwmgr_init();
init_cycfg_system();
if (CY_RSLT_SUCCESS == result)
@ -44,51 +84,32 @@ cy_rslt_t cybsp_init(void)
result = cybsp_register_sysclk_pm_callback();
}
#ifndef __MBED__
if (CY_RSLT_SUCCESS == result)
{
/* Initialize User LEDs */
/* Reserves: CYBSP_USER_LED1 */
result |= cybsp_led_init(CYBSP_USER_LED1);
/* Reserves: CYBSP_USER_LED2 */
result |= cybsp_led_init(CYBSP_USER_LED2);
/* Reserves: CYBSP_USER_LED3 */
result |= cybsp_led_init(CYBSP_USER_LED3);
/* Reserves: CYBSP_USER_LED4 */
result |= cybsp_led_init(CYBSP_USER_LED4);
/* Reserves: CYBSP_USER_LED5 */
result |= cybsp_led_init(CYBSP_USER_LED5);
/* Initialize User Buttons */
/* Reserves: CYBSP_USER_BTN1 */
result |= cybsp_btn_init(CYBSP_USER_BTN1);
CY_ASSERT(CY_RSLT_SUCCESS == result);
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance
* and one of available clock dividers */
result = cybsp_retarget_init();
}
}
#endif /* __MBED__ */
#if defined(CYBSP_WIFI_CAPABLE)
/* Initialize UDB SDIO interface. This must be done before any other HAL API attempts to allocate clocks or DMA
instances. The UDB SDIO interface uses specific instances which are reserved as part of this call.
NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done
when starting up WiFi. */
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */
result = cybsp_wifi_sdio_init();
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both. */
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}

59
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp.h
View File

@ -1,9 +1,8 @@
/***************************************************************************//**
* \file CY8CKIT-062-WIFI-BT/cybsp.h
* \file cybsp.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CKIT-062-WIFI-BT pioneer kit.
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
@ -25,28 +24,50 @@
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_core.h"
#if defined(CYBSP_WIFI_CAPABLE)
#include "cybsp_wifi_sdio.h"
#include "cyhal_sdio.h"
#endif
#ifndef __MBED__
#include "cybsp_retarget.h"
#include "cybsp_serial_flash.h"
#include "cybsp_rgb_led.h"
#endif /* __MBED__ */
#if defined(__cplusplus)
extern "C" {
#endif
// HAL HW configuration data
extern cyhal_qspi_t cybsp_qspi;
extern cyhal_uart_t cybsp_bt_uart;
extern cyhal_uart_t cybsp_debug_uart;
extern cyhal_i2c_t cybsp_i2c;
extern cyhal_rtc_t cybsp_rtc;
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
#if defined(__cplusplus)
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */

384
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/cybsp_types.h
View File

@ -25,223 +25,213 @@
#pragma once
#include "cyhal.h"
#include "cyhal_pin_package.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P0_2
/** Arduino D8 */
#define CYBSP_D8 P13_0
/** Arduino D9 */
#define CYBSP_D9 P13_1
/** Arduino D10 */
#define CYBSP_D10 P12_3
/** Arduino D11 */
#define CYBSP_D11 P12_0
/** Arduino D12 */
#define CYBSP_D12 P12_1
/** Arduino D13 */
#define CYBSP_D13 P12_2
/** Arduino D14 */
#define CYBSP_D14 P6_1
/** Arduino D15 */
#define CYBSP_D15 P6_0
// Generic signal names
/** Pin: WCO input */
#define CYBSP_WCO_IN P0_0
/** Pin: WCO output */
#define CYBSP_WCO_OUT P0_1
/** Pin: WIFI SDIO D0 */
/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: WIFI SDIO D1 */
/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: WIFI SDIO D2 */
/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: WIFI SDIO D3 */
/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: WIFI SDIO CMD */
/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: WIFI SDIO CLK */
/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: WIFI ON */
/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE P2_7
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX P3_0
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX P3_1
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS P3_2
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS P3_3
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE P3_5
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE P4_0
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL P6_0
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA P6_1
/** Pin: SWO */
#define CYBSP_SWO P6_4
/** Pin: SWDIO */
#define CYBSP_SWDIO P6_6
/** Pin: SWDCK */
#define CYBSP_SWDCK P6_7
/** Pin: CapSesnse TX */
#define CYBSP_CSD_TX P1_0
/** Pin: CapSesnse CINA */
#define CYBSP_CINA P7_1
/** Pin: CapSesnse CINB */
#define CYBSP_CINB P7_2
/** Pin: CapSesnse CMOD */
#define CYBSP_CMOD P7_7
/** Pin: CapSesnse Button 0 */
#define CYBSP_CSD_BTN0 P8_1
/** Pin: CapSesnse Button 1 */
#define CYBSP_CSD_BTN1 P8_2
/** Pin: CapSesnse Slider 0 */
#define CYBSP_CSD_SLD0 P8_3
/** Pin: CapSesnse Slider 1 */
#define CYBSP_CSD_SLD1 P8_4
/** Pin: CapSesnse Slider 2 */
#define CYBSP_CSD_SLD2 P8_5
/** Pin: CapSesnse Slider 3 */
#define CYBSP_CSD_SLD3 P8_6
/** Pin: CapSesnse Slider 4 */
#define CYBSP_CSD_SLD4 P8_7
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_enums Enumerated Types
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** Enum defining the different states for the LED. */
typedef enum
{
CYBSP_LED_STATE_ON = 0,
CYBSP_LED_STATE_OFF = 1,
} cybsp_led_state_t;
/** LED 8; User LED1 */
#define CYBSP_LED8 (P1_5)
/** LED 9; User LED2 */
#define CYBSP_LED9 (P13_7)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_LED_RGB_RED (P0_3)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_LED_RGB_GREEN (P1_1)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_LED_RGB_BLUE (P11_1)
/** Enum defining the different states for a button. */
typedef enum
{
CYBSP_BTN_PRESSED = 0,
CYBSP_BTN_OFF = 1,
} cybsp_btn_state_t;
/** LED 8; User LED1 */
#define CYBSP_USER_LED1 (CYBSP_LED8)
/** LED 9; User LED2 */
#define CYBSP_USER_LED2 (CYBSP_LED9)
/** LED 5: RGB LED - Red; User LED3 */
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_RED)
/** LED 5: RGB LED - Green; User LED4 */
#define CYBSP_USER_LED4 (CYBSP_LED_RGB_GREEN)
/** LED 5: RGB LED - Blue; User LED5 */
#define CYBSP_USER_LED5 (CYBSP_LED_RGB_BLUE)
/** LED 8; User LED1 */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** Enum defining the different LED pins on the board. */
typedef enum
{
CYBSP_LED9 = P13_7,
CYBSP_LED8 = P1_5,
CYBSP_LED_RGB_RED = P0_3,
CYBSP_LED_RGB_GREEN = P1_1,
CYBSP_LED_RGB_BLUE = P11_1,
/** \} group_bsp_pins_led */
/* Corresponds to: ioss[0].port[1].pin[5] */
CYBSP_USER_LED1 = CYBSP_LED8,
/* Corresponds to: ioss[0].port[13].pin[7] */
CYBSP_USER_LED2 = CYBSP_LED9,
/* Corresponds to: ioss[0].port[0].pin[3] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED4 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[11].pin[1] */
CYBSP_USER_LED5 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
/** Enum defining the different button pins on the board. */
typedef enum
{
CYBSP_SW2 = P0_4,
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW2,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** Switch 2; User Button 1 */
#define CYBSP_SW2 (P0_4)
/** \} group_bsp_enums */
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW2)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P2_7)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P3_0)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P3_1)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P3_2)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P3_3)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P3_4)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P3_5)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P4_0)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_1)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** \} group_bsp_pins_comm */
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P10_2
/** Arduino A3 */
#define CYBSP_A3 P10_3
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 (P5_0)
/** Arduino D1 */
#define CYBSP_D1 (P5_1)
/** Arduino D2 */
#define CYBSP_D2 (P5_2)
/** Arduino D3 */
#define CYBSP_D3 (P5_3)
/** Arduino D4 */
#define CYBSP_D4 (P5_4)
/** Arduino D5 */
#define CYBSP_D5 (P5_5)
/** Arduino D6 */
#define CYBSP_D6 (P5_6)
/** Arduino D7 */
#define CYBSP_D7 (P0_2)
/** Arduino D8 */
#define CYBSP_D8 (P13_0)
/** Arduino D9 */
#define CYBSP_D9 (P13_1)
/** Arduino D10 */
#define CYBSP_D10 (P12_3)
/** Arduino D11 */
#define CYBSP_D11 (P12_0)
/** Arduino D12 */
#define CYBSP_D12 (P12_1)
/** Arduino D13 */
#define CYBSP_D13 (P12_2)
/** Arduino D14 */
#define CYBSP_D14 (P6_1)
/** Arduino D15 */
#define CYBSP_D15 (P6_0)
/** \} group_bsp_pins_arduino */
/** \} group_bsp_pins */
#if defined(__cplusplus)
}

15
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,6 +24,14 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_USB_CLK_DIV_HW,
.channel_num = CYBSP_USB_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
{
@ -52,6 +60,13 @@
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 255U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);

6
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -35,6 +35,9 @@
extern "C" {
#endif
#define CYBSP_USB_CLK_DIV_ENABLED 1U
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_CLK_DIV_NUM 0U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 0U
@ -45,6 +48,9 @@ extern "C" {
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 3U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -24,6 +24,20 @@
#include "cycfg_peripherals.h"
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
cy_stc_csd_context_t cy_csd_0_context =
{
.lockKey = CY_CSD_NONE_KEY,
@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
.epBuffer = NULL,
.epBufferSize = 0U,
.dmaConfig[0] = NULL,
.dmaConfig[1] = NULL,
.dmaConfig[2] = NULL,
.dmaConfig[3] = NULL,
.dmaConfig[4] = NULL,
.dmaConfig[5] = NULL,
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USBUART_obj =
{
.type = CYHAL_RSC_USB,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
@ -163,4 +202,9 @@ void init_cycfg_peripherals(void)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
#endif //defined (CY_USING_HAL)
}

13
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -37,6 +37,7 @@
#include "cycfg_qspi_memslot.h"
#include "cy_mcwdt.h"
#include "cy_rtc.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
@ -113,6 +114,14 @@ extern "C" {
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern cy_stc_csd_context_t cy_csd_0_context;
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

58
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -240,6 +240,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
.channel_num = CYBSP_QSPI_SCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_USB_DP_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_USB_DP_PORT_NUM,
.channel_num = CYBSP_USB_DP_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_ANALOG,
.hsiom = CYBSP_USB_DM_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_USB_DM_PORT_NUM,
.channel_num = CYBSP_USB_DM_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
{
.outVal = 1,
@ -841,6 +889,16 @@ void init_cycfg_pins(void)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
#endif //defined (CY_USING_HAL)

56
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -252,6 +252,54 @@ extern "C" {
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_USB_DP_ENABLED 1U
#define CYBSP_USB_DP_PORT GPIO_PRT14
#define CYBSP_USB_DP_PORT_NUM 14U
#define CYBSP_USB_DP_PIN 0U
#define CYBSP_USB_DP_NUM 0U
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_0_HSIOM
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_USB_DM_ENABLED 1U
#define CYBSP_USB_DM_PORT GPIO_PRT14
#define CYBSP_USB_DM_PORT_NUM 14U
#define CYBSP_USB_DM_PIN 1U
#define CYBSP_USB_DM_NUM 1U
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
#ifndef ioss_0_port_14_pin_1_HSIOM
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_CSD_TX_ENABLED 1U
#define CYBSP_CSD_TX_PORT GPIO_PRT1
#define CYBSP_CSD_TX_PORT_NUM 1U
@ -841,6 +889,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,7 +24,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
&S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,19 +28,19 @@
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -76,7 +76,7 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.refDiv = 20U,
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
.enableOutputDiv = true,
.lockTolerance = 10U,
.lockTolerance = 4U,
.igain = 9U,
.pgain = 5U,
.settlingCount = 8U,

16
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,20 +1,6 @@
[Device="CY8C624ABZI-D44"]
[Device=CY8C624ABZI-D44]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[13].pin[7]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[5]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[1]
# WIFI
# CYBSP_WIFI_SDIO
sdhc[0]

333
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense
View File

@ -74,5 +74,336 @@
<Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
<Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
</CsxProperties>
<Widgets/>
<Widgets>
<Widget id="Button0" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="Button1" type="CSX_BUTTON">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Rx0" kind="Column">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Tx" kind="Row">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
<Widget id="LinearSlider0" type="LINEAR_SLIDER">
<WidgetProperties>
<Property id="DIPLEXING" value="false"/>
<Property id="MAX_POS_X" value="300"/>
<Property id="MAX_POS_Y" value="300"/>
<Property id="FINGER_CP" value="0.16"/>
<Property id="SNS_CLK" value="16"/>
<Property id="ROW_SNS_CLK" value="16"/>
<Property id="SNS_CLK_SOURCE" value="AUTO"/>
<Property id="TX_CLK" value="32"/>
<Property id="TX_CLK_SOURCE" value="AUTO"/>
<Property id="RESOLUTION" value="RES12BIT"/>
<Property id="NUM_CONV" value="100"/>
<Property id="IDAC_MOD0" value="32"/>
<Property id="IDAC_MOD1" value="32"/>
<Property id="IDAC_MOD2" value="32"/>
<Property id="ROW_IDAC_MOD0" value="32"/>
<Property id="ROW_IDAC_MOD1" value="32"/>
<Property id="ROW_IDAC_MOD2" value="32"/>
<Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
<Property id="FINGER_TH" value="100"/>
<Property id="PROX_TOUCH_TH" value="200"/>
<Property id="NOISE_TH" value="40"/>
<Property id="NNOISE_TH" value="40"/>
<Property id="LOW_BSLN_RST" value="30"/>
<Property id="HYSTERESIS" value="10"/>
<Property id="ON_DEBOUNCE" value="3"/>
<Property id="VELOCITY" value="45000"/>
<Property id="IIR_FILTER" value="false"/>
<Property id="IIR_FILTER_COEFF" value="128"/>
<Property id="MEDIAN_FILTER" value="false"/>
<Property id="AVG_FILTER" value="false"/>
<Property id="JITTER_FILTER" value="false"/>
<Property id="AIIR_FILTER" value="false"/>
<Property id="AIIR_NO_MOV_TH" value="3"/>
<Property id="AIIR_LITTLE_MOV_TH" value="7"/>
<Property id="AIIR_LARGE_MOV_TH" value="12"/>
<Property id="AIIR_MAXK" value="60"/>
<Property id="AIIR_MINK" value="1"/>
<Property id="AIIR_DIV_VAL" value="64"/>
<Property id="CENTROID_TYPE" value="CSD3X3"/>
<Property id="CROSS_COUPLING_POS_TH" value="5"/>
<Property id="EDGE_CORRECTION" value="true"/>
<Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
<Property id="EDGE_PENULTIMATE_TH" value="100"/>
<Property id="TWO_FINGER_DETECTION" value="false"/>
<Property id="ACCEL_COEFF" value="9"/>
<Property id="SPEED_COEFF" value="2"/>
<Property id="DIVISOR" value="4"/>
<Property id="SPEED_TH_X" value="3"/>
<Property id="SPEED_TH_Y" value="4"/>
<Property id="BALLISTIC_MULT" value="false"/>
<Property id="GESTURE_ENABLE" value="false"/>
<Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
<Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
<Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
<Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
<Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
<Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
<Property id="GESTURE_FILTERING_ENABLE" value="false"/>
<Property id="CLICK_TIMEOUT_MAX" value="1000"/>
<Property id="CLICK_TIMEOUT_MIN" value="0"/>
<Property id="CLICK_DISTANCE_MAX" value="100"/>
<Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
<Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
<Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
<Property id="SCROLL_DEBOUNCE" value="3"/>
<Property id="SCROLL_DISTANCE_MIN" value="20"/>
<Property id="ROTATE_DEBOUNCE" value="10"/>
<Property id="ROTATE_DISTANCE_MIN" value="50"/>
<Property id="ZOOM_DEBOUNCE" value="3"/>
<Property id="ZOOM_DISTANCE_MIN" value="50"/>
<Property id="FLICK_TIMEOUT_MAX" value="300"/>
<Property id="FLICK_DISTANCE_MIN" value="100"/>
<Property id="EDGE_EDGE_SIZE" value="200"/>
<Property id="EDGE_DISTANCE_MIN" value="200"/>
<Property id="EDGE_TIMEOUT_MAX" value="2000"/>
<Property id="EDGE_ANGLE_MAX" value="45"/>
</WidgetProperties>
<Electrodes>
<Electrode id="Sns0" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns1" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns2" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns3" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
<Electrode id="Sns4" kind="Sensor">
<ElectrodeProperties>
<Property id="IDAC0" value="32"/>
<Property id="IDAC1" value="32"/>
<Property id="IDAC2" value="32"/>
<Property id="PINS" value="Dedicated pin"/>
</ElectrodeProperties>
</Electrode>
</Electrodes>
</Widget>
</Widgets>
</Configuration>

71
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<Design version="11" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<Design version="11" xmlns="http://cypress.com/xsd/cydesignfile_v2">
<ToolInfo version="1.0.0"/>
<Devices>
<Device mpn="CY8C624ABZI-D44">
@ -134,6 +134,26 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[1]" alias="CYBSP_USB_DM" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[0]" alias="CYBSP_CSD_TX" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -364,6 +384,11 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="500"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_CSD_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="256"/>
<Param id="fracDivider" value="0"/>
@ -474,7 +499,7 @@
<Param id="hibernate" value="true"/>
</Block>
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
<Param id="trim" value="0.25"/>
</Block>
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="wco"/>
@ -531,7 +556,6 @@
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@ -571,6 +595,27 @@
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
<Param id="epMask" value="0"/>
<Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
<Param id="bufSize" value="512"/>
<Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
<Param id="enableLpm" value="false"/>
<Param id="lpmIntr" value="0x0U"/>
<Param id="ArbIntr" value="0x0U"/>
<Param id="ep0CntrIntr" value="0x2U"/>
<Param id="busResetIntr" value="0x2U"/>
<Param id="sofIntr" value="0x1U"/>
<Param id="ep0Intr" value="0x1U"/>
<Param id="ep1Intr" value="0x1U"/>
<Param id="ep2Intr" value="0x1U"/>
<Param id="ep3Intr" value="0x1U"/>
<Param id="ep4Intr" value="0x1U"/>
<Param id="ep5Intr" value="0x1U"/>
<Param id="ep6Intr" value="0x1U"/>
<Param id="ep7Intr" value="0x1U"/>
<Param id="inFlash" value="true"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
@ -645,6 +690,18 @@
<Port name="ioss[0].port[11].pin[7].digital_inout[0]"/>
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[0].aux[0]"/>
<Port name="usb[0].usb_dp_pad[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[1].aux[0]"/>
<Port name="usb[0].usb_dm_pad[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="usb[0].clock_dev_brs[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
<Port name="scb[3].clock[0]"/>
@ -661,6 +718,10 @@
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
<Net>
<Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
<Port name="usb[0].clk_usb_dev[0]"/>
</Net>
<Mux name="sense" location="csd[0].csd[0]">
<Arm>
<Port name="ioss[0].port[7].pin[7].analog[0]"/>
@ -706,8 +767,6 @@
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<Libraries/>
<ConfiguratorData/>
</Design>

101
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* \file TARGET_CY8CPROTO_062_4343W/cybsp.c
* \file cybsp.c
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CPROTO-062-4343W prototyping kit.
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
@ -25,17 +25,58 @@
#include <stdlib.h>
#include "cybsp.h"
#include "cyhal_utils.h"
#include "cycfg.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
cy_rslt_t result;
result = cyhal_hwmgr_init();
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
cy_rslt_t result = cyhal_hwmgr_init();
init_cycfg_system();
if (CY_RSLT_SUCCESS == result)
@ -43,42 +84,32 @@ cy_rslt_t cybsp_init(void)
result = cybsp_register_sysclk_pm_callback();
}
#ifndef __MBED__
if (CY_RSLT_SUCCESS == result)
{
/* Initialize User LEDs */
/* Reserves: CYBSP_USER_LED1 */
result |= cybsp_led_init(CYBSP_USER_LED1);
/* Initialize User Buttons */
/* Reserves: CYBSP_USER_BTN1 */
result |= cybsp_btn_init(CYBSP_USER_BTN1);
CY_ASSERT(CY_RSLT_SUCCESS == result);
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance
* and one of available clock dividers */
result = cybsp_retarget_init();
}
}
#endif /* __MBED__ */
#if defined(CYBSP_WIFI_CAPABLE)
/* Initialize SDIO interface.
NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done
when starting up WiFi. */
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */
result = cybsp_wifi_sdio_init();
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both. */
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}

53
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp.h
View File

@ -1,9 +1,8 @@
/***************************************************************************//**
* \file CY8CPROTO-062-4343W/cybsp.h
* \file cybsp.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CPROTO-062-4343W prototyping kit.
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
@ -25,20 +24,50 @@
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_core.h"
#if defined(CYBSP_WIFI_CAPABLE)
#include "cybsp_wifi_sdio.h"
#include "cyhal_sdio.h"
#endif
#ifndef __MBED__
#include "cybsp_retarget.h"
#include "cybsp_serial_flash.h"
#endif /* __MBED__ */
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(__cplusplus)
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */

218
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/cybsp_types.h
View File

@ -25,124 +25,144 @@
#pragma once
#include "cyhal.h"
#include "cyhal_pin_package.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
/** Pin: WIFI SDIO D0 */
/* Corresponds to: ioss[0].port[2].pin[0], sdhc[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: WIFI SDIO D1 */
/* Corresponds to: ioss[0].port[2].pin[1], sdhc[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: WIFI SDIO D2 */
/* Corresponds to: ioss[0].port[2].pin[2], sdhc[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: WIFI SDIO D3 */
/* Corresponds to: ioss[0].port[2].pin[3], sdhc[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: WIFI SDIO CMD */
/* Corresponds to: ioss[0].port[2].pin[4], sdhc[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: WIFI SDIO CLK */
/* Corresponds to: ioss[0].port[2].pin[5], sdhc[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: WIFI ON */
/* Corresponds to: ioss[0].port[2].pin[6], sdhc[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE P0_4
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX P3_0
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX P3_1
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS P3_2
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS P3_3
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE P4_0
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE P3_5
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[5].pin[0], scb[5] */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[5].pin[1], scb[5] */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_enums Enumerated Types
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** Enum defining the different states for the LED. */
typedef enum
{
CYBSP_LED_STATE_ON = 0,
CYBSP_LED_STATE_OFF = 1,
} cybsp_led_state_t;
/** LED 4; User LED1 (red) */
#define CYBSP_LED4 (P13_7)
/** Enum defining the different states for a button. */
typedef enum
{
CYBSP_BTN_PRESSED = 0,
CYBSP_BTN_OFF = 1,
} cybsp_btn_state_t;
/** LED 4; User LED1 (red) */
#define CYBSP_USER_LED1 (CYBSP_LED4)
/** LED 4; User LED1 (red) */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** Enum defining the different LED pins on the board. */
typedef enum
{
CYBSP_LED_RED = P13_7,
/** \} group_bsp_pins_led */
/* Corresponds to: ioss[0].port[13].pin[7] */
CYBSP_USER_LED1 = CYBSP_LED_RED,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
/** Enum defining the different button pins on the board. */
typedef enum
{
CYBSP_SW2 = P0_4,
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW2,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** \} group_bsp_enums */
/** Switch 2; User Button 1 */
#define CYBSP_SW2 (P0_4)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW2)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P0_4)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P3_0)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P3_1)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P3_2)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P3_3)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P3_4)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P4_0)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P3_5)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_1)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** \} group_bsp_pins_comm */
/** \} group_bsp_pins */
#if defined(__cplusplus)
}

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -24,18 +24,37 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_USB_CLK_DIV_HW,
.channel_num = CYBSP_USB_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_I2C_CLK_DIV_HW,
.channel_num = CYBSP_I2C_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void)
{
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 499U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 35U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_I2C_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
}

19
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -27,21 +27,28 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define peri_0_div_16_0_ENABLED 1U
#define peri_0_div_16_0_HW CY_SYSCLK_DIV_16_BIT
#define peri_0_div_16_0_NUM 0U
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 0U
#define CYBSP_USB_CLK_DIV_ENABLED 1U
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_CLK_DIV_NUM 0U
#define CYBSP_I2C_CLK_DIV_ENABLED 1U
#define CYBSP_I2C_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_I2C_CLK_DIV_NUM 1U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_I2C_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_clocks(void);
#if defined(__cplusplus)

95
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c
View File

@ -24,6 +24,20 @@
#include "cycfg_peripherals.h"
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config =
{
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
@ -32,34 +46,14 @@ const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config =
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR8_BITS,
.enableWakeFromSleep = false,
};
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
{
.uartMode = CY_SCB_UART_STANDARD,
.enableMutliProcessorMode = false,
.smartCardRetryOnNack = false,
.irdaInvertRx = false,
.irdaEnableLowPowerReceiver = false,
.oversample = 12,
.enableMsbFirst = false,
.dataWidth = 8UL,
.parity = CY_SCB_UART_PARITY_NONE,
.stopBits = CY_SCB_UART_STOP_BITS_1,
.enableInputFilter = false,
.breakWidth = 11UL,
.dropOnFrameError = false,
.dropOnParityError = false,
.receiverAddress = 0x0UL,
.receiverAddressMask = 0x0UL,
.acceptAddrInFifo = false,
.enableCts = false,
.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rtsRxFifoLevel = 0UL,
.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
.rxFifoTriggerLevel = 63UL,
.rxFifoIntEnableMask = 0UL,
.txFifoTriggerLevel = 63UL,
.txFifoIntEnableMask = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_I2C_obj =
{
.type = CYHAL_RSC_SCB,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_smif_config_t CYBSP_QSPI_config =
{
.mode = (uint32_t)CY_SMIF_NORMAL,
@ -67,11 +61,54 @@ const cy_stc_smif_config_t CYBSP_QSPI_config =
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_obj =
{
.type = CYHAL_RSC_SMIF,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
.epBuffer = NULL,
.epBufferSize = 0U,
.dmaConfig[0] = NULL,
.dmaConfig[1] = NULL,
.dmaConfig[2] = NULL,
.dmaConfig[3] = NULL,
.dmaConfig[4] = NULL,
.dmaConfig[5] = NULL,
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.enableLpm = false,
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USBUART_obj =
{
.type = CYHAL_RSC_USB,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void)
{
Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 1U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_I2C_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
#endif //defined (CY_USING_HAL)
}

27
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -28,9 +28,12 @@
#include "cycfg_notices.h"
#include "cy_scb_ezi2c.h"
#include "cy_sysclk.h"
#include "cy_scb_uart.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_smif.h"
#include "cycfg_qspi_memslot.h"
#include "cy_usbfs_dev_drv.h"
#if defined(__cplusplus)
extern "C" {
@ -39,9 +42,6 @@ extern "C" {
#define CYBSP_I2C_ENABLED 1U
#define CYBSP_I2C_HW SCB3
#define CYBSP_I2C_IRQ scb_3_interrupt_IRQn
#define CYBSP_DEBUG_UART_ENABLED 1U
#define CYBSP_DEBUG_UART_HW SCB5
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
#define CYBSP_QSPI_ENABLED 1U
#define CYBSP_QSPI_HW SMIF0
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
@ -60,10 +60,27 @@ extern "C" {
#define CYBSP_QSPI_SS2 (0UL)
#define CYBSP_QSPI_SS3 (0UL)
#define CYBSP_QSPI_DESELECT_DELAY 7
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
extern const cy_stc_scb_ezi2c_config_t CYBSP_I2C_config;
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_I2C_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_peripherals(void);

283
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
View File

@ -40,6 +40,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_IN_PORT_NUM,
.channel_num = CYBSP_WCO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
{
.outVal = 1,
@ -56,22 +64,14 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_SW2_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_PULLUP,
.hsiom = CYBSP_SW2_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_WCO_OUT_PORT_NUM,
.channel_num = CYBSP_WCO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
{
.outVal = 1,
@ -88,6 +88,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SS_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SS_PORT_NUM,
.channel_num = CYBSP_QSPI_SS_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
{
.outVal = 1,
@ -104,6 +112,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D3_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D3_PORT_NUM,
.channel_num = CYBSP_QSPI_D3_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
{
.outVal = 1,
@ -120,6 +136,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D2_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D2_PORT_NUM,
.channel_num = CYBSP_QSPI_D2_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
{
.outVal = 1,
@ -136,6 +160,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D1_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D1_PORT_NUM,
.channel_num = CYBSP_QSPI_D1_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
{
.outVal = 1,
@ -152,6 +184,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_D0_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_D0_PORT_NUM,
.channel_num = CYBSP_QSPI_D0_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
{
.outVal = 1,
@ -168,6 +208,14 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_QSPI_SCK_PORT_NUM,
.channel_num = CYBSP_QSPI_SCK_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
{
.outVal = 1,
@ -184,6 +232,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_ECO_IN_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_ECO_IN_PORT_NUM,
.channel_num = CYBSP_ECO_IN_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
{
.outVal = 1,
@ -200,22 +256,14 @@ const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED3_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED3_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_ECO_OUT_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_ECO_OUT_PORT_NUM,
.channel_num = CYBSP_ECO_OUT_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
{
.outVal = 1,
@ -232,6 +280,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_USB_DP_PORT_NUM,
.channel_num = CYBSP_USB_DP_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
{
.outVal = 1,
@ -248,54 +304,14 @@ const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t CYBSP_LED4_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = CYBSP_LED4_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_HIGHZ,
.hsiom = ioss_0_port_5_pin_0_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = ioss_0_port_5_pin_1_HSIOM,
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_USB_DM_PORT_NUM,
.channel_num = CYBSP_USB_DM_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config =
{
.outVal = 1,
@ -312,6 +328,14 @@ const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_I2C_SCL_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_I2C_SCL_PORT_NUM,
.channel_num = CYBSP_I2C_SCL_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config =
{
.outVal = 1,
@ -328,6 +352,14 @@ const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config =
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_I2C_SDA_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_I2C_SDA_PORT_NUM,
.channel_num = CYBSP_I2C_SDA_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
{
.outVal = 1,
@ -337,13 +369,21 @@ const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWO_PORT_NUM,
.channel_num = CYBSP_SWO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
{
.outVal = 1,
@ -353,13 +393,21 @@ const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWDIO_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWDIO_PORT_NUM,
.channel_num = CYBSP_SWDIO_PIN,
};
#endif //defined (CY_USING_HAL)
const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config =
{
.outVal = 1,
@ -369,58 +417,107 @@ const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config =
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_FULL,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SWCLK_obj =
{
.type = CYHAL_RSC_GPIO,
.block_num = CYBSP_SWCLK_PORT_NUM,
.channel_num = CYBSP_SWCLK_PIN,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void)
{
Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_SW2_PORT, CYBSP_SW2_PIN, &CYBSP_SW2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SS_PORT, CYBSP_QSPI_SS_PIN, &CYBSP_QSPI_SS_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SS_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D3_PORT, CYBSP_QSPI_D3_PIN, &CYBSP_QSPI_D3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D3_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D2_PORT, CYBSP_QSPI_D2_PIN, &CYBSP_QSPI_D2_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D2_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D1_PORT, CYBSP_QSPI_D1_PIN, &CYBSP_QSPI_D1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D1_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_D0_PORT, CYBSP_QSPI_D0_PIN, &CYBSP_QSPI_D0_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_D0_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_QSPI_SCK_PORT, CYBSP_QSPI_SCK_PIN, &CYBSP_QSPI_SCK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_QSPI_SCK_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
Cy_GPIO_Pin_Init(CYBSP_LED3_PORT, CYBSP_LED3_PIN, &CYBSP_LED3_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
Cy_GPIO_Pin_Init(CYBSP_LED4_PORT, CYBSP_LED4_PIN, &CYBSP_LED4_config);
Cy_GPIO_Pin_Init(ioss_0_port_5_pin_0_PORT, ioss_0_port_5_pin_0_PIN, &ioss_0_port_5_pin_0_config);
Cy_GPIO_Pin_Init(ioss_0_port_5_pin_1_PORT, ioss_0_port_5_pin_1_PIN, &ioss_0_port_5_pin_1_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_I2C_SCL_PORT, CYBSP_I2C_SCL_PIN, &CYBSP_I2C_SCL_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_I2C_SCL_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_I2C_SDA_PORT, CYBSP_I2C_SDA_PIN, &CYBSP_I2C_SDA_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_I2C_SDA_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
#endif //defined (CY_USING_HAL)
Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj);
#endif //defined (CY_USING_HAL)
}

324
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_gpio.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cycfg_routing.h"
#if defined(__cplusplus)
@ -45,6 +48,18 @@ extern "C" {
#endif
#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_ENABLED 1U
#define CYBSP_WCO_OUT_PORT GPIO_PRT0
#define CYBSP_WCO_OUT_PORT_NUM 0U
@ -57,18 +72,18 @@ extern "C" {
#endif
#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
#define CYBSP_SW2_ENABLED 1U
#define CYBSP_SW2_PORT GPIO_PRT0
#define CYBSP_SW2_PORT_NUM 0U
#define CYBSP_SW2_PIN 4U
#define CYBSP_SW2_NUM 4U
#define CYBSP_SW2_DRIVEMODE CY_GPIO_DM_PULLUP
#define CYBSP_SW2_INIT_DRIVESTATE 1
#ifndef ioss_0_port_0_pin_4_HSIOM
#define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_SW2_HSIOM ioss_0_port_0_pin_4_HSIOM
#define CYBSP_SW2_IRQ ioss_interrupts_gpio_0_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_ENABLED 1U
#define CYBSP_QSPI_SS_PORT GPIO_PRT11
#define CYBSP_QSPI_SS_PORT_NUM 11U
@ -81,6 +96,18 @@ extern "C" {
#endif
#define CYBSP_QSPI_SS_HSIOM ioss_0_port_11_pin_2_HSIOM
#define CYBSP_QSPI_SS_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_PORT_PIN P11_2
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SS_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_ENABLED 1U
#define CYBSP_QSPI_D3_PORT GPIO_PRT11
#define CYBSP_QSPI_D3_PORT_NUM 11U
@ -93,6 +120,18 @@ extern "C" {
#endif
#define CYBSP_QSPI_D3_HSIOM ioss_0_port_11_pin_3_HSIOM
#define CYBSP_QSPI_D3_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_PORT_PIN P11_3
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_ENABLED 1U
#define CYBSP_QSPI_D2_PORT GPIO_PRT11
#define CYBSP_QSPI_D2_PORT_NUM 11U
@ -105,6 +144,18 @@ extern "C" {
#endif
#define CYBSP_QSPI_D2_HSIOM ioss_0_port_11_pin_4_HSIOM
#define CYBSP_QSPI_D2_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_PORT_PIN P11_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_ENABLED 1U
#define CYBSP_QSPI_D1_PORT GPIO_PRT11
#define CYBSP_QSPI_D1_PORT_NUM 11U
@ -117,6 +168,18 @@ extern "C" {
#endif
#define CYBSP_QSPI_D1_HSIOM ioss_0_port_11_pin_5_HSIOM
#define CYBSP_QSPI_D1_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_PORT_PIN P11_5
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_ENABLED 1U
#define CYBSP_QSPI_D0_PORT GPIO_PRT11
#define CYBSP_QSPI_D0_PORT_NUM 11U
@ -129,6 +192,18 @@ extern "C" {
#endif
#define CYBSP_QSPI_D0_HSIOM ioss_0_port_11_pin_6_HSIOM
#define CYBSP_QSPI_D0_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_PORT_PIN P11_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_D0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_ENABLED 1U
#define CYBSP_QSPI_SCK_PORT GPIO_PRT11
#define CYBSP_QSPI_SCK_PORT_NUM 11U
@ -141,6 +216,18 @@ extern "C" {
#endif
#define CYBSP_QSPI_SCK_HSIOM ioss_0_port_11_pin_7_HSIOM
#define CYBSP_QSPI_SCK_IRQ ioss_interrupts_gpio_11_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_PORT_PIN P11_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_QSPI_SCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_ECO_IN_ENABLED 1U
#define CYBSP_ECO_IN_PORT GPIO_PRT12
#define CYBSP_ECO_IN_PORT_NUM 12U
@ -153,6 +240,18 @@ extern "C" {
#endif
#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM
#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_ECO_IN_HAL_PORT_PIN P12_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_ECO_OUT_ENABLED 1U
#define CYBSP_ECO_OUT_PORT GPIO_PRT12
#define CYBSP_ECO_OUT_PORT_NUM 12U
@ -165,18 +264,18 @@ extern "C" {
#endif
#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM
#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn
#define CYBSP_LED3_ENABLED 1U
#define CYBSP_LED3_PORT GPIO_PRT13
#define CYBSP_LED3_PORT_NUM 13U
#define CYBSP_LED3_PIN 7U
#define CYBSP_LED3_NUM 7U
#define CYBSP_LED3_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED3_INIT_DRIVESTATE 1
#ifndef ioss_0_port_13_pin_7_HSIOM
#define ioss_0_port_13_pin_7_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED3_HSIOM ioss_0_port_13_pin_7_HSIOM
#define CYBSP_LED3_IRQ ioss_interrupts_gpio_13_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_ECO_OUT_HAL_PORT_PIN P12_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_USB_DP_ENABLED 1U
#define CYBSP_USB_DP_PORT GPIO_PRT14
#define CYBSP_USB_DP_PORT_NUM 14U
@ -189,6 +288,18 @@ extern "C" {
#endif
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_USB_DM_ENABLED 1U
#define CYBSP_USB_DM_PORT GPIO_PRT14
#define CYBSP_USB_DM_PORT_NUM 14U
@ -201,40 +312,18 @@ extern "C" {
#endif
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
#define CYBSP_LED4_ENABLED 1U
#define CYBSP_LED4_PORT GPIO_PRT1
#define CYBSP_LED4_PORT_NUM 1U
#define CYBSP_LED4_PIN 5U
#define CYBSP_LED4_NUM 5U
#define CYBSP_LED4_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define CYBSP_LED4_INIT_DRIVESTATE 1
#ifndef ioss_0_port_1_pin_5_HSIOM
#define ioss_0_port_1_pin_5_HSIOM HSIOM_SEL_GPIO
#endif
#define CYBSP_LED4_HSIOM ioss_0_port_1_pin_5_HSIOM
#define CYBSP_LED4_IRQ ioss_interrupts_gpio_1_IRQn
#define ioss_0_port_5_pin_0_ENABLED 1U
#define ioss_0_port_5_pin_0_PORT GPIO_PRT5
#define ioss_0_port_5_pin_0_PORT_NUM 5U
#define ioss_0_port_5_pin_0_PIN 0U
#define ioss_0_port_5_pin_0_NUM 0U
#define ioss_0_port_5_pin_0_DRIVEMODE CY_GPIO_DM_HIGHZ
#define ioss_0_port_5_pin_0_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_0_HSIOM
#define ioss_0_port_5_pin_0_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_5_pin_0_IRQ ioss_interrupts_gpio_5_IRQn
#define ioss_0_port_5_pin_1_ENABLED 1U
#define ioss_0_port_5_pin_1_PORT GPIO_PRT5
#define ioss_0_port_5_pin_1_PORT_NUM 5U
#define ioss_0_port_5_pin_1_PIN 1U
#define ioss_0_port_5_pin_1_NUM 1U
#define ioss_0_port_5_pin_1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
#define ioss_0_port_5_pin_1_INIT_DRIVESTATE 1
#ifndef ioss_0_port_5_pin_1_HSIOM
#define ioss_0_port_5_pin_1_HSIOM HSIOM_SEL_GPIO
#endif
#define ioss_0_port_5_pin_1_IRQ ioss_interrupts_gpio_5_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
#endif //defined (CY_USING_HAL)
#define CYBSP_I2C_SCL_ENABLED 1U
#define CYBSP_I2C_SCL_PORT GPIO_PRT6
#define CYBSP_I2C_SCL_PORT_NUM 6U
@ -247,6 +336,18 @@ extern "C" {
#endif
#define CYBSP_I2C_SCL_HSIOM ioss_0_port_6_pin_0_HSIOM
#define CYBSP_I2C_SCL_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SCL_HAL_PORT_PIN P6_0
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SCL_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SCL_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SCL_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
#endif //defined (CY_USING_HAL)
#define CYBSP_I2C_SDA_ENABLED 1U
#define CYBSP_I2C_SDA_PORT GPIO_PRT6
#define CYBSP_I2C_SDA_PORT_NUM 6U
@ -259,8 +360,21 @@ extern "C" {
#endif
#define CYBSP_I2C_SDA_HSIOM ioss_0_port_6_pin_1_HSIOM
#define CYBSP_I2C_SDA_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SDA_HAL_PORT_PIN P6_1
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SDA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SDA_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_I2C_SDA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW
#endif //defined (CY_USING_HAL)
#define CYBSP_SWO_ENABLED 1U
#define CYBSP_SWO_PORT GPIO_PRT6
#define CYBSP_SWO_PORT_NUM 6U
#define CYBSP_SWO_PIN 4U
#define CYBSP_SWO_NUM 4U
#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
@ -270,8 +384,21 @@ extern "C" {
#endif
#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_PORT_PIN P6_4
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
#endif //defined (CY_USING_HAL)
#define CYBSP_SWDIO_ENABLED 1U
#define CYBSP_SWDIO_PORT GPIO_PRT6
#define CYBSP_SWDIO_PORT_NUM 6U
#define CYBSP_SWDIO_PIN 6U
#define CYBSP_SWDIO_NUM 6U
#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
@ -281,8 +408,21 @@ extern "C" {
#endif
#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
#endif //defined (CY_USING_HAL)
#define CYBSP_SWCLK_ENABLED 1U
#define CYBSP_SWCLK_PORT GPIO_PRT6
#define CYBSP_SWCLK_PORT_NUM 6U
#define CYBSP_SWCLK_PIN 7U
#define CYBSP_SWCLK_NUM 7U
#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
@ -292,29 +432,87 @@ extern "C" {
#endif
#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
#if defined (CY_USING_HAL)
#define CYBSP_SWCLK_HAL_PORT_PIN P6_7
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
#define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_SW2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SS_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SS_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D3_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D2_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D2_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_D0_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_D0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SCK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_QSPI_SCK_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED3_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
extern const cy_stc_gpio_pin_config_t CYBSP_LED4_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_0_config;
extern const cy_stc_gpio_pin_config_t ioss_0_port_5_pin_1_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SCL_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_I2C_SCL_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_I2C_SDA_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_I2C_SDA_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SWCLK_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_pins(void);

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h
View File

@ -40,8 +40,6 @@ void init_cycfg_routing(void);
#define ioss_0_port_11_pin_5_HSIOM P11_5_SMIF_SPI_DATA1
#define ioss_0_port_11_pin_6_HSIOM P11_6_SMIF_SPI_DATA0
#define ioss_0_port_11_pin_7_HSIOM P11_7_SMIF_SPI_CLK
#define ioss_0_port_5_pin_0_HSIOM P5_0_SCB5_UART_RX
#define ioss_0_port_5_pin_1_HSIOM P5_1_SCB5_UART_TX
#define ioss_0_port_6_pin_0_HSIOM P6_0_SCB3_I2C_SCL
#define ioss_0_port_6_pin_1_HSIOM P6_1_SCB3_I2C_SDA
#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO

62
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
View File

@ -71,13 +71,53 @@ static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
.refDiv = 20U,
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
.enableOutputDiv = true,
.lockTolerance = 10U,
.lockTolerance = 4U,
.igain = 9U,
.pgain = 5U,
.settlingCount = 8U,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
.cco_Freq = 355U,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 0U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 1U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 2U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 3U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
{
.type = CYHAL_RSC_CLKPATH,
.block_num = 4U,
.channel_num = 0U,
};
#endif //defined (CY_USING_HAL)
static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
{
.feedbackDiv = 30,
@ -501,4 +541,24 @@ void init_cycfg_system(void)
/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
SystemCoreClockUpdate();
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
#endif //defined (CY_USING_HAL)
}

19
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h
View File

@ -27,6 +27,9 @@
#include "cycfg_notices.h"
#include "cy_sysclk.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#include "cy_gpio.h"
#include "cy_syspm.h"
@ -75,6 +78,22 @@ extern "C" {
#define CY_CFG_PWR_VDDIO0_MV 3300
#define CY_CFG_PWR_VDDIO1_MV 3300
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_system(void);
#if defined(__cplusplus)

18
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,18 +1,4 @@
[Device="CYB06447BZI-D54"]
[Device=CYB06447BZI-D54]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[13].pin[7]
# CYBSP_USER_LED2
ioss[0].port[1].pin[5]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[5]
# CYBSP_DEBUG_UART_RX
ioss[0].port[5].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[5].pin[1]
# Nothing needs to be reserved for this board

63
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi Normal file
View File

@ -0,0 +1,63 @@
<?xml version="1.0"?>
<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
<Configuration app="QSPI" major="2" minor="0">
<DevicePath>PSoC 6.xml</DevicePath>
<SlotConfigs>
<SlotConfig>
<SlaveSlot>0</SlaveSlot>
<PartNumber>S25FL128S</PartNumber>
<MemoryMapped>true</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18000000</StartAddress>
<Size>0x1000000</Size>
<EndAddress>0x18FFFFFF</EndAddress>
<WriteEnable>true</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
<MemoryConfigsPath>S25FL128S</MemoryConfigsPath>
<ConfigDataInFlash>true</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>1</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18010000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1801FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>2</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18020000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1802FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
<SlotConfig>
<SlaveSlot>3</SlaveSlot>
<PartNumber>Not used</PartNumber>
<MemoryMapped>false</MemoryMapped>
<DualQuad>None</DualQuad>
<StartAddress>0x18030000</StartAddress>
<Size>0x10000</Size>
<EndAddress>0x1803FFFF</EndAddress>
<WriteEnable>false</WriteEnable>
<Encrypt>false</Encrypt>
<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
<ConfigDataInFlash>false</ConfigDataInFlash>
</SlotConfig>
</SlotConfigs>
</Configuration>

154
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -28,16 +28,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[0].pin[4]" alias="CYBSP_SW2" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[11].pin[2]" alias="CYBSP_QSPI_SS" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
@ -118,16 +108,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[13].pin[7]" alias="CYBSP_LED3" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[14].pin[0]" alias="CYBSP_USB_DP" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
<Param id="initialState" value="1"/>
@ -148,36 +128,6 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[1].pin[5]" alias="CYBSP_LED4" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[0]" alias="" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[5].pin[1]" alias="" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
<Param id="initialState" value="1"/>
<Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
<Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
<Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
<Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="ioss[0].port[6].pin[0]" alias="CYBSP_I2C_SCL" template="mxs40pin" version="1.1">
<Param id="DriveModes" value="CY_GPIO_DM_OD_DRIVESLOW"/>
<Param id="initialState" value="1"/>
@ -228,16 +178,11 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_16[0]" alias="" template="mxs40peripheralclock" version="1.0">
<Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="500"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_DEBUG_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="36"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[1]" alias="CYBSP_I2C_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="4"/>
<Param id="fracDivider" value="0"/>
@ -252,51 +197,6 @@
<Param id="EnableWakeup" value="false"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="scb[5]" alias="CYBSP_DEBUG_UART" template="mxs40uart" version="1.0">
<Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
<Param id="IrdaLowPower" value="false"/>
<Param id="BaudRate" value="115200"/>
<Param id="Oversample" value="12"/>
<Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
<Param id="DataWidth" value="8"/>
<Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
<Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
<Param id="EnableInputFilter" value="false"/>
<Param id="EnableTxEn" value="false"/>
<Param id="FlowControl" value="false"/>
<Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
<Param id="RtsTriggerLevel" value="63"/>
<Param id="RxTriggerLevel" value="63"/>
<Param id="TxTriggerLevel" value="63"/>
<Param id="MultiProc" value="false"/>
<Param id="MpRxAddress" value="0"/>
<Param id="MpRxAddressMask" value="255"/>
<Param id="MpRxAcceptAddress" value="false"/>
<Param id="DropOnFrameErr" value="false"/>
<Param id="DropOnParityErr" value="false"/>
<Param id="BreakSignalBits" value="11"/>
<Param id="SmCardRetryOnNack" value="false"/>
<Param id="IrdaPolarity" value="NON_INVERTING"/>
<Param id="inFlash" value="true"/>
<Param id="ApiMode" value="HIGH_LEVEL"/>
<Param id="IntrRxNotEmpty" value="false"/>
<Param id="IntrRxFull" value="false"/>
<Param id="IntrRxOverflow" value="false"/>
<Param id="IntrRxUnderflow" value="false"/>
<Param id="IntrRxFrameErr" value="false"/>
<Param id="IntrRxParityErr" value="false"/>
<Param id="IntrRxBreakDetected" value="false"/>
<Param id="IntrRxTrigger" value="false"/>
<Param id="IntrTxUartDone" value="false"/>
<Param id="IntrTxUartLostArb" value="false"/>
<Param id="IntrTxUartNack" value="false"/>
<Param id="IntrTxEmpty" value="false"/>
<Param id="IntrTxNotFull" value="false"/>
<Param id="IntrTxOverflow" value="false"/>
<Param id="IntrTxUnderflow" value="false"/>
<Param id="IntrTxTrigger" value="false"/>
</Block>
<Block location="smif[0]" alias="CYBSP_QSPI" template="mxs40smif" version="1.1">
<Param id="configurator" value="0"/>
<Param id="isrAlignment" value="false"/>
@ -334,7 +234,7 @@
<Param id="hibernate" value="true"/>
</Block>
<Block location="srss[0].clock[0].imo[0]" alias="" template="mxs40imo" version="1.0">
<Param id="trim" value="1"/>
<Param id="trim" value="0.25"/>
</Block>
<Block location="srss[0].clock[0].lfclk[0]" alias="" template="mxs40lfclk" version="1.1">
<Param id="sourceClock" value="wco"/>
@ -375,7 +275,6 @@
<Param id="accuracyPpm" value="150"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@ -390,6 +289,27 @@
<Param id="vddio0Mv" value="3300"/>
<Param id="vddio1Mv" value="3300"/>
</Block>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
<Param id="epMask" value="0"/>
<Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
<Param id="bufSize" value="512"/>
<Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
<Param id="enableLpm" value="false"/>
<Param id="lpmIntr" value="0x0U"/>
<Param id="ArbIntr" value="0x0U"/>
<Param id="ep0CntrIntr" value="0x2U"/>
<Param id="busResetIntr" value="0x2U"/>
<Param id="sofIntr" value="0x1U"/>
<Param id="ep0Intr" value="0x1U"/>
<Param id="ep1Intr" value="0x1U"/>
<Param id="ep2Intr" value="0x1U"/>
<Param id="ep3Intr" value="0x1U"/>
<Param id="ep4Intr" value="0x1U"/>
<Param id="ep5Intr" value="0x1U"/>
<Param id="ep6Intr" value="0x1U"/>
<Param id="ep7Intr" value="0x1U"/>
<Param id="inFlash" value="true"/>
</Block>
</BlockConfig>
<Netlist>
<Net>
@ -412,14 +332,6 @@
<Port name="ioss[0].port[0].pin[1].analog[0]"/>
<Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[0].digital_inout[0]"/>
<Port name="scb[5].uart_rx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[5].pin[1].digital_inout[0]"/>
<Port name="scb[5].uart_tx[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[6].pin[0].digital_inout[0]"/>
<Port name="scb[3].i2c_scl[0]"/>
@ -453,8 +365,16 @@
<Port name="smif[0].spi_clk[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[0].clk[0]"/>
<Port name="scb[5].clock[0]"/>
<Port name="ioss[0].port[14].pin[0].aux[0]"/>
<Port name="usb[0].usb_dp_pad[0]"/>
</Net>
<Net>
<Port name="ioss[0].port[14].pin[1].aux[0]"/>
<Port name="usb[0].usb_dm_pad[0]"/>
</Net>
<Net>
<Port name="peri[0].div_16[0].clk[0]"/>
<Port name="usb[0].clock_dev_brs[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[1].clk[0]"/>
@ -468,11 +388,13 @@
<Port name="smif[0].clk_if[0]"/>
<Port name="srss[0].clock[0].hfclk[2].root_clk[0]"/>
</Net>
<Net>
<Port name="srss[0].clock[0].hfclk[3].root_clk[0]"/>
<Port name="usb[0].clk_usb_dev[0]"/>
</Net>
</Netlist>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<Libraries/>
<ConfiguratorData/>
</Design>

94
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* \file CY8CPROTO-064-SB/cybsp.c
* \file cybsp.c
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CPROTO-064-SB prototyping kit.
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
@ -23,37 +23,93 @@
* limitations under the License.
*******************************************************************************/
#include <stdlib.h>
#include "cybsp.h"
#include "cyhal_utils.h"
#include "cycfg.h"
#if defined(__cplusplus)
extern "C" {
#endif
cy_rslt_t cybsp_init(void)
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
cy_rslt_t result = cyhal_hwmgr_init();
init_cycfg_system();
result = cybsp_register_sysclk_pm_callback();
#ifndef __MBED__
if (CY_RSLT_SUCCESS == result)
{
/* Initialize User LEDs */
result |= cybsp_led_init(CYBSP_USER_LED1);
result |= cybsp_led_init(CYBSP_USER_LED2);
/* Initialize User Buttons */
result |= cybsp_btn_init(CYBSP_USER_BTN1);
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
if (CY_RSLT_SUCCESS == result)
{
result = cybsp_retarget_init();
}
result = cybsp_register_sysclk_pm_callback();
}
#endif
#if defined(CYBSP_WIFI_CAPABLE)
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}

55
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h
View File

@ -1,9 +1,8 @@
/***************************************************************************//**
* \file CY8CPROTO-064-SB/cybsp.h
* \file cybsp.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CY8CPROTO-064-SB prototyping kit.
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
@ -25,12 +24,50 @@
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_core.h"
#ifndef __MBED__
#include "cybsp_retarget.h"
#endif /* __MBED__ */
#if defined(CYBSP_WIFI_CAPABLE)
#include "cyhal_sdio.h"
#endif
#if defined(__cplusplus)
}
extern "C" {
#endif
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */

187
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h
View File

@ -25,122 +25,115 @@
#pragma once
#include "cyhal.h"
#include "cyhal_pin_package.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
/* Board components mapping */
/** Pin: LED3 in the CY8CPROTO-064-SB board */
#define CYBSP_LED3 P13_7
/** Pin: LED4 in the CY8CPROTO-064-SB board */
#define CYBSP_LED4 P1_5
/** Pin: SW2 in the CY8CPROTO-064-SB board */
#define CYBSP_SW2 P0_4
/* Board peripheral count */
/** Macro: Number of LEDs on CY8CPROTO-064-SB board */
#define CYBSP_LED_COUNT 2
/** Macro: Number of buttons on CY8CPROTO-064-SB board */
#define CYBSP_BTN_COUNT 1
/* Generic signal names */
/** Pin: WCO input */
#define CYBSP_WCO_IN P0_0
/** Pin: WCO output */
#define CYBSP_WCO_OUT P0_1
/** Pin: ECO input */
#define CYBSP_ECO_IN P12_6
/** Pin: ECO output */
#define CYBSP_ECO_OUT P12_7
/** Pin: UART RX */
#define CYBSP_UART_RX P5_0
/** Pin: UART TX */
#define CYBSP_UART_TX P5_1
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX P5_0
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX P5_1
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL P6_0
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA P6_1
/** Pin: SWDIO */
#define CYBSP_SWDIO P6_6
/** Pin: SWDCK */
#define CYBSP_SWDCK P6_7
/** Pin: SWO */
#define CYBSP_SWO P6_4
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK P11_7
/** Pin: USB Device D+ */
#define CYBSP_USB_DP P14_0
/** Pin: USB Device D- */
#define CYBSP_USB_DM P14_1
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_enums Enumerated Types
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** Enum defining the different states for the LED. */
typedef enum
{
CYBSP_LED_STATE_ON = 0,
CYBSP_LED_STATE_OFF = 1,
} cybsp_led_state_t;
/** LED 3; User LED1 */
#define CYBSP_LED3 (P13_7)
/** LED 4; User LED2 */
#define CYBSP_LED4 (P1_5)
/** Enum defining the different states for a button. */
typedef enum
{
CYBSP_BTN_PRESSED = 0,
CYBSP_BTN_OFF = 1,
} cybsp_btn_state_t;
/** LED 3; User LED1 */
#define CYBSP_USER_LED1 (CYBSP_LED3)
/** LED 4; User LED2 */
#define CYBSP_USER_LED2 (CYBSP_LED4)
/** LED 3; User LED1 */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** Enum defining the different LED pins on the board. */
typedef enum
{
CYBSP_LED_RED = CYBSP_LED3,
CYBSP_LED_GREEN = CYBSP_LED4,
/** \} group_bsp_pins_led */
CYBSP_USER_LED = CYBSP_LED_RED,
CYBSP_USER_LED1 = CYBSP_LED_RED,
CYBSP_USER_LED2 = CYBSP_LED_GREEN,
} cybsp_led_t;
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** Enum defining the different button pins on the board. */
typedef enum
{
CYBSP_USER_BTN = CYBSP_SW2,
CYBSP_USER_BTN1 = CYBSP_SW2,
} cybsp_btn_t;
/** Switch 2; User Button 1 */
#define CYBSP_SW2 (P0_4)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW2)
/** Switch 2; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: UART RX */
#define CYBSP_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_UART_TX (P5_1)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P5_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P5_1)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** \} group_bsp_pins_comm */
/** \} group_bsp_pins */
/** \} group_bsp_enums */
#if defined(__cplusplus)
}

14
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_ARM/cyb06xx7_cm4_dual.sct
View File

@ -4,7 +4,7 @@
;*******************************************************************************
;* \file cyb06xx7_cm4_dual.sct
;* \version 2.50
;* \version 2.60
;*
;* Linker file for the ARMCC.
;*
@ -78,6 +78,7 @@
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; Size of the stack section at the end of CM4 SRAM
#define STACK_SIZE MBED_BOOT_STACK_SIZE
; The defines below describe the location and size of blocks of memory in the target.
@ -133,12 +134,9 @@
#define EFUSE_START 0x90700000
#define EFUSE_SIZE 0x100000
; Size and start address of the Cortex-M4 application image
#define FLASH_CM4_SIZE FLASH_SIZE
#define FLASH_CM4_START FLASH_START
; Cortex-M4 application image
LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
; Cortex-M4 application flash area
LR_IROM1 FLASH_START FLASH_SIZE
{
ER_FLASH_VECTORS +0
{
@ -159,7 +157,7 @@ LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
RW_RAM_DATA +0
{
* (.cy_ramfunc)
.ANY (+RW, +ZI)
* (+RW, +ZI)
}
; Place variables in the section that should not be initialized during the
@ -275,7 +273,7 @@ CYMETA 0x90500000
/* The following symbols used by the cymcuelftool. */
/* Flash */
#define __cy_memory_0_start 0x10000000
#define __cy_memory_0_length 0x00100000
#define __cy_memory_0_length 0x000D0000
#define __cy_memory_0_row_size 0x200
/* Emulated EEPROM Flash area */

18
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xx7_cm4_dual.ld
* \version 2.50
* \version 2.60
*
* Linker file for the GNU C compiler.
*
@ -76,6 +76,7 @@ ENTRY(Reset_Handler)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
/* Size of the stack section at the end of CM4 SRAM */
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Force symbol to be entered in the output file as an undefined symbol. Doing
@ -118,10 +119,6 @@ MEMORY
efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */
}
/* Size and start address of the Cortex-M4 application image */
FLASH_CM4_SIZE = LENGTH(flash);
FLASH_CM4_START = ORIGIN(flash);
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
@ -161,8 +158,8 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
SECTIONS
{
/* Cortex-M4 application image */
.text FLASH_CM4_START :
/* Cortex-M4 application flash area */
.text ORIGIN(flash) :
{
. = ALIGN(4);
__Vectors = . ;
@ -278,7 +275,6 @@ SECTIONS
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
@ -339,7 +335,7 @@ SECTIONS
__HeapLimit = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
@ -392,7 +388,7 @@ SECTIONS
KEEP(*(.cy_toc_part2))
} > sflash_toc_2
/* Supervisory Flash: Table of Content # 2 Copy */
.cy_rtoc_part2 :
{
@ -426,7 +422,7 @@ SECTIONS
/* The following symbols used by the cymcuelftool. */
/* Flash */
__cy_memory_0_start = 0x10000000;
__cy_memory_0_length = 0x00100000;
__cy_memory_0_length = 0x000D0000;
__cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */

12
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/cyb06xx7_cm4_dual.icf
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file cyb06xx7_cm4_dual.icf
* \version 2.50
* \version 2.60
*
* Linker file for the IAR compiler.
*
@ -156,7 +156,7 @@ if (!isdefinedsymbol(__STACK_SIZE)) {
/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
if (!isdefinedsymbol(__HEAP_SIZE)) {
define symbol __ICFEDIT_size_heap__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x0400;
} else {
define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
}
@ -191,8 +191,10 @@ do not initialize { section .noinit, section .intvec_ram };
/*-Placement-*/
/* Flash - Cortex-M4 application image */
place in IROM1_region { block RO };
/* Flash - Cortex-M4 application */
place at start of IROM1_region { block RO };
/* Used for the digital signature of the secure application and the Bootloader SDK application. */
".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
/* Emulated EEPROM Flash area */
@ -245,7 +247,7 @@ keep { section .cy_app_signature,
/* The following symbols used by the cymcuelftool. */
/* Flash */
define exported symbol __cy_memory_0_start = 0x10000000;
define exported symbol __cy_memory_0_length = 0x00100000;
define exported symbol __cy_memory_0_length = 0x000D0000;
define exported symbol __cy_memory_0_row_size = 0x200;
/* Emulated EEPROM Flash area */

4
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_IAR/startup_psoc6_01_cm4.S
View File

@ -310,10 +310,6 @@ intvec_copy
STR r0, [r1]
dsb
; Enable the FPU if used
LDR R0, =Cy_SystemInitFpuEnable
BLX R0
; Initialize data sections
LDR R0, =__iar_data_init3
BLX R0

7
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6.h
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6.h
* \version 2.50
* \version 2.60
*
* \brief Device system header file.
*
@ -320,6 +320,11 @@
* <th>Reason for Change</th>
* </tr>
* <tr>
* <td>2.60</td>
* <td>Updated linker scripts.</td>
* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
* </tr>
* <tr>
* <td>2.50</td>
* <td>Updated assembler files, C files, linker scripts.</td>
* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>

2
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/system_psoc6_cm4.c
View File

@ -1,6 +1,6 @@
/***************************************************************************//**
* \file system_psoc6_cm4.c
* \version 2.50
* \version 2.60
*
* The device system-source file.
*

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
View File

@ -28,7 +28,6 @@ void init_cycfg_all(void)
{
init_cycfg_system();
init_cycfg_clocks();
init_cycfg_dmas();
init_cycfg_routing();
init_cycfg_peripherals();
init_cycfg_pins();

1
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h
View File

@ -32,7 +32,6 @@ extern "C" {
#include "cycfg_notices.h"
#include "cycfg_system.h"
#include "cycfg_clocks.h"
#include "cycfg_dmas.h"
#include "cycfg_routing.h"
#include "cycfg_peripherals.h"
#include "cycfg_pins.h"

31
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
View File

@ -25,19 +25,11 @@
#include "cycfg_clocks.h"
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj =
const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_USB_UART_CLK_DIV_HW,
.channel_num = CYBSP_USB_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = CYBSP_SDIO_CLK_DIV_HW,
.channel_num = CYBSP_SDIO_CLK_DIV_NUM,
.block_num = CYBSP_USB_CLK_DIV_HW,
.channel_num = CYBSP_USB_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
@ -49,11 +41,11 @@
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t peri_0_div_8_3_obj =
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
{
.type = CYHAL_RSC_CLOCK,
.block_num = peri_0_div_8_3_HW,
.channel_num = peri_0_div_8_3_NUM,
.block_num = CYBSP_BT_UART_CLK_DIV_HW,
.channel_num = CYBSP_BT_UART_CLK_DIV_NUM,
};
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
@ -88,14 +80,7 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_USB_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&CYBSP_SDIO_CLK_DIV_obj);
cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
@ -109,7 +94,7 @@ void init_cycfg_clocks(void)
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 108U);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&peri_0_div_8_3_obj);
cyhal_hwmgr_reserve(&CYBSP_BT_UART_CLK_DIV_obj);
#endif //defined (CY_USING_HAL)
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h
View File

@ -35,18 +35,15 @@
extern "C" {
#endif
#define CYBSP_USB_UART_CLK_DIV_ENABLED 1U
#define CYBSP_USB_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_UART_CLK_DIV_NUM 0U
#define CYBSP_SDIO_CLK_DIV_ENABLED 1U
#define CYBSP_SDIO_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_SDIO_CLK_DIV_NUM 0U
#define CYBSP_USB_CLK_DIV_ENABLED 1U
#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
#define CYBSP_USB_CLK_DIV_NUM 0U
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
#define peri_0_div_8_3_ENABLED 1U
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
#define peri_0_div_8_3_NUM 3U
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_BT_UART_CLK_DIV_NUM 3U
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
#define CYBSP_CSD_CLK_DIV_NUM 4U
@ -58,16 +55,13 @@ extern "C" {
#define CYBSP_WL_UART_CLK_DIV_NUM 6U
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_USB_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_SDIO_CLK_DIV_obj;
extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t peri_0_div_8_3_obj;
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;

230
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c
View File

@ -1,230 +0,0 @@
/*******************************************************************************
* File Name: cycfg_dmas.c
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#include "cycfg_dmas.h"
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_1D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 1,
.xCount = 6,
.srcYincrement = 0,
.dstYincrement = 0,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig =
{
.descriptor = &cpuss_0_dw0_0_chan_0_Descriptor_0,
.preemptable = true,
.priority = 1,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_0_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_16CYC,
.interruptType = CY_DMA_1ELEMENT,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_1ELEMENT,
.dataSize = CY_DMA_BYTE,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_1D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 1,
.dstXincrement = 0,
.xCount = 5,
.srcYincrement = 0,
.dstYincrement = 0,
.yCount = 1,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig =
{
.descriptor = &cpuss_0_dw0_0_chan_1_Descriptor_0,
.preemptable = true,
.priority = 1,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 0U,
.channel_num = cpuss_0_dw0_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_4CYC,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_X_LOOP,
.dataSize = CY_DMA_HALFWORD,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_2D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 2,
.dstXincrement = 0,
.xCount = 10,
.srcYincrement = 10,
.dstYincrement = 0,
.yCount = 2,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig =
{
.descriptor = &cpuss_0_dw1_0_chan_1_Descriptor_0,
.preemptable = false,
.priority = 0,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_1_CHANNEL,
};
#endif //defined (CY_USING_HAL)
const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config =
{
.retrigger = CY_DMA_RETRIG_IM,
.interruptType = CY_DMA_DESCR,
.triggerOutType = CY_DMA_1ELEMENT,
.channelState = CY_DMA_CHANNEL_DISABLED,
.triggerInType = CY_DMA_X_LOOP,
.dataSize = CY_DMA_HALFWORD,
.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
.descriptorType = CY_DMA_2D_TRANSFER,
.srcAddress = NULL,
.dstAddress = NULL,
.srcXincrement = 0,
.dstXincrement = 2,
.xCount = 10,
.srcYincrement = 0,
.dstYincrement = 10,
.yCount = 2,
.nextDescriptor = NULL,
};
cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0 =
{
.ctl = 0UL,
.src = 0UL,
.dst = 0UL,
.xCtl = 0UL,
.yCtl = 0UL,
.nextPtr = 0UL,
};
const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig =
{
.descriptor = &cpuss_0_dw1_0_chan_3_Descriptor_0,
.preemptable = false,
.priority = 0,
.enable = false,
.bufferable = false,
};
#if defined (CY_USING_HAL)
const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj =
{
.type = CYHAL_RSC_DMA,
.block_num = 1U,
.channel_num = cpuss_0_dw1_0_chan_3_CHANNEL,
};
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void)
{
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_0_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw0_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_1_obj);
#endif //defined (CY_USING_HAL)
#if defined (CY_USING_HAL)
cyhal_hwmgr_reserve(&cpuss_0_dw1_0_chan_3_obj);
#endif //defined (CY_USING_HAL)
}

87
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h
View File

@ -1,87 +0,0 @@
/*******************************************************************************
* File Name: cycfg_dmas.h
*
* Description:
* DMA configuration
* This file was automatically generated and should not be modified.
*
********************************************************************************
* Copyright 2017-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
********************************************************************************/
#if !defined(CYCFG_DMAS_H)
#define CYCFG_DMAS_H
#include "cycfg_notices.h"
#include "cy_dma.h"
#if defined (CY_USING_HAL)
#include "cyhal_hwmgr.h"
#endif //defined (CY_USING_HAL)
#if defined(__cplusplus)
extern "C" {
#endif
#define cpuss_0_dw0_0_chan_0_ENABLED 1U
#define cpuss_0_dw0_0_chan_0_HW DW0
#define cpuss_0_dw0_0_chan_0_CHANNEL 0U
#define cpuss_0_dw0_0_chan_0_IRQ cpuss_interrupts_dw0_0_IRQn
#define cpuss_0_dw0_0_chan_1_ENABLED 1U
#define cpuss_0_dw0_0_chan_1_HW DW0
#define cpuss_0_dw0_0_chan_1_CHANNEL 1U
#define cpuss_0_dw0_0_chan_1_IRQ cpuss_interrupts_dw0_1_IRQn
#define cpuss_0_dw1_0_chan_1_ENABLED 1U
#define cpuss_0_dw1_0_chan_1_HW DW1
#define cpuss_0_dw1_0_chan_1_CHANNEL 1U
#define cpuss_0_dw1_0_chan_1_IRQ cpuss_interrupts_dw1_1_IRQn
#define cpuss_0_dw1_0_chan_3_ENABLED 1U
#define cpuss_0_dw1_0_chan_3_HW DW1
#define cpuss_0_dw1_0_chan_3_CHANNEL 3U
#define cpuss_0_dw1_0_chan_3_IRQ cpuss_interrupts_dw1_3_IRQn
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_0_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_0_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_0_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_0_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw0_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw0_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw0_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw0_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_1_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_1_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_1_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_1_obj;
#endif //defined (CY_USING_HAL)
extern const cy_stc_dma_descriptor_config_t cpuss_0_dw1_0_chan_3_Descriptor_0_config;
extern cy_stc_dma_descriptor_t cpuss_0_dw1_0_chan_3_Descriptor_0;
extern const cy_stc_dma_channel_config_t cpuss_0_dw1_0_chan_3_channelConfig;
#if defined (CY_USING_HAL)
extern const cyhal_resource_inst_t cpuss_0_dw1_0_chan_3_obj;
#endif //defined (CY_USING_HAL)
void init_cycfg_dmas(void);
#if defined(__cplusplus)
}
#endif
#endif /* CYCFG_DMAS_H */

3
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h
View File

@ -123,9 +123,8 @@ extern "C" {
#define CYBSP_RTC_YEAR_OFFSET (0U)
#define CYBSP_USBUART_ENABLED 1U
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 7U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 140U
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
#define CYBSP_USBUART_USB_CORE 4U
#define CYBSP_USBUART_HW USBFS0
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c
View File

@ -24,7 +24,7 @@
#include "cycfg_qspi_memslot.h"
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xECU,
@ -42,7 +42,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x06U,
@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x04U,
@ -78,7 +78,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0xDCU,
@ -96,7 +96,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x60U,
@ -114,7 +114,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x34U,
@ -132,7 +132,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd =
.dataWidth = CY_SMIF_WIDTH_QUAD
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x35U,
@ -150,7 +150,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x05U,
@ -168,7 +168,7 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
{
/* The 8-bit command. 1 x I/O read command. */
.command = 0x01U,
@ -186,34 +186,34 @@ const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
.dataWidth = CY_SMIF_WIDTH_SINGLE
};
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Specifies the number of address bytes used by the memory slave device. */
.numOfAddrBytes = 0x04U,
/* The size of the memory. */
.memSize = 0x04000000U,
/* Specifies the Read command. */
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readCmd,
.readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
/* Specifies the Write Enable command. */
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd,
.writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
/* Specifies the Write Disable command. */
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd,
.writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
/* Specifies the Erase command. */
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd,
.eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
/* Specifies the sector size of each erase. */
.eraseSize = 0x00040000U,
/* Specifies the Chip Erase command. */
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd,
.chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
/* Specifies the Program command. */
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_programCmd,
.programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
/* Specifies the page size for programming. */
.programSize = 0x00000200U,
/* Specifies the command to read the QE-containing status register. */
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd,
.readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
/* Specifies the command to read the WIP-containing status register. */
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd,
.readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
/* Specifies the command to write into the QE-containing status register. */
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
.writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
/* The mask for the status register. */
.stsRegBusyMask = 0x01U,
/* The mask for the status register. */
@ -226,7 +226,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0 =
.programTime = 1300U
};
const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
{
/* Determines the slot number where the memory device is placed. */
.slaveSelect = CY_SMIF_SLAVE_SELECT_0,
@ -244,11 +244,11 @@ const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0 =
Valid when the memory mapped mode is enabled. */
.dualQuadSlots = 0,
/* The configuration of the device. */
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0
.deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
&S25FL512SX4byteaddr_SlaveSlot_0
&S25FL512S_4byteaddr_SlaveSlot_0
};
const cy_stc_smif_block_config_t smifBlockConfig =

22
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h
View File

@ -28,19 +28,19 @@
#define CY_SMIF_DEVICE_NUM 1
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512SX4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd;
extern const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512SX4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0;
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
extern const cy_stc_smif_block_config_t smifBlockConfig;

44
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list
View File

@ -1,27 +1,14 @@
[Device="CY8C6247BZI-D54"]
[Device=CY8C6247BZI-D54]
[Blocks]
# User IO
# CYBSP_USER_LED1
ioss[0].port[0].pin[3]
# CYBSP_USER_LED2
ioss[0].port[1].pin[1]
# CYBSP_USER_LED3
ioss[0].port[10].pin[6]
# CYBSP_USER_BTN1
ioss[0].port[0].pin[4]
# Debug
# CYBSP_DEBUG_UART
scb[6]
# CYBSP_DEBUG_UART_RX
ioss[0].port[13].pin[0]
# CYBSP_DEBUG_UART_TX
ioss[0].port[13].pin[1]
# WIFI
# CYBSP_WIFI_SDIO
udb[0]
peri[0].div_8[0]
cpuss[0].dw0[0].chan[0]
cpuss[0].dw0[0].chan[1]
cpuss[0].dw1[0].chan[1]
cpuss[0].dw1[0].chan[3]
# CYBSP_WIFI_SDIO_D0
ioss[0].port[2].pin[0]
# CYBSP_WIFI_SDIO_D1
@ -35,4 +22,21 @@ ioss[0].port[2].pin[4]
# CYBSP_WIFI_SDIO_CLK
ioss[0].port[2].pin[5]
# CYBSP_WIFI_WL_REG_ON
ioss[0].port[2].pin[6]
ioss[0].port[2].pin[6]
[RoutingResources]
# CYBSP_WIFI_SDIO
cpuss[0].dw0_tr_in[0]
cpuss[0].dw0_tr_in[1]
cpuss[0].dw1_tr_in[1]
cpuss[0].dw1_tr_in[3]
udb[0].tr_udb[0]
udb[0].tr_udb[1]
udb[0].tr_udb[3]
udb[0].tr_udb[7]
tr_group[0].input[43]
tr_group[0].input[44]
tr_group[0].input[47]
tr_group[0].input[48]

136
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/COMPONENT_BSP_DESIGN_MODUS/design.modus
View File

@ -8,114 +8,6 @@
<Param id="dbgMode" value="SWD"/>
<Param id="traceEnable" value="true"/>
</Block>
<Block location="cpuss[0].dw0[0].chan[0]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="1"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="true"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="6"/>
<Param id="X_SRC_INCREMENT_0" value="0"/>
<Param id="X_DST_INCREMENT_0" value="1"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw0[0].chan[1]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="1"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="true"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_1ELEMENT"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_16CYC"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="ByteToByte"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="5"/>
<Param id="X_SRC_INCREMENT_0" value="1"/>
<Param id="X_DST_INCREMENT_0" value="0"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="1"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw1[0].chan[1]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="0"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="false"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_4CYC"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
<Param id="X_SRC_INCREMENT_0" value="2"/>
<Param id="X_DST_INCREMENT_0" value="0"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
<Param id="Y_SRC_INCREMENT_0" value="10"/>
<Param id="Y_DST_INCREMENT_0" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="cpuss[0].dw1[0].chan[3]" alias="" template="mxs40dma" version="1.0">
<Param id="CRC_DATA_REVERSE" value="false"/>
<Param id="CRC_DATA_XOR" value="0"/>
<Param id="CRC_REMINDER_REVERSE" value="false"/>
<Param id="CRC_REMINDER_XOR" value="0"/>
<Param id="CRC_POLYNOMIAL" value="79764919"/>
<Param id="CHANNEL_PRIORITY" value="0"/>
<Param id="NUM_OF_DESCRIPTORS" value="1"/>
<Param id="PREEMPTABLE" value="false"/>
<Param id="BUFFERABLE" value="false"/>
<Param id="DESCR_SELECTION" value="0"/>
<Param id="TRIG_OUT_TYPE_0" value="CY_DMA_1ELEMENT"/>
<Param id="INTR_OUT_0" value="CY_DMA_DESCR"/>
<Param id="ENABLE_CHAINING_0" value="false"/>
<Param id="CHAN_STATE_COMPL_0" value="CY_DMA_CHANNEL_DISABLED"/>
<Param id="TRIG_IN_TYPE_0" value="CY_DMA_X_LOOP"/>
<Param id="TRIG_DEACT_0" value="CY_DMA_RETRIG_IM"/>
<Param id="DATA_TRANSFER_WIDTH_0" value="HalfwordToHalfword"/>
<Param id="X_NUM_OF_ELEMENTS_0" value="10"/>
<Param id="X_SRC_INCREMENT_0" value="0"/>
<Param id="X_DST_INCREMENT_0" value="2"/>
<Param id="CRC_0" value="false"/>
<Param id="Y_NUM_OF_ELEMENTS_0" value="2"/>
<Param id="Y_SRC_INCREMENT_0" value="0"/>
<Param id="Y_DST_INCREMENT_0" value="10"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="csd[0].csd[0]" alias="CYBSP_CapSense" template="mxs40csd" version="2.0">
<Param id="CapSenseEnable" value="true"/>
<Param id="CapSenseCore" value="4"/>
@ -762,22 +654,17 @@
<Param id="sioOutputBuffer" value="true"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="peri[0].div_16[0]" alias="CYBSP_USB_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Block location="peri[0].div_16[0]" alias="CYBSP_USB_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="1000"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[0]" alias="CYBSP_SDIO_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="1"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[1]" alias="CYBSP_CSD_COMM_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="8"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
</Block>
<Block location="peri[0].div_8[3]" alias="" template="mxs40peripheralclock" version="1.0">
<Block location="peri[0].div_8[3]" alias="CYBSP_BT_UART_CLK_DIV" template="mxs40peripheralclock" version="1.0">
<Param id="intDivider" value="109"/>
<Param id="fracDivider" value="0"/>
<Param id="startOnReset" value="true"/>
@ -1041,7 +928,6 @@
<Param id="inFlash" value="true"/>
</Block>
<Block location="srss[0].power[0]" alias="" template="mxs40power" version="1.2">
<Param id="pwrEstimator" value="0"/>
<Param id="pwrMode" value="LDO_1_1"/>
<Param id="actPwrMode" value="LP"/>
<Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
@ -1081,12 +967,10 @@
<Param id="dstStopHour" value="0"/>
<Param id="inFlash" value="true"/>
</Block>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.0">
<Param id="configurator" value=""/>
<Param id="UsbCore" value="4"/>
<Block location="usb[0]" alias="CYBSP_USBUART" template="mxs40usbfsdevice" version="1.1">
<Param id="epMask" value="7"/>
<Param id="bufSize" value="140"/>
<Param id="mngMode" value="CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU"/>
<Param id="bufSize" value="140"/>
<Param id="epAccess" value="CY_USBFS_DEV_DRV_USE_8_BITS_DR"/>
<Param id="enableLpm" value="false"/>
<Param id="lpmIntr" value="0x0U"/>
@ -1246,6 +1130,14 @@
<Port name="peri[0].div_8[3].clk[0]"/>
<Port name="scb[2].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[5].clk[0]"/>
<Port name="scb[1].clock[0]"/>
</Net>
<Net>
<Port name="peri[0].div_8[6].clk[0]"/>
<Port name="scb[5].clock[0]"/>
</Net>
<Net>
<Port name="smif[0].clk_hf[0]"/>
<Port name="srss[0].clock[0].hfclk[0].root_clk[0]"/>
@ -1303,8 +1195,6 @@
<Netlist/>
</Device>
</Devices>
<Libraries>
<Library name="psoc6sw" version="1.2"/>
</Libraries>
<Libraries/>
<ConfiguratorData/>
</Design>

107
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.c
View File

@ -1,9 +1,9 @@
/***************************************************************************//**
* \file CYW943012P6EVB-01/cybsp.c
* \file cybsp.c
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CYW943012P6EVB-01 kit.
* Provides initialization code for starting up the hardware contained on the
* Cypress board.
*
********************************************************************************
* \copyright
@ -25,17 +25,58 @@
#include <stdlib.h>
#include "cybsp.h"
#include "cyhal_utils.h"
#include "cycfg.h"
#if defined(__cplusplus)
extern "C" {
#endif
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
#if defined(CYBSP_WIFI_CAPABLE)
static cyhal_sdio_t sdio_obj;
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif
/**
* Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
*/
static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
cy_rslt_t cybsp_init(void)
{
cy_rslt_t result;
result = cyhal_hwmgr_init();
/* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
cy_rslt_t result = cyhal_hwmgr_init();
init_cycfg_system();
if (CY_RSLT_SUCCESS == result)
@ -43,48 +84,32 @@ cy_rslt_t cybsp_init(void)
result = cybsp_register_sysclk_pm_callback();
}
#ifndef __MBED__
if (CY_RSLT_SUCCESS == result)
{
/* Initialize User LEDs */
/* Reserves: CYBSP_USER_LED1 */
result |= cybsp_led_init(CYBSP_USER_LED1);
/* Reserves: CYBSP_USER_LED2 */
result |= cybsp_led_init(CYBSP_USER_LED2);
/* Reserves: CYBSP_USER_LED3 */
result |= cybsp_led_init(CYBSP_USER_LED3);
/* Initialize User Buttons */
/* Reserves: CYBSP_USER_BTN1 */
result |= cybsp_btn_init(CYBSP_USER_BTN1);
CY_ASSERT(CY_RSLT_SUCCESS == result);
/* Initialize retargetting stdio to 'DEBUG_UART' peripheral */
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_DEBUG_UART_RX, CYBSP_DEBUG_UART_TX, corresponding SCB instance
* and one of available clock dividers */
result = cybsp_retarget_init();
}
}
#endif /* __MBED__ */
#if defined(CYBSP_WIFI_CAPABLE)
/* Initialize UDB SDIO interface. This must be done before any other HAL API attempts to allocate clocks or DMA
instances. The UDB SDIO interface uses specific instances which are reserved as part of this call.
NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically done
when starting up WiFi. */
/* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
* specific peripheral instances.
* NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
* done when starting up WiFi.
*/
if (CY_RSLT_SUCCESS == result)
{
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK and CYBSP_WIFI_WL_REG_ON */
result = cybsp_wifi_sdio_init();
/* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
* CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
*/
result = cyhal_sdio_init(
&sdio_obj,
CYBSP_WIFI_SDIO_CMD,
CYBSP_WIFI_SDIO_CLK,
CYBSP_WIFI_SDIO_D0,
CYBSP_WIFI_SDIO_D1,
CYBSP_WIFI_SDIO_D2,
CYBSP_WIFI_SDIO_D3);
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both. */
* user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
* (cyreservedresources.list) to make sure no resources are reserved by both.
*/
return result;
}

53
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp.h
View File

@ -1,9 +1,8 @@
/***************************************************************************//**
* \file CYW943012P6EVB-01/cybsp.h
* \file cybsp.h
*
* Description:
* Provides APIs for interacting with the hardware contained on the Cypress
* CYW943012P6EVB-01 kit.
* \brief
* Basic API for setting up boards containing a Cypress MCU.
*
********************************************************************************
* \copyright
@ -25,20 +24,50 @@
#pragma once
#include "cy_result.h"
#include "cybsp_types.h"
#include "cybsp_core.h"
#if defined(CYBSP_WIFI_CAPABLE)
#include "cybsp_wifi_sdio.h"
#include "cyhal_sdio.h"
#endif
#ifndef __MBED__
#include "cybsp_retarget.h"
#include "cybsp_rgb_led.h"
#endif /* __MBED__ */
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(__cplusplus)
/**
* \addtogroup group_bsp_macros Macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_macros */
/**
* \addtogroup group_bsp_functions Functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
#if defined(CYBSP_WIFI_CAPABLE)
/**
* \brief Get the initialized sdio object used for communicating with the WiFi Chip.
* \note This function should only be called after cybsp_init();
* \returns The initialized sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_functions */
#ifdef __cplusplus
}
#endif
#endif /* __cplusplus */

438
targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/cybsp_types.h
View File

@ -25,286 +25,204 @@
#pragma once
#include "cyhal.h"
#include "cyhal_pin_package.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_pin_state Pin States
* \{
*/
/** Pin state for the LED on. */
#define CYBSP_LED_STATE_ON (0U)
/** Pin state for the LED off. */
#define CYBSP_LED_STATE_OFF (1U)
/** Pin state for when a button is pressed. */
#define CYBSP_BTN_PRESSED (0U)
/** Pin state for when a button is released. */
#define CYBSP_BTN_OFF (1U)
/** \} group_bsp_pin_state */
/**
* \addtogroup group_bsp_pins Pin Mappings
* \{
*/
// Arduino connector namings
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P6_4
/** Arduino A3 */
#define CYBSP_A3 P6_5
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 P5_0
/** Arduino D1 */
#define CYBSP_D1 P5_1
/** Arduino D2 */
#define CYBSP_D2 P5_2
/** Arduino D3 */
#define CYBSP_D3 P5_3
/** Arduino D4 */
#define CYBSP_D4 P5_4
/** Arduino D5 */
#define CYBSP_D5 P5_5
/** Arduino D6 */
#define CYBSP_D6 P5_6
/** Arduino D7 */
#define CYBSP_D7 P5_7
/** Arduino D8 */
#define CYBSP_D8 NC
/** Arduino D9 */
#define CYBSP_D9 NC
/** Arduino D10 */
#define CYBSP_D10 P0_5
/** Arduino D11 */
#define CYBSP_D11 P0_2
/** Arduino D12 */
#define CYBSP_D12 P0_3
/** Arduino D13 */
#define CYBSP_D13 P0_4
/** Arduino D14 */
#define CYBSP_D14 P1_0
/** Arduino D15 */
#define CYBSP_D15 P1_1
// Generic signal names
/** Pin: CYBSP_WCO_IN */
#define CYBSP_WCO_IN P0_0
/** Pin: CYBSP_WCO_OUT */
#define CYBSP_WCO_OUT P0_1
/** Pin: CYBSP_CSD_TX */
#define CYBSP_CSD_TX P1_0
/** Pin: CYBSP_WL_SECI_IN */
#define CYBSP_WL_SECI_IN P1_2
/** Pin: CYBSP_WL_FRAM_SYNC */
#define CYBSP_WL_FRAM_SYNC P1_3
/** Pin: CYBSP_WL_PRIORITY */
#define CYBSP_WL_PRIORITY P1_4
/** Pin: CYBSP_WL_SECI_OUT */
#define CYBSP_WL_SECI_OUT P1_5
/** Pin: CYBSP_WIFI_SDIO_D0 */
/* Corresponds to: ioss[0].port[2].pin[0], udb[0] */
#define CYBSP_WIFI_SDIO_D0 P2_0
/** Pin: CYBSP_WIFI_SDIO_D1 */
/* Corresponds to: ioss[0].port[2].pin[1], udb[0] */
#define CYBSP_WIFI_SDIO_D1 P2_1
/** Pin: CYBSP_WIFI_SDIO_D2 */
/* Corresponds to: ioss[0].port[2].pin[2], udb[0] */
#define CYBSP_WIFI_SDIO_D2 P2_2
/** Pin: CYBSP_WIFI_SDIO_D3 */
/* Corresponds to: ioss[0].port[2].pin[3], udb[0] */
#define CYBSP_WIFI_SDIO_D3 P2_3
/** Pin: CYBSP_WIFI_SDIO_CMD */
/* Corresponds to: ioss[0].port[2].pin[4], udb[0] */
#define CYBSP_WIFI_SDIO_CMD P2_4
/** Pin: CYBSP_WIFI_SDIO_CLK */
/* Corresponds to: ioss[0].port[2].pin[5], udb[0] */
#define CYBSP_WIFI_SDIO_CLK P2_5
/** Pin: CYBSP_WIFI_WL_REG_ON */
/* Corresponds to: ioss[0].port[2].pin[6], udb[0] */
#define CYBSP_WIFI_WL_REG_ON P2_6
/** Pin: CYBSP_WIFI_HOST_WAKE */
#define CYBSP_WIFI_HOST_WAKE P2_7
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM CYHAL_GPIO_DRIVE_ANALOG
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT CYHAL_GPIO_IRQ_RISE
/** Pin: CYBSP_BT_UART_RX */
#define CYBSP_BT_UART_RX P3_0
/** Pin: CYBSP_BT_UART_TX */
#define CYBSP_BT_UART_TX P3_1
/** Pin: CYBSP_BT_UART_RTS */
#define CYBSP_BT_UART_RTS P3_2
/** Pin: CYBSP_BT_UART_CTS */
#define CYBSP_BT_UART_CTS P3_3
/** Pin: BT Power */
#define CYBSP_BT_POWER P3_4
/** Pin: CYBSP_BT_HOST_WAKE */
#define CYBSP_BT_HOST_WAKE P3_5
/** Pin: CYBSP_BT_DEVICE_WAKE */
#define CYBSP_BT_DEVICE_WAKE P4_0
/** Pin: CYBSP_BT_RST */
#define CYBSP_BT_RST P4_1
/** Pin: UART RX */
/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */
#define CYBSP_DEBUG_UART_RX P13_0
/** Pin: UART TX */
/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */
#define CYBSP_DEBUG_UART_TX P13_1
/** Pin: CYBSP_I2C_SCL */
#define CYBSP_I2C_SCL P6_0
/** Pin: CYBSP_I2C_SDA */
#define CYBSP_I2C_SDA P6_1
/** Pin: CYBSP_TDO_SWO */
#define CYBSP_TDO_SWO P6_4
/** Pin: CYBSP_TMS_SWDIO */
#define CYBSP_TMS_SWDIO P6_6
/** Pin: CYBSP_SWCLK */
#define CYBSP_SWCLK P6_7
/** Pin: CYBSP_TRACECLK */
#define CYBSP_TRACECLK P7_0
/** Pin: CYBSP_CINTA */
#define CYBSP_CINTA P7_1
/** Pin: CYBSP_CINTB */
#define CYBSP_CINTB P7_2
/** Pin: CYBSP_CMOD */
#define CYBSP_CMOD P7_7
/** Pin: CYBSP_CSD_BTN0 */
#define CYBSP_CSD_BTN0 P8_1
/** Pin: CYBSP_CSD_BTN1 */
#define CYBSP_CSD_BTN1 P8_2
/** Pin: CYBSP_CSD_SLD0 */
#define CYBSP_CSD_SLD0 P8_3
/** Pin: CYBSP_CSD_SLD1 */
#define CYBSP_CSD_SLD1 P8_4
/** Pin: CYBSP_CSD_SLD2 */
#define CYBSP_CSD_SLD2 P8_5
/** Pin: CYBSP_CSD_SLD3 */
#define CYBSP_CSD_SLD3 P8_6
/** Pin: CYBSP_CSD_SLD4 */
#define CYBSP_CSD_SLD4 P8_7
/** Pin: CYBSP_TRACEDATA3 */
#define CYBSP_TRACEDATA3 P9_0
/** Pin: CYBSP_TRACEDATA2 */
#define CYBSP_TRACEDATA2 P9_1
/** Pin: CYBSP_TRACEDATA1 */
#define CYBSP_TRACEDATA1 P9_2
/** Pin: CYBSP_TRACEDATA0 */
#define CYBSP_TRACEDATA0 P9_3
/** Pin: CYBSP_ROW6_SPI_MOSI */
#define CYBSP_ROW6_SPI_MOSI P10_0
/** Pin: CYBSP_COL8_SPI_MISO */
#define CYBSP_COL8_SPI_MISO P10_1
/** Pin: CYBSP_ROW7_SPI_CLK */
#define CYBSP_ROW7_SPI_CLK P10_2
/** Pin: CYBSP_COL7_SPI_CS */
#define CYBSP_COL7_SPI_CS P10_3
/** Pin: CYBSP_BAT_MON */
#define CYBSP_BAT_MON P10_4
/** Pin: CYBSP_WL_WAKE */
#define CYBSP_WL_WAKE P10_7
/** Pin: CYBSP_UART_RX */
#define CYBSP_UART_RX P11_0
/** Pin: CYBSP_UART_TX */
#define CYBSP_UART_TX P11_1
/** Pin: CYBSP_QSPI_SS */
#define CYBSP_QSPI_SS P11_2
/** Pin: CYBSP_QSPI_D3 */
#define CYBSP_QSPI_D3 P11_3
/** Pin: CYBSP_QSPI_D2 */
#define CYBSP_QSPI_D2 P11_4
/** Pin: CYBSP_QSPI_D1 */
#define CYBSP_QSPI_D1 P11_5
/** Pin: CYBSP_QSPI_D0 */
#define CYBSP_QSPI_D0 P11_6
/** Pin: CYBSP_QSPI_SCK */
#define CYBSP_QSPI_SCK P11_7
/** Pin: CYBSP_BT_GPIO4 */
#define CYBSP_BT_GPIO4 P12_0
/** Pin: CYBSP_BT_GPIO5 */
#define CYBSP_BT_GPIO5 P12_1
/** Pin: CYBSP_BT_GPIO2 */
#define CYBSP_BT_GPIO2 P12_2
/** Pin: CYBSP_BT_GPIO3 */
#define CYBSP_BT_GPIO3 P12_3
/** Pin: CYBSP_ECO_IN */
#define CYBSP_ECO_IN P12_6
/** Pin: CYBSP_ECO_OUT */
#define CYBSP_ECO_OUT P12_7
/** Pin: CYBSP_P6_UART_RX */
/* Corresponds to: ioss[0].port[13].pin[0], scb[6] */
#define CYBSP_P6_UART_RX P13_0
/** Pin: CYBSP_P6_UART_TX */
/* Corresponds to: ioss[0].port[13].pin[1], scb[6] */
#define CYBSP_P6_UART_TX P13_1
/** Pin: CYBSP_USB_DEV_VBUS_DET */
#define CYBSP_USB_DEV_VBUS_DET P13_4
/** Pin: CYBSP_USB_HOST_EN */
#define CYBSP_USB_HOST_EN P13_5
/** Pin: CYBSP_USB_INT_L */
#define CYBSP_USB_INT_L P13_7
/** Pin: CYBSP_USB_DP */
#define CYBSP_USB_DP P14_0
/** Pin: CYBSP_USB_DM */
#define CYBSP_USB_DM P14_1
/** \} group_bsp_pins */
/**
* \addtogroup group_bsp_enums Enumerated Types
* \addtogroup group_bsp_pins_led LED Pins
* \{
*/
/** Enum defining the different states for the LED. */
typedef enum
{
CYBSP_LED_STATE_ON = 0,
CYBSP_LED_STATE_OFF = 1,
} cybsp_led_state_t;
/** LED 5: RGB LED - Red; User LED1 */
#define CYBSP_LED_RGB_RED (P0_3)
/** LED 5: RGB LED - Green; User LED2 */
#define CYBSP_LED_RGB_GREEN (P1_1)
/** LED 5: RGB LED - Blue; User LED3 */
#define CYBSP_LED_RGB_BLUE (P10_6)
/** Enum defining the different states for a button. */
typedef enum
{
CYBSP_BTN_PRESSED = 0,
CYBSP_BTN_OFF = 1,
} cybsp_btn_state_t;
/** LED 5: RGB LED - Red; User LED1 */
#define CYBSP_USER_LED1 (CYBSP_LED_RGB_RED)
/** LED 5: RGB LED - Green; User LED2 */
#define CYBSP_USER_LED2 (CYBSP_LED_RGB_GREEN)
/** LED 5: RGB LED - Blue; User LED3 */
#define CYBSP_USER_LED3 (CYBSP_LED_RGB_BLUE)
/** LED 8; User LED1 */
#define CYBSP_USER_LED (CYBSP_USER_LED1)
/** Enum defining the different LED pins on the board. */
typedef enum
{
CYBSP_LED_RGB_RED = P0_3,
CYBSP_LED_RGB_GREEN = P1_1,
CYBSP_LED_RGB_BLUE = P10_6,
/** \} group_bsp_pins_led */
/* Corresponds to: ioss[0].port[0].pin[3] */
CYBSP_USER_LED1 = CYBSP_LED_RGB_RED,
/* Corresponds to: ioss[0].port[1].pin[1] */
CYBSP_USER_LED2 = CYBSP_LED_RGB_GREEN,
/* Corresponds to: ioss[0].port[10].pin[6] */
CYBSP_USER_LED3 = CYBSP_LED_RGB_BLUE,
CYBSP_USER_LED = CYBSP_USER_LED1,
} cybsp_led_t;
/**
* \addtogroup group_bsp_pins_btn Button Pins
* \{
*/
/** Enum defining the different button pins on the board. */
typedef enum
{
CYBSP_SW6 = P0_4,
/** Switch 6; User Button 1 */
#define CYBSP_SW6 (P0_4)
/* Corresponds to: ioss[0].port[0].pin[4] */
CYBSP_USER_BTN1 = CYBSP_SW6,
CYBSP_USER_BTN = CYBSP_USER_BTN1,
} cybsp_btn_t;
/** Switch 6; User Button 1 */
#define CYBSP_USER_BTN1 (CYBSP_SW6)
/** Switch 6; User Button 1 */
#define CYBSP_USER_BTN (CYBSP_USER_BTN1)
/** \} group_bsp_enums */
/** \} group_bsp_pins_btn */
/**
* \addtogroup group_bsp_pins_comm Communication Pins
* \{
*/
/** Pin: WIFI SDIO D0 */
#define CYBSP_WIFI_SDIO_D0 (P2_0)
/** Pin: WIFI SDIO D1 */
#define CYBSP_WIFI_SDIO_D1 (P2_1)
/** Pin: WIFI SDIO D2 */
#define CYBSP_WIFI_SDIO_D2 (P2_2)
/** Pin: WIFI SDIO D3 */
#define CYBSP_WIFI_SDIO_D3 (P2_3)
/** Pin: WIFI SDIO CMD */
#define CYBSP_WIFI_SDIO_CMD (P2_4)
/** Pin: WIFI SDIO CLK */
#define CYBSP_WIFI_SDIO_CLK (P2_5)
/** Pin: WIFI ON */
#define CYBSP_WIFI_WL_REG_ON (P2_6)
/** Pin: WIFI Host Wakeup */
#define CYBSP_WIFI_HOST_WAKE (P2_7)
/** Pin: BT UART RX */
#define CYBSP_BT_UART_RX (P3_0)
/** Pin: BT UART TX */
#define CYBSP_BT_UART_TX (P3_1)
/** Pin: BT UART RTS */
#define CYBSP_BT_UART_RTS (P3_2)
/** Pin: BT UART CTS */
#define CYBSP_BT_UART_CTS (P3_3)
/** Pin: BT Power */
#define CYBSP_BT_POWER (P3_4)
/** Pin: BT Host Wakeup */
#define CYBSP_BT_HOST_WAKE (P3_5)
/** Pin: BT Device Wakeup */
#define CYBSP_BT_DEVICE_WAKE (P4_0)
/** Pin: UART RX */
#define CYBSP_DEBUG_UART_RX (P13_0)
/** Pin: UART TX */
#define CYBSP_DEBUG_UART_TX (P13_1)
/** Pin: I2C SCL */
#define CYBSP_I2C_SCL (P6_0)
/** Pin: I2C SDA */
#define CYBSP_I2C_SDA (P6_1)
/** Pin: SWO */
#define CYBSP_SWO (P6_4)
/** Pin: SWDIO */
#define CYBSP_SWDIO (P6_6)
/** Pin: SWDCK */
#define CYBSP_SWDCK (P6_7)
/** Pin: QUAD SPI SS */
#define CYBSP_QSPI_SS (P11_2)
/** Pin: QUAD SPI D3 */
#define CYBSP_QSPI_D3 (P11_3)
/** Pin: QUAD SPI D2 */
#define CYBSP_QSPI_D2 (P11_4)
/** Pin: QUAD SPI D1 */
#define CYBSP_QSPI_D1 (P11_5)
/** Pin: QUAD SPI D0 */
#define CYBSP_QSPI_D0 (P11_6)
/** Pin: QUAD SPI SCK */
#define CYBSP_QSPI_SCK (P11_7)
/** Host-wake GPIO drive mode */
#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
/** Host-wake IRQ event */
#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
/** \} group_bsp_pins_comm */
/**
* \addtogroup group_bsp_pins_arduino Arduino Header Pins
* \{
*/
/** Arduino A0 */
#define CYBSP_A0 P10_0
/** Arduino A1 */
#define CYBSP_A1 P10_1
/** Arduino A2 */
#define CYBSP_A2 P6_4
/** Arduino A3 */
#define CYBSP_A3 P6_5
/** Arduino A4 */
#define CYBSP_A4 P10_4
/** Arduino A5 */
#define CYBSP_A5 P10_5
/** Arduino D0 */
#define CYBSP_D0 (P5_0)
/** Arduino D1 */
#define CYBSP_D1 (P5_1)
/** Arduino D2 */
#define CYBSP_D2 (P5_2)
/** Arduino D3 */
#define CYBSP_D3 (P5_3)
/** Arduino D4 */
#define CYBSP_D4 (P5_4)
/** Arduino D5 */
#define CYBSP_D5 (P5_5)
/** Arduino D6 */
#define CYBSP_D6 (P5_6)
/** Arduino D7 */
#define CYBSP_D7 (P5_7)
/** Arduino D8 */
#define CYBSP_D8 (NC)
/** Arduino D9 */
#define CYBSP_D9 (NC)
/** Arduino D10 */
#define CYBSP_D10 (P0_5)
/** Arduino D11 */
#define CYBSP_D11 (P0_2)
/** Arduino D12 */
#define CYBSP_D12 (P0_3)
/** Arduino D13 */
#define CYBSP_D13 (P0_4)
/** Arduino D14 */
#define CYBSP_D14 (P1_0)
/** Arduino D15 */
#define CYBSP_D15 (P1_1)
/** \} group_bsp_pins_arduino */
/** \} group_bsp_pins */
#if defined(__cplusplus)
}

4
targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.c
View File

@ -23,7 +23,7 @@
* limitations under the License.
*******************************************************************************/
#if defined(TARGET_WHD)
#if defined(CYBSP_WIFI_CAPABLE)
#include <stdlib.h>
#include "cy_network_buffer.h"
@ -108,4 +108,4 @@ whd_result_t cy_buffer_add_remove_at_front(whd_buffer_t *buffer, int32_t add_rem
return WHD_SUCCESS;
}
#endif /* defined(TARGET_WHD) */
#endif /* defined(CYBSP_WIFI_CAPABLE) */

4
targets/TARGET_Cypress/TARGET_PSOC6/common/cy_network_buffer.h
View File

@ -32,7 +32,7 @@
*/
#pragma once
#if defined(TARGET_WHD)
#if defined(CYBSP_WIFI_CAPABLE)
#include <stdint.h>
#include <stdbool.h>
@ -176,6 +176,6 @@ void cy_network_process_ethernet_data(whd_interface_t interface, whd_buffer_t bu
}
#endif /* __cplusplus */
#endif /* defined(TARGET_WHD) */
#endif /* defined(CYBSP_WIFI_CAPABLE) */
/** \} group_bsp_network_buffer */

32
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash_prog.c → targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_prog.c
View File

@ -1,11 +1,12 @@
/***************************************************************************//**
* \file cybsp_serial_flash_prog.c
* \file cy_serial_flash_prog.c
*
* \brief
* Provides variables necessary to inform programming tools how to program the
* attached serial flash memory. The variables used here must be placed at
* specific locations in order to be detected and used by programming tools
* to know that there is an attached memory and its characteristics.
* to know that there is an attached memory and its characteristics. Uses the
* configuration provided as part of BSP.
*
********************************************************************************
* \copyright
@ -26,22 +27,22 @@
*******************************************************************************/
/**
* \addtogroup group_bsp_serial_flash Serial Flash
* \addtogroup group_serial_flash Serial Flash
* \{
* Variables for informing programming tools that there is an attached memory device and what
* its characteristics are so it can be programmed just like the on-chip memory.
*
* \defgroup group_bsp_serial_flash_variables Variables
* \defgroup group_serial_flash_variables Variables
*/
#include <stdint.h>
#include "cybsp_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(CYBSP_QSPI_SCK) && (DEVICE_QSPI)
#if defined(CY_ENABLE_XIP_PROGRAM)
#include "cycfg_qspi_memslot.h"
typedef struct
@ -51,7 +52,7 @@ typedef struct
} stc_smif_ipblocks_arr_t;
/**
* \addtogroup group_bsp_serial_flash_variables
* \addtogroup group_serial_flash_variables
* \{
*/
@ -61,7 +62,7 @@ typedef struct
* are multiple ways this can be accomplished including:
* 1) Placing it in a dedicated memory block with a known address. (as done here)
* 2) Placing it at an absolute location via a the linker script
* 3) Using cymcuelftool to recompute the checksum and patch the elf file after linking
* 3) Using 'cymcuelftool -S' to recompute the checksum and patch the elf file after linking
*/
CY_SECTION(".cy_sflash_user_data") __attribute__( (used) )
const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig, 0x00000000};
@ -81,14 +82,21 @@ const uint32_t cyToc[128] =
0, /* Offset=0x0008: Key Storage Address */
(int)&smifIpBlocksArr, /* Offset=0x000C: This points to a null terminated array of SMIF structures. */
0x10000000u, /* Offset=0x0010: App image start address */
[127] = 0x0B1F0000 /* Offset=0x01FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */
/* Offset=0x0014-0x01F7: Reserved */
[126] = 0x000002C2, /* Offset=0x01F8: Bits[ 1: 0] CLOCK_CONFIG (0=8MHz, 1=25MHz, 2=50MHz, 3=100MHz)
Bits[ 4: 2] LISTEN_WINDOW (0=20ms, 1=10ms, 2=1ms, 3=0ms, 4=100ms)
Bits[ 6: 5] SWJ_PINS_CTL (0/1/3=Disable SWJ, 2=Enable SWJ)
Bits[ 8: 7] APP_AUTHENTICATION (0/2/3=Enable, 1=Disable)
Bits[10: 9] FB_BOOTLOADER_CTL: UNUSED */
[127] = 0x3BB30000 /* Offset=0x01FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */
};
/** \} group_bsp_serial_flash_variables */
#endif /* defined(CYBSP_QSPI_SCK) && (DEVICE_QSPI) */
/** \} group_serial_flash_variables */
#endif /* defined(CY_ENABLE_XIP_PROGRAM) */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_serial_flash */
/** \} group_serial_flash */

218
targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.c Normal file
View File

@ -0,0 +1,218 @@
/***************************************************************************//**
* \file cy_serial_flash_qspi.c
*
* \brief
* Provides APIs for interacting with an external flash connected to the SPI or
* QSPI interface, uses SFDP to auto-discover memory properties if SFDP is
* enabled in the configuration.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdbool.h>
#include "cy_serial_flash_qspi.h"
#include "cyhal_qspi.h"
#include "cy_utils.h"
#ifdef CY_IP_MXSMIF
#if defined(__cplusplus)
extern "C" {
#endif
/** \cond internal */
/** Timeout to apply while polling the memory for its ready status after quad
* enable command has been sent out. Quad enable is a non-volatile write.
*/
#define CY_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US (5000lu) /* in microseconds */
/* Number of memories supported by the driver */
#define SMIF_MEM_DEVICES (1u)
/* SMIF slot from which the memory configuration is picked up - fixed to 0 as the driver
* supports only one device */
#define MEM_SLOT (0u)
/** \endcond */
static cyhal_qspi_t qspi_obj;
static cy_stc_smif_mem_config_t * qspi_mem_config[SMIF_MEM_DEVICES];
static cy_stc_smif_block_config_t qspi_block_config =
{
/* The number of SMIF memories defined. */
.memCount = SMIF_MEM_DEVICES,
/* The pointer to the array of memory config structures of size memCount. */
.memConfig = (cy_stc_smif_mem_config_t**)qspi_mem_config,
/* The version of the SMIF driver. */
.majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
/* The version of the SMIF driver. */
.minorVersion = CY_SMIF_DRV_VERSION_MINOR
};
/* The driver supports only one memory. When multiple memory configurations
* are generated by the SMIF configurator tool, provide only the
* configuration for memory that need to be supported by the driver.
* Memory configuration can be changed by deinit followed by init with new
* configuration */
cy_rslt_t cy_serial_flash_qspi_init(
const cy_stc_smif_mem_config_t* mem_config,
cyhal_gpio_t io0,
cyhal_gpio_t io1,
cyhal_gpio_t io2,
cyhal_gpio_t io3,
cyhal_gpio_t io4,
cyhal_gpio_t io5,
cyhal_gpio_t io6,
cyhal_gpio_t io7,
cyhal_gpio_t sclk,
cyhal_gpio_t ssel,
uint32_t hz)
{
cy_en_smif_status_t smifStatus = CY_SMIF_SUCCESS;
cy_rslt_t result = cyhal_qspi_init(&qspi_obj, io0, io1, io2, io3, io4, io5, io6, io7,
sclk, ssel, hz, 0);
qspi_mem_config[MEM_SLOT] = (cy_stc_smif_mem_config_t*) mem_config;
if(CY_RSLT_SUCCESS == result)
{
/* Perform SFDP detection and XIP register configuration depending on the
* memory configuration.
*/
smifStatus = Cy_SMIF_MemInit(qspi_obj.base, &qspi_block_config, &qspi_obj.context);
if(CY_SMIF_SUCCESS == smifStatus)
{
/* Enable Quad mode (1-1-4 or 1-4-4 modes) to use all the four I/Os during
* communication.
*/
if(qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->readCmd->dataWidth == CY_SMIF_WIDTH_QUAD
|| qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->programCmd->dataWidth == CY_SMIF_WIDTH_QUAD)
{
bool isQuadEnabled = false;
smifStatus = Cy_SMIF_MemIsQuadEnabled(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], &isQuadEnabled, &qspi_obj.context);
if(CY_SMIF_SUCCESS == smifStatus)
{
if(!isQuadEnabled)
{
smifStatus = Cy_SMIF_MemEnableQuadMode(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], CY_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US, &qspi_obj.context);
}
}
}
}
}
if((CY_RSLT_SUCCESS == result) && (CY_SMIF_SUCCESS == smifStatus))
{
return CY_RSLT_SUCCESS;
}
else
{
Cy_SMIF_MemDeInit(qspi_obj.base);
cy_serial_flash_qspi_deinit();
return (cy_rslt_t)smifStatus;
}
}
void cy_serial_flash_qspi_deinit(void)
{
Cy_SMIF_MemDeInit(qspi_obj.base);
cyhal_qspi_free(&qspi_obj);
}
size_t cy_serial_flash_qspi_get_size(void)
{
return (size_t)qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->memSize;
}
/* address is ignored for the memory with uniform sector size. Currently,
* QSPI Configurator does not support memories with hybrid sectors.
*/
size_t cy_serial_flash_qspi_get_erase_size(uint32_t addr)
{
CY_UNUSED_PARAMETER(addr);
return (size_t)qspi_block_config.memConfig[MEM_SLOT]->deviceCfg->eraseSize;
}
cy_rslt_t cy_serial_flash_qspi_read(uint32_t addr, size_t length, uint8_t *buf)
{
/* Cy_SMIF_MemRead() returns error if (addr + length) > total flash size. */
return (cy_rslt_t)Cy_SMIF_MemRead(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], addr, buf, length, &qspi_obj.context);
}
cy_rslt_t cy_serial_flash_qspi_write(uint32_t addr, size_t length, const uint8_t *buf)
{
/* Cy_SMIF_MemWrite() returns error if (addr + length) > total flash size. */
return (cy_rslt_t)Cy_SMIF_MemWrite(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], addr, (uint8_t *)buf, length, &qspi_obj.context);
}
/* Does not support hybrid sectors, sector size must be uniform on the entire
* chip. Use cy_serial_flash_qspi_get_erase_size(addr) to implement hybrid sector
* support when QSPI Configurator and PDL supports memories with hybrid sectors.
*/
cy_rslt_t cy_serial_flash_qspi_erase(uint32_t addr, size_t length)
{
cy_en_smif_status_t smifStatus;
/* If the erase is for the entire chip, use chip erase command */
if((addr == 0u) && (length == cy_serial_flash_qspi_get_size()))
{
smifStatus = Cy_SMIF_MemEraseChip(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], &qspi_obj.context);
}
else
{
/* Cy_SMIF_MemEraseSector() returns error if (addr + length) > total flash size
* or if addr is not aligned to erase sector size or if (addr + length)
* is not aligned to erase sector size.
*/
smifStatus = Cy_SMIF_MemEraseSector(qspi_obj.base, qspi_block_config.memConfig[MEM_SLOT], addr, length, &qspi_obj.context);
}
return (cy_rslt_t)smifStatus;
}
// This function enables or disables XIP on the MCU, does not send any command
// to the serial flash. XIP register configuration is already done as part of
// cy_serial_flash_qspi_init() if MMIO mode is enabled in the QSPI
// Configurator.
cy_rslt_t cy_serial_flash_qspi_enable_xip(bool enable)
{
if(enable)
{
Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_MEMORY);
}
else
{
Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_NORMAL);
}
return CY_RSLT_SUCCESS;
}
#if defined(__cplusplus)
}
#endif
#endif /* CY_IP_MXSMIF */

92
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.h → targets/TARGET_Cypress/TARGET_PSOC6/common/cy_serial_flash_qspi.h
View File

@ -1,5 +1,5 @@
/***************************************************************************//**
* \file cybsp_serial_flash.h
* \file cy_serial_flash_qspi.h
*
* \brief
* Provides APIs for interacting with an external flash connected to the SPI or
@ -25,55 +25,83 @@
*******************************************************************************/
/**
* \addtogroup group_bsp_serial_flash Serial Flash
* \addtogroup group_serial_flash Serial Flash
* \{
* Driver for interfacing with the serial flash (QSPI NOR flash) on Cypress boards.
* Driver for interfacing with the serial flash (QSPI NOR flash).
*
* \defgroup group_bsp_serial_flash_macros Macros
* \defgroup group_bsp_serial_flash_functions Functions
* \defgroup group_serial_flash_macros Macros
* \defgroup group_serial_flash_functions Functions
*/
#pragma once
#include <stddef.h>
#include "cy_result.h"
#include "cy_pdl.h"
#include "cyhal.h"
#ifdef CY_IP_MXSMIF
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_serial_flash_macros
* \addtogroup group_serial_flash_macros
* \{
*/
/** The function or operation is not supported on the target or the memory */
#define CYBSP_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 6))
#define CY_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_BOARD_LIB_SERIAL_FLASH, 1))
/** \} group_bsp_serial_flash_macros */
/** \} group_serial_flash_macros */
/**
* \addtogroup group_bsp_serial_flash_functions
* \addtogroup group_serial_flash_functions
* \{
*/
/**
* \brief Initializes the serial flash on the board.
* \brief Initializes the serial flash memory.
* \param mem_config Memory configuration to be used for initializing
* \param io0 Data/IO pin 0 connected to the memory
* \param io1 Data/IO pin 1 connected to the memory
* \param io2 Data/IO pin 2 connected to the memory
* \param io3 Data/IO pin 3 connected to the memory
* \param io4 Data/IO pin 4 connected to the memory
* \param io5 Data/IO pin 5 connected to the memory
* \param io6 Data/IO pin 6 connected to the memory
* \param io7 Data/IO pin 7 connected to the memory
* \param sclk Clock pin connected to the memory
* \param ssel Slave select pin connected to the memory
* \param hz Clock frequency to be used with the memory
* \returns CY_RSLT_SUCCESS if the initialization was successful, an error code
* otherwise.
*/
cy_rslt_t cybsp_serial_flash_init(void);
cy_rslt_t cy_serial_flash_qspi_init(
const cy_stc_smif_mem_config_t* mem_config,
cyhal_gpio_t io0,
cyhal_gpio_t io1,
cyhal_gpio_t io2,
cyhal_gpio_t io3,
cyhal_gpio_t io4,
cyhal_gpio_t io5,
cyhal_gpio_t io6,
cyhal_gpio_t io7,
cyhal_gpio_t sclk,
cyhal_gpio_t ssel,
uint32_t hz);
/**
* \brief De-initializes the serial flash on the board.
* \brief De-initializes the serial flash memory.
*/
void cybsp_serial_flash_deinit(void);
void cy_serial_flash_qspi_deinit(void);
/**
* \brief Returns the size of the serial flash on the board in bytes.
* \brief Returns the size of the serial flash memory in bytes.
* \returns Memory size in bytes.
*/
size_t cybsp_serial_flash_get_size(void);
size_t cy_serial_flash_qspi_get_size(void);
/**
* \brief Returns the size of the erase sector to which the given address
@ -81,38 +109,38 @@ size_t cybsp_serial_flash_get_size(void);
* \param addr Address that belongs to the sector for which size is returned.
* \returns Erase sector size in bytes.
*/
size_t cybsp_serial_flash_get_erase_size(uint32_t addr);
size_t cy_serial_flash_qspi_get_erase_size(uint32_t addr);
/**
* \brief Reads data from the serial flash on the board. This is a blocking
* \brief Reads data from the serial flash memory. This is a blocking
* function. Returns error if (addr + length) exceeds the flash size.
* \param addr Starting address to read from
* \param length Number of data bytes to read
* \param buf Pointer to the buffer to store the data read from the memory
* \returns CY_RSLT_SUCCESS if the read was successful, an error code otherwise.
*/
cy_rslt_t cybsp_serial_flash_read(uint32_t addr, size_t length, uint8_t *buf);
cy_rslt_t cy_serial_flash_qspi_read(uint32_t addr, size_t length, uint8_t *buf);
/**
* \brief Writes the data to the serial flash on the board. The program area
* \brief Writes the data to the serial flash memory. The program area
* must have been erased prior to calling this API using
* \ref cybsp_serial_flash_erase() This is a blocking function. Returns error if
* \ref cy_serial_flash_qspi_erase() This is a blocking function. Returns error if
* (addr + length) exceeds the flash size.
* \param addr Starting address to write to
* \param length Number of bytes to write
* \param buf Pointer to the buffer storing the data to be written
* \returns CY_RSLT_SUCCESS if the write was successful, an error code
* otherwise.
* otherwise.
*/
cy_rslt_t cybsp_serial_flash_write(uint32_t addr, size_t length, const uint8_t *buf);
cy_rslt_t cy_serial_flash_qspi_write(uint32_t addr, size_t length, const uint8_t *buf);
/**
* \brief Erases the serial flash on the board, uses chip erase command when
* \brief Erases the serial flash memory, uses chip erase command when
* addr = 0 and length = flash_size otherwise uses sector erase command. This is
* a blocking function. Returns error if addr or (addr + length) is not aligned
* to the sector size or if (addr + length) exceeds the flash size.
* Call \ref cybsp_serial_flash_get_size() to get the flash size and
* call \ref cybsp_serial_flash_get_erase_size() to get the size of an erase
* Call \ref cy_serial_flash_qspi_get_size() to get the flash size and
* call \ref cy_serial_flash_qspi_get_erase_size() to get the size of an erase
* sector.
*
* \param addr Starting address to begin erasing
@ -120,24 +148,26 @@ cy_rslt_t cybsp_serial_flash_write(uint32_t addr, size_t length, const uint8_t *
* \returns CY_RSLT_SUCCESS if the erase was successful, an error code
* otherwise.
*/
cy_rslt_t cybsp_serial_flash_erase(uint32_t addr, size_t length);
cy_rslt_t cy_serial_flash_qspi_erase(uint32_t addr, size_t length);
/**
* \brief Enables Execute-in-Place (memory mapped) mode on the MCU. This
* function does not send any command to the serial flash. This may not be
* supported on all the targets in which case
* CYBSP_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED is returned.
* CY_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED is returned.
* \param enable true: XIP mode is set, false: normal mode is set
* \returns CY_RSLT_SUCCESS if the operation was successful.
* CYBSP_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED if the target does not
* CY_RSLT_SERIAL_FLASH_ERR_UNSUPPORTED if the target does not
* support XIP.
*/
cy_rslt_t cybsp_serial_flash_enable_xip(bool enable);
cy_rslt_t cy_serial_flash_qspi_enable_xip(bool enable);
/** \} group_bsp_serial_flash_functions */
/** \} group_serial_flash_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_bsp_serial_flash */
#endif /* CY_IP_MXSMIF */
/** \} group_serial_flash */

92
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.c
View File

@ -1,92 +0,0 @@
/***************************************************************************//**
* \file cybsp_core.c
*
* \brief
* Provides utility functions that are used by board support packages.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cybsp_core.h"
#include "cyhal.h"
#if defined(__cplusplus)
extern "C" {
#endif
cy_rslt_t cybsp_led_init(cybsp_led_t which)
{
return cyhal_gpio_init((cyhal_gpio_t)which, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, CYBSP_LED_STATE_OFF);
}
void cybsp_led_set_state(cybsp_led_t which, bool on)
{
cyhal_gpio_write((cyhal_gpio_t)which, on);
}
void cybsp_led_toggle(cybsp_led_t which)
{
cyhal_gpio_toggle((cyhal_gpio_t)which);
}
cy_rslt_t cybsp_btn_init(cybsp_btn_t which)
{
return cyhal_gpio_init((cyhal_gpio_t)which, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_PULLUP, CYBSP_BTN_OFF);
}
bool cybsp_btn_get_state(cybsp_btn_t which)
{
return cyhal_gpio_read((cyhal_gpio_t)which);
}
void cybsp_btn_set_interrupt(cybsp_btn_t which, cyhal_gpio_event_t type, cyhal_gpio_event_callback_t callback, void *callback_arg)
{
cyhal_gpio_register_callback((cyhal_gpio_t)which, callback, callback_arg);
cyhal_gpio_enable_event((cyhal_gpio_t)which, type, 7, 1);
}
/* The sysclk deep sleep callback is recommended to be the last callback that
* is executed before entry into deep sleep mode and the first one upon
* exit the deep sleep mode.
* Doing so minimizes the time spent on low power mode entry and exit.
*/
#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
#define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u)
#endif
cy_rslt_t cybsp_register_sysclk_pm_callback(void)
{
cy_rslt_t result = CY_RSLT_SUCCESS;
static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
.callback = &Cy_SysClk_DeepSleepCallback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cybsp_sysclk_pm_callback_param,
.order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
};
if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
{
result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
}
return result;
}
#if defined(__cplusplus)
}
#endif

150
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_core.h
View File

@ -1,150 +0,0 @@
/***************************************************************************//**
* \file cybsp_core.h
*
* \brief
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_core Core
* \{
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
* \defgroup group_bsp_core_macros Macros
* \defgroup group_bsp_core_functions Functions
*/
#pragma once
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_gpio.h"
#include "cybsp_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_core_macros
* \{
*/
/** Failed to configure sysclk power management callback */
#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
/** \} group_bsp_core_macros */
/**
* \addtogroup group_bsp_core_functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
/**
* \brief Init and allocate the specified LED, setting the GPIO drive mode as necessary
* \param which The specific LED number to enable, see BSP header file for available LEDs
* \returns CY_RSLT_SUCCESS if the LED was enabled successfully
*/
cy_rslt_t cybsp_led_init(cybsp_led_t which);
/**
* \brief Toggle the specified LED
* \param which The specific LED number to enable, see BSP header file for available LEDs
*/
void cybsp_led_toggle(cybsp_led_t which);
/**
* \brief Sets the state of the LED.
* \param which The specific LED number to set state, see BSP header file for available LEDs
* \param on Whether the LED should be turned on (true) or off (false)
*/
void cybsp_led_set_state(cybsp_led_t which, bool on);
/**
* \brief Turns the LED on.
* \param which The specific LED number to set state, see BSP header file for available LEDs
* \returns CY_RSLT_SUCCESS if the LED was turned on
*/
static inline void cybsp_led_on(cybsp_led_t which)
{
cybsp_led_set_state(which, CYBSP_LED_STATE_ON);
}
/**
* \brief Turns the LED off.
* \param which The specific LED number to set state, see BSP header file for available LEDs
* \returns CY_RSLT_SUCCESS if the LED was turned off
*/
static inline void cybsp_led_off(cybsp_led_t which)
{
cybsp_led_set_state(which, CYBSP_LED_STATE_OFF);
}
/**
* \brief Init and allocate the specified button, setting the GPIO drive mode as necessary
* \param which The specific button number to enable, see BSP header file for available buttones
* \returns CY_RSLT_SUCCESS if the button was enabled successfully
*/
cy_rslt_t cybsp_btn_init(cybsp_btn_t which);
/**
* \brief Sets the state of the button.
* \param which The specific button number to get state from, see BSP header file for available buttones
* \returns State of the button
*/
bool cybsp_btn_get_state(cybsp_btn_t which);
/**
* \brief Sets the interrupt to trigger when the button state is changed.
* \param which The specific button number to get state from, see BSP header file for available buttones
* \param type The type sets level vs edge and active high vs active low
* \param callback The function pointer to call when the button state changes. NULL to unregister.
* \param callback_arg The optional argument to provide when the callback is executed. This can be NULL.
*/
void cybsp_btn_set_interrupt(cybsp_btn_t which, cyhal_gpio_event_t type, cyhal_gpio_event_callback_t callback, void *callback_arg);
/**
* \brief Registers a power management callback that prepares the clock system
* for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
* NOTE: This is called automatically as part of \ref cybsp_init
* \returns CY_RSLT_SUCCESS if the callback is sucessfully registered, if there is
* a problem registering the callback it returns CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK.
*/
cy_rslt_t cybsp_register_sysclk_pm_callback(void);
/** \} group_bsp_core_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */
/** \} group_bsp_core */

180
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_serial_flash.c
View File

@ -1,180 +0,0 @@
/***************************************************************************//**
* \file cybsp_serial_flash.c
*
* \brief
* Provides APIs for interacting with an external flash connected to the SPI or
* QSPI interface, uses the configuration generated by the QSPI configurator,
* uses SFDP to auto-discover memory properties if SFDP is enabled in the
* configuration.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdbool.h>
#include "cybsp_serial_flash.h"
#include "cy_pdl.h"
#include "cyhal_qspi.h"
#include "cy_utils.h"
#include "cybsp.h"
#if defined(__cplusplus)
extern "C" {
#endif
#if defined(CYBSP_QSPI_SCK)
#include "cycfg_qspi_memslot.h"
/** \cond internal */
#define QSPI_BUS_FREQUENCY_HZ (50000000lu)
/** Timeout to apply while polling the memory for its ready status after quad
* enable command has been sent out. Quad enable is a non-volatile write.
*/
#define CYBSP_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US (5000lu) /* in microseconds */
/* SMIF slot number to which the memory is connected */
#define MEM_SLOT (0u)
/** \endcond */
static cyhal_qspi_t qspi_obj;
cy_rslt_t cybsp_serial_flash_init(void)
{
cy_en_smif_status_t smifStatus = CY_SMIF_SUCCESS;
cy_rslt_t result = cyhal_qspi_init(&qspi_obj, CYBSP_QSPI_D0, CYBSP_QSPI_D1, CYBSP_QSPI_D2, CYBSP_QSPI_D3, NC, NC, NC, NC,
CYBSP_QSPI_SCK, CYBSP_QSPI_SS, QSPI_BUS_FREQUENCY_HZ, 0);
if(CY_RSLT_SUCCESS == result)
{
/* Perform SFDP detection and XIP register configuration depending on the
* memory configuration.
*/
smifStatus = Cy_SMIF_Memslot_Init(qspi_obj.base, (cy_stc_smif_block_config_t *) &smifBlockConfig, &qspi_obj.context);
if(CY_SMIF_SUCCESS == smifStatus)
{
/* Enable Quad mode (1-1-4 or 1-4-4 modes) to use all the four I/Os during
* communication.
*/
if(smifMemConfigs[MEM_SLOT]->deviceCfg->readCmd->dataWidth == CY_SMIF_WIDTH_QUAD
|| smifMemConfigs[MEM_SLOT]->deviceCfg->programCmd->dataWidth == CY_SMIF_WIDTH_QUAD)
{
bool isQuadEnabled = false;
smifStatus = Cy_SMIF_MemIsQuadEnabled(qspi_obj.base, smifMemConfigs[MEM_SLOT], &isQuadEnabled, &qspi_obj.context);
if(CY_SMIF_SUCCESS == smifStatus)
{
if(!isQuadEnabled)
{
smifStatus = Cy_SMIF_MemEnableQuadMode(qspi_obj.base, smifMemConfigs[MEM_SLOT], CYBSP_SERIAL_FLASH_QUAD_ENABLE_TIMEOUT_US, &qspi_obj.context);
}
}
}
}
}
if((CY_RSLT_SUCCESS == result) && (CY_SMIF_SUCCESS == smifStatus))
{
return CY_RSLT_SUCCESS;
}
else
{
cybsp_serial_flash_deinit();
return (cy_rslt_t)smifStatus;
}
}
void cybsp_serial_flash_deinit(void)
{
cyhal_qspi_free(&qspi_obj);
}
size_t cybsp_serial_flash_get_size(void)
{
return (size_t)smifMemConfigs[MEM_SLOT]->deviceCfg->memSize;
}
/* address is ignored for the memory with uniform sector size. Currently,
* QSPI Configurator does not support memories with hybrid sectors.
*/
size_t cybsp_serial_flash_get_erase_size(uint32_t addr)
{
CY_UNUSED_PARAMETER(addr);
return (size_t)smifMemConfigs[MEM_SLOT]->deviceCfg->eraseSize;
}
cy_rslt_t cybsp_serial_flash_read(uint32_t addr, size_t length, uint8_t *buf)
{
/* Cy_SMIF_MemRead() returns error if (addr + length) > total flash size. */
return (cy_rslt_t)Cy_SMIF_MemRead(qspi_obj.base, smifMemConfigs[MEM_SLOT], addr, buf, length, &qspi_obj.context);
}
cy_rslt_t cybsp_serial_flash_write(uint32_t addr, size_t length, const uint8_t *buf)
{
/* Cy_SMIF_MemWrite() returns error if (addr + length) > total flash size. */
return (cy_rslt_t)Cy_SMIF_MemWrite(qspi_obj.base, smifMemConfigs[MEM_SLOT], addr, (uint8_t *)buf, length, &qspi_obj.context);
}
/* Does not support hybrid sectors, sector size must be uniform on the entire
* chip. Use cybsp_serial_flash_get_erase_size(addr) to implement hybrid sector
* support when QSPI Configurator and PDL supports memories with hybrid sectors.
*/
cy_rslt_t cybsp_serial_flash_erase(uint32_t addr, size_t length)
{
cy_en_smif_status_t smifStatus;
/* If the erase is for the entire chip, use chip erase command */
if((addr == 0u) && (length == cybsp_serial_flash_get_size()))
{
smifStatus = Cy_SMIF_MemEraseChip(qspi_obj.base, smifMemConfigs[MEM_SLOT], &qspi_obj.context);
}
else
{
/* Cy_SMIF_MemEraseSector() returns error if (addr + length) > total flash size
* or if addr is not aligned to erase sector size or if (addr + length)
* is not aligned to erase sector size.
*/
smifStatus = Cy_SMIF_MemEraseSector(qspi_obj.base, smifMemConfigs[MEM_SLOT], addr, length, &qspi_obj.context);
}
return (cy_rslt_t)smifStatus;
}
// This function enables or disables XIP on the MCU, does not send any command
// to the serial flash. XIP register configuration is already done as part of
// cybsp_serial_flash_init() if MMIO mode is enabled in the QSPI
// Configurator.
cy_rslt_t cybsp_serial_flash_enable_xip(bool enable)
{
if(enable)
{
Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_MEMORY);
}
else
{
Cy_SMIF_SetMode(qspi_obj.base, CY_SMIF_NORMAL);
}
return CY_RSLT_SUCCESS;
}
#endif /* defined(CYBSP_QSPI_SCK) */
#if defined(__cplusplus)
}
#endif

78
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.c
View File

@ -23,13 +23,12 @@
*******************************************************************************/
#if defined(CYBSP_WIFI_CAPABLE)
#include "cybsp_types.h"
#include "cybsp.h"
#include "cybsp_wifi.h"
#include "cy_network_buffer.h"
#include "cyabs_rtos.h"
#include "whd_types.h"
#include "cyhal.h"
#include "cybsp_wifi_sdio.h"
#include "cycfg.h"
#if defined(__cplusplus)
@ -40,6 +39,7 @@ extern "C" {
#define THREAD_PRIORITY CY_RTOS_PRIORITY_HIGH
#define COUNTRY WHD_COUNTRY_AUSTRALIA
#define DEFAULT_OOB_PIN 0
#define WLAN_POWER_UP_DELAY_MS 250
#define SDIO_ENUMERATION_TRIES 500
#define SDIO_RETRY_DELAY_MS 1
@ -83,6 +83,7 @@ extern "C" {
#endif /* (CY_SDIO_BUS_USE_OOB_INTR != 0) */
static whd_driver_t whd_drv;
static whd_buffer_funcs_t buffer_ops =
{
.whd_host_buffer_get = cy_host_buffer_get,
@ -152,32 +153,49 @@ static cy_rslt_t cybsp_sdio_enumerate(const cyhal_sdio_t *sdio_object)
return result;
}
static cy_rslt_t init_sdio_bus(void)
static cy_rslt_t reset_wifi_chip(void)
{
cyhal_sdio_t* sdio_p = cybsp_get_wifi_sdio_obj();
cy_rslt_t result = cybsp_sdio_enumerate(sdio_p);
/* WiFi into reset */
cy_rslt_t result = cyhal_gpio_init(CYBSP_WIFI_WL_REG_ON, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_PULLUP, 0);
if(result == CY_RSLT_SUCCESS)
{
whd_sdio_config_t whd_sdio_config;
whd_oob_config_t oob_config;
cyhal_sdio_cfg_t config;
/* WiFi out of reset */
cyhal_gpio_write(CYBSP_WIFI_WL_REG_ON, true);
Cy_SysLib_Delay(WLAN_POWER_UP_DELAY_MS);
}
return result;
}
oob_config.host_oob_pin = CY_WIFI_HOST_WAKE_GPIO;
oob_config.dev_gpio_sel = DEFAULT_OOB_PIN;
oob_config.is_falling_edge = (CY_WIFI_HOST_WAKE_IRQ_EVENT == CYHAL_GPIO_IRQ_FALL)
? WHD_TRUE
: WHD_FALSE;
oob_config.intr_priority = CY_WIFI_OOB_INTR_PRIORITY;
static cy_rslt_t init_sdio_bus(void)
{
cy_rslt_t result = reset_wifi_chip();
if(result == CY_RSLT_SUCCESS)
{
cyhal_sdio_t* sdio_p = cybsp_get_wifi_sdio_obj();
cy_rslt_t result = cybsp_sdio_enumerate(sdio_p);
if(result == CY_RSLT_SUCCESS)
{
whd_sdio_config_t whd_sdio_config;
whd_oob_config_t oob_config;
cyhal_sdio_cfg_t config;
whd_sdio_config.sdio_1bit_mode = WHD_FALSE;
whd_sdio_config.high_speed_sdio_clock = WHD_FALSE;
whd_sdio_config.oob_config = oob_config;
whd_bus_sdio_attach(whd_drv, &whd_sdio_config, sdio_p);
oob_config.host_oob_pin = CY_WIFI_HOST_WAKE_GPIO;
oob_config.dev_gpio_sel = DEFAULT_OOB_PIN;
oob_config.is_falling_edge = (CY_WIFI_HOST_WAKE_IRQ_EVENT == CYHAL_GPIO_IRQ_FALL)
? WHD_TRUE
: WHD_FALSE;
oob_config.intr_priority = CY_WIFI_OOB_INTR_PRIORITY;
/* Increase frequency to 25 MHz for better performance */
config.frequencyhal_hz = 25000000;
config.block_size = 0;
cyhal_sdio_configure(sdio_p, &config);
whd_sdio_config.sdio_1bit_mode = WHD_FALSE;
whd_sdio_config.high_speed_sdio_clock = WHD_FALSE;
whd_sdio_config.oob_config = oob_config;
whd_bus_sdio_attach(whd_drv, &whd_sdio_config, sdio_p);
/* Increase frequency to 25 MHz for better performance */
config.frequencyhal_hz = 25000000;
config.block_size = 0;
cyhal_sdio_configure(sdio_p, &config);
}
}
return result;
}
@ -186,7 +204,7 @@ cy_rslt_t cybsp_wifi_init_primary(whd_interface_t* interface)
{
whd_init_config_t whd_init_config;
whd_init_config.thread_stack_size = (uint32_t)THREAD_STACK_SIZE;
whd_init_config.thread_stack_start = (uint8_t *)malloc(THREAD_STACK_SIZE);
whd_init_config.thread_stack_start = NULL;
whd_init_config.thread_priority = (uint32_t)THREAD_PRIORITY;
whd_init_config.country = COUNTRY;
@ -207,6 +225,20 @@ cy_rslt_t cybsp_wifi_init_secondary(whd_interface_t* interface, whd_mac_t* mac_a
return whd_add_secondary_interface(whd_drv, mac_address, interface);
}
cy_rslt_t cybsp_wifi_deinit(whd_interface_t interface)
{
cy_rslt_t result = whd_wifi_off(interface);
if(result == CY_RSLT_SUCCESS)
{
result = whd_deinit(interface);
if(result == CY_RSLT_SUCCESS)
{
cyhal_gpio_free(CYBSP_WIFI_WL_REG_ON);
}
}
return result;
}
whd_driver_t cybsp_get_wifi_driver(void)
{
return whd_drv;

28
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi.h
View File

@ -48,9 +48,12 @@ extern "C" {
* \{
*/
/** Initialization of the wifi driver failed. */
/** Initialization of the WiFi driver failed. */
#define CYBSP_RSLT_WIFI_INIT_FAILED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 4))
/** SDIO enumeration failed. */
#define CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 5))
/** \} group_bsp_board_macros */
/**
@ -58,17 +61,21 @@ extern "C" {
* \{
*/
/** Initializes the primary interface for the wifi driver on the board. This function does the following
* 1) Initializes the wifi driver.
* 2) Turns on the WIFI chip.
/** Initializes the primary interface for the WiFi driver on the board. This function
* does the following
* 1) Initializes the WiFi driver.
* 2) Turns on the WiFi chip.
*
* @note This function cannot be called multiple times. The user needs to first de-initialize
* before calling this function again.
*
* @param[out] interface Interface to be initialized
* @return CY_RSLT_SUCCESS for successful initialization or error if initialization failed.
*/
cy_rslt_t cybsp_wifi_init_primary(whd_interface_t* interface);
/** This function initializes and adds a secondary interface to the wifi driver.
* @note This function does not initialize the wifi driver or turn on the wifi chip.
/** This function initializes and adds a secondary interface to the WiFi driver.
* @note This function does not initialize the WiFi driver or turn on the WiFi chip.
* That is required to be done by the primary interface
*
* @param[out] interface Interface to be initialized
@ -77,6 +84,15 @@ cy_rslt_t cybsp_wifi_init_primary(whd_interface_t* interface);
*/
cy_rslt_t cybsp_wifi_init_secondary(whd_interface_t* interface, whd_mac_t* mac_address);
/** De-initializes all WiFi interfaces and the WiFi driver. This function does the following
* 1) Deinitializes all WiFi interfaces and WiFi driver.
* 2) Turns off the WiFi chip.
*
* @param[in] interface Interface to be de-initialized.
* @return CY_RSLT_SUCCESS for successful de-initialization or error if de-initialization failed.
*/
cy_rslt_t cybsp_wifi_deinit(whd_interface_t interface);
/** Gets the wifi driver instance initialized by the driver. This should only be called
* after the interface is initialized by cybsp_wifi_init_primary().
*

73
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.c
View File

@ -1,73 +0,0 @@
/***************************************************************************//**
* \file cybsp_wifi_sdio.c
*
* \brief
* Utility functions to intialize the SDIO communication bus used to
* communicate with the WiFi radio.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cybsp_wifi_sdio.h"
#include "cyhal_gpio_impl.h"
#include "cybsp_types.h"
#if defined(CYBSP_WIFI_CAPABLE)
#define WLAN_POWER_UP_DELAY_MS 250
static cyhal_sdio_t sdio_obj;
static cy_rslt_t reset_wifi_chip(void)
{
/* WiFi into reset */
cy_rslt_t result = cyhal_gpio_init(CYBSP_WIFI_WL_REG_ON, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_PULLUP, 0);
if(result == CY_RSLT_SUCCESS)
{
/* WiFi out of reset */
cyhal_gpio_write(CYBSP_WIFI_WL_REG_ON, true);
Cy_SysLib_Delay(WLAN_POWER_UP_DELAY_MS);
}
return result;
}
void cybsp_wifi_sdio_deinit(void)
{
cyhal_sdio_free(&sdio_obj);
cyhal_gpio_free(CYBSP_WIFI_WL_REG_ON);
}
cy_rslt_t cybsp_wifi_sdio_init(void)
{
cy_rslt_t result = cyhal_sdio_init(&sdio_obj, CYBSP_WIFI_SDIO_CMD, CYBSP_WIFI_SDIO_CLK, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3);
if(result == CY_RSLT_SUCCESS)
{
cy_rslt_t result = reset_wifi_chip();
if (result != CY_RSLT_SUCCESS)
{
cybsp_wifi_sdio_deinit();
}
}
return result;
}
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
{
return &sdio_obj;
}
#endif /* defined(CYBSP_WIFI_CAPABLE) */

85
targets/TARGET_Cypress/TARGET_PSOC6/common/cybsp_wifi_sdio.h
View File

@ -1,85 +0,0 @@
/***************************************************************************//**
* \file cybsp_wifi_sdio.h
*
* \brief
* Utility functions to intialize the SDIO communication bus used to
* communicate with the WiFi radio.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_bsp_board_wifi WiFi
* \ingroup group_bsp_abstraction
* \{
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
* \defgroup group_bsp_board_wifi_macros Macros
* \defgroup group_bsp_board_wifi_functions Functions
*/
#pragma once
#include "cy_result.h"
#include "cyhal.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_bsp_board_wifi_macros
* \{
*/
/** SDIO enumeration failed. */
#define CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 5))
/** \} group_bsp_board_wifi_macros */
/**
* \addtogroup group_bsp_board_wifi_functions
* \{
*/
/** Initializes and enumerates the SDIO object connected to the wifi chip.
* The following operations are performed,
* -# Initializes the SDIO interface on the board connect to the wifi chip.
* -# Resets the wifi chip.
*
* @return CY_RSLT_SUCCESS for successful initialization or error if initialization failed.
*/
cy_rslt_t cybsp_wifi_sdio_init(void);
/** Frees up any resources allocated by the cybsp_wifi_sdio_init() */
void cybsp_wifi_sdio_deinit(void);
/** Get the initialized sdio object. This should only be called after cybsp_wifi_sdio_init();
*
* @return The initialized and enumerated sdio object.
*/
cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
/** \} group_bsp_board_wifi_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */
/** \} group_bsp_board_wifi */

12
targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c
View File

@ -19,13 +19,13 @@
#include "device.h"
#include "cycfg.h"
#include "cyhal_hwmgr.h"
#include "cybsp_core.h"
#include "cybsp.h"
#include "mbed_power_mgmt.h"
#include "rtos_idle.h"
#include "us_ticker_api.h"
#if defined(CYBSP_ENABLE_FLASH_STORAGE)
#include "cybsp_serial_flash.h"
#endif /* defined(CYBSP_ENABLE_FLASH_STORAGE) */
#if defined(MBED_CONF_TARGET_XIP_ENABLE)
#include "cy_serial_flash_qspi.h"
#endif /* defined(MBED_CONF_TARGET_XIP_ENABLE) */
#if defined(COMPONENT_SPM_MAILBOX)
void mailbox_init(void);
@ -93,8 +93,8 @@ void mbed_sdk_init(void)
#if MBED_CONF_TARGET_XIP_ENABLE
/* The linker script allows storing data in external memory, if needed, enable access to that memory. */
cybsp_serial_flash_init();
cybsp_serial_flash_enable_xip(true);
cy_serial_flash_init();
cy_serial_flash_enable_xip(true);
#endif
/* Enable global interrupts (disabled in CM4 startup assembly) */