Commit Graph

20 Commits (16a40c9f9c3883ba1cbdb775d22c1884911dfc63)

Author SHA1 Message Date
Dustin Crossman 563edb294d Store RTC century and RTC state information in persistent BREG register. 2020-02-12 15:05:26 -08:00
Dustin Crossman 3fdb820b26 Update psoc6hal to 1.1.1.11145. 2020-02-12 15:05:16 -08:00
Martin Kojtal b8045fb29b
Merge pull request #12164 from shuopeng-deng/pr-dev/remove-hardcoded-timeout-in-cypress-bt-code
Pr dev/remove hardcoded timeout in cypress bt code
2020-01-02 12:52:51 +00:00
Shuopeng Deng 7e79623b39 Removed a hardcoded timeout in CyH4TransportDriver.cpp
Replaced a hardcoded timeout in CyH4TransportDriver.cpp with a cypress
hal function. The cypress PUTC hal API only blocks until data has been
send into the HW buffer, not until all data has been out of the HW
buffer. Modified an API to block untill all tx transmit is complete.
This allows the removal of a hardcoded timeout in
CyH4TransportDriver.cpp that waits for data int the HW buffer to be
sent.
2019-12-19 15:35:38 -08:00
Anna Bridge 3ad3110888
Merge pull request #12019 from shuopeng-deng/pr/cypress-lptimer-hal-rework
Cypress: rework lptimer hal
2019-12-17 16:19:43 +00:00
YARB(Cypress) a79b1b3369 Fix for ARM issue 11859.
1. Clear UART events before enabling
2. Reset device before return from test case
2019-12-09 12:58:47 +02:00
Shuopeng Deng 823d50d6fd rework cypress lptimer hal
Changed set_match api to use an absolute ticks rather than delayed tick to match api name.
Added api set_delay to delay by a specific amount of ticks. Removed unused set_time api.
Simplified the logic for computing interrupts match value for cascading counters.
Fixed an issue when incorrect base time would be read when trying to set match values.
2019-11-27 12:20:37 -08:00
yarb fe91262535 Fix ARM issue 11795: - Cypress: SPI FPGA test: tester always respond 0 when MODE other then 0 (CY MR 1202) 2019-11-05 11:32:30 +02:00
yarb 50b0847003 Cypress: fix gpio mode none 2019-10-30 12:03:53 +02:00
Matthew Macovsky baf375f8cb Allow for arbitrary QSPI alt sizes
The QSPI spec allows alt to be any size that is a multiple of the
number of data lines. For example, Micron's N25Q128A uses only a
single alt cycle for all read modes (1, 2, or 4 bits depending on
how many data lines are in use).
2019-09-30 14:45:08 -07:00
Ryan Morse 54d962a240 Moved TriggerMux initialization out of the HAL and into the BSP since that is what dictates what trigger muxes actually need to be used 2019-09-27 13:01:38 -07:00
Kyle Kearney 8aa449c662 Improve psoc6csp doxygen comments 2019-09-18 12:13:34 -07:00
Kyle Kearney e8dc5f111c Update to latest HAL
- Add const and static qualifiers in places where they are
  applicable but missing
- Remove headers for drivers that aren't implemented yet
- Misc minor bugfixes
2019-09-18 12:07:08 -07:00
Kyle Kearney ad6e833450 Enable SDIO DeepSleep Callback 2019-08-28 10:56:14 -07:00
Ryan Morse 5c899a3350 Bug fixes to interrupt/event handling in SDHC HAL 2019-08-27 15:29:32 -07:00
Shuopeng Deng 8ad377add3 Fix I2C handling of 1 byte external memory address 2019-08-27 15:10:34 -07:00
Ryan Morse 459666f8f2 Fixed issue in QSPI when there aren't 8 pins 2019-08-27 15:10:34 -07:00
Kyle Kearney 375221097c Update CSP to latest
Update HAL adapter for interface changes
Misc minor fixes to HAL adapter
2019-08-27 15:10:34 -07:00
Kyle Kearney b65be5fa29 Bug fixes to I2C and SPI drivers
- Fix assert when spi_master_block_write called with 0 size
- Fix assert when spi_format called before spi_frequency
- Simplify implementation of spi_master_write
- Simplify pointer arithmetic expressions in cyhal_spi_transfer and
  cyhal_spi_transfer_async
- Fix I2C driver not honoring the frequency specified during init.
2019-07-23 15:40:45 -07:00
Volodymyr Medvid a9cd9482c0 PSOC6: add psoc6csp asset with Cypress HAL implementation
PSoC 6 Chip Support Package provides hardware abstraction layer
for Cypress PSoC 6 device peripherals.
2019-07-08 13:26:46 +03:00