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PSOC6: add psoc6csp asset with Cypress HAL implementation 

PSoC 6 Chip Support Package provides hardware abstraction layer
for Cypress PSoC 6 device peripherals.
pull/10692/head
Volodymyr Medvid 2019-05-27 16:14:11 +03:00 committed by Volodymyr Medvid
parent c9105eb068
commit a9cd9482c0
106 changed files with 34612 additions and 0 deletions
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76
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/COMPONENT_RTX/cyabs_rtos_impl.h Normal file
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/***************************************************************************//**
* \file cyabs_rtos_impl.h
*
* \brief
* Internal definitions for RTOS abstraction layer
*
********************************************************************************
* \copyright
* Copyright 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef INCLUDED_CYABS_RTOS_IMPL_H_
#define INCLUDED_CYABS_RTOS_IMPL_H_
#include "cmsis_os2.h"
#include "rtx_os.h"
#ifdef __cplusplus
extern "C"
{
#endif
/******************************************************
* Constants
******************************************************/
#define CY_RTOS_MIN_STACK_SIZE 300 /** Minimum stack size */
#define CY_RTOS_ALIGNMENT_MASK 0x00000007UL /** Checks for 8-bit alignement */
/******************************************************
* Type Definitions
******************************************************/
/* RTOS thread priority */
typedef enum
{
CY_RTOS_PRIORITY_MIN = osPriorityNone,
CY_RTOS_PRIORITY_LOW = osPriorityLow,
CY_RTOS_PRIORITY_BELOWNORMAL = osPriorityBelowNormal,
CY_RTOS_PRIORITY_NORMAL = osPriorityNormal,
CY_RTOS_PRIORITY_ABOVENORMAL = osPriorityAboveNormal,
CY_RTOS_PRIORITY_HIGH = osPriorityHigh,
CY_RTOS_PRIORITY_REALTIME = osPriorityRealtime,
CY_RTOS_PRIORITY_MAX = osPriorityRealtime7
} cy_thread_priority_t ;
typedef osThreadId_t cy_thread_t; /** CMSIS definition of a thread handle */
typedef uint32_t cy_thread_arg_t; /** Argument passed to the entry function of a thread */
typedef osMutexId_t cy_mutex_t; /** CMSIS definition of a mutex */
typedef osSemaphoreId_t cy_semaphore_t; /** CMSIS definition of a semaphore */
typedef osEventFlagsId_t cy_event_t; /** CMSIS definition of an event */
typedef osMessageQueueId_t cy_queue_t; /** CMSIS definition of a message queue */
typedef osTimerId_t cy_timer_t; /** CMSIS definition of a timer */
typedef uint32_t cy_timer_callback_arg_t; /** Argument passed to the timer callback function */
typedef uint32_t cy_time_t; /** Time in milliseconds */
typedef osStatus_t cy_rtos_error_t; /** CMSIS definition of a error status */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_CYABS_RTOS_IMPL_H_ */

30
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_chip.h Normal file
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/***************************************************************************//**
* \file cyabs_chip.h
*
* \brief
* Basic abstraction layer for dealing with chips containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware peripherals. Depending on the specific chip being used, not all
* features may be supported.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cyhal.h"

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_fs.h Normal file
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/***************************************************************************//**
* \file cyabs_fs.h
*
* \brief
* Basic file system abstraction layer. This API provides convenience methods
* for reading and writing values.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_abstraction_fs File system abstraction
* \ingroup group_abstraction
* \{
* Basic file system abstraction layer. This API provides convenience methods
* for reading and writing values.
*
* \defgroup group_abstraction_fs_macros Macros
* \defgroup group_abstraction_fs_data_structures Data Structures
* \defgroup group_abstraction_fs_functions Functions
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_abstraction_fs_macros
* \{
*/
#define CY_O_RDONLY (1 << 0) /**< TODO */
#define CY_O_WRONLY (1 << 1) /**< TODO */
#define CY_O_RDWR (1 << 2) /**< TODO */
#define CY_O_APPEND (1 << 3) /**< TODO */
#define CY_O_CREAT (1 << 4) /**< TODO */
/** \} group_abstraction_fs_macros */
/**
* \addtogroup group_abstraction_fs_data_structures
* \{
*/
typedef uint32_t cy_handle_t; /**< Resource handle */
/** \} group_abstraction_fs_data_structures */
/**
* \addtogroup group_abstraction_fs_functions
* \{
*/
/**
* \brief open or create a file and return a handle
* \param path the path name of the file to open
* \param oflag the mode to use when opening the file
* \param handle pointer to location re receive handle
* \returns CY_RSLT_SUCCESS if successful, otherwise error code
*/
cy_rslt_t cy_fs_open(const char *path, uint32_t oflag, cy_handle_t *handle) ;
/**
* \brief close an open file
* \param handle a file handle to an open file
* \returns CY_RSLT_SUCCESS if successful, otherwise error code
*/
cy_rslt_t cy_fs_close(cy_handle_t handle) ;
/**
* \brief read data from a file
* \param handle a file handle open for reading or read/write
* \param buf the buffer for the read data
* \param nbyte the size of the buffer in bytes, the number of bytes read on return
* \returns CY_RSLT_SUCCESS if successful, otherwise error code
*/
cy_rslt_t cy_fs_read(cy_handle_t handle, void *buf, size_t *nbyte) ;
/**
* \brief write data to a file
* \param handle a file handle open for writing or read/write
* \param buf the buffer for the data to write
* \param nbyte the size of the buffer in bytes, the number of bytes written on return
* \returns CY_RSLT_SUCCESS if successful, otherwise error code
*/
cy_rslt_t cy_fs_write(cy_handle_t handle, const void *buf, size_t *nbyte) ;
/** \} group_abstraction_fs_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_abstraction_fs */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/abstraction/include/cyabs_resource.h Normal file
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/***************************************************************************//**
* \file cyabs_resource.h
*
* \brief
* Basic abstraction layer for dealing with resources.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_abstraction_resource Resource abstraction
* \ingroup group_abstraction
* \{
* Basic abstraction layer for dealing with resources.
*
* \defgroup group_abstraction_resource_macros Macros
* \defgroup group_abstraction_resource_enums Enums
* \defgroup group_abstraction_resource_data_structures Data Structures
* \defgroup group_abstraction_resource_functions Functions
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_abstraction_resource_macros
* \{
*/
/** Error code for when the specified resource operation is not valid. */
#define CY_RSLT_RSC_ERROR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 0))
/** Error indicating that memory for the specified resource could not be allocated. */
#define CY_RSLT_RSC_ERROR_UNAVAILABLE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 1))
/** Error code for when the specified resource offset is not valid for the specified resource. */
#define CY_RSLT_RSC_ERROR_OFFSET (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 2))
/** Error code for when the specified resource can not be opened for reading. */
#define CY_RSLT_RSC_ERROR_OPEN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 3))
/** Error code for when the specified location can not be accessed in the specified resource. */
#define CY_RSLT_RSC_ERROR_SEEK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 4))
/** Error code for when the specified resource can not be read. */
#define CY_RSLT_RSC_ERROR_READ (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_RESOURCE, 5))
/** \} group_abstraction_resource_macros */
/**
* \addtogroup group_abstraction_resource_enums
* \{
*/
/** Different types of memory that the resources can be stored in. */
typedef enum
{
CY_RESOURCE_IN_MEMORY, /**< resource location in memory */
CY_RESOURCE_IN_FILESYSTEM, /**< resource location in filesystem */
CY_RESOURCE_IN_EXTERNAL_STORAGE /**< resource location in external storage */
} cy_resource_location_t;
/** \} group_abstraction_resource_enums */
/**
* \addtogroup group_abstraction_resource_data_structures
* \{
*/
/** Filesystem handle */
typedef struct
{
unsigned long offset; /**< Offset to the start of the resource */
const char* filename; /**< name of the resource */
} cy_filesystem_resource_handle_t;
/** Resource handle structure */
typedef struct
{
cy_resource_location_t location; /**< resource location */
unsigned long size; /**< resource size */
union
{
cy_filesystem_resource_handle_t fs; /** < filesystem resource handle */
const uint8_t* mem_data; /** < memory resource handle */
void* external_storage_context; /** < external storage context */
} val;
} cy_resource_handle_t;
/** \} group_abstraction_resource_data_structures */
/**
* \addtogroup group_abstraction_resource_functions
* \{
*/
/**
* \brief return the block size for the resource
* \param handle handle to a resource
* \param size pointer to a uint32_t to receive the size
* \returns CY_RSLT_SUCCESS if the size was found, otherwise an error
*/
cy_rslt_t cy_resource_get_block_size(const cy_resource_handle_t *handle, uint32_t *size);
/**
* \brief return the total size for the resource
* \param handle handle to a resource
* \param size pointer to a uint32_t to receive the size
* \returns CY_RSLT_SUCCESS if the size was found, otherwise an error
*/
cy_rslt_t cy_resource_get_total_size(const cy_resource_handle_t *handle, uint32_t *size);
/**
* \brief return the total number of blocks that exist for the resource
* \param handle handle to a resource
* \param blocks pointer to a uint32_t to receive the count
* \returns CY_RSLT_SUCCESS if the count was found, otherwise an error
*/
cy_rslt_t cy_resource_get_block_count(const cy_resource_handle_t *handle, uint32_t *blocks);
/**
* \brief read data from a resource
* \param handle the handle to the resource
* \param blockno the block number of the data from the resource
* \param buffer pointer to receive buffer address from resource. The buffer must be freed when done. Eg: free(buffer)
* \param size location to receive the size of the block read
* \returns CY_RSLT_SUCCESS if data read, otherwise an error
*/
cy_rslt_t cy_resource_read(const cy_resource_handle_t *handle, uint32_t blockno, uint8_t **buffer, uint32_t *size);
/**
* \brief optimized version of read for resources stored in memory (\see CY_RESOURCE_IN_MEMORY)
* \param handle the handle to the resource
* \param buffer pointer to receive buffer address from resource. This does NOT need to be freed.
* \param size location to receive the size of the block read
* \returns CY_RSLT_SUCCESS if data read, otherwise an error
*/
cy_rslt_t cy_resource_readonly_memory(const cy_resource_handle_t *handle, const uint8_t **buffer, uint32_t *size);
/** \} group_abstraction_resource_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_abstraction_resource */

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/***************************************************************************//**
* \file cyabs_rtos.h
*
* \brief
* Defines the Cypress RTOS Interface. Provides prototypes for functions that
* allow Cypress libraries to use RTOS resources such as threads, mutexes & timing
* functions in an abstract way. The APIs are implemented
* in the Port Layer RTOS interface which is specific to the RTOS in use.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef INCLUDED_CY_RTOS_INTERFACE_H_
#define INCLUDED_CY_RTOS_INTERFACE_H_
#include "cyabs_rtos_impl.h"
#include <cy_result.h>
#include <stdint.h>
#include <stdbool.h>
/*
* Note, cyabs_rtos_impl.h above is included and is the implementation of some basic
* types for the abstraction layer. The types expected to be defined are.
*
* cy_thread_t : typedef from underlying RTOS thread type
* cy_thread_arg_t : typedef from the RTOS type that is passed to the
* entry function of a thread.
* cy_mutex_t : typedef from the underlying RTOS mutex type
* cy_event_t : typedef from the underlying RTOS event type
* cy_queue_t : typedef from the underlying RTOS queue type
* cy_timer_callback_arg_t : typedef from the RTOS type that is passed
* : to the timer callback function
* cy_timer_t : typedef from the underlying RTOS timer type
* cy_time_t : count of time in milliseconds
* cy_rtos_error_t : typedef from the underlying RTOS error type *
*
* The following #defines need to be provided for thread standard priorities:
* CY_THREAD_PRIORITY_LOW
* CY_THREAD_PRIORITY_NORMAL
* CY_THREAD_PRIORITY_HIGH
*/
/**
* \addtogroup group_abstraction_rtos RTOS abstraction
* \ingroup group_abstraction
* \{
* Basic abstraction layer for dealing with RTOSes.
*
* \defgroup group_abstraction_rtos_macros Macros
* \defgroup group_abstraction_rtos_enums Enums
* \defgroup group_abstraction_rtos_data_structures Data Structures
* \defgroup group_abstraction_rtos_functions Functions
*/
#ifdef __cplusplus
extern "C"
{
#endif
/*********************************************** CONSTANTS **********************************************/
/**
* \addtogroup group_abstraction_rtos_macros
* \{
*/
/** Used with RTOS calls that require a timeout. This implies the call will never timeout. */
#define CY_RTOS_NEVER_TIMEOUT ( (uint32_t)0xffffffffUL )
//
// Note on error strategy. If the error is a normal part of operation (timeouts, full queues, empty
// queues), the these errors are listed here and the abstraction layer implementation must map from the
// underlying errors to these. If the errors are special cases, the the error CY_RTOS_GENERAL_ERROR can be
// returns and cy_rtos_last_error() used to retrieve the RTOS specific error message.
//
/** Requested operationd did not complete in the specified time */
#define CY_RTOS_TIMEOUT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 0)
/** The RTOS could not allocate memory for the specified operation */
#define CY_RTOS_NO_MEMORY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 1)
/** An error occured in the RTOS */
#define CY_RTOS_GENERAL_ERROR CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 2)
/** The Queue is already full and can't accept any more items at this time */
#define CY_RTOS_QUEUE_FULL CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 3)
/** The Queue is empty and has nothing to remove */
#define CY_RTOS_QUEUE_EMPTY CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 4)
/** A bad argument was passed into the APIs */
#define CY_RTOS_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_OS, 5)
/** \} group_abstraction_rtos_macros */
/*********************************************** TYPES **********************************************/
/**
* \addtogroup group_abstraction_rtos_data_structures
* \{
*/
/**
* The type of a function that is the entry point for a thread
*
* @param[in] arg the argument passed from the thread create call to the entry function
*/
typedef void (*cy_thread_entry_fn_t)(cy_thread_arg_t arg) ;
/**
* The type of timer
*/
typedef enum cy_timer_trigger_type
{
cy_timer_type_periodic = osTimerPeriodic, /**< called periodically until stopped */
cy_timer_type_once = osTimerOnce, /**< called once only */
} cy_timer_trigger_type_t ;
/**
* The callback function to be called by a timeer
*/
typedef void (*cy_timer_callback_t)(cy_timer_callback_arg_t arg) ;
/** \} group_abstraction_rtos_data_structures */
/**
* \addtogroup group_abstraction_rtos_functions
* \{
*/
/**
* Return the last error from the RTOS.
*
* The functions in the RTOS abstraction layer adhere to the Cypress return
* results calling convention. The underlying RTOS implementations will not but rather
* will have their own error code conventions. This function is provided as a service
* to the developer, mostly for debugging, and returns the underlying RTOS error code
* from the last RTOS abstraction layer that returned CY_RTOS_GENERAL_ERROR.
*
* @return RTOS specific error code.
*/
extern cy_rtos_error_t cy_rtos_last_error() ;
/*********************************************** Threads **********************************************/
/** Create a thread with specific thread argument.
*
* This function is called to startup a new thread. If the thread can exit, it must call
* cy_rtos_finish_thread() just before doing so. All created threds that can terminate, either
* by themselves or forcefully by another thread MUST be joined in order to cleanup any resources
* that might have been allocated for them.
*
* @param[out] thread Pointer to a variable which will receive the new thread handle
* @param[in] entry_function Function pointer which points to the main function for the new thread
* @param[in] name String thread name used for a debugger
* @param[in] stack The buffer to use for the thread stack
* @param[in] stack_size The size of the thread stack in bytes
* @param[in] priority The priority of the thread. Values are operating system specific, but some
* common priority levels are defined:
* CY_THREAD_PRIORITY_LOW
* CY_THREAD_PRIORITY_NORMAL
* CY_THREAD_PRIORITY_HIGH
* @param[in] arg The argument to pass to the new thread
*
* @return The status of thread create request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function,
const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg);
/** Exit the current thread.
*
* This function is called just before a thread exits. In some cases it is sufficient
* for a thread to just return to exit, but in other cases, the RTOS must be explicitly
* signaled. In cases where a return is sufficient, this should be a null funcition.
* where the RTOS must be signaled, this function should perform that In cases operation.
* In code using RTOS services, this function should be placed at any at any location
* where the main thread function will return, exiting the thread. Threads that can
* exit must still be joined (cy_rtos_join_thread) to ensure their resources are fully
* cleaned up.
*
* @return The status of thread exit request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_exit_thread();
/** Terminates another thread.
*
* This function is called to terminate another thread and reap the resoruces claimed
* by it thread. This should be called both when forcibly terminating another thread
* as well as any time a thread can exit on its own. For some RTOS implementations
* this is not required as the thread resoruces are claimed as soon as it exits. In
* other cases, this must be called to reclaim resources. Threads that are terminated
* must still be joined (cy_rtos_join_thread) to ensure their resources are fully
* cleaned up.
*
* @param[in] thread Handle of the thread to terminate
*
* @returns The status of the thread terminate. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread);
/** Checks if the thread is running
*
* This function is called to determine if a thread is running or not.
*
* @param[in] thread handle of the terminated thread to delete
* @param[out] state returns true if the thread is running, otherwise false
*
* @returns The status of the thread check. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *state) ;
/** Waits for a thread to complete.
*
* This must be called on any thread that can complete to ensure that any resources that
* were allocated for it are cleaned up.
*
* @param[in] thread Handle of the thread to wait for
*
* @returns The status of thread join request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread);
/*********************************************** Mutexes **********************************************/
/** Create a mutex.
*
* This is basically a binary mutex which can be used to synchronize between threads
* and between threads and ISRs.
*
* @param[out] mutex Pointer to the mutex handle to be initialized
*
* @return The status of mutex creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_init_mutex(cy_mutex_t *mutex);
/** Get a mutex.
*
* If the mutex is available, it is acquired and this function returned.
* If the mutex is not available, the thread waits until the mutex is available
* or until the timeout occurs.
*
* @note This function must not be called from an interrupt context as it may block.
*
* @param[in] mutex Pointer to the mutex handle
* @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get
* the mutex. Use the NEVER_TIMEOUT constant to wait forever. Must
* be zero is in_isr is true
*
* @return The status of the get mutex. Returns timeout if mutex was not acquired
* before timeout_ms period. [CY_RSLT_SUCCESS, CY_RTOS_TIMEOUT]
*/
extern cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms) ;
/** Set a mutex.
*
* The mutex is released allowing any other threads waiting on the mutex to
* obtain the sempahore.
*
* @param[in] mutex Pointer to the mutex handle
*
* @return The status of the set mutex request. [CY_RSLT_SUCCESS, CY_RTOS_TIMEOUT]
*
*/
extern cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex);
/** Deletes a mutex.
*
* This function frees the resources associated with a sempahore.
*
* @param[in] mutex Pointer to the mutex handle
*
* @return The status to the delete request. [CY_RSLT_SUCCESS, CY_RTOS_TIMEOUT]
*/
extern cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex);
/*********************************************** Semaphores **********************************************/
/**
* Create a semaphore
*
* This is basically a counting semaphore.
*
* @param[in,out] semaphore Pointer to the semaphore handle to be initialized
* @param[in] maxcount The maximum count for this semaphore
* @param[in] initcount The initial count for this sempahore
*
* @return The status of the sempahore creation. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount);
/**
* Get/Acquire a semaphore
*
* If the semaphore count is zero, waits until the semaphore count is greater than zero.
* Once the semaphore count is greater than zero, this function decrements
* the count and return. It may also return if the timeout is exceeded.
*
* @param[in] semaphore Pointer to the semaphore handle
* @param[in] timeout_ms Maximum number of milliseconds to wait while attempting to get
* the semaphore. Use the NEVER_TIMEOUT constant to wait forever. Must
* be zero is in_isr is true
* @param[in] in_isr true if we are trying to get the semaphore from with an ISR
* @return The status of get semaphore operation [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr) ;
/**
* Set/Release a semaphore
*
* Increments the semaphore count, up to the maximum count for this semaphore.
*
* @param[in] semaphore Pointer to the semaphore handle
* @param[in] in_isr Value of true indicates calling from interrupt context
* Value of false indicates calling from normal thread context
* @return The status of set semaphore operation [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr);
/**
* Deletes a sempahore
*
* This function frees the resources associated with a sempahore.
*
* @param[in] semaphore Pointer to the sempahore handle
*
* @return The status of semaphore deletion [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore);
/*********************************************** Events **********************************************/
/** Create an event.
*
* This is an event which can be used to signal a set of threads
* with a 32 bit data element.
*
* @param[in,out] event Pointer to the event handle to be initialized
*
* @return The status of the event initialization request.
* [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_init_event(cy_event_t *event) ;
/** Set the event flag bits.
*
* This is an event which can be used to signal a set of threads
* with a 32 bit data element. Any threads waiting on this event are released
*
* @param[in] event Pointer to the event handle
* @param[in] bits The value of the 32 bit flags
* @param[in] in_isr If true, this is called from an ISR, otherwise from a thread
*
* @return The status of the set request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ;
/**
* Clear the event flag bits
*
* This function clears bits in the event.
*
* @param[in] event Pointer to the event handle
* @param[in] bits Any bits set in this value, will be cleared in the event.
* @param[in] in_isr if true, this is called from an ISR, otherwise from a thread
*
* @return The status of the clear flags request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr) ;
/** Get the event bits.
*
* Returns the current bits for the event.
*
* @param[in] event Pointer to the event handle
* @param[out] bits pointer to receive the value of the event flags
*
* @return The status of the get request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits) ;
/** Wait for the event and return bits.
*
* Waits for the event to be set and then returns the bits assocaited
* with the event, or waits for the given timeout period.
* @note This function returns if any bit in the set is set.
*
* @param[in] event Pointer to the event handle
* @param[in,out] bits pointer to receive the value of the event flags
* @param[in] clear if true, clear any bits set that cause the wait to return
* if false, do not clear bits
* @param[in] all if true, all bits in the initial bits value must be set to return
* if false, any one bit in the initial bits value must be set to return
* @param[in] timeout The amount of time to wait in milliseconds
*
* @return The status of the wait for event request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout) ;
/** Deinitialize a event.
*
* This function frees the resources associated with an event.
*
* @param[in] event Pointer to the event handle
*
* @return The status of the deletion request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_deinit_event(cy_event_t *event) ;
/*********************************************** Queues **********************************************/
/** Create a queue.
*
* This is a queue of data where entries are placed on the back of the queue
* and removed from the front of the queue.
*
* @param[out] queue Pointer to the queue handle
* @param[in] length The maximum length of the queue in items
* @param[in] itemsize The size of each item in the queue.
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize) ;
/** Put an item in a queue.
*
* This function puts an item in the queue. The item is copied
* into the queue using a memory copy and the data pointed to by item_ptr
* is no longer referenced once the call returns.
*
* @note If in_isr is true, timeout_ms must be zero.
*
* @param[in] queue Pointer to the queue handle
* @param[in] item_ptr Pointer to the item to place in the queue
* @param[in] timeout_ms The time to wait to place the item in the queue
* @param[in] in_isr If true this is being called from within and ISR
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR, CY_RTOS_QUEUE_FULL]
*/
extern cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr) ;
/** Gets an item in a queue.
*
* This function gets an item fropm the queue. The item is copied
* out of the queue into the memory provide by item_ptr. This space must be
* large enough to hold a queue entry as defined when the queue was initialized.
*
* @note If in_isr is true, timeout_ms must be zero.
*
* @param[in] queue Pointer to the queue handle
* @param[in] item_ptr Pointer to the memory for the item from the queue
* @param[in] timeout_ms The time to wait to place the item in the queue
* @param[in] in_isr If true this is being called from within and ISR
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_NO_MEMORY, CY_RTOS_GENERAL_ERROR, CY_RTOS_QUEUE_EMPTY]
*/
extern cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr) ;
/** Return the number of items in the queue.
*
* This function returns the number of items currently in the queue.
*
* @param[in] queue Pointer to the queue handle
* @param[out] num_waiting Pointer to the return count
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting) ;
/** Return the amount of empty space in the queue.
*
* This function returns the amount of empty space in the
* queue. For instance, if the queue was created with 10 entries max and there
* are currently 2 entries in the queue, this will return 8.
*
* @param[in] queue Pointer to the queue handle
* @param[out] num_spaces Pointer to the return count.
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces) ;
/** Reset the queue.
*
* This function sets the queue to empty.
*
* @param[in] queue pointer to the queue handle
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue) ;
/** Deinitialize the queue handle.
*
* This function deinitializes the queue and returns all
* resources used by the queue.
*
* @param[in] queue Pointer to the queue handle
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue) ;
/*********************************************** Timers **********************************************/
/** Create a new timer.
*
* This function intializes a timer object. @note The timer is
* not active until start is called.
*
* @param[out] timer Pointer to the timer handle to initalize
* @param[in] type Type of timer (periodic or once)
* @param[in] fun The functiuon
* @param[in] arg Argument to pass along to the callback function
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type,
cy_timer_callback_t fun, cy_timer_callback_arg_t arg) ;
/** Start a timer.
*
* @note The callback may be (likely will be) called from a different thread.
*
* @param[in] timer Pointer to the timer handle
* @param[in] num_ms The number of miliseconds to wait before the timer fires
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms) ;
/** Stop a timer.
*
* @param[in] timer Pointer to the timer handle
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer) ;
/** Returns state of a timer.
*
* @param[in] timer Pointer to the timer handle
* @param[out] state Return value for state, true if running, false otherwise
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state) ;
/** Deinit the timer.
*
* This function de initializes the timer and frees all consumed
* resources.
*
* @param[in] timer Pointer to the timer handle
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer) ;
/*********************************************** Time **********************************************/
/** Gets time in milliseconds since RTOS start.
*
* @note Since this is only 32 bits, it will roll over every 49 days, 17 hours, 2 mins, 47.296 seconds
*
* @param[out] tval Pointer to the struct to populate with the RTOS time
*
* @returns Time in milliseconds since the RTOS started.
*/
extern cy_rslt_t cy_rtos_get_time(cy_time_t *tval);
/** Delay for a number of milliseconds.
*
* Processing of this function depends on the minimum sleep
* time resolution of the RTOS. The current thread should sleep for
* the longest period possible which is less than the delay required,
* then makes up the difference with a tight loop.
*
* @param[in] num_ms The number of miliseconds to delay for
*
* @return The status of the creation request. [CY_RSLT_SUCCESS, CY_RTOS_GENERAL_ERROR]
*/
extern cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms);
/** \} group_abstraction_rtos_functions */
/** @} */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* ifndef INCLUDED_CY_RTOS_INTERFACE_H_ */

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/***************************************************************************//**
* \file cybsp_api_core.h
*
* \brief
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_abstraction_board Board abstraction
* \ingroup group_abstraction
* \{
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
* \defgroup group_abstraction_board_macros Macros
* \defgroup group_abstraction_board_functions Functions
*/
#pragma once
#include <stdbool.h>
#include "cy_result.h"
#include "cybsp_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_abstraction_board_macros
* \{
*/
/** \} group_abstraction_board_macros */
/**
* \addtogroup group_abstraction_board_functions
* \{
*/
/**
* \brief Initialize all hardware on the board
* \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
* a problem initializing any hardware it returns an error code specific
* to the hardware module that had a problem.
*/
cy_rslt_t cybsp_init(void);
/**
* \brief Init and allocate the specified LED, setting the GPIO drive mode as necessary
* \param which The specific LED number to enable, see BSP header file for available LEDs
* \returns CY_RSLT_SUCCESS if the LED was enabled successfully
*/
cy_rslt_t cybsp_led_init(cybsp_led_t which);
/**
* \brief Toggle the specified LED
* \param which The specific LED number to enable, see BSP header file for available LEDs
*/
void cybsp_led_toggle(cybsp_led_t which);
/**
* \brief Sets the state of the LED.
* \param which The specific LED number to set state, see BSP header file for available LEDs
* \param on Whether the LED should be turned on (true) or off (false)
*/
void cybsp_led_set_state(cybsp_led_t which, bool on);
/**
* \brief Turns the LED on.
* \param which The specific LED number to set state, see BSP header file for available LEDs
* \returns CY_RSLT_SUCCESS if the LED was turned on
*/
static inline void cybsp_led_on(cybsp_led_t which)
{
cybsp_led_set_state(which, CYBSP_LED_STATE_ON);
}
/**
* \brief Turns the LED off.
* \param which The specific LED number to set state, see BSP header file for available LEDs
* \returns CY_RSLT_SUCCESS if the LED was turned off
*/
static inline void cybsp_led_off(cybsp_led_t which)
{
cybsp_led_set_state(which, CYBSP_LED_STATE_OFF);
}
/**
* \brief Init and allocate the specified button, setting the GPIO drive mode as necessary
* \param which The specific button number to enable, see BSP header file for available buttones
* \returns CY_RSLT_SUCCESS if the button was enabled successfully
*/
cy_rslt_t cybsp_btn_init(cybsp_btn_t which);
/**
* \brief Sets the state of the button.
* \param which The specific button number to get state from, see BSP header file for available buttones
* \returns State of the button
*/
bool cybsp_btn_get_state(cybsp_btn_t which);
/**
* \brief Sets the interrupt to trigger when the button state is changed.
* \param which The specific button number to get state from, see BSP header file for available buttones
* \param type The type sets level vs edge and active high vs active low
* \param callback The function pointer to call when the button state changes
*/
void cybsp_btn_set_interrupt(cybsp_btn_t which, cyhal_gpio_irq_event_t type, void (*callback)(void));
/** \} group_abstraction_board_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */
/** \} group_abstraction_board */

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/***************************************************************************//**
* \file cybsp_api_wifi.h
*
* \brief
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_abstraction_board_wifi Board Wifi abstraction
* \ingroup group_abstraction
* \{
* Basic abstraction layer for dealing with boards containing a Cypress MCU. This
* API provides convenience methods for initializing and manipulating different
* hardware found on the board.
*
* \defgroup group_abstraction_board_wifi_macros Macros
* \defgroup group_abstraction_board_wifi_functions Functions
*/
#pragma once
#include "cybsp_api_core.h"
#include "whd_wifi_api.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_abstraction_board_wifi_macros
* \{
*/
/** Indicates that the wifi driver is available and can be used. */
#define CYBSP_WIFI_CAPABLE 1
/** Initialization of the wifi driver failed. */
#define CYBSP_RSLT_WIFI_INIT_FAILED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 4))
/** SDIO enumeration failed. */
#define CYBSP_RSLT_WIFI_SDIO_ENUM_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 5))
/** \} group_abstraction_board_wifi_macros */
/**
* \addtogroup group_abstraction_board_wifi_functions
* \{
*/
/** Initializes the SDIO interface on the board. This only needs to be called if the
* SDIO interface needs to be initialized before the general wifi interface. If not
* called directly, it will automatically be called by cybsp_wifi_init().
*
* @return CY_RSLT_SUCCESS for successful initialization or error if initialization failed.
*/
cy_rslt_t cybsp_sdio_init(void);
/** Initializes the wifi chip on the board.
*
* @return CY_RSLT_SUCCESS for successful initialization or error if initialization failed.
*/
cy_rslt_t cybsp_wifi_init(void);
/** Gets the wifi driver instance initialized by the driver. This should only be called
* after the interface is initialized by cybsp_wifi_init().
*
* @return Wifi driver instance pointer.
*/
whd_driver_t* cybsp_get_wifi_driver(void);
/** \} group_abstraction_board_wifi_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */
/** \} group_abstraction_board_wifi */

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/***************************************************************************//**
* \file cyabs_rtos.c
*
* \brief
* Implementation for CMSIS RTOS v2 abstraction
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdlib.h>
#include <assert.h>
#include "cyabs_rtos.h"
#if defined(__cplusplus)
extern "C" {
#endif
/******************************************************
* Error Converter
******************************************************/
/* Last received error status */
static cy_rtos_error_t dbgErr;
cy_rtos_error_t cy_rtos_last_error() { return dbgErr; }
/* Converts internal error type to external error type */
static cy_rslt_t error_converter(cy_rtos_error_t internalError)
{
cy_rslt_t value;
switch (internalError)
{
case osOK:
value = CY_RSLT_SUCCESS;
break;
case osErrorTimeout:
value = CY_RTOS_TIMEOUT;
break;
case osErrorParameter:
value = CY_RTOS_BAD_PARAM;
break;
case osErrorNoMemory:
value = CY_RTOS_NO_MEMORY;
break;
case osError:
case osErrorResource:
case osErrorISR:
default:
value = CY_RTOS_GENERAL_ERROR;
break;
}
/* Update the last known error status */
dbgErr = internalError;
return value;
}
/******************************************************
* Threads
******************************************************/
cy_rslt_t cy_rtos_create_thread(cy_thread_t *thread, cy_thread_entry_fn_t entry_function,
const char *name, void *stack, uint32_t stack_size, cy_thread_priority_t priority, cy_thread_arg_t arg)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
osThreadAttr_t attr;
if (thread == NULL || stack_size < CY_RTOS_MIN_STACK_SIZE)
status = CY_RTOS_BAD_PARAM;
else
{
attr.name = name;
attr.attr_bits = osThreadJoinable;
attr.cb_size = osRtxThreadCbSize;
attr.stack_size = stack_size;
attr.priority = (osPriority_t)priority;
attr.tz_module = 0;
attr.reserved = 0;
/* Allocate stack if NULL was passed */
if ((uint32_t *)stack == NULL)
{
/* Note: 1 malloc so that it can be freed with 1 call when terminating */
uint32_t cb_mem_pad = (~osRtxThreadCbSize + 1) & CY_RTOS_ALIGNMENT_MASK;
attr.cb_mem = malloc(osRtxThreadCbSize + cb_mem_pad + stack_size);
if (attr.cb_mem != NULL)
attr.stack_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxThreadCbSize + cb_mem_pad);
}
else
{
attr.cb_mem = malloc(osRtxThreadCbSize);
attr.stack_mem = stack;
}
if (attr.cb_mem == NULL)
status = CY_RTOS_NO_MEMORY;
else
{
assert(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
assert(((uint32_t)attr.stack_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
*thread = osThreadNew((osThreadFunc_t)entry_function, (void *)arg, &attr );
assert((*thread == attr.cb_mem) || (*thread == NULL));
status = (*thread == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS;
}
}
return status;
}
cy_rslt_t cy_rtos_exit_thread()
{
osThreadExit();
}
cy_rslt_t cy_rtos_terminate_thread(cy_thread_t *thread)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (thread == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osThreadTerminate(*thread);
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_is_thread_running(cy_thread_t *thread, bool *state)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
if ((thread == NULL) || (state == NULL))
status = CY_RTOS_BAD_PARAM;
else
{
*state = (osThreadGetState(*thread) == osThreadRunning) ? true : false;
}
return status;
}
cy_rslt_t cy_rtos_join_thread(cy_thread_t *thread)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (thread == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osThreadJoin(*thread);
status = error_converter(statusInternal);
if (status == CY_RSLT_SUCCESS)
{
free(*thread);
*thread = NULL;
}
}
return status;
}
/******************************************************
* Mutexes
******************************************************/
cy_rslt_t cy_rtos_init_mutex(cy_mutex_t *mutex)
{
cy_rslt_t status;
osMutexAttr_t attr;
if (mutex == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
attr.name = NULL;
attr.attr_bits = osMutexRecursive | osMutexPrioInherit;
attr.cb_mem = malloc(osRtxMutexCbSize);
attr.cb_size = osRtxMutexCbSize;
if (attr.cb_mem == NULL)
status = CY_RTOS_NO_MEMORY;
else
{
assert(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
*mutex = osMutexNew(&attr);
assert((*mutex == attr.cb_mem) || (*mutex == NULL));
status = (*mutex == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS;
}
}
return status;
}
cy_rslt_t cy_rtos_get_mutex(cy_mutex_t *mutex, cy_time_t timeout_ms)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (mutex == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osMutexAcquire(*mutex, timeout_ms);
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_set_mutex(cy_mutex_t *mutex)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (mutex == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osMutexRelease(*mutex);
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_deinit_mutex(cy_mutex_t *mutex)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (mutex == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osMutexDelete(*mutex);
status = error_converter(statusInternal);
if (status == CY_RSLT_SUCCESS)
{
free(*mutex);
*mutex = NULL;
}
}
return status;
}
/******************************************************
* Semaphores
******************************************************/
cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, uint32_t initcount)
{
cy_rslt_t status;
osSemaphoreAttr_t attr;
if (semaphore == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
attr.name = NULL;
attr.attr_bits = 0U;
attr.cb_mem = malloc(osRtxSemaphoreCbSize);
attr.cb_size = osRtxSemaphoreCbSize;
if (attr.cb_mem == NULL)
status = CY_RTOS_NO_MEMORY;
else
{
assert(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
*semaphore = osSemaphoreNew(maxcount, initcount, &attr);
assert((*semaphore == attr.cb_mem) || (*semaphore == NULL));
status = (*semaphore == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS;
}
}
return status;
}
cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
cy_rtos_error_t statusInternal;
if (semaphore == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
/* Not allowed to be called in ISR if timeout != 0 */
if ((!in_isr) || (in_isr && (timeout_ms == 0U)))
statusInternal = osSemaphoreAcquire(*semaphore, timeout_ms);
else
statusInternal = osErrorISR;
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
cy_rtos_error_t statusInternal;
(void)in_isr; // Unused parameter in this implementation
if (semaphore == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osSemaphoreRelease(*semaphore);
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_deinit_semaphore(cy_semaphore_t *semaphore)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (semaphore == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osSemaphoreDelete(*semaphore);
status = error_converter(statusInternal);
if (status == CY_RSLT_SUCCESS)
{
free(*semaphore);
*semaphore = NULL;
}
}
return status;
}
/******************************************************
* Events
******************************************************/
#define CY_RTOS_EVENT_ERRORFLAG 0x80000000UL
#define CY_RTOS_EVENT_FLAGS 0x7FFFFFFFUL
cy_rslt_t cy_rtos_init_event(cy_event_t *event)
{
cy_rslt_t status;
osEventFlagsAttr_t attr;
if (event == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
attr.name = NULL;
attr.attr_bits = 0U;
attr.cb_mem = malloc(osRtxEventFlagsCbSize);
attr.cb_size = osRtxEventFlagsCbSize;
if (attr.cb_mem == NULL)
status = CY_RTOS_NO_MEMORY;
else
{
assert(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
*event = osEventFlagsNew(&attr);
assert((*event == attr.cb_mem) || (*event == NULL));
status = (*event == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS;
}
}
return status;
}
cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
cy_rtos_error_t statusInternal;
(void)in_isr; // Unused parameter in this implementation
if (event == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = (osStatus_t)osEventFlagsSet(*event, bits);
if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL)
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
cy_rtos_error_t statusInternal;
(void)in_isr; // Unused parameter in this implementation
if (event == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = (osStatus_t)osEventFlagsClear(*event, bits);
if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) != 0UL)
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_getbits_event(cy_event_t *event, uint32_t *bits)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
if ((event == NULL) || (bits == NULL))
status = CY_RTOS_BAD_PARAM;
else
*bits = osEventFlagsGet(*event);
return status;
}
cy_rslt_t cy_rtos_waitbits_event(cy_event_t *event, uint32_t *bits, bool clear, bool all, cy_time_t timeout)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
cy_rtos_error_t statusInternal;
uint32_t flagOption;
if ((event == NULL) || (bits == NULL))
status = CY_RTOS_BAD_PARAM;
else
{
flagOption = (all) ? osFlagsWaitAll : osFlagsWaitAny;
if (!clear)
flagOption |= osFlagsNoClear;
statusInternal = (osStatus_t)osEventFlagsWait(*event, *bits, flagOption, timeout);
if ((statusInternal & CY_RTOS_EVENT_ERRORFLAG) == 0UL)
*bits = statusInternal;
else
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_deinit_event(cy_event_t *event)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (event == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osEventFlagsDelete(*event);
status = error_converter(statusInternal);
if (status == CY_RSLT_SUCCESS)
{
free(*event);
*event = NULL;
}
}
return status;
}
/******************************************************
* Queues
******************************************************/
cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize)
{
cy_rslt_t status;
osMessageQueueAttr_t attr;
if (queue == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
attr.name = NULL;
attr.attr_bits = 0U;
attr.cb_size = osRtxMessageQueueCbSize;
uint32_t blockSize = ((itemsize + 3U) & ~3UL) + sizeof(osRtxMessage_t);
attr.mq_size = blockSize * length;
/* Note: 1 malloc for both so that they can be freed with 1 call */
uint32_t cb_mem_pad = (8 - (osRtxMessageQueueCbSize & 0x07)) & 0x07;
attr.cb_mem = malloc(osRtxMessageQueueCbSize + cb_mem_pad + attr.mq_size);
if (attr.cb_mem != NULL)
attr.mq_mem = (uint32_t *)((uint32_t)attr.cb_mem + osRtxMessageQueueCbSize + cb_mem_pad);
if (attr.cb_mem == NULL)
status = CY_RTOS_NO_MEMORY;
else
{
assert(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
assert(((uint32_t)attr.mq_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
*queue = osMessageQueueNew(length, itemsize, &attr);
assert((*queue == attr.cb_mem) || (*queue == NULL));
status = (*queue == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS;
}
}
return status;
}
cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms, bool in_isr)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if ((queue == NULL) || (item_ptr == NULL))
status = CY_RTOS_BAD_PARAM;
else
{
/* Not allowed to be called in ISR if timeout != 0 */
if ((!in_isr) || (in_isr && (timeout_ms == 0U)))
statusInternal = osMessageQueuePut(*queue, (uint8_t *)item_ptr, 0u, timeout_ms);
else
statusInternal = osErrorISR;
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if ((queue == NULL) || (item_ptr == NULL))
status = CY_RTOS_BAD_PARAM;
else
{
/* Not allowed to be called in ISR if timeout != 0 */
if ((!in_isr) || (in_isr && (timeout_ms == 0U)))
statusInternal = osMessageQueueGet(*queue, (uint8_t *)item_ptr, 0u, timeout_ms);
else
statusInternal = osErrorISR;
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_count_queue(cy_queue_t *queue, size_t *num_waiting)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
if ((queue == NULL) || (num_waiting == NULL))
status = CY_RTOS_BAD_PARAM;
else
*num_waiting = osMessageQueueGetCount(*queue);
return status;
}
cy_rslt_t cy_rtos_space_queue(cy_queue_t *queue, size_t *num_spaces)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
if ((queue == NULL) || (num_spaces == NULL))
status = CY_RTOS_BAD_PARAM;
else
*num_spaces = osMessageQueueGetSpace(*queue);
return status;
}
cy_rslt_t cy_rtos_reset_queue(cy_queue_t *queue)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (queue == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osMessageQueueReset(*queue);
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_deinit_queue(cy_queue_t *queue)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (queue == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osMessageQueueDelete(*queue);
status = error_converter(statusInternal);
if (status == CY_RSLT_SUCCESS)
{
free(*queue);
*queue = NULL;
}
}
return status;
}
/******************************************************
* Timers
******************************************************/
cy_rslt_t cy_rtos_init_timer(cy_timer_t *timer, cy_timer_trigger_type_t type,
cy_timer_callback_t fun, cy_timer_callback_arg_t arg)
{
cy_rslt_t status;
osTimerAttr_t attr;
if (timer == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
attr.name = NULL;
attr.attr_bits = 0U;
attr.cb_mem = malloc(osRtxTimerCbSize);
attr.cb_size = osRtxTimerCbSize;
if (attr.cb_mem == NULL)
status = CY_RTOS_NO_MEMORY;
else
{
osTimerType_t osTriggerType = (cy_timer_type_periodic == type)
? osTimerPeriodic
: osTimerOnce;
assert(((uint32_t)attr.cb_mem & CY_RTOS_ALIGNMENT_MASK) == 0UL);
*timer = osTimerNew( (osTimerFunc_t)fun, osTriggerType, (void *)arg, &attr );
assert((*timer == attr.cb_mem) || (*timer == NULL));
status = (*timer == NULL) ? CY_RTOS_GENERAL_ERROR : CY_RSLT_SUCCESS;
}
}
return status;
}
cy_rslt_t cy_rtos_start_timer(cy_timer_t *timer, cy_time_t num_ms)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (timer == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
/* Get Number of ticks per second */
uint32_t tick_freq = osKernelGetTickFreq();
/* Convert ticks count to time in milliseconds */
if (tick_freq != 0)
{
uint32_t ticks = ((num_ms * tick_freq) / 1000);
statusInternal = osTimerStart(*timer, ticks);
status = error_converter(statusInternal);
}
else
status = CY_RTOS_GENERAL_ERROR;
}
return status;
}
cy_rslt_t cy_rtos_stop_timer(cy_timer_t *timer)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (timer == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osTimerStop(*timer);
status = error_converter(statusInternal);
}
return status;
}
cy_rslt_t cy_rtos_is_running_timer(cy_timer_t *timer, bool *state)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
if ((timer == NULL) || (state == NULL))
status = CY_RTOS_BAD_PARAM;
else
*state = osTimerIsRunning(*timer);
return status;
}
cy_rslt_t cy_rtos_deinit_timer(cy_timer_t *timer)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
if (timer == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
statusInternal = osTimerDelete(*timer);
status = error_converter(statusInternal);
if (status == CY_RSLT_SUCCESS)
{
free(*timer);
*timer = NULL;
}
}
return status;
}
/******************************************************
* Time
******************************************************/
cy_rslt_t cy_rtos_get_time(cy_time_t *tval)
{
cy_rslt_t status = CY_RSLT_SUCCESS;
uint32_t tick_freq;
if (tval == NULL)
status = CY_RTOS_BAD_PARAM;
else
{
/* Get Number of ticks per second */
tick_freq = osKernelGetTickFreq();
/* Convert ticks count to time in milliseconds */
if (tick_freq != 0)
*tval = ((osKernelGetTickCount() * 1000) / tick_freq);
else
status = CY_RTOS_GENERAL_ERROR;
}
return status;
}
cy_rslt_t cy_rtos_delay_milliseconds(cy_time_t num_ms)
{
cy_rslt_t status;
cy_rtos_error_t statusInternal;
statusInternal = osDelay(num_ms);
status = error_converter(statusInternal);
return status;
}
#if defined(__cplusplus)
}
#endif

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/***************************************************************************//**
* \file cy_resource_access.c
*
* \brief
* Provides API for reading data from resource files however they are stored.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "cyabs_resource.h"
#include "cy_utils.h"
#if defined(__cplusplus)
extern "C" {
#endif
cy_rslt_t cy_resource_get_block_size(const cy_resource_handle_t *handle, uint32_t *size)
{
switch (handle->location)
{
case CY_RESOURCE_IN_MEMORY:
*size = handle->size;
return CY_RSLT_SUCCESS;
case CY_RESOURCE_IN_FILESYSTEM:
case CY_RESOURCE_IN_EXTERNAL_STORAGE:
//TODO: implement
default:
CY_ASSERT(false);
*size = 0;
return CY_RSLT_RSC_ERROR_UNSUPPORTED;
}
}
cy_rslt_t cy_resource_get_total_size(const cy_resource_handle_t *handle, uint32_t *size)
{
*size = handle->size;
return CY_RSLT_SUCCESS;
}
cy_rslt_t cy_resource_get_block_count(const cy_resource_handle_t *handle, uint32_t *blocks)
{
uint32_t block_size;
uint32_t total_size = handle->size;
cy_rslt_t rslt = cy_resource_get_block_size(handle, &block_size);
if (rslt == CY_RSLT_SUCCESS && block_size > 0)
{
*blocks = (total_size + block_size - 1) / block_size;
}
else
{
*blocks = 0;
}
return rslt;
}
cy_rslt_t cy_resource_read(const cy_resource_handle_t *handle, uint32_t blockno, uint8_t **buffer, uint32_t *size)
{
cy_rslt_t result = cy_resource_get_block_size(handle, size);
if (CY_RSLT_SUCCESS != result)
{
return result;
}
void *p = malloc(*size);
if (!p)
{
return CY_RSLT_RSC_ERROR_UNAVAILABLE;
}
*buffer = p;
switch (handle->location)
{
case CY_RESOURCE_IN_MEMORY:
CY_ASSERT(0 == blockno);
memcpy(*buffer, handle->val.mem_data, *size);
return CY_RSLT_SUCCESS;
case CY_RESOURCE_IN_FILESYSTEM:
case CY_RESOURCE_IN_EXTERNAL_STORAGE:
//TODO: implement
default:
free(p);
CY_ASSERT(false);
*size = 0;
return CY_RSLT_RSC_ERROR_UNSUPPORTED;
}
}
cy_rslt_t cy_resource_readonly_memory(const cy_resource_handle_t *handle, const uint8_t **buffer, uint32_t *size)
{
if (CY_RESOURCE_IN_MEMORY == handle->location)
{
*buffer = handle->val.mem_data;
*size = handle->size;
return CY_RSLT_SUCCESS;
}
else
{
return CY_RSLT_RSC_ERROR_UNSUPPORTED;
}
}
#if defined(__cplusplus)
}
#endif

134
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/***************************************************************************//**
* \file cy_result.h
*
* \brief
* Basic function result handling. Defines a simple type for conveying
* information about whether something succeeded or details about any issues
* that were detected.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_result Result Type
* \ingroup group_abstraction
* \{
* Basic function result handling. Defines a simple type for conveying
* information about whether something succeeded or details about any issues
* that were detected.
*
* \defgroup group_result_macros Macros
*/
#pragma once
#include <stdint.h>
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_result_macros
* \{
*/
/** Mask for the bit at position "x" */
#define CY_BIT_MASK(x) ((1U << (x)) - 1U)
/** Bit position of the result code */
#define CY_RSLT_CODE_POSITION (0U)
/** Bit width of the result code */
#define CY_RSLT_CODE_WIDTH (16U)
/** Bit position of the result type */
#define CY_RSLT_TYPE_POSITION (16U)
/** Bit width of the result type */
#define CY_RSLT_TYPE_WIDTH (2U)
/** Bit position of the module identifier */
#define CY_RSLT_MODULE_POSITION (18U)
/** Bit width of the module identifier */
#define CY_RSLT_MODULE_WIDTH (14U)
/** Mask for the result code */
#define CY_RSLT_CODE_MASK CY_BIT_MASK(CY_RSLT_CODE_WIDTH)
/** Mask for the module identifier */
#define CY_RSLT_MODULE_MASK CY_BIT_MASK(CY_RSLT_MODULE_WIDTH)
/** Mask for the result type */
#define CY_RSLT_TYPE_MASK CY_BIT_MASK(CY_RSLT_TYPE_WIDTH)
/** Informational-only result status */
#define CY_RSLT_TYPE_INFO (0U)
/** Warning result */
#define CY_RSLT_TYPE_WARNING (1U)
/** Error result */
#define CY_RSLT_TYPE_ERROR (2U)
/** Fatal error result */
#define CY_RSLT_TYPE_FATAL (3U)
/** Get the value of the result code field */
#define CY_RSLT_GET_CODE(x) (((x) >> CY_RSLT_CODE_POSITION) & CY_RSLT_CODE_MASK)
/** Get the value of the result type field */
#define CY_RSLT_GET_TYPE(x) (((x) >> CY_RSLT_TYPE_POSITION) & CY_RSLT_TYPE_MASK)
/** Get the value of the module identifier field */
#define CY_RSLT_GET_MODULE(x) (((x) >> CY_RSLT_MODULE_POSITION) & CY_RSLT_MODULE_MASK)
/**** DRIVER Module codes: 0x0000 - 0x00FF ****/
/** Base identifier for peripheral driver library */
#define CY_RSLT_MODULE_DRIVERS_PDL_BASE (0x0000U)
/** Base identifier for peripheral driver library */
#define CY_RSLT_MODULE_DRIVERS_WHD_BASE (0x0080U)
/**** ABSTRACTION Module codes: 0x0100 - 0x01FF ****/
/** Base identifier for chip support modules */
#define CY_RSLT_MODULE_ABSTRACTION_HAL_BASE (0x0100U)
/** Base identifier for board support modules */
#define CY_RSLT_MODULE_ABSTRACTION_BSP (0x0180U)
/** Base identifier for file system modules */
#define CY_RSLT_MODULE_ABSTRACTION_FS (0x0181U)
/** Base identifier for resource abstraction modules */
#define CY_RSLT_MODULE_ABSTRACTION_RESOURCE (0x0182U)
/** Base identifier for rtos abstraction modules */
#define CY_RSLT_MODULE_ABSTRACTION_OS (0x0183U)
/** Base identifier for environment abstraction modules */
#define CY_RSLT_MODULE_ABSTRACTION_ENV (0x0184U)
/**** Middleware Module codes: 0x0200 - 0x02FF ****/
#define CY_RSLT_MODULE_MIDDLEWARE_BASE (0x0200U)
/** Provides the result of an operation as a structured bitfield */
typedef uint32_t cy_rslt_t;
/** Result value indicating success */
#define CY_RSLT_SUCCESS ((cy_rslt_t)0x00000000U)
/** Create a result value from the specified type, module, and result code */
#define CY_RSLT_CREATE(type, module, code) \
((((module) & CY_RSLT_MODULE_MASK) << CY_RSLT_MODULE_POSITION) | \
(((code) & CY_RSLT_CODE_MASK) << CY_RSLT_CODE_POSITION) | \
(((type) & CY_RSLT_TYPE_MASK) << CY_RSLT_TYPE_POSITION))
/** \} group_result_macros */
#ifdef __cplusplus
}
#endif
/** \} group_result */

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/***************************************************************************//**
* \file cy_utils.h
*
* \brief
* Basic utility macros and functions.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_utils Utilities
* \ingroup group_abstraction
* \{
* Basic utility macros and functions.
*
* \defgroup group_utils_macros Macros
*/
#pragma once
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_utils_macros
* \{
*/
/** Simple macro to supress the unused parameter warning by casting to void. */
#define CY_UNUSED_PARAMETER(x) ( (void)(x) )
static inline uint32_t CY_HALT()
{
__asm(" bkpt 1");
return 0;
}
#ifdef CY_ASSERT
#undef CY_ASSERT
#endif /* ifdef(CY_ASSERT) */
/** Utility macro when neither NDEBUG or CY_NO_ASSERT is not declared to check a condition and, if false, trigger a breakpoint */
#if defined(NDEBUG) || defined(CY_NO_ASSERT)
#define CY_ASSERT(x) CY_UNUSED_PARAMETER(x)
#else
#define CY_ASSERT(x) do { \
if(!(x)) \
{ \
CY_HALT(); \
} \
} while(0)
#endif /* defined(NDEBUG) */
/** \} group_utils_macros */
#ifdef __cplusplus
}
#endif
/** \} group_utils */

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/*******************************************************************************
* File Name: cyhal.h
*
* Description:
* Top-level HAL header file that includes all available HAL header files. This
* will pull in all of the specific HAL files needed. Not all of these may be
* supported in the target device. The target device must provide a
* cyhal_hw_types.h file that is in the include path for the hal headers to
* depend on. The cyhal_hw_types.h file must provide definitions for each of
* the resource types consumed by the HAL driver functions. Additionally, the
* implementation may define a cyhal_implementation.h file that provides any
* custom includes. This file is optional per implementation.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal
* \{
* TODO: high-level HAL description
* update hal/include/cyhal.h to change this text
* \} group_hal
*/
#pragma once
#include "cyhal_adc.h"
#include "cyhal_comp.h"
#include "cyhal_crc.h"
#include "cyhal_crc_impl.h"
#include "cyhal_dac.h"
#include "cyhal_dma.h"
#include "cyhal_flash.h"
#include "cyhal_gpio.h"
#include "cyhal_hwmgr.h"
#include "cyhal_i2c.h"
#include "cyhal_i2s.h"
#include "cyhal_interconnect.h"
#include "cyhal_lptimer.h"
#include "cyhal_opamp.h"
#include "cyhal_pdmpcm.h"
#include "cyhal_pwm.h"
#include "cyhal_qspi.h"
#include "cyhal_rtc.h"
#include "cyhal_sdhc.h"
#include "cyhal_sdio.h"
#include "cyhal_spi.h"
#include "cyhal_system.h"
#include "cyhal_timer.h"
#include "cyhal_trng.h"
#include "cyhal_uart.h"
#include "cyhal_usb_dev.h"
/** \} group_hal */

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/***************************************************************************//**
* \file cyhal_adc.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Analog to
* Digital Converter. This interface abstracts out the chip specific details.
* If any chip specific functionality is necessary, or performance is critical
* the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_adc ADC (Analog to Digital Converter)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress ADC.
*
* \defgroup group_hal_adc_macros Macros
* \defgroup group_hal_adc_functions ADC Functions
* \defgroup group_hal_adc_channel_functions ADC Channel Functions
* \defgroup group_hal_adc_data_structures Data Structures
* \defgroup group_hal_adc_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#include "cyhal_hwmgr.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_adc_macros
* \{
*/
/** Maximum value that the ADC can return */
#define CYHAL_ADC_MAX_VALUE 0x0FFF
/** Bad argument */
#define CYHAL_ADC_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 0))
/** Failed to initialize ADC clock */
#define CYHAL_ADC_RSLT_FAILED_CLOCK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 1))
/** Failed to initialize ADC */
#define CYHAL_ADC_RSLT_FAILED_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 2))
/** No channels available */
#define CYHAL_ADC_RSLT_NO_CHANNELS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 3))
/** \} group_hal_adc_macros */
/**
* \addtogroup group_hal_adc_functions
* \{
*/
/** Initialize adc peripheral
*
* @param[out] obj The adc object to initialize
* @param[in] pin A pin corresponding to the ADC block to initialize
* Note: This pin is not reserved, it is just used to identify which ADC block to allocate.
* If multiple channels will be allocated for a single ADC instance, only one pin should be
* passed here; it does not matter which one. After calling this function once, call
* cyhal_adc_channel_init once for each pin whose value should be measured.
* @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated
* @return The status of the init request
*/
cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk);
/** Uninitialize the adc peripheral and cyhal_adc_t object
*
* @param[in,out] obj The adc object
*/
void cyhal_adc_free(cyhal_adc_t *obj);
/** \} group_hal_adc_functions */
/**
* \addtogroup group_hal_adc_channel_functions
* \{
*/
/** Initialize a single-ended adc channel.
*
* Configures the pin used by adc.
* @param[out] obj The adc channel object to initialize
* @param[in] adc The adc for which the channel should be initialized
* @param[in] pin The adc pin name
* @return The status of the init request
*/
cy_rslt_t cyhal_adc_channel_init(cyhal_adc_channel_t *obj, cyhal_adc_t* adc, cyhal_gpio_t pin);
/** Uninitialize the adc channel and cyhal_adc_channel_t object
*
* @param[in,out] obj The adc channel object
*/
void cyhal_adc_channel_free(cyhal_adc_channel_t *obj);
/** Read the value from adc pin, represented as an unsigned 16bit value
* where 0x0000 represents the minimum value in the ADC's range, and 0xFFFF
* represents the maximum value in the ADC's range.
*
* @param[in] obj The adc object
* @return An unsigned 16bit value representing the current input voltage
*/
uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj);
/** \} group_hal_adc_channel_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_adc */

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/***************************************************************************//**
* \file cyhal_analog_common.h
*
* \brief
* Provides common functionality that needs to be shared among all drivers that
* interact with the Programmable Analog Subsystem.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#if defined(__cplusplus)
extern "C" {
#endif
/**
* Initialize the programmable analog. This utilizes reference counting to avoid
* repeatedly initializing the analog subsystem when multiple analog blocks are in use
* */
void cyhal_analog_init();
/**
* Uninitialize the programmable analog. This utilizes reference counting to avoid
* disabling the analog subsystem until all blocks which require it have been freed.
*/
void cyhal_analog_free();
#if defined(__cplusplus)
}
#endif

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/***************************************************************************//**
* \file cyhal_comp.h
*
* Provides a high level interface for interacting with the Cypress Comparator.
* This interface abstracts out the chip specific details.
* If any chip specific functionality is necessary, or performance is critical,
* the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_comp COMP (Comparator)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress Comparator.
*
* \defgroup group_hal_comp_macros Macros
* \defgroup group_hal_comp_functions Functions
* \defgroup group_hal_comp_data_structures Data Structures
* \defgroup group_hal_comp_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_comp_enums
* \{
*/
/** Comparator interrupt triggers */
typedef enum {
CYHAL_COMP_IRQ_NONE, //!< Interrupts disabled
CYHAL_COMP_IRQ_RISE, //!< Rising edge
CYHAL_COMP_IRQ_FALL, //!< Falling edge
} cyhal_comp_irq_event_t;
/** Comparator power options */
typedef enum {
CYHAL_COMP_POWER_OFF, //!< Block is turned off
CYHAL_COMP_POWER_LOW, //!< Block runs in low power/speed mode
CYHAL_COMP_POWER_MEDIUM, //!< Block runs in medium power/speed mode
CYHAL_COMP_POWER_HIGH, //!< Block runs in high power/speed mode
} cyhal_comp_power_t;
/** Comparator output modes */
typedef enum {
CYHAL_COMP_OUTPUT_PULSE, //!< Pulse output
CYHAL_COMP_OUTPUT_DIRECT, //!< Level output directly
CYHAL_COMP_OUTPUT_SYNC, //!< Level output after synchronous edge detection
} cyhal_comp_output_t;
/** \} group_hal_comp_enums */
/**
* \addtogroup group_hal_comp_data_structures
* \{
*/
/** Configuration options for the comparator */
typedef struct
{
cyhal_comp_power_t power; //!< Power mode to operate in (0=off, 1=low, 2=medium, 3=high)
cyhal_comp_output_t output; //!< Output configuration (0=pulse, 1=direct, 2=sync)
bool hysteresis; //!< Should this use hysteresis
bool deepsleep; //!< Does this need to operate in deepsleep
} cyhal_comp_config_t;
/** Handler for comparator interrupts */
typedef void (*cyhal_comp_irq_handler_t)(void *handler_arg, cyhal_comp_irq_event_t event);
/** \} group_hal_comp_data_structures */
/**
* \addtogroup group_hal_comp_functions
* \{
*/
/** Initialize the comparator peripheral.
*
* @param[out] obj The comparator object
* @param[in] vinp The vplus pin
* @param[in] vinm The vminus pin
* @param[in] vout The vout pin
* @return The status of the init request
*/
cy_rslt_t cyhal_comp_init(cyhal_comp_t *obj, cyhal_gpio_t vinp, cyhal_gpio_t vinm, cyhal_gpio_t vout);
/** Release the comparator peripheral.
*
* @param[in,out] obj The comparator object
*/
void cyhal_comp_free(cyhal_comp_t *obj);
/** Reconfigure the comparator object
*
* @param[in,out] obj The comparator object
* @param[in] cfg Configuration to apply to the comparator
* @return The status of the power request
*/
cy_rslt_t cyhal_comp_configure(cyhal_comp_t *obj, const cyhal_comp_config_t cfg);
/** Gets the result of the comparator object
*
* @param[in] obj The comparator object
* @return The comparator output state
*/
bool cyhal_comp_output(cyhal_comp_t *obj);
/** Register/clear an interrupt handler for the comparator toggle IRQ event
*
* @param[in] obj The comparator object
* @param[in] handler The function to call when the specified event happens
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_comp_register_irq(cyhal_comp_t *obj, cyhal_comp_irq_handler_t handler, void *handler_arg);
/** Enable or Disable the comparator IRQ
*
* @param[in] obj The comparator object
* @param[in] event The comparator IRQ event
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_cyhal_comp_irq_enable(cyhal_comp_t *obj, cyhal_comp_irq_event_t event, bool enable);
/** \} group_hal_comp_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_comp */

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/***************************************************************************//**
* \file cyhal_crc.h
*
* \brief
* Provides a high level interface for interacting with the Cypress CRC.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_crc CRC (Cyclic Redundancy Check)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress CRC.
*
* \defgroup group_hal_crc_macros Macros
* \defgroup group_hal_crc_functions Functions
* \defgroup group_hal_crc_data_structures Data Structures
* \defgroup group_hal_crc_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_crc_macros
* \{
*/
/** Invalid argument */
#define CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_CRC, 0))
/** \} group_hal_crc_macros */
/**
* \addtogroup group_hal_crc_data_structures
* \{
*/
/** CRC algorithm parameters */
typedef struct
{
uint32_t width; //!< Bit width of the CRC
uint32_t polynomial; //!< The polynomial to use
uint32_t lfsrInitState; //!< Initial state of the LFSR
uint32_t dataXor; //!< Byte mask to xor with the data
uint32_t remXor; //!< Mask to xor with the remainder.
/**
* The order in which data should be processed.
* If 0, data is processed MSB first.
* If 1, data is processed LSB first.
*/
uint8_t dataReverse;
uint8_t remReverse; //!< If 1, the remainder is reversed. If 0, it is not.
} crc_algorithm_t;
/** \} group_hal_crc_data_structures */
/**
* \addtogroup group_hal_crc_functions
* \{
*/
/** Initialize the CRC generator. This function reserves the CRYPTO block for CRC calculations.
*
* @param[out] obj The CRC generator object
* @return The status of the init request.
*/
cy_rslt_t cyhal_crc_init(cyhal_crc_t *obj);
/** Release the CRC generator.
*
* @param[in,out] obj The CRC generator object
*/
void cyhal_crc_free(cyhal_crc_t *obj);
/** Initializes a CRC calculation.
*
* @param[in,out] obj The CRC generator object
* @param[in] algorithm The CRC algorithm to use for computations
* @return The status of the compute request
*/
cy_rslt_t cyhal_crc_start(cyhal_crc_t *obj, const crc_algorithm_t *algorithm);
/** Computes the CRC for the given data. This function can be called multiple times to
* provide addtional data. This CRC generator will compute the CRC for including all data
* that was provided during previous calls.
*
* @param[in] obj The CRC generator object
* @param[in] data The data to compute a CRC over
* @param[in] length The number of bytes of data to process
* @return The status of the compute request
*/
cy_rslt_t cyhal_crc_compute(const cyhal_crc_t *obj, const uint8_t *data, size_t length);
/** Provides final result for a CRC calculation. This will compute the CRC for all data that
* was provided when during the diffrent calls to cyhal_crc_compute.
*
* @param[in] obj The CRC generator object
* @param[out] crc The computed CRC
* @return The status of the compute request
*/
cy_rslt_t cyhal_crc_finish(const cyhal_crc_t *obj, uint32_t *crc);
/** \} group_hal_crc_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_crc */

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/***************************************************************************//**
* \file cyhal_crc_impl.h
*
* Description:
* Provides a high level interface for interacting with the Cypress GPIO. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cyhal_crc.h"
#include "cyhal_hwmgr.h"
#include "cy_utils.h"
#if defined(CY_IP_MXCRYPTO)
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
__STATIC_INLINE cy_rslt_t cyhal_crc_start_internal(cyhal_crc_t *obj, const crc_algorithm_t *algorithm)
{
if(NULL == obj || NULL == algorithm)
return CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT;
obj->crc_width = algorithm->width;
return Cy_Crypto_Core_Crc_CalcInit(obj->base,
algorithm->width,
algorithm->polynomial,
algorithm->dataReverse,
algorithm->dataXor,
algorithm->remReverse,
algorithm->remXor,
algorithm->lfsrInitState);
}
#define cyhal_crc_start(obj, algorithm) cyhal_crc_start_internal(obj, algorithm)
__STATIC_INLINE cy_rslt_t cyhal_crc_compute_internal(const cyhal_crc_t *obj, const uint8_t *data, size_t length)
{
if(NULL == obj || NULL == data || 0 == length)
return CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT;
return Cy_Crypto_Core_Crc_CalcPartial(obj->base, data, length);
}
#define cyhal_crc_compute(obj, data, length) cyhal_crc_compute_internal(obj, data, length)
__STATIC_INLINE cy_rslt_t cyhal_crc_finish_internal(const cyhal_crc_t *obj, uint32_t *crc)
{
if(NULL == obj || NULL == crc)
return CYHAL_CRC_RSLT_ERR_BAD_ARGUMENT;
return Cy_Crypto_Core_Crc_CalcFinish(obj->base, obj->crc_width, crc);
}
#define cyhal_crc_finish(obj, crc) cyhal_crc_finish_internal(obj, crc)
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* defined(CY_IP_MXCRYPTO) */

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/***************************************************************************//**
* \file cyhal_crypto_common.h
*
* Description:
* This file provides common defines and addresses required by drivers using the
* Crypto block.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cy_device.h"
#include "cy_pdl.h"
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(CY_IP_MXCRYPTO)
#if defined(__cplusplus)
extern "C" {
#endif
/** Block count for CRYPTO blocks */
#define CYHAL_CRYPTO_INST_COUNT CY_IP_MXCRYPTO_INSTANCES
/** The start address of the CRYPTO blocks */
extern CRYPTO_Type* cyhal_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT];
/** Reserve the Crypto block and enable it.
*
* @param[out] base Base address to the Crypto block.
* @param[out] obj resource inst for the function (eg. CRC, TRNG) in the Crypto block.
* @return The status of the reserve request.
*/
cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource);
/** Free the Crypto block and disable it.
*
* @param[in] base Base address to the Crypto block.
* @param[in] obj resource inst for the funtion in Crypto block.
*/
void cyhal_crypto_free(CRYPTO_Type* base, const cyhal_resource_inst_t *resource);
#if defined(__cplusplus)
}
#endif
#endif /* defined(CY_IP_MXCRYPTO) */

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/***************************************************************************//**
* \file cyhal_dac.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Digital to
* Analog Converter. This interface abstracts out the chip specific details. If
* any chip specific functionality is necessary, or performance is critical the
* low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_dac DAC (Digital to Analog Converter)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress DAC.
*
* \defgroup group_hal_dac_macros Macros
* \defgroup group_hal_dac_functions Functions
* \defgroup group_hal_dac_data_structures Data Structures
* \defgroup group_hal_dac_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#include "cyhal_hwmgr.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_dac_macros
* \{
*/
/** Bad argument */
#define CYHAL_DAC_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DAC, 0))
/** Failed to initialize DAC */
#define CYHAL_DAC_RSLT_FAILED_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DAC, 1))
/** \} group_hal_adc_macros */
/**
* \addtogroup group_hal_dac_functions
* \{
*/
/** Initialize the dac peripheral
*
* Configures the pin used by dac.
* @param[in] obj The dac object to initialize
* @param[in] pin The dac pin name
* @return The status of the init request
*/
cy_rslt_t cyhal_dac_init(cyhal_dac_t *obj, cyhal_gpio_t pin);
/** Release the dac object
*
* @param[in,out] obj The dac object
*/
void cyhal_dac_free(cyhal_dac_t *obj);
/** Set the output voltage, as a normalized unsigned 16-bit value
* (where 0 is the lowest value the DAC can output and 0xFFFF
* is the highest)
*
* @param[in] obj The dac object
* @param[in] value The 16-bit output value to set
*/
void cyhal_dac_write(const cyhal_dac_t *obj, uint16_t value);
/** Read the current DAC output voltage setting, as a normalized unsigned
* 16-bit value (where 0 is the lowest value the DAC can output and 0xFFFF
* is the highest).
* Note: Depending on the precision of the underlying hardware, this may not
* precisely match the most recent value passed in to cyhal_dac_write.
*
* @param[in] obj The dac object
* @return The 16-bit output value
*/
uint16_t cyhal_dac_read(cyhal_dac_t *obj);
/** \} group_hal_dac_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_dac */

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/***************************************************************************//**
* \file cyhal_dma.h
*
* \brief
* Provides a high level interface for interacting with the Cypress DMA.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_dma DMA (Direct Memory Access)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress DMA.
*
* \defgroup group_hal_dma_macros Macros
* \defgroup group_hal_dma_functions Functions
* \defgroup group_hal_dma_data_structures Data Structures
* \defgroup group_hal_dma_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_dma_enums
* \{
*/
/** Direction for DMA transfers */
typedef enum
{
CYHAL_DMA_DIRECTION_MEM2MEM, //!< Memory to memory
CYHAL_DMA_DIRECTION_MEM2PERIPH, //!< Memory to peripheral
CYHAL_DMA_DIRECTION_PERIPH2MEM, //!< Peripheral to memory
} cyhal_dma_direction_t;
/** DMA interrupt triggers */
typedef enum {
/** TODO: Fill in */
CYHAL_DMA_TBD,
} cyhal_dma_irq_event_t;
/** \} group_hal_dma_enums */
/**
* \addtogroup group_hal_dma_data_structures
* \{
*/
/** Initial configuration of a DMA channel */
typedef struct
{
uint32_t src_addr; //!< source address
int8_t src_increment; //!< source address auto increment amount
uint32_t dst_addr; //!< destination address
int8_t dst_increment; //!< destination address auto increment amount
uint32_t length; //!< length of data to be transferred
uint8_t beat_size; //!< beat size to be set (8, 16, 32)
//cyhal_source_t trigger_source; //!< Source signal for initiating the DMA transfer
} cyhal_dma_cfg_t;
/** Handler for DMA interrupts */
typedef void (*cyhal_dma_irq_handler_t)(void *handler_arg, cyhal_dma_irq_event_t event);
/** \} group_hal_dma_data_structures */
/**
* \addtogroup group_hal_dma_functions
* \{
*/
/** Initialize the DMA peripheral
*
* @param[out] obj The DMA object to initialize
* @param[in] priority The priority of this DMA operation relative to others
* @param[in] direction The direction memory is copied
* @return The status of the init request
*/
cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction);
/** Release the DMA object
*
* @param[in,out] obj The DMA object
*/
void cyhal_dma_free(cyhal_dma_t *obj);
/** Setup a DMA descriptor for specified resource
*
* @param[in] obj The DMA object
* @param[in] cfg Configuration prameters for the transfer
* @return The status of the setup_transfer request
*/
cy_rslt_t cyhal_dma_setup_transfer(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg);
/** Start DMA transfer
*
* Kick starts transfer in DMA channel with specified channel id
* @param[in] obj The DMA object
* @return The status of the start_transfer request
*/
cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj);
/** DMA channel busy check
*
* To check whether DMA channel is busy with a job or not
* @param[in] obj The DMA object
* @return Is the DMA object being used
*/
bool cyhal_dma_busy(cyhal_dma_t *obj);
/** The DMA interrupt handler registration
*
* @param[in] obj The DMA object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_dma_register_irq(cyhal_dma_t *obj, cyhal_dma_irq_handler_t handler, void *handler_arg);
/** Configure DMA interrupt enablement.
*
* @param[in] obj The DMA object
* @param[in] event The DMA IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_dma_irq_enable(cyhal_dma_t *obj, cyhal_dma_irq_event_t event, bool enable);
/** \} group_hal_dma_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_dma */

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/***************************************************************************//**
* \file cyhal_flash.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Flash memory.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_flash Flash
* \ingroup group_hal
* \{
* Flash HAL high-level description
*
* \defgroup group_hal_flash_macros Macros
* \defgroup group_hal_flash_functions Functions
* \defgroup group_hal_flash_data_structures Data Structures
* \defgroup group_hal_flash_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_flash_macros
* \{
*/
/** Invalid argument */
#define CYHAL_FLASH_RSLT_ERR_ADDRESS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_FLASH, 0))
/** \} group_hal_flash_macros */
/**
* \addtogroup group_hal_flash_data_structures
* \{
*/
/** Information about a flash memory */
typedef struct
{
uint32_t start_address; //!< Start address of the memory
uint32_t size; //!< Size of the flash memory
uint32_t sector_size; //!< Sector size of the memory
uint32_t page_size; //!< Sector size of the memory
uint8_t erase_value; //!< The flash erase value
} cyhal_flash_info_t;
/** \} group_hal_flash_data_structures */
/*******************************************************************************
* Functions
*******************************************************************************/
/**
* \addtogroup group_hal_flash_functions
* \{
*/
/** Initialize the flash peripheral and the flash_t object
*
* @param[out] obj The flash object
* @return The status of the init request
*/
cy_rslt_t cyhal_flash_init(cyhal_flash_t *obj);
/** Uninitialize the flash peripheral and the flash_t object
*
* @param[out] obj The flash object.
*/
void cyhal_flash_free(cyhal_flash_t *obj);
/** Gets key flash charactoristics including the start address size,
* and erase values
*
* @param[in] obj The flash object.
* @param[out] info The flash configuration info.
*/
void cyhal_flash_get_info(const cyhal_flash_t *obj, cyhal_flash_info_t *info);
/** Read data starting at defined address
*
* @param[in] obj The flash object.
* @param[in] address Address to begin reading from.
* @param[out] data The buffer to read data into.
* @param[in] size The number of bytes to read.
* @return The status of the read request.
*/
cy_rslt_t cyhal_flash_read(cyhal_flash_t *obj, uint32_t address, uint8_t *data, size_t size);
/** Erase one page starting at defined address. The address must be at page boundary. This
* will block until the erase operation is complete.
*
* @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and
* the total erase size.
*
* @param[in] obj The flash object
* @param[in] address The page starting address
* @return The status of the erase request
*/
cy_rslt_t cyhal_flash_erase(cyhal_flash_t *obj, uint32_t address);
/** Write one page starting at defined address. The address must be at page boundary. This
* will block until the write operation is complete.
*
* @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and
* the total write size. The provided data buffer must be at least as large as the flash
* page_size.
*
* @param[in] obj The flash object
* @param[in] address The page starting address
* @param[in] data The data to write to the flash
* @return The status of the write request
*/
cy_rslt_t cyhal_flash_write(cyhal_flash_t *obj, uint32_t address, const uint32_t *data);
/** Program one page starting at defined address. The address must be at page boundary. This
* will block until the write operation is complete.
*
* @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and
* the total program size. The provided data buffer must be at least as large as the flash
* page_size.
*
* @param[in] obj The flash object
* @param[in] address The sector starting address
* @param[in] data The data buffer to be programmed
* @return The status of the program request
*/
cy_rslt_t cyhal_flash_program(cyhal_flash_t *obj, uint32_t address, const uint32_t *data);
/** Starts an asynchronous erase of a single page of flash. Returns immediately and reports
* a successful start or reason for failure.
*
* @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and
* the total erase size.
*
* @param[in] obj The Flash object being operated on
* @param[in] address The address to start erasing from
* @return The status of the start_erase request
*/
cy_rslt_t cyhal_flash_start_erase(cyhal_flash_t *obj, uint32_t address);
/** Starts an asynchronous write to a single page of flash. Returns immediately and reports
* a successful start or reason for failure.
*
* @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and
* the total write size. The provided data buffer must be at least as large as the flash
* page_size.
*
* @param[in] obj The Flash object being operated on
* @param[in] address The address to start writing to
* @param[in] data The data to write to flash
* @return The status of the start_write request
*/
cy_rslt_t cyhal_flash_start_write(cyhal_flash_t *obj, uint32_t address, const uint32_t* data);
/** Starts asynchronous programming of a single page of flash. Returns immediately and reports
* a successful start or reason for failure.
*
* @see cyhal_flash_get_info() to get the flash charactoristics for legal address values and
* the total program size. The provided data buffer must be at least as large as the flash
* page_size.
*
* @param[in] obj The Flash object being operated on
* @param[in] address The address to start programming
* @param[in] data The data to write to flash
* @return The status of the start_program request
*/
cy_rslt_t cyhal_flash_start_program(cyhal_flash_t *obj, uint32_t address, const uint32_t* data);
/** Reports a successful operation result, reason of failure or busy status
*
* @param[in] obj The Flash object being operated on
* @return Whether the flash operation is complete
*/
bool cyhal_flash_is_operation_complete(cyhal_flash_t *obj);
/** \} group_hal_flash_functions */
/** \} group_hal_flash_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_flash */

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/***************************************************************************//**
* \file cyhal_gpio.h
*
* \brief
* Provides a high level interface for interacting with the Cypress GPIO.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_gpio GPIO (General Purpose Input Output)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress GPIO.
*
* \defgroup group_hal_gpio_macros Macros
* \defgroup group_hal_gpio_functions Functions
* \defgroup group_hal_gpio_data_structures Data Structures
* \defgroup group_hal_gpio_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* Defines
*******************************************************************************/
/**
* \addtogroup group_hal_gpio_macros
* \{
*/
/** Integer representation of no connect pin (required to exist in all BSPs) */
#define CYHAL_NC_PIN_VALUE ((cyhal_gpio_t)0xFFFFFFFF)
/** \} group_hal_gpio_macros */
/**
* \addtogroup group_hal_gpio_enums
* \{
*/
/*******************************************************************************
* Enumerations
*******************************************************************************/
/** Pin IRQ events */
typedef enum {
CYHAL_GPIO_IRQ_NONE = 0, /**< No interrupt */
CYHAL_GPIO_IRQ_RISE = 1, /**< Interrupt on rising edge */
CYHAL_GPIO_IRQ_FALL = 2, /**< Interrupt on falling edge */
CYHAL_GPIO_IRQ_BOTH = 3, /**< Interrupt on both rising and falling edges */
} cyhal_gpio_irq_event_t;
/** Pin direction */
typedef enum {
CYHAL_GPIO_DIR_INPUT = 0, /**< Input pin */
CYHAL_GPIO_DIR_OUTPUT = 1, /**< Output pin */
CYHAL_GPIO_DIR_BIDIRECTIONAL = 2, /**< Input and output pin */
} cyhal_gpio_direction_t;
/** Pin drive mode */
typedef enum {
CYHAL_GPIO_DRIVE_ANALOG = 0, /**< Analog Hi-Z */
CYHAL_GPIO_DRIVE_PULLUP = 2, /**< Pull-up resistor */
CYHAL_GPIO_DRIVE_PULLDOWN = 3, /**< Pull-down resistor */
CYHAL_GPIO_DRIVE_OPENDRAINDRIVESLOW = 4, /**< Open-drain, Drives Low */
CYHAL_GPIO_DRIVE_OPENDRAINDRIVESHIGH = 5, /**< Open-drain, Drives High */
CYHAL_GPIO_DRIVE_STRONG = 6, /**< Strong output */
CYHAL_GPIO_DRIVE_PULLUPDOWN = 7, /**< Pull-up and pull-down resistors */
} cyhal_gpio_drive_mode_t;
/** \} group_hal_gpio_enums */
/**
* \addtogroup group_hal_gpio_data_structures
* \{
*/
/** GPIO callback function type */
typedef void (*cyhal_gpio_irq_handler_t)(void *handler_arg, cyhal_gpio_irq_event_t event);
/** \} group_hal_gpio_data_structures */
/**
* \addtogroup group_hal_gpio_functions
* \{
*/
/*******************************************************************************
* Functions
*******************************************************************************/
/** Initialize the GPIO pin
*
* @param[in] pin The GPIO pin to initialize
* @param[in] direction The pin direction (input/output)
* @param[in] drvMode The pin drive mode
* @param[in] initVal Initial value on the pin
*
* @return The status of the init request
*/
cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal);
/** Uninitialize the gpio peripheral and the cyhal_gpio_t object
*
* @param[in] pin Pin number
*/
void cyhal_gpio_free(cyhal_gpio_t pin);
/** Set the pin direction
*
* @param[in] pin The pin number
* @param[in] direction The pin direction to be set
* @return The status of the dir request
*/
cy_rslt_t cyhal_gpio_direction(cyhal_gpio_t pin, cyhal_gpio_direction_t direction);
/** Set the input pin mode
*
* @param[in] pin The GPIO object
* @param[in] drvMode The pin mode to be set
*
* @return The status of the mode request
*/
cy_rslt_t cyhal_gpio_drivemode(cyhal_gpio_t pin, cyhal_gpio_drive_mode_t drvMode);
/** Set the output value for the pin. This only works for output & in_out pins.
*
* @param[in] pin The GPIO object
* @param[in] value The value to be set (high = true, low = false)
*/
void cyhal_gpio_write(cyhal_gpio_t pin, bool value);
/** Read the input value. This only works for input & in_out pins.
*
* @param[in] pin The GPIO object
* @return The value of the IO (true = high, false = low)
*/
bool cyhal_gpio_read(cyhal_gpio_t pin);
/** Toggle the output value
*
* @param[in] pin The GPIO object
*/
void cyhal_gpio_toggle(cyhal_gpio_t pin);
/** Register/clear an interrupt handler for the pin toggle pin IRQ event
*
* @param[in] pin The pin number
* @param[in] intrPriority The NVIC interrupt channel priority
* @param[in] handler The function to call when the specified event happens
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_gpio_register_irq(cyhal_gpio_t pin, uint8_t intrPriority, cyhal_gpio_irq_handler_t handler, void *handler_arg);
/** Enable or Disable the GPIO IRQ
*
* @param[in] pin The GPIO object
* @param[in] event The GPIO IRQ event
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_gpio_irq_enable(cyhal_gpio_t pin, cyhal_gpio_irq_event_t event, bool enable);
/** \} group_hal_gpio_functions */
#ifdef __cplusplus
}
#endif /* __cplusplus */
/** \} group_hal_gpio */

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/***************************************************************************//**
* \file cyhal_gpio_impl.h
*
* Description:
* Provides a high level interface for interacting with the Cypress GPIO. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cy_gpio.h"
#include "cyhal_gpio.h"
#include "cyhal_utils.h"
#include "cy_utils.h"
#ifdef CY_IP_MXS40IOSS
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* Defines
*******************************************************************************/
#define CYHAL_GET_PORTADDR(pin) (Cy_GPIO_PortToAddr(CYHAL_GET_PORT(pin))) /**< Macro to get the port address from pin */
/*******************************************************************************
* Functions
*******************************************************************************/
__STATIC_INLINE void cyhal_gpio_write_internal(cyhal_gpio_t pin, bool value)
{
Cy_GPIO_Write(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), value);
}
#define cyhal_gpio_write(pin, value) cyhal_gpio_write_internal(pin, value)
__STATIC_INLINE bool cyhal_gpio_read_internal(cyhal_gpio_t pin)
{
return 0 != Cy_GPIO_Read(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin));
}
#define cyhal_gpio_read(pin) cyhal_gpio_read_internal(pin)
__STATIC_INLINE void cyhal_gpio_toggle_internal(cyhal_gpio_t pin)
{
Cy_GPIO_Inv(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin));
}
#define cyhal_gpio_toggle(pin) cyhal_gpio_toggle_internal(pin)
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* CY_IP_MXS40IOSS */

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/***************************************************************************//**
* \file cyhal_hw_resources.h
*
* \brief
* Provides a struct definitions for configuration resources in the PDL.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_hw_resources PSoC 6 Hardware Resources
* \ingroup group_hal_psoc6
* \{
* Struct definitions for configuration resources in the PDL.
*
* \defgroup group_hal_hw_resources_macros Macros
* \defgroup group_hal_hw_resources_functions Functions
* \defgroup group_hal_hw_resources_data_structures Data Structures
* \defgroup group_hal_hw_resources_enums Enumerated Types
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup group_hal_hw_resources_enums
* \{
*/
/* NOTE: Any changes made to this enum must also be made to the hardware manager resource tracking */
/** Resource types that the hardware manager supports */
typedef enum
{
CYHAL_RSC_ADC, /*!< Analog to digital converter */
CYHAL_RSC_BLESS, /*!< Bluetooth communications block */
CYHAL_RSC_CAN, /*!< CAN communication block */
CYHAL_RSC_CLKPATH, /*!< System clock clock path, used to drive hfclks */
CYHAL_RSC_CLOCK, /*!< Clock divider */
CYHAL_RSC_CRC, /*!< CRC hardware accelerator */
CYHAL_RSC_DAC, /*!< Digital to analog converter */
CYHAL_RSC_DMA, /*!< DMA controller */
CYHAL_RSC_GPIO, /*!< General purpose I/O pin */
CYHAL_RSC_I2S, /*!< I2S communications block */
CYHAL_RSC_LCD, /*!< Segment LCD controller */
CYHAL_RSC_LPCOMP, /*!< Low power comparator */
CYHAL_RSC_LPTIMER, /*!< Low power timer */
CYHAL_RSC_OPAMP, /*!< Opamp */
CYHAL_RSC_PDM, /*!< PCM/PDM communications block */
CYHAL_RSC_SMIF, /*!< Quad-SPI communications block */
CYHAL_RSC_TRNG, /*!< Hardware random number generator */
CYHAL_RSC_RTC, /*!< Real time clock */
CYHAL_RSC_SCB, /*!< Serial Communications Block */
CYHAL_RSC_SDHC, /*!< SD Host Controller */
CYHAL_RSC_TCPWM, /*!< Timer/Counter/PWM block */
CYHAL_RSC_UDB, /*!< UDB Array */
CYHAL_RSC_USB, /*!< USB communication block */
CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */
} cyhal_resource_t;
/** \} group_hal_hw_resources_enums */
/**
* \addtogroup group_hal_hw_resources_data_structures
* \{
*/
/** Represents a particular instance of a resource on the chip */
typedef struct
{
cyhal_resource_t type; //!< The resource block type
uint8_t block_num; //!< The resource block index
/**
* The channel number, if the resource type defines multiple channels
* per block instance. Otherwise, 0 */
uint8_t channel_num;
} cyhal_resource_inst_t;
/** \} group_hal_hw_resources_data_structures */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_hw_resources */

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/***************************************************************************//**
* \file cyhal_hw_types.h
*
* \brief
* Provides a struct definitions for configuration resources in the PDL.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_hw_types PSoC 6 Hardware Types
* \ingroup group_hal_psoc6
* \{
* Struct definitions for configuration resources in the PDL.
*
* \defgroup group_hal_hw_types_macros Macros
* \defgroup group_hal_hw_types_functions Functions
* \defgroup group_hal_hw_types_data_structures Data Structures
* \defgroup group_hal_hw_types_enums Enumerated Types
*/
#pragma once
#include "cy_pdl.h"
#include "cyhal_hw_resources.h"
#include "cyhal_pin_package.h"
#include <stdbool.h>
#if defined(CYHAL_UDB_SDIO)
#include "SDIO_HOST.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup group_hal_hw_types_data_structures
* \{
*/
typedef uint32_t cyhal_source_t; //!< Routable signal source
typedef uint32_t cyhal_dest_t; //!< Routable signal destination
/** Available clock divider types */
typedef cy_en_divider_types_t cyhal_clock_divider_types_t;
/** Clock divider object */
typedef struct {
cyhal_clock_divider_types_t div_type;
uint8_t div_num;
} cyhal_clock_divider_t;
/** ADC object */
typedef struct {
#ifdef CY_IP_MXS40PASS_SAR
SAR_Type* base;
cyhal_resource_inst_t resource;
cyhal_clock_divider_t clock;
bool dedicated_clock;
// channel_used is a bit field. The maximum channel count
// supported by the SAR IP is 16
uint16_t channel_used;
#else
void *empty;
#endif
} cyhal_adc_t;
/** ADC channel object */
typedef struct {
#ifdef CY_IP_MXS40PASS_SAR
cyhal_adc_t* adc;
cyhal_gpio_t pin;
uint8_t channel_idx;
#else
void *empty;
#endif
} cyhal_adc_channel_t;
/** Comparator object */
typedef struct {
#if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(PASS_NR_CTBS)
/* TODO: define */
void * TODO_define;
#else
void *empty;
#endif
} cyhal_comp_t;
/** CRC object */
typedef struct {
#if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT)
CRYPTO_Type* base;
cyhal_resource_inst_t resource;
uint32_t crc_width;
#endif
} cyhal_crc_t;
/** DAC object */
typedef struct {
#ifdef CY_IP_MXS40PASS_CTDAC
CTDAC_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin;
#else
void *empty;
#endif
} cyhal_dac_t;
/** DMA object */
typedef struct {
#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES)
cyhal_resource_inst_t resource;
#else
void *empty;
#endif
} cyhal_dma_t;
/** Flash object */
typedef struct {
void *empty;
} cyhal_flash_t;
/** I2C object */
typedef struct {
#ifdef CY_IP_MXSCB
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_sda;
cyhal_gpio_t pin_scl;
cyhal_clock_divider_t clock;
bool is_shared_clock;
cy_stc_scb_i2c_context_t context;
cy_stc_scb_i2c_master_xfer_config_t rx_config;
cy_stc_scb_i2c_master_xfer_config_t tx_config;
bool is_slave;
bool async;
uint32_t address;
uint32_t irq_cause;
uint16_t pending;
uint16_t events;
uint32_t handler;
#else
void *empty;
#endif
} cyhal_i2c_t;
/** I2S object */
typedef struct {
#ifdef CY_IP_MXAUDIOSS_INSTANCES
/* TODO: define */
void * TODO_define;
#else
void *empty;
#endif
} cyhal_i2s_t;
/** LPTIMER object */
typedef struct {
#ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES
MCWDT_STRUCT_Type *base;
cyhal_resource_inst_t resource;
#else
void *empty;
#endif
} cyhal_lptimer_t;
/** OpAmp object */
typedef struct {
#ifdef PASS_NR_CTBS
/* TODO: define */
void * TODO_define;
#else
void *empty;
#endif
} cyhal_opamp_t;
/** PDM-PCM object */
typedef struct {
#ifdef CY_IP_MXAUDIOSS_INSTANCES
/* TODO: define */
void * TODO_define;
#else
void *empty;
#endif
} cyhal_pdm_pcm_t;
/** PWM object */
typedef struct {
#ifdef CY_IP_MXTCPWM
TCPWM_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin;
cyhal_clock_divider_t clock;
uint32_t clock_hz;
bool dedicated_clock;
#else
void *empty;
#endif
} cyhal_pwm_t;
/** SMIF object */
typedef struct {
#ifdef CY_IP_MXSMIF
SMIF_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_io0;
cyhal_gpio_t pin_io1;
cyhal_gpio_t pin_io2;
cyhal_gpio_t pin_io3;
cyhal_gpio_t pin_io4;
cyhal_gpio_t pin_io5;
cyhal_gpio_t pin_io6;
cyhal_gpio_t pin_io7;
cyhal_gpio_t pin_sclk;
cyhal_gpio_t pin_ssel;
uint32_t frequency;
uint8_t mode;
cy_stc_smif_context_t context;
cy_en_smif_slave_select_t slave_select;
cy_en_smif_data_select_t data_select;
uint32_t irq_cause;
#else
void *empty;
#endif /* ifdef CY_IP_MXSMIF */
} cyhal_qspi_t;
/** RNG object */
typedef struct {
#if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT)
CRYPTO_Type* base;
cyhal_resource_inst_t resource;
#endif
} cyhal_trng_t;
/** RTC object */
typedef struct {
uint8_t placeholder;
} cyhal_rtc_t;
/** SDHC object */
typedef struct {
#ifdef CY_IP_MXSDHC
SDHC_Type* base;
cyhal_resource_inst_t resource;
bool emmc;
cy_en_sd_host_dma_type_t dmaType;
bool enableLedControl;
cy_stc_sd_host_context_t context;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data0;
cyhal_gpio_t pin_data1;
cyhal_gpio_t pin_data2;
cyhal_gpio_t pin_data3;
cyhal_gpio_t pin_data4;
cyhal_gpio_t pin_data5;
cyhal_gpio_t pin_data6;
cyhal_gpio_t pin_data7;
cyhal_gpio_t pin_cardDetect;
cyhal_gpio_t pin_ioVoltSel;
cyhal_gpio_t pin_cardIfPwrEn;
cyhal_gpio_t pin_cardMechWriteProt;
cyhal_gpio_t pin_ledCtrl;
cyhal_gpio_t pin_cardEmmcReset;
#else
void *empty;
#endif
} cyhal_sdhc_t;
/** SDIO object */
typedef struct {
#if defined(CY_IP_MXSDHC)
SDHC_Type* base;
cyhal_resource_inst_t resource;
bool emmc;
cy_en_sd_host_dma_type_t dmaType;
cy_stc_sd_host_context_t context;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data0;
cyhal_gpio_t pin_data1;
cyhal_gpio_t pin_data2;
cyhal_gpio_t pin_data3;
uint32_t frequencyhal_hz;
uint16_t block_size;
uint32_t irq_cause;
#elif defined(CYHAL_UDB_SDIO)
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_clk;
cyhal_gpio_t pin_cmd;
cyhal_gpio_t pin_data0;
cyhal_gpio_t pin_data1;
cyhal_gpio_t pin_data2;
cyhal_gpio_t pin_data3;
cyhal_clock_divider_t clock;
cyhal_dma_t dma0Ch0;
cyhal_dma_t dma0Ch1;
cyhal_dma_t dma1Ch1;
cyhal_dma_t dma1Ch3;
uint32_t frequencyhal_hz;
uint16_t block_size;
stc_sdio_irq_cb_t* pfuCb;
uint32_t irq_cause;
#else
void *empty;
#endif /* defined(CY_IP_MXSDHC) */
} cyhal_sdio_t;
/** SPI object */
typedef struct {
#ifdef CY_IP_MXSCB
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_miso;
cyhal_gpio_t pin_mosi;
cyhal_gpio_t pin_sclk;
cyhal_gpio_t pin_ssel;
cyhal_clock_divider_t clock;
cy_en_scb_spi_sclk_mode_t clk_mode;
uint8_t mode;
uint8_t data_bits;
bool is_slave;
bool alloc_clock;
uint8_t oversample_value;
bool msb_first;
cy_stc_scb_spi_context_t context;
uint32_t irq_cause;
uint16_t pending;
void *rx_buffer;
uint32_t rx_buffer_size;
void *tx_buffer;
uint32_t tx_buffer_size;
bool is_async;
#else
void *empty;
#endif
} cyhal_spi_t;
/** Callbacks for Sleep and Deepsleep APIs */
#define cyhal_system_call_back_t cy_stc_syspm_callback_t
/** Enum for clock type to configure. HFCLKs are configured using different APIs and does not using this enum */
typedef enum
{
CYHAL_SYSTEM_CLOCK_CM4,
CYHAL_SYSTEM_CLOCK_CM0,
CYHAL_SYSTEM_CLOCK_PERI,
} cyhal_system_clock_t;
/** Divider for CM4, CM0 and Peri clock. Supports values between [1, 256] */
typedef uint16_t cyhal_system_divider_t;
/** Timer object */
typedef struct {
#ifdef CY_IP_MXTCPWM
TCPWM_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin;
cyhal_clock_divider_t clock;
uint32_t clock_hz;
uint8_t direction;
bool is_continuous;
bool is_compare;
#else
void *empty;
#endif
} cyhal_timer_t;
/** UART object */
typedef struct {
#ifdef CY_IP_MXSCB
CySCB_Type* base;
cyhal_resource_inst_t resource;
cyhal_gpio_t pin_rx;
cyhal_gpio_t pin_tx;
cyhal_gpio_t pin_cts;
cyhal_gpio_t pin_rts;
bool is_user_clock;
cyhal_clock_divider_t clock;
cy_stc_scb_uart_context_t context;
cy_stc_scb_uart_config_t config;
uint32_t irq_cause;
cy_stc_syspm_callback_params_t pm_params;
cy_stc_syspm_callback_t pm_callback;
en_hsiom_sel_t saved_tx_hsiom;
en_hsiom_sel_t saved_rts_hsiom;
#else
void *empty;
#endif
} cyhal_uart_t;
/** USB Device object */
typedef struct {
#ifdef CY_IP_MXUSBFS
USBFS_Type* base;
cy_stc_usbfs_dev_drv_context_t context;
cyhal_resource_inst_t resource;
cyhal_resource_inst_t pll_resource;
cyhal_clock_divider_t clock;
bool shared_clock;
cyhal_gpio_t pin_dp;
cyhal_gpio_t pin_dm;
uint8_t *rd_data[CY_USBFS_DEV_DRV_NUM_EPS_MAX];
uint32_t rd_size[CY_USBFS_DEV_DRV_NUM_EPS_MAX];
#else
void *empty;
#endif
} cyhal_usb_dev_t;
/** \} group_hal_hw_types_data_structures */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_hw_types */

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/***************************************************************************//**
* \file cyhal_hwmgr.h
*
* \brief
* Provides a high level interface for managing hardware resources. This is
* used to track what hardware blocks are already being used so they are not over
* allocated.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_hwmgr HWMGR (Hardware Manager)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress Hardware Manager.
*
* \defgroup group_hal_hwmgr_macros Macros
* \defgroup group_hal_hwmgr_functions Functions
* \defgroup group_hal_hwmgr_data_structures Data Structures
* \defgroup group_hal_hwmgr_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_hwmgr_enums
* \{
*/
/** Enum to in indicate which module an errors occurred in. */
enum cyhal_rslt_module_chip
{
CYHAL_RSLT_MODULE_CHIP_HWMGR = CY_RSLT_MODULE_ABSTRACTION_HAL_BASE, //!< An error occurred in hardware management module
CYHAL_RSLT_MODULE_ADC, //!< An error occurred in ADC module
CYHAL_RSLT_MODULE_COMP, //!< An error occurred in comparator module
CYHAL_RSLT_MODULE_CRC, //!< An error occurred in crypto CRC module
CYHAL_RSLT_MODULE_DAC, //!< An error occurred in DAC module
CYHAL_RSLT_MODULE_DMA, //!< An error occurred in DMA module
CYHAL_RSLT_MODULE_FLASH, //!< An error occurred in flash module
CYHAL_RSLT_MODULE_GPIO, //!< An error occurred in GPIO module
CYHAL_RSLT_MODULE_I2C, //!< An error occurred in I2C module
CYHAL_RSLT_MODULE_I2S, //!< An error occurred in I2S module
CYHAL_RSLT_MODULE_INTERCONNECT, //!< An error occurred in Interconnct module
CYHAL_RSLT_MODULE_OPAMP, //!< An error occurred in OpAmp module
CYHAL_RSLT_MODULE_PDMPCM, //!< An error occurred in PDM/PCM module
CYHAL_RSLT_MODULE_PWM, //!< An error occurred in PWM module
CYHAL_RSLT_MODULE_QSPI, //!< An error occurred in QSPI module
CYHAL_RSLT_MODULE_RTC, //!< An error occurred in RTC module
CYHAL_RSLT_MODULE_SDHC, //!< An error occurred in SDHC module
CYHAL_RSLT_MODULE_SDIO, //!< An error occurred in SDIO module
CYHAL_RSLT_MODULE_SPI, //!< An error occurred in SPI module
CYHAL_RSLT_MODULE_SYSTEM, //!< An error occurred in System module
CYHAL_RSLT_MODULE_TIMER, //!< An error occurred in Timer module
CYHAL_RSLT_MODULE_TRNG, //!< An error occurred in RNG module
CYHAL_RSLT_MODULE_UART, //!< An error occurred in UART module
CYHAL_RSLT_MODULE_USB, //!< An error occurred in USB module
CYHAL_RSLT_MODULE_WDT, //!< An error occurred in WDT module
};
/** \} group_hal_hwmgr_enums */
/**
* \addtogroup group_hal_hwmgr_macros
* \{
*/
/** The requested resource type is invalid */
#define CYHAL_HWMGR_RSLT_ERR_INVALID (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_CHIP_HWMGR, 0))
/** The requested resource is already in use */
#define CYHAL_HWMGR_RSLT_ERR_INUSE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_CHIP_HWMGR, 1))
/** No resources of the requested type are available */
#define CYHAL_HWMGR_RSLT_ERR_NONE_FREE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_CHIP_HWMGR, 2))
/** Attempt to free a resource that was not used */
#define CYHAL_HWMGR_RSLT_WARN_UNUSED (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_CHIP_HWMGR, 50))
/** \} group_hal_hwmgr_macros */
/**
* \addtogroup group_hal_hwmgr_functions
* \{
*/
/** Initializes the hardware manager to keep track of what resources are being used.
*
* @return The status of the init request
*/
cy_rslt_t cyhal_hwmgr_init();
/** Reserve the specified resource.
*
* @param[in] obj The resource object that should be reserved
* @return The status of the reserve request
*/
cy_rslt_t cyhal_hwmgr_reserve(const cyhal_resource_inst_t* obj);
/** Free the specified resource to allow it to be used by something else.
*
* @param[in,out] obj The resource object to free
*/
void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj);
/** Reserve the specified resource.
*
* @param[in] type The type of resource that should be reserved
* @param[out] obj The resource object that was be reserved
* @return The status of the allocate request
*/
cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj);
/** Allocates a free block of the specified type if available
*
* @param[in] type The type of resource to allocate
* @param[out] obj The resource object to free
* @return The status of the allocate request
*/
cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj);
/** Allocate (pick and reserve) an DMA resource and provide a reference to it.
*
* @param[out] obj The resource object that was allocated
* @return The status of the reserve request
*/
cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj);
/** Allocate (pick and reserve) an Clock Divider resource and provide a reference to it.
*
* @param[out] obj The resource object that was allocated
* @param[in] div The type of divider to allocate
* @param[in] accept_larger Whether a larger type can be provided if there are none of the requested size available
* @return The status of the reserve request
*/
cy_rslt_t cyhal_hwmgr_allocate_clock(cyhal_clock_divider_t* obj, cyhal_clock_divider_types_t div, bool accept_larger);
/** Free the specified Clock Divider resource and allow it be used by something else.
*
* @param[in] obj The resource object that was allocated
*/
void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj);
/** Marks the specified resource as having already been configured (eg: it doesn't need to be configured again).
*
* @param[in] type The type of hardware block to reserve
* @param[in] block The block number of to reserve
* @param[in] channel The block's channel instance number to reserve (0 if there are no channels in the block)
* @return The status of the set request
*/
cy_rslt_t cyhal_hwmgr_set_configured(cyhal_resource_t type, uint8_t block, uint8_t channel);
/** Marks the specified resource as not having already been configured (eg: it still needs to be configured before being used).
*
* @param[in] type The type of hardware block to reserve
* @param[in] block The block number of to reserve
* @param[in] channel The block's channel instance number to reserve (0 if there are no channels in the block)
* @return The status of the set request
*/
cy_rslt_t cyhal_hwmgr_set_unconfigured(cyhal_resource_t type, uint8_t block, uint8_t channel);
/** Checks to see if the specified resource has already been configured (eg: it doesn't need to be configured again).
*
* @param[in] type The type of hardware block to reserve
* @param[in] block The block number of to reserve
* @param[in] channel The block's channel instance number to reserve (0 if there are no channels in the block)
* @return Whether the block is currently configured
*/
bool cyhal_hwmgr_is_configured(cyhal_resource_t type, uint8_t block, uint8_t channel);
/** \} group_hal_hwmgr_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_hwmgr */

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/***************************************************************************//**
* \file cyhal_i2c.h
*
* \brief
* Provides a high level interface for interacting with the Cypress I2C.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_i2c I2C (Inter-Integrated Circuit)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress I2C.
*
* \defgroup group_hal_i2c_macros Macros
* \defgroup group_hal_i2c_functions Functions
* \defgroup group_hal_i2c_data_structures Data Structures
* \defgroup group_hal_i2c_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_i2c_macros
* \{
*/
/** The requested resource type is invalid */
#define CYHAL_I2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0))
/** Can not reach desired data rate */
#define CYHAL_I2C_RSLT_ERR_CAN_NOT_REACH_DR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0))
/** Address size is not correct, should be 1 or two */
#define CYHAL_I2C_RSLT_ERR_INVALID_ADDRESS_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0))
/** \} group_hal_i2c_macros */
/**
* \addtogroup group_hal_i2c_enums
* \{
*/
/** Enum to enable/disable/report interrupt cause flags. */
typedef enum
{
CYHAL_I2C_IRQ_NONE = 0, //!< Disable all interrupt call backs
CYHAL_I2C_SLAVE_READ_EVENT = 1 << 1, /* Indicates that the slave was addressed and the master wants to read data. */
CYHAL_I2C_SLAVE_WRITE_EVENT = 1 << 2, /* Indicates that the slave was addressed and the master wants to write data. */
CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT = 1 << 3, /* All slave data from the configured Read buffer has been loaded into the TX FIFO. */
CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4, /* The master has read all data out of the configured Read buffer. */
CYHAL_I2C_SLAVE_RD_CMPLT_EVENT = 1 << 5, /* Indicates the master completed reading from the slave (set by the master NAK or Stop) */
CYHAL_I2C_SLAVE_WR_CMPLT_EVENT = 1 << 6, /* Indicates the master completed writing to the slave (set by the master Stop or Restart)*/
CYHAL_I2C_SLAVE_ERR_EVENT = 1 << 7, /* Indicates the I2C hardware detected an error. */
CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT = 1 << 17, /* All data specified by Cy_SCB_I2C_MasterWrite has been loaded into the TX FIFO. */
CYHAL_I2C_MASTER_WR_CMPLT_EVENT = 1 << 18, /* The master write started by Cy_SCB_I2C_MasterWrite is complete.*/
CYHAL_I2C_MASTER_RD_CMPLT_EVENT = 1 << 19, /* The master read started by Cy_SCB_I2C_MasterRead is complete.*/
CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /* Indicates the I2C hardware has detected an error. */
} cyhal_i2c_irq_event_t;
/** \} group_hal_i2c_enums */
/**
* \addtogroup group_hal_i2c_data_structures
* \{
*/
/** Handler for I2C interrupts */
typedef void (*cyhal_i2c_irq_handler_t)(void *handler_arg, cyhal_i2c_irq_event_t event);
/** Initial I2C configuration */
typedef struct
{
bool is_slave; /* I2C mode, is the device a master or slave */
uint16_t address; /* Address of this slave device (7-bit), should be set to 0 for master */
uint32_t frequencyhal_hz; /* Frequency that the I2C bus runs at */
} cyhal_i2c_cfg_t;
/** \} group_hal_i2c_data_structures */
/**
* \addtogroup group_hal_i2c_functions
* \{
*/
/** Initialize the I2C peripheral, and configures its specifieds pins. By default
* it is setup as a Master running at 400kHz. This can be changed by calling
* cyhal_i2c_set_config().
* NOTE: Master/Slave specific functions only work when the block is configured
* to be in that mode.
*
* @param[out] obj The I2C object
* @param[in] sda The sda pin
* @param[in] scl The scl pin
* @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated
* @return The status of the init request
*/
cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk);
/** Deinitialize the i2c object
*
* @param[in,out] obj The i2c object
*/
void cyhal_i2c_free(cyhal_i2c_t *obj);
/** Configure the I2C block
*
* @param[in] obj The I2C object
* @param[in] cfg Configuration settings to apply
* @return The status of the set_config request
*/
cy_rslt_t cyhal_i2c_set_config(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg);
/**
* I2C master send
*
* @param[in] obj The I2C object
* @param[in] dev_addr device address (7-bit)
* @param[in] data i2c send data
* @param[in] size i2c send data size
* @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever
*
* @return The status of the master_send request
*/
cy_rslt_t cyhal_i2c_master_send(cyhal_i2c_t *obj, uint16_t dev_addr, const uint8_t *data, uint16_t size, uint32_t timeout);
/**
* I2C master recv
*
* @param[in] obj The I2C object
* @param[in] dev_addr device address (7-bit)
* @param[out] data i2c receive data
* @param[in] size i2c receive data size
* @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever
*
* @return The status of the master_recv request
*/
cy_rslt_t cyhal_i2c_master_recv(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout);
/**
* I2C slave send
* The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
*
* @param[in] obj The I2C object
* @param[in] data i2c slave send data
* @param[in] size i2c slave send data size
* @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever
*
* @return The status of the slave_send request
*/
cy_rslt_t cyhal_i2c_slave_send(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size, uint32_t timeout);
/**
* I2C slave receive
* The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
*
* @param[in] obj The I2C object
* @param[out] data i2c slave receive data
* @param[in] size i2c slave receive data size
* @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever
*
* @return The status of the slave_recv request
*/
cy_rslt_t cyhal_i2c_slave_recv(cyhal_i2c_t *obj, uint8_t *data, uint16_t size, uint32_t timeout);
/** Perform an i2c write using a block of data stored at the specified memory location
*
* @param[in] obj The I2C object
* @param[in] address device address (7-bit)
* @param[in] mem_addr mem address to store the written data
* @param[in] mem_addr_size number of bytes in the mem address
* @param[in] data i2c master send data
* @param[in] size i2c master send data size
* @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever
* @return The status of the write request
*/
cy_rslt_t cyhal_i2c_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout);
/** Perform an i2c read using a block of data stored at the specified memory location
*
* @param[in] obj The I2C object
* @param[in] address device address (7-bit)
* @param[in] mem_addr mem address to store the written data
* @param[in] mem_addr_size number of bytes in the mem address
* @param[out] data i2c master send data
* @param[in] size i2c master send data size
* @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever
* @return The status of the read request
*/
cy_rslt_t cyhal_i2c_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout);
/** Start I2C asynchronous transfer
*
* @param[in] obj The I2C object
* @param[in] tx The transmit buffer
* @param[in] tx_size The number of bytes to transmit
* @param[out] rx The receive buffer
* @param[in] rx_size The number of bytes to receive
* @param[in] address device address (7-bit)
* @return The status of the transfer_async request
*/
cy_rslt_t cyhal_i2c_transfer_async(cyhal_i2c_t *obj, const void *tx, size_t tx_size, void *rx, size_t rx_size, uint16_t address);
/** Abort asynchronous transfer
*
* This function does not perform any check - that should happen in upper layers.
* @param[in] obj The I2C object
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_i2c_abort_async(cyhal_i2c_t *obj);
/** The I2C interrupt handler registration
*
* @param[in] obj The I2C object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_i2c_register_irq(cyhal_i2c_t *obj, cyhal_i2c_irq_handler_t handler, void *handler_arg);
/** Configure and Enable or Disable I2C Interrupt.
*
* @param[in] obj The I2C object
* @param[in] event The I2C IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_i2c_irq_enable(cyhal_i2c_t *obj, cyhal_i2c_irq_event_t event, bool enable);
/** \} group_hal_i2c_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_i2c */

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/***************************************************************************//**
* \file cyhal_i2s.h
*
* \brief
* Provides a high level interface for interacting with the Cypress I2S.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_i2s I2S (Inter-IC Sound)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress I2S.
*
* \defgroup group_hal_i2s_macros Macros
* \defgroup group_hal_i2s_functions Functions
* \defgroup group_hal_i2s_data_structures Data Structures
* \defgroup group_hal_i2s_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_i2s_enums
* \{
*/
/** I2S interrupt triggers */
typedef enum {
/** TODO: Fill in */
CYHAL_I2S_TBD,
} cyhal_i2s_irq_t;
/** \} group_hal_i2s_enums */
/**
* \addtogroup group_hal_i2s_data_structures
* \{
*/
/** Handler for SPI interrupts */
typedef void (*cyhal_i2s_irq_handler_t)(void *handler_arg, cyhal_i2s_irq_t event);
/** \} group_hal_i2s_data_structures */
/**
* \addtogroup group_hal_i2s_functions
* \{
*/
/** Initialize the I2S peripheral. It sets the default parameters for I2S
* peripheral, and configures its specifieds pins.
*
* @param[out] obj The I2S object
* @param[in] tx_sck The transmit clock pin
* @param[in] tx_ws The transmit word select pin
* @param[in] tx_sdo The data out pin
* @param[in] rx_sck The receive clock pin
* @param[in] rx_ws The receive word select pin
* @param[in] rx_sdi The data in pin
* @return The status of the init request
*/
cy_rslt_t cyhal_i2s_init(cyhal_i2s_t *obj, cyhal_gpio_t tx_sck, cyhal_gpio_t tx_ws, cyhal_gpio_t tx_sdo, cyhal_gpio_t rx_sck, cyhal_gpio_t rx_ws, cyhal_gpio_t rx_sdi);
/** Deinitialize the i2s object
*
* @param[in,out] obj The i2s object
*/
void cyhal_i2s_free(cyhal_i2s_t *obj);
/** Configure the I2S frequency
*
* @param[in] obj The I2S object
* @param[in] hz Frequency in Hz
* @return The status of the frequency request
*/
cy_rslt_t cyhal_i2s_frequency(cyhal_i2s_t *obj, int hz);
/** Configure I2S as slave or master.
* @param[in] obj The I2S object
* @param[in] is_slave Enable hardware as a slave (true) or master (false)
* @return The status of the mode request
*/
cy_rslt_t cyhal_i2s_mode(cyhal_i2s_t *obj, int is_slave);
/** Blocking reading data
*
* @param[in] obj The I2S object
* @param[out] data The buffer for receiving
* @param[in,out] length in - Number of bytes to read, out - number of bytes read
* @return The status of the read request
*/
cy_rslt_t cyhal_i2s_read(cyhal_i2s_t *obj, uint8_t *data, size_t *length);
/** Blocking sending data
*
* @param[in] obj The I2S object
* @param[in] data The buffer for sending
* @param[in] length Number of bytes to write
* @param[in] stop Stop to be generated after the transfer is done
* @return The status of the write request
*/
cy_rslt_t cyhal_i2s_write(cyhal_i2s_t *obj, const uint8_t *data, size_t length, bool stop);
/** Start I2S asynchronous transfer
*
* @param[in] obj The I2S object
* @param[in] tx The transmit buffer
* @param[in,out] tx_length in - The number of bytes to transmit, out - The number of bytes actually transmitted
* @param[out] rx The receive buffer
* @param[in,out] rx_length in - The number of bytes to receive, out - The number of bytes actually received
* @return The status of the transfer_async request
*/
cy_rslt_t cyhal_i2s_transfer_async(cyhal_i2s_t *obj, const void *tx, size_t *tx_length, void *rx, size_t *rx_length);
/** Abort I2S asynchronous transfer
*
* This function does not perform any check - that should happen in upper layers.
* @param[in] obj The I2S object
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_i2s_abort_async(cyhal_i2s_t *obj);
/** The I2S interrupt handler registration
*
* @param[in] obj The I2S object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_i2s_register_irq(cyhal_i2s_t *obj, cyhal_i2s_irq_handler_t handler, void *handler_arg);
/** Configure I2S interrupt. This function is used for word-approach
*
* @param[in] obj The I2S object
* @param[in] event The I2S IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_i2s_irq_enable(cyhal_i2s_t *obj, cyhal_i2s_irq_t event, bool enable);
/** \} group_hal_i2s_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_i2s */

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/***************************************************************************//**
* \file cyhal_implementation.h
*
* \brief
* Provides references for the PSoC 6 specific implementation of the HAL drivers.
* This includes references to implementation specific header files and any
* supporting data types. This file should not be used directly. It should only
* be referenced by HAL drivers to pull in the implementation specific code.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_psoc6 PSoC 6 HAL Implementation
* \{
* PSoC 6 specific implementation of the HAL drivers
* \} group_hal_psoc6
*/
#pragma once
#include "cy_pdl.h"
#include "cyhal.h"
#include "cyhal_hw_types.h"
#include "cyhal_crc_impl.h"
#include "cyhal_gpio_impl.h"
#include "cyhal_scb_common.h"
#include "cyhal_utils.h"
#include "cyhal_system_impl.h"
#include "cyhal_trng_impl.h"

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/***************************************************************************//**
* \file cyhal_interconnect.h
*
* \brief
* Provides a high level interface for interacting with the internal digital
* routing on the chip. This interface abstracts out the chip specific details.
* If any chip specific functionality is necessary, or performance is critical
* the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_interconnect INTERCONNECT (Internal digital routing)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress digital routing.
*
* \defgroup group_hal_interconnect_macros Macros
* \defgroup group_hal_interconnect_functions Functions
* \defgroup group_hal_interconnect_data_structures Data Structures
* \defgroup group_hal_interconnect_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_interconnect_macros
* \{
*/
/** No connection is available */
#define CYHAL_CONNECT_RSLT_NO_CONNECTION (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 0))
/** The connections source and destination are already connected */
#define CYHAL_CONNECT_RSLT_ALREADY_CONNECTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 1))
/** Invalid 1-to-1 trigger connection */
#define CYHAL_CONNECT_RSLT_INVALID_1TO1_CONNECTION (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_INTERCONNECT, 2))
/** \} group_hal_interconnect_macros */
/**
* \addtogroup group_hal_interconnect_functions
* \{
*/
/** Connects two digital terminals. The source will be routed to the destination via the trigger routing
* framework in the device. This supports both the trigger mux routing and the 1:1 triggers. As expected,
* a single source can drive multiple destinations, but a destination can only be driven by a single source.
* If the output is already connected, or the connection can not be established an error will be returned.
* @param[in] source The source of the signal to connect
* @param[in] dest The destination of the signal to connect
* @return The status of the connect request
*/
cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest);
/** Connect a pin to a peripheral terminal. This will route a direct connect from the pin to the peripheral.
* Any previous direct connection from the pin will be overriden.
* @param[in] pin_connection Details about the pin and its target connection
* @return The status of the connect request
*/
cy_rslt_t cyhal_connect_pin(const cyhal_resource_pin_mapping_t *pin_connection);
/** Disconnect a peripheral from a pin. This will also reset the pin's drive mode to High-Z.
* @param[in] pin The pin to disconnect
* @return The status of the disconnect request
*/
cy_rslt_t cyhal_disconnect_pin(cyhal_gpio_t pin);
#if defined(__cplusplus)
}
#endif
/** \} group_hal_interconnect_functions */
/** \} group_hal_interconnect */

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/***************************************************************************//**
* \file cyhal_lptimer.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Low-Power Timer.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_lptimer LPTIMER (Low-Power Timer)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress LPTIMER.
*
* \defgroup group_hal_lptimer_macros Macros
* \defgroup group_hal_lptimer_functions Functions
* \defgroup group_hal_lptimer_data_structures Data Structures
* \defgroup group_hal_lptimer_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_lptimer_enums
* \{
*/
/** LPTIMER interrupt triggers */
typedef enum {
CYHAL_LPTIMER_COMPARE_MATCH,
} cyhal_lptimer_irq_event_t;
/** \} group_hal_lptimer_enums */
/**
* \addtogroup group_hal_lptimer_data_structures
* \{
*/
/** Handler for LPTIMER interrupts */
typedef void (*cyhal_lptimer_irq_handler_t)(void *handler_arg, cyhal_lptimer_irq_event_t event);
/** \} group_hal_lptimer_data_structures */
/**
* \addtogroup group_hal_lptimer_functions
* \{
*/
/** Initialize the LPTIMER
*
* Initialize or re-initialize the LPTIMER. This resets all the
* clocking and prescaler registers, along with disabling
* the compare interrupt. Refer to the BSP for the clock source
* for the LPTIMER.
*
* @param[out] obj The LPTIMER object
* @return The status of the init request
*/
cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj);
/** Deinitialize the LPTIMER
*
* Powers down the LPTIMER.
* After calling this function no other LPTIMER functions should be called except
* cyhal_lptimer_init(). Calling any function other than init after freeing is
* undefined.
*
* @param[inout] obj The LPTIMER object
*/
void cyhal_lptimer_free(cyhal_lptimer_t *obj);
/** Reload/Reset the Low-Power timer.
*
* @param[in] obj The LPTIMER object
* @return The status of the reload request
*/
cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj);
/** Set timeframe between interrupts
*
* Configures the LPTIMER in free-running mode. Generates an interrupt on match.
* This function is for initial configuration. For quick updates to the match
* value, use cyhal_lptimer_set_time().
*
* @param[in] obj The LPTIMER object
* @param[in] time The time in ticks to be set
*
* @return The status of the set_time request
*/
cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time);
/** Update the match/compare value
*
* Quickly update the match value of an already configured LPTIMER set up
* to generate an interrupt on match. Note that this function does not
* reinitialize the counter or the associated peripheral initialization
* sequence.
*
* @param[in] obj The LPTIMER object
* @param[in] value The match value in ticks
*
* @return The status of the set_match request
*/
cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value);
/** Read the current tick
*
* If no rollover has occurred, the seconds passed since cyhal_lptimer_init() or cyhal_lptimer_set_time()
* was called can be found by dividing the ticks returned by this function
* by the frequency of the source clock (refer to the BSP for the clock source).
*
* @param[in] obj The LPTIMER object
* @return The timer's timer value in ticks
*/
uint32_t cyhal_lptimer_read(const cyhal_lptimer_t *obj);
/** The LPTIMER match interrupt handler registration
*
* @param[in] obj The LPTIMER object
* @param[in] handler The callback handler which will be invoked when the interrupt triggers
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_lptimer_register_irq(cyhal_lptimer_t *obj, cyhal_lptimer_irq_handler_t handler, void *handler_arg);
/** Configure and Enable/Disable the LPTIMER interrupt
*
* @param[in] obj The LPTIMER object
* @param[in] event The LPTIMER IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_lptimer_irq_enable(cyhal_lptimer_t *obj, cyhal_lptimer_irq_event_t event, bool enable);
/** Manually trigger the LPTIMER interrupt.
*
* @param[in] obj The LPTIMER object
*/
void cyhal_lptimer_irq_trigger(cyhal_lptimer_t *obj);
/** \} group_hal_lptimer_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_lptimer */

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/***************************************************************************//**
* \file cyhal_opamp.h
*
* \brief
* Provides a high level interface for interacting with the Cypress OpAmp.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_opamp OPAMP (Operational Amplifier)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress OpAmp.
*
* \defgroup group_hal_opamp_macros Macros
* \defgroup group_hal_opamp_functions Functions
* \defgroup group_hal_opamp_data_structures Data Structures
* \defgroup group_hal_opamp_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_opamp_functions
* \{
*/
/** Initialize the opamp peripheral.
* If vinp is NULL, it will initialize in follower mode.
*
* @param[out] obj The opamp object
* @param[in] vinp The vplus pin
* @param[in] vinm The vminus pin
* @param[in] vout The vout pin
* @return The status of the init request
*/
cy_rslt_t cyhal_opamp_init(cyhal_opamp_t *obj, cyhal_gpio_t vinp, cyhal_gpio_t vinm, cyhal_gpio_t vout);
/** Release the opamp peripheral.
*
* @param[in,out] obj The opamp object
*/
void cyhal_opamp_free(cyhal_opamp_t *obj);
/** Reconfigure the opamp object
*
* @param[in,out] obj The opamp object
* @param[in] power Power mode to operate in (0=off, 1=low, 2=medium, 3=high)
* @param[in] deepsleep Does this need to operate in deepsleep
* @return The status of the power request
*/
cy_rslt_t cyhal_opamp_power(cyhal_opamp_t *obj, uint8_t power, bool deepsleep);
/** \} group_hal_opamp_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_opamp */

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/***************************************************************************//**
* \file cyhal_pdmpcm.h
*
* \brief
* Provides a high level interface for interacting with the Cypress PDM/PCM.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_pdmpcm PDM/PCM (PDM-PCM Converter)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress PDM/PCM.
*
* \defgroup group_hal_pdmpcm_macros Macros
* \defgroup group_hal_pdmpcm_functions Functions
* \defgroup group_hal_pdmpcm_data_structures Data Structures
* \defgroup group_hal_pdmpcm_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_pdmpcm_enums
* \{
*/
/** PDM/PCM interrupt triggers */
typedef enum {
/** TODO: Fill in */
CY_PDM_PCM_TBD,
} cyhal_pdm_pcm_irq_event_t;
/** \} group_hal_pdmpcm_enums */
/**
* \addtogroup group_hal_pdmpcm_data_structures
* \{
*/
/** Describes the current configuration of a PDM/PCM */
typedef struct
{
/** TODO: define */
void * cfg;
} cyhal_pdm_pcm_cfg_t;
/** Handler for PDM/PCM interrupts */
typedef void (*cyhal_pdm_pcm_irq_handler_t)(void *handler_arg, cyhal_pdm_pcm_irq_event_t event);
/** \} group_hal_pdmpcm_data_structures */
/**
* \addtogroup group_hal_pdmpcm_functions
* \{
*/
/** Initialize the PDM/PCM peripheral
*
* Configures the pins used by PDM/PCM converter, sets a default format and frequency, and enables the peripheral
* @param[out] obj The PDM/PCM object to initialize
* @param[in] in The pin to use for PDM input
* @param[in] clk The pin to use for PDM clock output
* @return The status of the init request
*/
cy_rslt_t cyhal_pdm_pcm_init(cyhal_pdm_pcm_t *obj, cyhal_gpio_t in, cyhal_gpio_t clk);
/** Release a PDM/PCM object
*
* Return the peripheral, pins and clock owned by the PDM/PCM object to their reset state
* @param[in,out] obj The PDM/PCM object to deinitialize
*/
void cyhal_pdm_pcm_free(cyhal_pdm_pcm_t *obj);
/** Updates the configuration of the PDM/PCM object
*
* @param[inout] obj The PDM/PCM object to configure
* @param[in] cfg The configuration of the PDM/PCM
* @return The status of the format request
*/
cy_rslt_t cyhal_pdm_pcm_config(cyhal_pdm_pcm_t *obj, const cyhal_pdm_pcm_cfg_t *cfg);
/** Clears the FIFO
*
* @param[in] obj The PDM/PCM peripheral to use for sending
* @return The status of the clear request
*/
cy_rslt_t cyhal_pdm_pcm_clear(cyhal_pdm_pcm_t *obj);
/** Reads a block out of the FIFO
*
* @param[in] obj The PDM/PCM peripheral to use for sending
* @param[out] data Pointer to the byte-array of data to read from the device
* @param[in,out] length Number of bytes to read, updated with the number actually read
* @return The status of the read request
*/
cy_rslt_t cyhal_pdm_pcm_read(cyhal_pdm_pcm_t *obj, uint8_t *data, uint32_t *length);
/** Begin the PDM/PCM transfer
*
* @param[in] obj The PDM/PCM object that holds the transfer information
* @param[out] data The receive buffer
* @param[in,out] length Number of bytes to read, updated with the number actually read
* @return The status of the read_async request
*/
cy_rslt_t cyhal_pdm_pcm_read_async(cyhal_pdm_pcm_t *obj, void *data, size_t length);
/** Checks if the specified PDM/PCM peripheral is in use
*
* @param[in] obj The PDM/PCM peripheral to check
* @return Indication of whether the PDM/PCM is still transmitting
*/
bool cyhal_pdm_pcm_is_busy(cyhal_pdm_pcm_t *obj);
/** Abort an PDM/PCM transfer
*
* @param[in] obj The PDM/PCM peripheral to stop
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_pdm_pcm_abort_async(cyhal_pdm_pcm_t *obj);
/** The PDM/PCM interrupt handler registration
*
* @param[in] obj The PDM/PCM object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_pdm_pcm_register_irq(cyhal_pdm_pcm_t *obj, cyhal_pdm_pcm_irq_handler_t handler, void *handler_arg);
/** Configure PDM/PCM interrupt enablement.
*
* @param[in] obj The PDM/PCM object
* @param[in] event The PDM/PCM IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_pdm_pcm_irq_enable(cyhal_pdm_pcm_t *obj, cyhal_pdm_pcm_irq_event_t event, bool enable);
/** \} group_hal_pdmpcm_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_pdmpcm */

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/***************************************************************************//**
* \file cyhal_pin_package.h
*
* Description:
* Provides definitions for the pinout for each supported device.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_pin_package PSoC 6 Pin Packages
* \ingroup group_hal_psoc6
* \{
* Definitions for the pinout for each supported device
*
* \defgroup group_hal_pin_package_macros Macros
* \defgroup group_hal_pin_package_functions Functions
* \defgroup group_hal_pin_package_data_structures Data Structures
* \defgroup group_hal_pin_package_enums Enumerated Types
*/
#pragma once
#include "cy_gpio.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/**
* \addtogroup group_hal_pin_package_enums
* \{
*/
/** Port names */
typedef enum {
CYHAL_PORT_0 = 0x0,
CYHAL_PORT_1 = 0x1,
CYHAL_PORT_2 = 0x2,
CYHAL_PORT_3 = 0x3,
CYHAL_PORT_4 = 0x4,
CYHAL_PORT_5 = 0x5,
CYHAL_PORT_6 = 0x6,
CYHAL_PORT_7 = 0x7,
CYHAL_PORT_8 = 0x8,
CYHAL_PORT_9 = 0x9,
CYHAL_PORT_10 = 0xA,
CYHAL_PORT_11 = 0xB,
CYHAL_PORT_12 = 0xC,
CYHAL_PORT_13 = 0xD,
CYHAL_PORT_14 = 0xE,
CYHAL_PORT_15 = 0xF,
} cyhal_port_t;
/** \} group_hal_pin_package_enums */
/**
* \addtogroup group_hal_pin_package_data_structures
* \{
*/
/** GPIO pin configuration object */
typedef uint16_t cyhal_gpio_cfg_t; // 8bit hsiom, 8bit mode
/** \} group_hal_pin_package_data_structures */
/** \cond INTERNAL */
#define CY_GPIO_CFG_CREATE(hsiom, mode) ((cyhal_gpio_cfg_t)(((hsiom) << 8) + (mode)))
#define CY_GPIO_CFG_GET_MODE(x) ((uint8_t)((x) & 0xFF))
#define CY_GPIO_CFG_GET_HSIOM(x) ((en_hsiom_sel_t)(((x) >> 8) & 0xFF))
#define CYHAL_PIN_OUT_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_STRONG_IN_OFF)
#define CYHAL_PIN_OUT_BUF_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_STRONG)
#define CYHAL_PIN_OD_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_OD_DRIVESLOW_IN_OFF)
#define CYHAL_PIN_IN_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_HIGHZ)
#define CYHAL_PIN_PULLUP_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(hsiom, CY_GPIO_DM_PULLUP)
#define CYHAL_PIN_ANALOG_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(HSIOM_SEL_GPIO, CY_GPIO_DM_ANALOG)
#define CYHAL_PIN_AUX_FUNCTION(hsiom) CY_GPIO_CFG_CREATE(HSIOM_SEL_GPIO, CY_GPIO_DM_ANALOG)
/** \endcond */
#include "cy_device.h"
#if defined(_GPIO_PSOC6_01_104_M_CSP_BLE_H_)
#include "pin_packages/cyhal_psoc6_01_104_m_csp_ble.h"
#elif defined(_GPIO_PSOC6_01_104_M_CSP_BLE_USB_H_)
#include "pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h"
#elif defined(_GPIO_PSOC6_01_116_BGA_BLE_H_)
#include "pin_packages/cyhal_psoc6_01_116_bga_ble.h"
#elif defined(_GPIO_PSOC6_01_116_BGA_USB_H_)
#include "pin_packages/cyhal_psoc6_01_116_bga_usb.h"
#elif defined(_GPIO_PSOC6_01_124_BGA_H_)
#include "pin_packages/cyhal_psoc6_01_124_bga.h"
#elif defined(_GPIO_PSOC6_01_124_BGA_SIP_H_)
#include "pin_packages/cyhal_psoc6_01_124_bga_sip.h"
#elif defined(_GPIO_PSOC6_01_43_SMT_H_)
#include "pin_packages/cyhal_psoc6_01_43_smt.h"
#elif defined(_GPIO_PSOC6_01_68_QFN_BLE_H_)
#include "pin_packages/cyhal_psoc6_01_68_qfn_ble.h"
#elif defined(_GPIO_PSOC6_01_80_WLCSP_H_)
#include "pin_packages/cyhal_psoc6_01_80_wlcsp.h"
#elif defined(_GPIO_PSOC6_02_100_WLCSP_H_)
#include "pin_packages/cyhal_psoc6_02_100_wlcsp.h"
#elif defined(_GPIO_PSOC6_02_124_BGA_H_)
#include "pin_packages/cyhal_psoc6_02_124_bga.h"
#elif defined(_GPIO_PSOC6_02_128_TQFP_H_)
#include "pin_packages/cyhal_psoc6_02_128_tqfp.h"
#elif defined(_GPIO_PSOC6_02_68_QFN_H_)
#include "pin_packages/cyhal_psoc6_02_68_qfn.h"
#elif defined(_GPIO_PSOC6_03_100_TQFP_H_)
#include "pin_packages/cyhal_psoc6_03_100_tqfp.h"
#elif defined(_GPIO_PSOC6_03_49_WLCSP_H_)
#include "pin_packages/cyhal_psoc6_03_49_wlcsp.h"
#elif defined(_GPIO_PSOC6_03_68_QFN_H_)
#include "pin_packages/cyhal_psoc6_03_68_qfn.h"
#else
#error "Unhandled Device/PinPackage combination"
#endif
#if defined(__cplusplus)
}
#endif /* __cplusplus */
/** \} group_hal_adc */

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/***************************************************************************//**
* \file cyhal_pwm.h
*
* \brief
* Provides a high level interface for interacting with the Cypress PWM.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_pwm PWM (Pulse Width Modulator)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress PWM.
*
* \defgroup group_hal_pwm_macros Macros
* \defgroup group_hal_pwm_functions Functions
* \defgroup group_hal_pwm_data_structures Data Structures
* \defgroup group_hal_pwm_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include "cy_result.h"
#include "cyhal_hwmgr.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_pwm_macros
* \{
*/
/** Bad argument */
#define CYHAL_PWM_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 0))
/** Failed to initialize PWM clock */
#define CYHAL_PWM_RSLT_FAILED_CLOCK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 1))
/** Failed to initialize PWM */
#define CYHAL_PWM_RSLT_FAILED_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 2))
/** \} group_hal_pwm_macros */
/**
* \addtogroup group_hal_pwm_functions
* \{
*/
/** Initialize the PWM out peripheral and configure the pin
*
* @param[out] obj The PWM object to initialize
* @param[in] pin The PWM pin to initialize
* @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated
* @return The status of the init request
*/
cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk);
/** Deinitialize the PWM object
*
* @param[in,out] obj The PWM object
*/
void cyhal_pwm_free(cyhal_pwm_t *obj);
/** Set the number of microseconds for the PWM period & pulse width
*
* @param[in] obj The PWM object
* @param[in] period_us The period in microseconds
* @param[in] pulse_width_us The pulse width in microseconds
* @return The status of the period request
*/
cy_rslt_t cyhal_pwm_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us);
/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
*
* @param[in] obj The PWM object
* @param[in] duty_cycle The percentage of time the output is high
* @param[in] frequencyhal_hz The frequency of the PWM
* @return The status of the pulsewidth request
*/
cy_rslt_t cyhal_pwm_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz);
/** Starts the PWM with the provided period and pulsewidth
*
* @param[in] obj The PWM object
* @return The status of the start request
*/
cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj);
/** Stops the PWM from running
*
* @param[in] obj The PWM object
* @return The status of the stop request
*/
cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj);
/** \} group_hal_pwm_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_pwm */

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/***************************************************************************//**
* \file cyhal_qspi.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Quad-SPI.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_qspi QSPI (Quad Serial Peripheral Interface)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress Quad-SPI.
*
* \defgroup group_hal_qspi_macros Macros
* \defgroup group_hal_qspi_functions Functions
* \defgroup group_hal_qspi_data_structures Data Structures
* \defgroup group_hal_qspi_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_qspi_enums
* \{
*/
/** QSPI Bus width
*
* Some parts of commands provide variable bus width
*/
typedef enum cyhal_qspi_bus_width {
CYHAL_QSPI_CFG_BUS_SINGLE,
CYHAL_QSPI_CFG_BUS_DUAL,
CYHAL_QSPI_CFG_BUS_QUAD,
CYHAL_QSPI_CFG_BUS_OCTAL
} cyhal_qspi_bus_width_t;
/** Size in bits */
typedef enum cyhal_qspi_size {
CYHAL_QSPI_CFG_SIZE_8,
CYHAL_QSPI_CFG_SIZE_16,
CYHAL_QSPI_CFG_SIZE_24,
CYHAL_QSPI_CFG_SIZE_32
} cyhal_qspi_size_t;
/** QSPI interrupt triggers */
typedef enum {
CYHAL_QSPI_IRQ_NONE = 0, /**< Disable all interrupts. >*/
CYHAL_QSPI_IRQ_TRANSMIT_DONE = 1 << 0, /**< Async transmit done. >*/
CYHAL_QSPI_IRQ_RECEIVE_DONE = 1 << 1, /**< Async receive done. >*/
} cyhal_qspi_irq_event_t;
/** \} group_hal_qspi_enums */
/**
* \addtogroup group_hal_qspi_macros
* \{
*/
#define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/
#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/
#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/
#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/
/** \} group_hal_qspi_macros */
/**
* \addtogroup group_hal_qspi_data_structures
* \{
*/
/** QSPI command settings */
typedef struct cyhal_qspi_command {
struct {
cyhal_qspi_bus_width_t bus_width; /**< Bus width for the instruction >*/
uint8_t value; /**< Instruction value >*/
bool disabled; /**< Instruction phase skipped if disabled is set to true >*/
} instruction;
struct {
cyhal_qspi_bus_width_t bus_width; /**< Bus width for the address >*/
cyhal_qspi_size_t size; /**< Address size >*/
uint32_t value; /**< Address value >*/
bool disabled; /**< Address phase skipped if disabled is set to true >*/
} address;
struct {
cyhal_qspi_bus_width_t bus_width; /**< Bus width for alternative >*/
cyhal_qspi_size_t size; /**< Alternative size >*/
uint32_t value; /**< Alternative value >*/
bool disabled; /**< Alternative phase skipped if disabled is set to true >*/
} alt;
uint8_t dummy_count; /**< Dummy cycles count >*/
struct {
cyhal_qspi_bus_width_t bus_width; /**< Bus width for data >*/
} data;
} cyhal_qspi_command_t;
/** Handler for QSPI interrupts */
typedef void (*cyhal_qspi_irq_handler_t)(void *handler_arg, cyhal_qspi_irq_event_t event);
/** \} group_hal_qspi_data_structures */
/**
* \addtogroup group_hal_qspi_functions
* \{
*/
/** Initialize QSPI peripheral.
*
* It should initialize QSPI pins (io0-io3, sclk and ssel), set frequency, clock polarity and phase mode.
* The clock for the peripheral should be enabled
*
* @param[out] obj QSPI object
* @param[in] io0 Data pin 0
* @param[in] io1 Data pin 1
* @param[in] io2 Data pin 2
* @param[in] io3 Data pin 3
* @param[in] io4 Data pin 4
* @param[in] io5 Data pin 5
* @param[in] io6 Data pin 6
* @param[in] io7 Data pin 7
* @param[in] sclk The clock pin
* @param[in] ssel The chip select pin
* @param[in] hz The bus frequency
* @param[in] mode Clock polarity and phase mode (0 - 3)
* @return The status of the init request
*/
cy_rslt_t cyhal_qspi_init(
cyhal_qspi_t *obj, cyhal_gpio_t io0, cyhal_gpio_t io1, cyhal_gpio_t io2, cyhal_gpio_t io3, cyhal_gpio_t io4, cyhal_gpio_t io5,
cyhal_gpio_t io6, cyhal_gpio_t io7, cyhal_gpio_t sclk, cyhal_gpio_t ssel, uint32_t hz, uint8_t mode
);
/** Deinitilize QSPI peripheral
*
* It should release pins that are associated with the QSPI object, and disable clocks for QSPI peripheral module
* that was associated with the object
*
* @param[in,out] obj QSPI object
*/
void cyhal_qspi_free(cyhal_qspi_t *obj);
/** Set the QSPI baud rate
*
* Actual frequency may differ from the desired frequency due to available dividers and the bus clock
* Configures the QSPI peripheral's baud rate
* @param[in] obj The SPI object to configure
* @param[in] hz The baud rate in Hz
* @return The status of the frequency request
*/
cy_rslt_t cyhal_qspi_frequency(cyhal_qspi_t *obj, uint32_t hz);
/** Receive a command and block of data
*
* @param[in] obj QSPI object
* @param[in] command QSPI command
* @param[out] data RX buffer
* @param[in,out] length in - RX buffer length in bytes, out - number of bytes read
* @return The status of the read request
*/
cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length);
/** Receive a command and block of data in asynchronous mode. Require __enable_irq() call in order to work.
*
* @param[in] obj QSPI object
* @param[in] command QSPI command
* @param[out] data RX buffer
* @param[in,out] length in - RX buffer length in bytes, out - number of bytes read
* @return The status of the read request
*/
cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length);
/** Send a command and block of data
*
* @param[in] obj QSPI object
* @param[in] command QSPI command
* @param[in] data TX buffer
* @param[in,out] length in - TX buffer length in bytes, out - number of bytes written
* @return The status of the write request
*/
cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length);
/** Send a command and block of data in asynchronous mode. Require __enable_irq() call in order to work.
*
* @param[in] obj QSPI object
* @param[in] command QSPI command
* @param[in] data TX buffer
* @param[in,out] length in - TX buffer length in bytes, out - number of bytes written
* @return The status of the write request
*/
cy_rslt_t cyhal_qspi_write_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length);
/** Send a command (and optionally data) and get the response. Can be used to send/receive device specific commands
*
* @param[in] obj QSPI object
* @param[in] command QSPI command
* @param[in] tx_data TX buffer
* @param[in,out] tx_size in - TX buffer length in bytes, out - bytes actually written
* @param[out] rx_data RX buffer
* @param[in,out] rx_size in - RX buffer length in bytes, out - bytes actually read
* @return The status of the transfer request
*/
cy_rslt_t cyhal_qspi_transfer(
cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *tx_data, size_t tx_size, void *rx_data,
size_t rx_size
);
/** The QSPI interrupt handler registration
*
* @param[in] obj The QSPI object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_qspi_register_irq(cyhal_qspi_t *obj, cyhal_qspi_irq_handler_t handler, void *handler_arg);
/** Configure QSPI interrupt enablement.
*
* @param[in] obj The QSPI object
* @param[in] event The QSPI IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_qspi_irq_enable(cyhal_qspi_t *obj, cyhal_qspi_irq_event_t event, bool enable);
/** \} group_hal_qspi_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_qspi */

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/***************************************************************************//**
* \file cyhal_rtc.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Real-Time Clock.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_rtc RTC (Real-Time Clock)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress RTC.
*
* \defgroup group_hal_rtc_macros Macros
* \defgroup group_hal_rtc_functions Functions
* \defgroup group_hal_rtc_data_structures Data Structures
* \defgroup group_hal_rtc_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include <time.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
/** RTC not initialized */
#define CY_RSLT_RTC_NOT_INITIALIZED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 0)
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_rtc_enums
* \{
*/
/** RTC interrupt triggers */
typedef enum {
CYHAL_RTC_ALARM,
} cyhal_rtc_irq_event_t;
/** \} group_hal_rtc_enums */
/**
* \addtogroup group_hal_rtc_data_structures
* \{
*/
/** Defines which fields should be active for the alarm. */
typedef struct
{
uint8_t en_sec : 1; /** !< Enable match of seconds */
uint8_t en_min : 1; /** !< Enable match of minutes */
uint8_t en_hour : 1; /** !< Enable match of hours */
uint8_t en_day : 1; /** !< Enable match of day of week */
uint8_t en_date : 1; /** !< Enable match of date in month */
uint8_t en_month : 1; /** !< Enable match of month */
} cyhal_alarm_active_t;
/** Handler for RTC interrupts */
typedef void (*cyhal_rtc_irq_handler_t)(void *handler_arg, cyhal_rtc_irq_event_t event);
/** \} group_hal_rtc_data_structures */
/**
* \addtogroup group_hal_rtc_functions
* \{
*/
/** Initialize the RTC peripheral
*
* Powerup the RTC in perpetration for access. This function must be called
* before any other RTC functions ares called. This does not change the state
* of the RTC. It just enables access to it.
* NOTE: Before calling this, make sure all necessary System Clocks are setup
* correctly. Generally this means making sure the RTC has access to a Crystal
* for optimal accuracy and operation in low power.
*
* @param[out] obj RTC object
* @return The status of the init request
*/
cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj);
/** Deinitialize RTC
*
* Powerdown the RTC in preparation for sleep, powerdown or reset. That should only
* affect the CPU domain and not the time keeping logic.
* After this function is called no other RTC functions should be called
* except for rtc_init.
*
* @param[in,out] obj RTC object
*/
void cyhal_rtc_free(cyhal_rtc_t *obj);
/** Check if the RTC has the time set and is counting
*
* @param[in] obj RTC object
* @return Whether the RTC is enabled or not
*/
bool cyhal_rtc_is_enabled(cyhal_rtc_t *obj);
/** Get the current time from the RTC peripheral
*
* @param[in] obj RTC object
* @param[out] time The current time (see: https://en.cppreference.com/w/cpp/chrono/c/tm)
* @return The status of the read request
*/
cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time);
/** Write the current time in seconds to the RTC peripheral
*
* @param[in] obj RTC object
* @param[in] time The time to be set (see: https://en.cppreference.com/w/cpp/chrono/c/tm)
* @return The status of the write request
*/
cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time);
/** Set an alarm for the specified time in seconds to the RTC peripheral
*
* @param[in] obj RTC object
* @param[in] time The alarm time to be set (see: https://en.cppreference.com/w/cpp/chrono/c/tm)
* @param[in] active The set of fields that are checked to trigger the alarm
* @return The status of the alarm request
*/
cy_rslt_t cyhal_rtc_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active);
/** The RTC alarm interrupt handler registration
*
* @param[in] obj The RTC object
* @param[in] handler The callback handler which will be invoked when the alarm fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_rtc_register_irq(cyhal_rtc_t *obj, cyhal_rtc_irq_handler_t handler, void *handler_arg);
/** Configure RTC alarm interrupt enablement.
*
* @param[in] obj The RTC object
* @param[in] event The RTC IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_rtc_irq_enable(cyhal_rtc_t *obj, cyhal_rtc_irq_event_t event, bool enable);
/** \} group_hal_rtc_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_rtc */

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/***************************************************************************//**
* \file cyhal_scb_common.h
*
* \brief
* Provides a struct definitions for configuration resources in the SCB (UART, I2C, SPI).
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cy_device.h"
#include "cy_pdl.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** The start address of the SCB blocks */
extern CySCB_Type* CY_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES];
/** The interrupt number of the SCB blocks. */
extern IRQn_Type CY_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES];
#if defined(__cplusplus)
}
#endif

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/***************************************************************************//**
* \file cyhal_sdhc.h
*
* \brief
* Provides a high level interface for interacting with the Cypress SDHC.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_sdhc SDHC (SD Host Controller)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress SDHC.
*
* \defgroup group_hal_sdhc_macros Macros
* \defgroup group_hal_sdhc_functions Functions
* \defgroup group_hal_sdhc_data_structures Data Structures
* \defgroup group_hal_sdhc_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_sdhc_enums
* \{
*/
/** Card types */
typedef enum
{
CYHAL_SDHC_SD, //!< Secure Digital card
CYHAL_SDHC_SDIO, //!< CD Input Output card
CYHAL_SDHC_EMMC, //!< Embedded Multimedia card
CYHAL_SDHC_COMBO, //!< Combo Card (SD + SDIO)
CYHAL_SDHC_UNUSABLE, //!< Unusable card or unsupported type
CYHAL_SDHC_NOT_EMMC, //!< Not an eMMC card
} cyhal_sdhc_card_type_t;
/** SDHC interrupt triggers */
typedef enum {
CYHAL_SDHC_CMD_COMPLETE, //!> Command Complete
CYHAL_SDHC_XFER_COMPLETE, //!> Host read/write transfer is complete
CYHAL_SDHC_BGAP_EVENT, //!> This bit is set when both read/write transaction is stopped
CYHAL_SDHC_DMA_INTERRUPT, //!> Host controller detects an SDMA Buffer Boundary during transfer
CYHAL_SDHC_BUF_WR_READY, //!> This bit is set if the Buffer Write Enable changes from 0 to 1
CYHAL_SDHC_BUF_RD_READY, //!> This bit is set if the Buffer Read Enable changes from 0 to 1
CYHAL_SDHC_CARD_INSERTION, //!> This bit is set if the Card Inserted in the Present State
CYHAL_SDHC_CARD_REMOVAL, //!> This bit is set if the Card Inserted in the Present State
CYHAL_SDHC_CARD_INTERRUPT, //!> The synchronized value of the DAT[1] interrupt input for SD mode
CYHAL_SDHC_INT_A,
CYHAL_SDHC_INT_B,
CYHAL_SDHC_INT_C,
CYHAL_SDHC_RE_TUNE_EVENT, //!> This bit is set if the Re-Tuning Request changes from 0 to 1
CYHAL_SDHC_FX_EVENT, //!> This status is set when R[14] of response register is set to 1
CYHAL_SDHC_CQE_EVENT, //!> This status is set if Command Queuing/Crypto event has occurred
CYHAL_SDHC_ERR_INTERRUPT, //!> If any of the bits in the Error Interrupt Status register are set
CYHAL_SDHC_ALL_INTERRUPTS, //!> Is used to enable/disable all interrupts
} cyhal_sdhc_irq_event_t;
/** \} group_hal_sdhc_enums */
/**
* \addtogroup group_hal_sdhc_data_structures
* \{
*/
/** Handler for SDHC interrupts */
typedef void (*cyhal_sdhc_irq_handler_t)(void *handler_arg, cyhal_sdhc_irq_event_t event);
/** Defines configuration options for the SDHC block */
typedef struct
{
bool enableLedControl; //!< Drive one IO to indicate when the card is being accessed
bool lowVoltageSignaling; //!< Whether 1.8V signaling is supported
uint8_t busWidth; //!< The desired bus width
} cyhal_sdhc_config_t;
/** \} group_hal_sdhc_data_structures */
/**
* \addtogroup group_hal_sdhc_functions
* \{
*/
/** Initialize the SDHC peripheral
*
* @param[out] obj The SDHC object
* @param[out] clk The pin connected to the clk signal
* @param[in] cmd The pin connected to the command signal
* @param[in] data0 The pin connected to the data0 signal
* @param[in] data1 The pin connected to the data1 signal
* @param[in] data2 The pin connected to the data2 signal
* @param[in] data3 The pin connected to the data3 signal
* @param[in] data4 The pin connected to the data4 signal
* @param[in] data5 The pin connected to the data5 signal
* @param[in] data6 The pin connected to the data6 signal
* @param[in] data7 The pin connected to the data7 signal
* @param[in] cardDetect The pin connected to the cardDetect signal
* @param[out] ioVoltSel The pin connected to the ioVoltSel signal
* @param[out] cardIfPwrEn The pin connected to the cardIfPwrEn signal
* @param[in] cardMechWriteProt The pin connected to the cardMechWriteProt signal
* @param[in] ledCtrl The pin connected to the ledCtrl signal
* @param[in] cardEmmcReset The pin connected to the cardEmmcReset signal
* @return The status of the init request
*/
cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj,
cyhal_gpio_t cmd,
cyhal_gpio_t clk,
cyhal_gpio_t data0,
cyhal_gpio_t data1,
cyhal_gpio_t data2,
cyhal_gpio_t data3,
cyhal_gpio_t data4,
cyhal_gpio_t data5,
cyhal_gpio_t data6,
cyhal_gpio_t data7,
cyhal_gpio_t cardDetect,
cyhal_gpio_t ioVoltSel,
cyhal_gpio_t cardIfPwrEn,
cyhal_gpio_t cardMechWriteProt,
cyhal_gpio_t ledCtrl,
cyhal_gpio_t cardEmmcReset);
/** Release the SDHC peripheral, not currently invoked. It requires further
* resource management.
*
* @param[in,out] obj The SDHC object
*/
void cyhal_sdhc_free(cyhal_sdhc_t *obj);
/** Configure the SDHC block.
*
* @param[in,out] obj The SDHC object
* @param[in] config The card configuration object
* @return The status of the configure request
*/
cy_rslt_t cyhal_sdhc_configure(cyhal_sdhc_t *obj, const cyhal_sdhc_config_t *config);
/** Attempts to read data over the SDHC peripheral.
*
* @param[in] obj The SDHC object
* @param[in] address The address to read data from
* @param[out] data Pointer to the byte-array of data to read from the device
* @param[in,out] length Number of bytes to read, updated with the number actually read
* @return The status of the read request
*/
cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length);
/** Attempts to write data over SDHC peripheral
*
* @param[in] obj The SDHC object
* @param[in] address The address to write data to
* @param[in] data Pointer to the byte-array of data to write to the device
* @param[in,out] length Number of bytes to read, updated with the number actually read
* @return The status of the write request
*/
cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length);
/** Attempts to erase a block of data over the SDHC peripheral
*
* @param[in] obj The SDHC object
* @param[in] startAddr Is the address of the first byte to erase
* @param[in] length The number of bytes (starting at startAddr) to erase
* @return The status of the erase request
*/
cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t length);
/** Begin the SDHC read
*
* @param[in] obj The SDHC object that holds the transfer information
* @param[in] address The address to read data from
* @param[out] data The receive buffer
* @param[in,out] length Number of bytes to read, updated with the number actually read
* @return The status of the read_async request
*/
cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length);
/** Begin the SDHC write
*
* @param[in] obj The SDHC object that holds the transfer information
* @param[in] address The address to write data to
* @param[in] data The transmit buffer
* @param[in,out] length Number of bytes to read, updated with the number actually read
* @return The status of the write_async request
*/
cy_rslt_t cyhal_sdhc_write_async(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length);
/** Checks if the specified SDHC peripheral is in use
*
* @param[in] obj The SDHC peripheral to check
* @return Indication of whether the SDHC is still transmitting
*/
bool cyhal_sdhc_is_busy(const cyhal_sdhc_t *obj);
/** Abort an SDHC transfer
*
* @param[in] obj The SDHC peripheral to stop
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_sdhc_abort_async(const cyhal_sdhc_t *obj);
/** The SDHC interrupt handler registration
*
* @param[in] obj The SDHC object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_sdhc_register_irq(cyhal_sdhc_t *obj, cyhal_sdhc_irq_handler_t handler, void *handler_arg);
/** Configure SDHC interrupt enablement.
*
* @param[in] obj The SDHC object
* @param[in] event The SDHC IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_sdhc_irq_enable(cyhal_sdhc_t *obj, cyhal_sdhc_irq_event_t event, bool enable);
/** \} group_hal_sdhc_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_sdhc */

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/***************************************************************************//**
* \file cyhal_sdio.h
*
* \brief
* Provides a high level interface for interacting with the Cypress SDIO interface.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_sdio SDIO (Secure Digital Input Output)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress SDIO interface.
*
* \defgroup group_hal_sdio_macros Macros
* \defgroup group_hal_sdio_functions Functions
* \defgroup group_hal_sdio_data_structures Data Structures
* \defgroup group_hal_sdio_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_sdio_macros
* \{
*/
#define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/
#define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/
#define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/
#define CYHAL_SDIO_RET_CMD_IDX_ERROR (0x04) /**< The index for the command didn't match*/
#define CYHAL_SDIO_RET_CMD_EB_ERROR (0x08) /**< There was an end bit error on the command*/
#define CYHAL_SDIO_RET_DAT_CRC_ERROR (0x10) /**< There was a data CRC Error*/
#define CYHAL_SDIO_RET_CMD_TIMEOUT (0x20) /**< The command didn't finish before the timeout period was over*/
#define CYHAL_SDIO_RET_DAT_TIMEOUT (0x40) /**< The data didn't finish before the timeout period was over*/
#define CYHAL_SDIO_RET_RESP_FLAG_ERROR (0x80) /**< There was an error in the resposne flag for command 53*/
#define CYHAL_SDIO_CLOCK_ERROR (0x100) /**< Failed to initial clock for SDIO */
#define CYHAL_SDIO_BAD_ARGUMENT (0x200) /**< Bad argument passed for SDIO */
#define CYHAL_SDIO_SEMA_NOT_INITED (0x400) /**< Semaphore is not initiated */
#define CYHAL_SDIO_FUNC_NOT_SUPPORTED (0x800) /**< Function is not supported */
/* HAL return value defines */
/** Incorrect parameter value define */
#define CYHAL_SDIO_RSLT_ERR_BAD_PARAM CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, \
CYHAL_RSLT_MODULE_SDIO, \
CYHAL_SDIO_BAD_ARGUMENT)
/** Clock initialization error define */
#define CYHAL_SDIO_RSLT_ERR_CLOCK CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, \
CYHAL_RSLT_MODULE_SDIO, \
CYHAL_SDIO_CLOCK_ERROR)
/** Semaphore not initiated error define */
#define CYHAL_SDIO_RSLT_ERR_SEMA_NOT_INITED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, \
CYHAL_RSLT_MODULE_SDIO, \
CYHAL_SDIO_SEMA_NOT_INITED)
/** Error define based on SDIO lower function return value */
#define CYHAL_SDIO_RSLT_ERR_FUNC_RET(retVal) CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, \
CYHAL_RSLT_MODULE_SDIO, (retVal))
/** \} group_hal_sdio_macros */
/**
* \addtogroup group_hal_sdio_enums
* \{
*/
/** Commands that can be issued */
typedef enum
{
CYHAL_SDIO_CMD_GO_IDLE_STATE = 0, //!> Go to idle state
CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR = 3, //!> Send a relative address
CYHAL_SDIO_CMD_IO_SEND_OP_COND = 5, //!> Send an OP IO
CYHAL_SDIO_CMD_SELECT_CARD = 7, //!> Send a card select
CYHAL_SDIO_CMD_GO_INACTIVE_STATE = 15, //!> Go to inactive state
CYHAL_SDIO_CMD_IO_RW_DIRECT = 52, //!> Perform a direct read/write
CYHAL_SDIO_CMD_IO_RW_EXTENDED = 53, //!> Perform an extended read/write
} cyhal_sdio_command_t;
/** Types of transfer that can be performed */
typedef enum
{
CYHAL_READ, //!> Read from the card
CYHAL_WRITE //!> Write to the card
} cyhal_transfer_t;
/** Events that can cause an SDIO interrupt */
typedef enum {
CYHAL_SDIO_CMD_COMPLETE = 0x0001, //!> Command Complete
CYHAL_SDIO_XFER_COMPLETE = 0x0002, //!> Host read/write transfer is complete
CYHAL_SDIO_BGAP_EVENT = 0x0004, //!> This bit is set when both read/write transaction is stopped
CYHAL_SDIO_DMA_INTERRUPT = 0x0008, //!> Host controller detects an SDMA Buffer Boundary during transfer
CYHAL_SDIO_BUF_WR_READY = 0x0010, //!> This bit is set if the Buffer Write Enable changes from 0 to 1
CYHAL_SDIO_BUF_RD_READY = 0x0020, //!> This bit is set if the Buffer Read Enable changes from 0 to 1
CYHAL_SDIO_CARD_INSERTION = 0x0040, //!> This bit is set if the Card Inserted in the Present State
CYHAL_SDIO_CARD_REMOVAL = 0x0080, //!> This bit is set if the Card Inserted in the Present State
CYHAL_SDIO_CARD_INTERRUPT = 0x0100, //!> The synchronized value of the DAT[1] interrupt input for SD mode
CYHAL_SDIO_INT_A = 0x0200, //!> Reserved: set to 0
CYHAL_SDIO_INT_B = 0x0400, //!> Reserved: set to 0
CYHAL_SDIO_INT_C = 0x0800, //!> Reserved: set to 0,
CYHAL_SDIO_RE_TUNE_EVENT = 0x1000, //!> Reserved: set to 0,
CYHAL_SDIO_FX_EVENT = 0x2000, //!> This status is set when R[14] of response register is set to 1
CYHAL_SDIO_CQE_EVENT = 0x4000, //!> This status is set if Command Queuing/Crypto event has occurred
CYHAL_SDIO_ERR_INTERRUPT = 0x8000, //!> If any of the bits in the Error Interrupt Status register are set
CYHAL_SDIO_ALL_INTERRUPTS = 0xE1FF, //!> Is used to enable/disable all interrupts
} cyhal_sdio_irq_event_t;
/** \} group_hal_sdio_enums */
/**
* \addtogroup group_hal_sdio_data_structures
* \{
*/
/** SDIO controller initial configuration */
typedef struct
{
uint32_t frequencyhal_hz; //!< Clock frequency, in hertz
uint16_t block_size; //!< Block size
} cyhal_sdio_cfg_t;
/** Handler for SDIO interrupts */
typedef void (*cyhal_sdio_irq_handler_t)(void *handler_arg, cyhal_sdio_irq_event_t event);
/** \} group_hal_sdio_data_structures */
/**
* \addtogroup group_hal_sdio_functions
* \{
*/
/** Initialize the SDIO peripheral
*
* @param[out] obj The SDIO object
* @param[out] clk The pin connected to the clk signal
* @param[in] cmd The pin connected to the command signal
* @param[in] data0 The pin connected to the data0 signal
* @param[in] data1 The pin connected to the data1 signal
* @param[in] data2 The pin connected to the data2 signal
* @param[in] data3 The pin connected to the data3 signal
* @return The status of the init request
*/
cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3);
/** Release the SDIO peripheral, not currently invoked. It requires further
* resource management.
*
* @param[in,out] obj The SDIO object
*/
void cyhal_sdio_free(cyhal_sdio_t *obj);
/** Configure the SDIO block.
*
* @param[in,out] obj The SDIO object
* @param[in] config The sdio configuration to apply
* @return The status of the configure request
*/
cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config);
/** Sends a command to the SDIO block.
*
* @param[in,out] obj The SDIO object
* @param[in] direction The direction of transfer (read/write)
* @param[in] command The SDIO command to send
* @param[in] argument The argument to the command
* @param[out] response The response from the SDIO device
* @return The status of the configure request
*/
cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response);
/** Performs a bulk data transfer (CMD=53) to the SDIO block.
*
* @param[in,out] obj The SDIO object
* @param[in] direction The direction of transfer (read/write)
* @param[in] argument The argument to the command
* @param[in] data The data to send to the SDIO device. The data buffer
* should be aligned to the block size (64 bytes) if data
* size is greater that block size (64 bytes).
* @param[in] length The number of bytes to send
* @param[out] response The response from the SDIO device
* @return The status of the configure request
*/
cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response);
/** Performs a bulk asynchronus data transfer (CMD=53) to the SDIO block.
*
* @param[in,out] obj The SDIO object
* @param[in] direction The direction of transfer (read/write)
* @param[in] argument The argument to the command
* @param[in] data The data to send to the SDIO device
* @param[in] length The number of bytes to send
* @return The status of the configure request
*/
cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length);
/** Checks if the specified SDIO is in use
*
* @param[in] obj The SDIO peripheral to check
* @return Indication of whether the SDIO is still transmitting
*/
bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj);
/** Abort an SDIO transfer
*
* @param[in] obj The SDIO peripheral to stop
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj);
/** The sdio interrupt handler registration
*
* @param[in] obj The SDIO object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_sdio_register_irq(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg);
/** Configure sdio interrupt.
*
* @param[in] obj The SDIO object
* @param[in] event The sdio IRQ type
* @param[in] enable Set to non-zero to enable events, or zero to disable them
*/
void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool enable);
/** \} group_hal_sdio_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_sdio */

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/***************************************************************************//**
* \file cyhal_spi.h
*
* \brief
* Provides a high level interface for interacting with the Cypress SPI.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_spi SPI (Serial Peripheral Interface)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress SPI.
*
* \defgroup group_hal_spi_macros Macros
* \defgroup group_hal_spi_functions Functions
* \defgroup group_hal_spi_data_structures Data Structures
* \defgroup group_hal_spi_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_implementation.h"
#include "cyhal_hwmgr.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_spi_macros
* \{
*/
/** Bad argument */
#define CYHAL_SPI_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0))
/** Failed to initialize SPI clock */
#define CYHAL_SPI_RSLT_CLOCK_ERROR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 1))
/** Failed to Transfer SPI data */
#define CYHAL_SPI_RSLT_TRANSFER_ERROR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 2))
/** Provided clock is not supported by SPI */
#define CYHAL_SPI_RSLT_CLOCK_NOT_SUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 3))
/** Provided PIN configuration is not supported by SPI */
#define CYHAL_SPI_RSLT_PIN_CONFIG_NOT_SUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 5))
/** Provided PIN configuration is not supported by SPI */
#define CYHAL_SPI_RSLT_INVALID_PIN_API_NOT_SUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 6))
/** The requested resource type is invalid */
#define CYHAL_SPI_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 7))
/** \} group_hal_spi_macros */
/** SPI interrupt triggers */
typedef enum {
CYHAL_SPI_IRQ_NONE = 0, //!< Disable all interrupt call backs
/** All transfer data has been moved into data FIFO */
CYHAL_SPI_IRQ_DATA_IN_FIFO = 1 << 1,
/** Transfer complete. */
CYHAL_SPI_IRQ_DONE = 1 << 2,
/** An error occurred while transferring data */
CYHAL_SPI_IRQ_ERROR = 1 << 3,
} cyhal_spi_irq_event_t;
/** Handler for SPI interrupts */
typedef void (*cyhal_spi_irq_handler_t)(void *handler_arg, cyhal_spi_irq_event_t event);
/** SPI operating modes */
typedef enum
{
/** Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation */
CYHAL_SPI_MODE_00_MSB,
/** Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation */
CYHAL_SPI_MODE_00_LSB,
/** Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation */
CYHAL_SPI_MODE_01_MSB,
/** Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation */
CYHAL_SPI_MODE_01_LSB,
/** Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation */
CYHAL_SPI_MODE_10_MSB,
/** Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation */
CYHAL_SPI_MODE_10_LSB,
/** Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation */
CYHAL_SPI_MODE_11_MSB,
/** Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation */
CYHAL_SPI_MODE_11_LSB,
} cyhal_spi_mode_t;
/** Initial SPI configuration. */
typedef struct
{
cyhal_spi_mode_t mode; //!< The operating mode
uint8_t data_bits; //!< The number of bits per transfer
bool is_slave; //!< Whether the peripheral is operating as slave or master
} cyhal_spi_cfg_t;
/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* @param[out] obj The SPI object to initialize
* @param[in] mosi The pin to use for MOSI
* @note At least MOSI or MISO pin should be non-NC
* @param[in] miso The pin to use for MISO
* @note At least MOSI or MISO pin should be non-NC
* @param[in] sclk The pin to use for SCLK
* @note This pin cannot be NC
* @param[in] ssel The pin to use for SSEL
* @note This pin can be NC
* @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated
* @param[in] bits The number of bits per frame
* @note bits should be 8 or 16
* @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
* @param[in] is_slave false for master mode or true for slave mode operation
* @return The status of the init request
*/
cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, const cyhal_clock_divider_t *clk,
uint8_t bits, cyhal_spi_mode_t mode, bool is_slave);
/** Release a SPI object
*
* Return the peripheral, pins and clock owned by the SPI object to their reset state
* @param[in,out] obj The SPI object to deinitialize
*/
void cyhal_spi_free(cyhal_spi_t *obj);
/** Set the SPI baud rate
*
* Actual frequency may differ from the desired frequency due to available dividers and bus clock
* Configures the SPI peripheral's baud rate
* @param[in,out] obj The SPI object to configure
* @param[in] hz The baud rate in Hz
* @return The status of the frequency request
*/
cy_rslt_t cyhal_spi_frequency(cyhal_spi_t *obj, uint32_t hz);
/** Get a received value out of the SPI receive buffer
*
* Blocks until a value is available
* @param[in] obj The SPI peripheral to read
* @param[in] value The value received
* @return The status of the read request
* @note
* - In Master mode, MISO pin required to be non-NC for this API to operate
* - In Slave mode, MOSI pin required to be non-NC for this API to operate
*/
cy_rslt_t cyhal_spi_read(cyhal_spi_t *obj, uint32_t* value);
/** Write a byte out
*
* @param[in] obj The SPI peripheral to use for sending
* @param[in] value The value to send
* @return The status of the write request
* @note
* - In Master mode, MOSI pin required to be non-NC for this API to operate
* - In Slave mode, MISO pin required to be non-NC for this API to operate
*/
cy_rslt_t cyhal_spi_write(cyhal_spi_t *obj, uint32_t value);
/** Write a block out and receive a value
*
* The total number of bytes sent and received will be the maximum of
* tx_length and rx_length. The bytes written will be padded with the
* value 0xff.
*
* @param[in] obj The SPI peripheral to use for sending
* @param[in] tx Pointer to the byte-array of data to write to the device
* @param[in,out] tx_length Number of bytes to write, updated with the number actually written
* @param[out] rx Pointer to the byte-array of data to read from the device
* @param[in,out] rx_length Number of bytes to read, udpated with the number actually read
* @param[in] write_fill Default data transmitted while performing a read
* @return The status of the transfer request
* @note Both MOSI and MISO pins required to be non-NC for this API to operate
*/
cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill);
/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
*
* @param[in] obj The SPI object that holds the transfer information
* @param[in] tx The transmit buffer
* @param[in,out] tx_length The number of bytes to transmit
* @param[out] rx The receive buffer
* @param[in,out] rx_length The number of bytes to receive
* @return The status of the transfer_async request
* @note Both MOSI and MISO pins required to be non-NC for this API to operate
*/
cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length);
/** Checks if the specified SPI peripheral is in use
*
* @param[in] obj The SPI peripheral to check
* @return Indication of whether the SPI is still transmitting
*/
bool cyhal_spi_is_busy(cyhal_spi_t *obj);
/** Abort an SPI transfer
*
* @param[in] obj The SPI peripheral to stop
* @return The status of the abort_async request
*/
cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj);
/** The SPI interrupt handler registration
*
* @param[in] obj The SPI object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_spi_register_irq(cyhal_spi_t *obj, cyhal_spi_irq_handler_t handler, void *handler_arg);
/** Configure SPI interrupt. This function is used for word-approach
*
* @param[in] obj The SPI object
* @param[in] event The SPI IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_spi_irq_enable(cyhal_spi_t *obj, cyhal_spi_irq_event_t event, bool enable);
/** \} group_hal_spi_functions */
#if defined(__cplusplus)
}
#endif

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/***************************************************************************//**
* \file cyhal_system.h
*
* \brief
* Provides a high level interface for interacting with the Cypress power
* management and system clock configuration. This interface abstracts out the
* chip specific details. If any chip specific functionality is necessary, or
* performance is critical the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_system SYSTEM (Power Management and System Clock)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress power management
* and system clock configuration.
*
* \defgroup group_hal_system_macros Macros
* \defgroup group_hal_system_functions Functions
* \defgroup group_hal_system_data_structures Data Structures
* \defgroup group_hal_system_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cyhal_hwmgr.h"
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_system_macros
* \{
*/
/** An error occurred in System module */
#define CYHAL_SYSTEM_RSLT_ERROR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 0))
/** An error occurred in System module */
#define CYHAL_SYSTEM_RSLT_INVALID_CLK_DIVIDER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 1))
/** An error occurred in System module */
#define CYHAL_SYSTEM_RSLT_UNABLE_TO_SET_CLK_FREQ (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 2))
/** An error occurred in System module */
#define CYHAL_SYSTEM_RSLT_SRC_CLK_DISABLED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 3))
/** An error occurred in System module */
#define CYHAL_SYSTEM_RSLT_NO_VALID_DIVIDER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 4))
/** \} group_hal_system_macros */
/**
* \addtogroup group_hal_system_functions
* \{
*/
/** Enter a critical section
*
* Disables interrupts and returns a value indicating whether the interrupts were previously
* enabled.
*
* @return Returns the state before entering the critical section. This value must be provided
* to \ref cyhal_system_critical_section_exit() to properly restore the state
*/
uint32_t cyhal_system_critical_section_enter(void);
/** Exit a critical section
*
* Re-enables the interrupts if they were enabled before
* cyhal_system_critical_section_enter() was called. The argument should be the value
* returned from \ref cyhal_system_critical_section_enter().
*
* @param[in] oldState The state of interrupts from cyhal_system_critical_section_enter()
*/
void cyhal_system_critical_section_exit(uint32_t oldState);
/** Send the device to sleep
*
*
* The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
* system clock to the core is stopped until a reset or an interrupt occurs.
*
* @return Returns CY_RSLT_SUCCESS if the processor successfully entered and exited sleep,
* otherwise error
*/
cy_rslt_t cyhal_system_sleep(void);
/** Send the device to deep sleep
*
* This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
* has the same sleep features as sleep plus it powers down peripherals and clocks. All state
* is still maintained.
*
* @return Returns CY_RSLT_SUCCESS if the processor successfully entered and exited sleep,
* otherwise error
*/
cy_rslt_t cyhal_system_deepsleep(void);
/** Register the specified handler with the power manager to be notified when the power
* state changes.
*
* @param[in] handler The handler to notify on power transitions
* @return The status of the register_callback request
*/
cy_rslt_t cyhal_system_register_callback(cyhal_system_call_back_t *handler);
/** Removes the specified handler from the power manager so no future notification are made.
*
* @param[in] handler The handler to remove from receiving notifications
* @return The status of the unregister_callback request
*/
cy_rslt_t cyhal_system_unregister_callback(cyhal_system_call_back_t const *handler);
/** Sets the specified clock's frequency and enables it.
* This will turn on any additional clocks needed to drive this.
*
* @param[in] clock ID of clock to configure
* @param[in] frequencyhal_hz The frequency to run the clock at
* @return The status of the clock_frequency request
*/
cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz);
/** Divides the clock frequency by the divider
*
* @param[in] clock The clock to configure divider value for
* @param[in] divider The divider value to divide the frequency by
* @return The status of setting the divider
*/
cy_rslt_t cyhal_system_clock_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider);
/** \} group_hal_system_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_system */

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/***************************************************************************//**
* \file cyhal_system_impl.h
*
* \brief
* Provides a PSoC Specific interface for interacting with the Cypress power
* management and system clock configuration. This interface abstracts out the
* chip specific details. If any chip specific functionality is necessary, or
* performance is critical the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cyhal_system.h"
#ifdef CY_IP_MXS40SRSS
#define cyhal_system_critical_section_enter() Cy_SysLib_EnterCriticalSection()
#define cyhal_system_critical_section_exit(x) Cy_SysLib_ExitCriticalSection(x)
#define cyhal_system_sleep() Cy_SysPm_CpuEnterSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)
#define cyhal_system_deepsleep() Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT)
#endif /* CY_IP_MXS40SRSS */

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/***************************************************************************//**
* \file cyhal_timer.h
*
* \brief
* Provides a high level interface for interacting with the Cypress Timer/Counter.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_timer TIMER (Timer/Counter)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress GPIO.
*
* \defgroup group_hal_timer_macros Macros
* \defgroup group_hal_timer_functions Functions
* \defgroup group_hal_timer_data_structures Data Structures
* \defgroup group_hal_timer_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_timer_enums
* \{
*/
/** Timer directions */
typedef enum
{
CYHAL_TIMER_DIR_UP, //!< Counts up
CYHAL_TIMER_DIR_DOWN, //!< Counts down
CYHAL_TIMER_DIR_UP_DOWN, //!< Counts up and down, terminal count occurs on both overflow and underflow.
} cyhal_timer_direction_t;
/** Timer interrupt triggers */
typedef enum {
CYHAL_TIMER_IRQ_NONE,
CYHAL_TIMER_IRQ_TERMINAL_COUNT,
CYHAL_TIMER_IRQ_CAPTURE_COMPARE,
CYHAL_TIMER_IRQ_ALL,
} cyhal_timer_irq_event_t;
/** \} group_hal_timer_enums */
/**
* \addtogroup group_hal_timer_data_structures
* \{
*/
/** Describes the current configuration of a timer/counter */
typedef struct
{
/**
* Whether the timer is set to continously run.
* If true, the timer will run forever.
* Otherwise, the timer will run once and stop (one shot).
*/
bool is_continuous; //!< Whether the timer/counter operates continuous (true) or one shot (false)
cyhal_timer_direction_t direction; //!< Direction the timer/counter is running
bool is_compare; //!< Is it in compare (true) or capture (false) mode
uint32_t period; //!< Timer/counter period
uint32_t compare_value; //!< Timer/counter comparison value
uint32_t value; //!< Current value of the timer/counter
} cyhal_timer_cfg_t;
/** Handler for test interrupts */
typedef void (*cyhal_timer_irq_handler_t)(void *handler_arg, cyhal_timer_irq_event_t event);
/** \} group_hal_timer_data_structures */
/**
* \addtogroup group_hal_hwmgr_macros
* \{
*/
/** Bad argument. eg: null pointer */
#define CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 0))
/** Failed to initialize Timer clock */
#define CYHAL_TIMER_RSLT_ERR_CLOCK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 1))
/** Failed to initialize Timer */
#define CYHAL_TIMER_RSLT_ERR_INIT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TIMER, 2))
/** \} group_hal_hwmgr_macros */
/**
* \addtogroup group_hal_timer_functions
* \{
*/
/** Initialize the timer/counter peripheral and configure the pin
*
* @param[out] obj The timer/counter object to initialize
* @param[in] pin optional - The timer/counter compare/capture pin to initialize
* @param[in] clk optional - The shared clock to use, if not provided a new clock will be allocated
* @return The status of the init request
*/
cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk);
/** Deinitialize the timer/counter object
*
* @param[in,out] obj The timer/counter object
*/
void cyhal_timer_free(cyhal_timer_t *obj);
/** Updates the configuration of the timer/counter object
*
* @param[in] obj The timer/counter object
* @param[in] cfg The configuration of the timer/counter
* @return The status of the info request
*/
cy_rslt_t cyhal_timer_set_config(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg);
/** Starts the timer/counter with the pre-set configuration.
*
* @param[in] obj The timer/counter object
* @return The status of the start request
*/
cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj);
/** Stops the timer/counter.
*
* @param[in] obj The timer/counter object
* @return The status of the stop request
*/
cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj);
/** The timer/counter interrupt handler registration
*
* @param[in] obj The timer/counter object
* @param[in] priority The NVIC interrupt channel priority
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_timer_register_irq(cyhal_timer_t *obj, uint8_t priority, cyhal_timer_irq_handler_t handler, void *handler_arg);
/** Configure timer/counter interrupt enablement.
*
* @param[in] obj The timer/counter object
* @param[in] event The timer/counter IRQ type
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_timer_irq_enable(cyhal_timer_t *obj, cyhal_timer_irq_event_t event, bool enable);
/** \} group_hal_timer_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_timer */

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/***************************************************************************//**
* \file cyhal_trng.h
*
* \brief
* Provides a high level interface for interacting with the Cypress True Random
* Number Generator. This interface abstracts out the chip specific details. If
* any chip specific functionality is necessary, or performance is critical the
* low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_trng TRNG (True Random Number Generator)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress TRNG.
*
* \defgroup group_hal_trng_macros Macros
* \defgroup group_hal_trng_functions Functions
* \defgroup group_hal_trng_data_structures Data Structures
* \defgroup group_hal_trng_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/** Arguments passed the function are not valid. */
#define CYHAL_TRNG_RSLT_ERR_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TRNG, 0))
/** Hardware error in the crypto block. This will only occur if the Ring oscillators in the TRNG generator are explicitly
* disabled during TRNG generation.
*/
#define CYHAL_TRNG_RSLT_ERR_HW (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_TRNG, 1))
/**
* \addtogroup group_hal_trng_functions
* \{
*/
/** Initialize the random number generator.
*
* @param[out] obj The random number generator object
* @return The status of the init request
*/
cy_rslt_t cyhal_trng_init(cyhal_trng_t *obj);
/** Release the random number generator.
*
* @param[in,out] obj The random number generator object
*/
void cyhal_trng_free(cyhal_trng_t *obj);
/** Generate a random number.
*
* @param[in] obj The random number generator object
* @return The random number generated
*/
uint32_t cyhal_trng_generate(const cyhal_trng_t *obj);
/** \} group_hal_trng_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_trng */

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/***************************************************************************//**
* \file cyhal_trng_impl.h
*
* \brief
* Provides an implementation of the Cypress TRNG HAL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#pragma once
#include "cyhal_trng.h"
#if defined(CY_IP_MXCRYPTO)
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/* Initialization polynomial values for True Random Number Generator */
#define CYHAL_GARO31_INITSTATE (0x04c11db7UL)
#define CYHAL_FIRO31_INITSTATE (0x04c11db7UL)
#define MAX_TRNG_BIT_SIZE (32UL)
static inline uint32_t cyhal_trng_generate_internal(const cyhal_trng_t *obj)
{
CY_ASSERT(NULL != obj);
uint32_t value;
cy_en_crypto_status_t status = Cy_Crypto_Core_Trng(
obj->base, CYHAL_GARO31_INITSTATE, CYHAL_FIRO31_INITSTATE, MAX_TRNG_BIT_SIZE, &value);
(void)status;
CY_ASSERT(CY_CRYPTO_SUCCESS == status);
return value;
}
#define cyhal_trng_generate(obj) cyhal_trng_generate_internal(obj)
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* defined(CY_IP_MXCRYPTO) */

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/***************************************************************************//**
* \file cyhal_uart.h
*
* \brief
* Provides a high level interface for interacting with the Cypress UART.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_uart UART (Universal Asynchronous Receiver-Transmitter)
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress UART.
*
* \defgroup group_hal_uart_macros Macros
* \defgroup group_hal_uart_functions Functions
* \defgroup group_hal_uart_data_structures Data Structures
* \defgroup group_hal_uart_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hw_types.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_uart_macros
* \{
*/
/** The requested resource type is invalid */
#define CYHAL_UART_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 0))
/** Failed to confiugre power management callback */
#define CYHAL_UART_RSLT_ERR_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 1))
/** The getc call timed out with no received data */
#define CY_RSLT_ERR_CSP_UART_GETC_TIMEOUT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_UART, 2))
/** The actual baud rate is greater than 10% off the requested baud rate */
#define CY_RSLT_WRN_CSP_UART_BAUD_TOLERANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_UART, 3))
/** The baud rate to set to if no clock is specfied in the init function */
#define CYHAL_UART_DEFAULT_BAUD 115200
/** The maximum allowable difference between baud requested and actual baud **/
#define CYHAL_UART_MAX_BAUD_PERCENT_DIFFERENCE 10
/** \} group_hal_uart_macros */
/**
* \addtogroup group_hal_uart_enums
* \{
*/
/** UART Parity */
typedef enum
{
CYHAL_UART_PARITY_NONE, /**< UART has no parity check */
CYHAL_UART_PARITY_EVEN, /**< UART has even parity check */
CYHAL_UART_PARITY_ODD, /**< UART has odd parity check */
} cyhal_uart_parity_t;
/** Enum to enable/disable/report interrupt cause flags. */
typedef enum
{
CYHAL_UART_IRQ_NONE = 0, //!< Disable all interrupt call backs
CYHAL_UART_IRQ_TX_TRANSMIT_IN_FIFO = 1 << 1, //!< All tx data from transmit has been moved to uart FIFO
CYHAL_UART_IRQ_TX_DONE = 1 << 2, //!< All tx data has been transmitted
CYHAL_UART_IRQ_TX_ERROR = 1 << 3, //!< An error occurred in tx
CYHAL_UART_IRQ_RX_FULL = 1 << 4, //!< The rx software buffer is full, additional data are store into fifo buffer.
CYHAL_UART_IRQ_RX_DONE = 1 << 5, //!< All rx data has been received
CYHAL_UART_IRQ_RX_ERROR = 1 << 6, //!< An error occurred in rx
CYHAL_UART_IRQ_RX_NOT_EMPTY = 1 << 7, //!< The rx hardware buffer is not empty
CYHAL_UART_IRQ_TX_EMPTY = 1 << 8, //!< The tx hardware buffer is empty
} cyhal_uart_irq_event_t;
/** \} group_hal_uart_enums */
/**
* \addtogroup group_hal_uart_data_structures
* \{
*/
/** Initial UART configuration */
typedef struct
{
uint32_t data_bits; //!< The number of start bits
uint32_t stop_bits; //!< The number of stop bits
cyhal_uart_parity_t parity; //!< The parity
uint8_t *rx_buffer; //!< The rx software buffer pointer, if NULL, no rx software buffer will be used
uint32_t rx_buffer_size; //!< The number of bytes in the rx software buffer
} cyhal_uart_cfg_t;
/** UART callback function type */
typedef void (*cyhal_uart_irq_handler_t)(void *handler_arg, cyhal_uart_irq_event_t event);
/** \} group_hal_uart_data_structures */
/**
* \addtogroup group_hal_uart_functions
* \{
*/
/** Initialize the uart peripheral. It sets the default parameters for uart
* peripheral, and configures its specifieds pins.
*
* @param[out] obj The uart object
* @param[in] tx The TX pin name, if no TX pin use NC
* @param[in] rx The RX pin name, if no RX pin use NC
* @param[in] clk The clock to use can be shared, if not provided a new clock will be,
* allocated and the default baud rate set
* @param[in] cfg The uart configuration data for data bits, stop bits and parity,
* if not provided, default values of (8, 1, none) will be used
* @return The status of the init request
*/
cy_rslt_t cyhal_uart_init(cyhal_uart_t *obj, cyhal_gpio_t tx, cyhal_gpio_t rx, const cyhal_clock_divider_t *clk, const cyhal_uart_cfg_t *cfg);
/** Release the uart peripheral, not currently invoked. It requires further
* resource management.
*
* @param[in,out] obj The uart object
*/
void cyhal_uart_free(cyhal_uart_t *obj);
/** Configure the baud rate
*
* @param[in,out] obj The uart object
* @param[in] baudrate The baud rate to be configured
* @param[out] actualbaud The actual baud rate achieved by the HAL
* Specify NULL if you do not want this information.
* @return The status of the baud request
*/
cy_rslt_t cyhal_uart_baud(cyhal_uart_t *obj, uint32_t baudrate, uint32_t *actualbaud);
/** Configure the data bits, stop bits, and parity
*
* @param[in,out] obj The uart object
* @param[in] cfg The uart configuration data for data bits, stop bits and parity.
* rx_buffer and rx_buffer_size are ignored.
* @return The status of the format request
*/
cy_rslt_t cyhal_uart_format(cyhal_uart_t *obj, const cyhal_uart_cfg_t *cfg);
/** Get character. This is a blocking call, waiting for a character
*
* @param[in] obj The uart object
* @param[out] value The value read from the serial port
* @param[in] timeout The time in ms to spend attempting to receive from serial port
* timeout = zero is wait forever
* @return The status of the getc request
*/
cy_rslt_t cyhal_uart_getc(cyhal_uart_t *obj, uint8_t *value, uint32_t timeout);
/** Send a character. This is a blocking call, waiting for a peripheral to be available
* for writing
*
* @param[in] obj The uart object
* @param[in] value The character to be sent
* @return The status of the putc request
*/
cy_rslt_t cyhal_uart_putc(cyhal_uart_t *obj, uint32_t value);
/** Check the number of bytes avaialable to read from the receive buffers
*
* @param[in] obj The uart object
* @return The number of readable bytes
*/
uint32_t cyhal_uart_readable(cyhal_uart_t *obj);
/** Check the number of bytes than can be written to the transmit buffer
*
* @param[in] obj The uart object
* @return The number of bytes that can be written
*/
uint32_t cyhal_uart_writable(cyhal_uart_t *obj);
/** Clear the uart peripheral buffers
*
* @param[in] obj The uart object
* @return The status of the clear request
*/
cy_rslt_t cyhal_uart_clear(cyhal_uart_t *obj);
/** Configure the uart for the flow control. It sets flow control in the hardware
* if a uart peripheral supports it, otherwise software emulation is used.
*
* @param[in,out] obj The uart object
* @param[in] cts The TX pin name
* @param[in] rts The RX pin name
* @return The status of the init_flow_control request
*/
cy_rslt_t cyhal_uart_set_flow_control(cyhal_uart_t *obj, cyhal_gpio_t cts, cyhal_gpio_t rts);
/** Begin synchronous TX transfer. The used buffer is specified in the uart object,
* tx_buff
*
* @param[in] obj The uart object
* @param[in] tx The transmit buffer
* @param[in,out] tx_length [in] The number of bytes to transmit, [out] number actually transmitted
* @return The status of the tx request
*/
cy_rslt_t cyhal_uart_tx(cyhal_uart_t *obj, void *tx, size_t *tx_length);
/** Begin synchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the uart object - rx_buff
*
* @param[in] obj The uart object
* @param[in] rx The receive buffer
* @param[in,out] rx_length [in] The number of bytes to receive, [out] number actually received
* @return The status of the rx request
*/
cy_rslt_t cyhal_uart_rx(cyhal_uart_t *obj, void *rx, size_t *rx_length);
/** Begin asynchronous TX transfer. The transmit buffer is a user defined buffer that will be
* sent on the uart. The user must register a callback with cyhal_uart_irq_register_irq. If
* desired, TX callback events can be enabled using cyhal_uart_irq_enable with the appropriate
* events.
*
* @param[in] obj The uart object
* @param[in] tx The transmit buffer
* @param[in] length The number of bytes to transmit
* @return The status of the tx_async request
*/
cy_rslt_t cyhal_uart_tx_async(cyhal_uart_t *obj, void *tx, size_t length);
/** Begin asynchronous RX transfer. Recevied data is placed in the user specified buffer.
* The user must register a callback with cyhal_uart_irq_register_irq. RX callback events
* can be enabled using cyhal_uart_irq_enable with the appropriate events.
*
* @param[in] obj The uart object
* @param[out] rx The user specified receive buffer
* @param[in] length The number of bytes to receive
* @return The status of the rx_async request
*/
cy_rslt_t cyhal_uart_rx_async(cyhal_uart_t *obj, void *rx, size_t length);
/** Attempts to determine if the uart peripheral is already in use for TX
*
* @param[in] obj The uart object
* @return Is the TX channel active
*/
bool cyhal_uart_is_tx_active(cyhal_uart_t *obj);
/** Attempts to determine if the uart peripheral is already in use for RX
*
* @param[in] obj The uart object
* @return Is the RX channel active
*/
bool cyhal_uart_is_rx_active(cyhal_uart_t *obj);
/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flushes the TX hardware buffer if TX FIFO is used
*
* @param[in] obj The uart object
* @return The status of the tx_abort request
*/
cy_rslt_t cyhal_uart_tx_abort(cyhal_uart_t *obj);
/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
* flushes the RX hardware buffer if RX FIFO is used
*
* @param[in] obj The uart object
* @return The status of the rx_abort request
*/
cy_rslt_t cyhal_uart_rx_abort(cyhal_uart_t *obj);
/** The uart interrupt handler registration
*
* @param[in] obj The uart object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
* @param[in] handler_arg Generic argument that will be provided to the handler when called
*/
void cyhal_uart_register_irq(cyhal_uart_t *obj, cyhal_uart_irq_handler_t handler, void *handler_arg);
/** Configure uart interrupt. This function is used for word-approach
*
* @param[in] obj The uart object
* @param[in] event The uart IRQ type, this argument supports the bitwise-or of multiple enum flag values
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_uart_irq_enable(cyhal_uart_t *obj, cyhal_uart_irq_event_t event, bool enable);
/** \} group_hal_uart_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_uart */

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/***************************************************************************//**
* \file cyhal_usb_dev.h
*
* \brief
* Provides a high level interface for interacting with the Cypress USB Device.
* This interface abstracts out the chip specific details.
* If any chip specific functionality is necessary, or performance is critical
* the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_usb_dev USB Device
* \ingroup group_hal
* \{
* High level interface for interacting with the Cypress USB Device.
*
* \defgroup group_hal_usb_dev_macros Macros
* \defgroup group_hal_usb_dev_functions Functions
* \defgroup group_hal_usb_dev_data_structures Data Structures
* \defgroup group_hal_usb_dev_enums Enumerated Types
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "cy_result.h"
#include "cyhal_hwmgr.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_usb_dev_macros
* \{
*/
/** The usb error */
#define CYHAL_USB_DEV_RSLT_ERR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 0))
/** The driver configuration is not supported by the HAL */
#define CYHAL_USB_DEV_RSLT_ERR_BAD_DRV_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 1))
/** The configuration of USB clock failed */
#define CYHAL_USB_DEV_RSLT_ERR_CLK_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 2))
/** Returns true if endpoint direction is IN */
#define CYHAL_USB_DEV_IS_IN_EP(endpoint) (0U != (0x80U & (uint32_t) (endpoint)))
/** Returns endpoint number (type uint32_t) */
#define CYHAL_USB_DEV_GET_EP_NUM(endpoint) ((uint32_t) (endpoint) & 0x0FU)
/** Returns endpoint index (type uint32_t) */
#define CYHAL_USB_DEV_GET_EP_IDX(endpoint) (CYHAL_USB_DEV_GET_EP_NUM(endpoint) - 1U)
/** \} group_hal_usb_dev_macros */
/**
* \addtogroup group_hal_usb_dev_enums
* \{
*/
/** USB Device Endpoints types */
typedef enum
{
CYHAL_USB_DEV_EP_TYPE_CTRL = 0,
CYHAL_USB_DEV_EP_TYPE_ISO = 1,
CYHAL_USB_DEV_EP_TYPE_BULK = 2,
CYHAL_USB_DEV_EP_TYPE_INT = 3
} cyhal_usb_dev_ep_type_t;
/** Service Callback Events */
typedef enum
{
CYHAL_USB_DEV_EVENT_BUS_RESET, /**< Callback hooked to bus reset interrupt */
CYHAL_USB_DEV_EVENT_EP0_SETUP, /**< Callback hooked to endpoint 0 SETUP packet interrupt */
CYHAL_USB_DEV_EVENT_EP0_IN, /**< Callback hooked to endpoint 0 IN packet interrupt */
CYHAL_USB_DEV_EVENT_EP0_OUT, /**< Callback hooked to endpoint 0 OUT packet interrupt */
} cyhal_usb_dev_event_t;
/** \} group_hal_usb_dev_enums */
/**
* \addtogroup group_hal_usb_dev_data_structures
* \{
*/
/** USB endpoint address (it consists from endpoint number and direction) */
typedef uint8_t cyhal_usb_dev_ep_t;
/** Handler for USB Device interrupt */
typedef void (*cyhal_usb_dev_irq_handler_t)(void);
/** Handler for the transfer completion event for data endpoints (not applicable for endpoint 0)*/
typedef void (* cyhal_usb_dev_endpoint_handler_t)(cyhal_usb_dev_ep_t endpoint);
/** Handler for the events for USB Device */
typedef void (*cyhal_usb_dev_event_handler_t)(void);
/** Handler for the events for USB Device */
typedef void (*cyhal_usb_dev_sof_handler_t)(uint32_t frame_number);
/** \} group_hal_usb_dev_data_structures */
/**
* \addtogroup group_hal_usb_dev_functions
* \{
*/
/**
* Initialize this USBPhy instance.
*
* @param[in,out] obj The usb device object
* @param[in] dp The D+ pin to initialize
* @param[in] dm The D- pin to initialize
* @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated
*
* @return The status of the initialization request
*/
cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk);
/**
* Power down this USBPhy instance
*
* Disable interrupts and stop sending events.
*
* @param[in,out] obj The usb device object
*/
void cyhal_usb_dev_free(cyhal_usb_dev_t *obj);
/**
* Make the USB phy visible to the USB host
*
* Enable either the D+ or D- pull-up so the host can detect
* the presence of this device.
*
* @param[in,out] obj The usb device object
*/
void cyhal_usb_dev_connect(cyhal_usb_dev_t *obj);
/**
* Detach the USB phy
*
* Disable the D+ and D- pull-up and stop responding to
* USB traffic.
*
* @param[in,out] obj The usb device object
*/
void cyhal_usb_dev_disconnect(cyhal_usb_dev_t *obj);
/**
* Set this device to the configured state
*
* Enable added endpoints if they are not enabled
* already.
*
* @param[in,out] obj The usb device object
*/
void cyhal_usb_dev_configure(cyhal_usb_dev_t *obj);
/**
* Leave the configured state
*
* This is a notification to the USBPhy indicating that the device
* is leaving the configured state. The USBPhy can disable all
* endpoints other than endpoint 0.
*
* @param[in,out] obj The usb device object
*/
void cyhal_usb_dev_unconfigure(cyhal_usb_dev_t *obj);
/**
* Configure start of frame interrupt enablement.
*
* @param[in,out] obj The usb device object
* @param[in] enable True to turn on interrupt and start calling sof callback on every frame,
* False to turn off interrupt and stop calling sof callback.
*/
void cyhal_usb_dev_sof_enable(cyhal_usb_dev_t *obj, bool enable);
/**
* Set the USBPhy's address
*
* @param[in,out] obj The usb device object
* @param[in] address This device's USB address
*/
void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address);
/**
* Get wMaxPacketSize of endpoint 0.
* The endpoint 0 has dedicated buffer.
*
* @param[in,out] obj The usb device object
*
* @return The size allocated for endpoint 0
*/
uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj);
/**
* Read the contents of the SETUP packet
*
* @param[in,out] obj The usb device object
* @param[in] buffer Buffer to fill with data
* @param[in] size Size of buffer passed in
*/
void cyhal_usb_dev_ep0_setup_read_result(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size);
/**
* Start receiving a packet of up to wMaxPacketSize on endpoint 0
*
* @param[in,out] obj The usb device object
* @param[in] buffer Buffer to fill with the data read
* @param[in] size Size of buffer
*/
void cyhal_usb_dev_ep0_read(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size);
/**
* Read the contents of a received packet
*
* @param[in,out] obj The usb device object
*
* @return Actual number of bytes that was read
*/
uint32_t cyhal_usb_dev_ep0_read_result(cyhal_usb_dev_t *obj);
/**
* Write a packet on endpoint 0
*
* @param[in,out] obj The usb device object
* @param[in] buffer Buffer fill with data to send
* @param[in] size Size of data to send
*
* @return The number of bytes that were written.
*/
uint32_t cyhal_usb_dev_ep0_write(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size);
/**
* Protocol stall on endpoint 0.
* Stall all IN and OUT packets on endpoint 0 until a SETUP packet is received.
*
* @param[in,out] obj The usb device object
*
* @note The stall is cleared automatically when a setup packet is received
*/
void cyhal_usb_dev_ep0_stall(cyhal_usb_dev_t *obj);
/**
* Configure an endpoint.
*
* @param[in,out] obj The usb device object
* @param[in] alloc True to allocates buffer for the endpoint, false to skip allocation
* @param[in] enable True to enable endpoint operation, false to skip enablement
* @param[in] endpoint Endpoint to configure and enable
* @param[in] maxPacket The maximum packet size that can be sent or received
* @param[in] type The type of endpoint (does not care when enable parameter is false)
*
* @return The status of the endpoint add request
*
* @note
* - This function cannot be used to configure endpoint 0. That must be done
* with cyhal_usb_dev_ep0_get_max_packet.
* - After endpoint was enabled it must be removed with cyhal_usb_dev_endpoint_remove
* and then enabled again.
*/
cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enable ,cyhal_usb_dev_ep_t endpoint, uint32_t maxPacket, cyhal_usb_dev_ep_type_t type);
/**
* Disable an endpoint
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to disable
*
* @return The status of the endpoint remove request
*/
cy_rslt_t cyhal_usb_dev_endpoint_remove(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint);
/**
* Perform a functional stall on the given endpoint
*
* Set the HALT feature for this endpoint so that all further
* communication is aborted.
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to stall
*
* @return The status of the endpoint stall request
*/
cy_rslt_t cyhal_usb_dev_endpoint_stall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint);
/**
* Unstall the endpoint
*
* Clear the HALT feature on this endpoint so communication can
* resume.
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to stall
*
* @return The status of the endpoint unstall request
*/
cy_rslt_t cyhal_usb_dev_endpoint_unstall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint);
/**
* Return the endpoint stall state
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to check stall state
*
* @return True if endpoint stalled, false otherwise.
*/
bool cyhal_usb_dev_endpoint_is_stalled(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint);
/**
* Start a read on the given endpoint
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to start the read on
* @param[in] data Buffer to fill with data
* @param[in] size Size of the read buffer. This must be at least
* the max packet size for this endpoint.
*
* @return The status of start a read operation
*/
cy_rslt_t cyhal_usb_dev_endpoint_read(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint8_t *data, uint32_t size);
/**
* Finish a read on the given endpoint
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to check
* @param[out] actSize Actual number of bytes that was read
*
* @return The status of a finish read
*/
cy_rslt_t cyhal_usb_dev_endpoint_read_result(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint32_t *actSize);
/**
* Start a write on the given endpoint
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to write to
* @param[in] data Buffer to write
* @param[in] size Size of data to write
*
* @return The status of a write request
*/
cy_rslt_t cyhal_usb_dev_endpoint_write(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint8_t const *data, uint32_t size);
/**
* Abort the current transfer if it has not yet been sent
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to abort the transfer on. It is implementation defined
* if this function has an effect on receive endpoints.
*
* @return The status of an abort request
*
* @note
* For the ISOC endpoints in pending state this function does not wait for
* bus activity completion because these endpoints do not have handshake and are
* always accessible to the Host. Therefore it is safe to call this function for
* ISOC endpoint when the Host will not access them during abort.
*/
cy_rslt_t cyhal_usb_dev_endpoint_abort(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint);
/** The USB Device interrupt handler registration
*
* @param[in,out] obj The usb device object
* @param[in] handler The interrupt handler function which will be invoked when the interrupt fires
*
* @return The status of the register_irq request
*/
cy_rslt_t cyhal_usb_dev_register_irq(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_handler_t handler);
/**
* Configure USB Device interrupt enablement.
*
* @param[in,out] obj The usb device object
* @param[in] enable True to turn on interrupts, False to turn off
*/
void cyhal_usb_dev_irq_enable(cyhal_usb_dev_t *obj, bool enable);
/**
* Default USB Device interrupt handler.
*
* @param[in,out] obj The usb device object
*/
void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj);
/**
* The USB Device endpoint complete callback handler registration
*
* @param[in,out] obj The usb device object
* @param[in] endpoint Endpoint to registers handler
* @param[in] handler The callback handler which will be invoked when the endpoint comp
*/
void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_handler_t handler);
/**
* The USB Device event complete callback handler registration. The events are defined by x type.
*
* @param[in,out] obj The usb device object
* @param[in] event The event that triggers the callback, see /ref cyhal_usb_dev_event_t
* @param[in] handler The callback handler which will be invoked when the interrupt fires
*/
void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_event_t event, cyhal_usb_dev_event_handler_t handler);
/**
* The USB Device start of frame (SOF) complete callback handler registration.
*
* @param[in,out] obj The usb device object
* @param[in] handler The callback handler which will be invoked when the interrupt fires
*/
void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_handler_t handler);
/** \} group_hal_usb_dev_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_usb_dev */

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/***************************************************************************//**
* \file cyhal_utils.h
*
* \brief
* Provides utility functions for working with the PSoC 6 HAL implementation.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
/**
* \addtogroup group_hal_utils PSoC 6 Utility Functions
* \ingroup group_hal_psoc6
* \{
* Utility functions for working with the PSoC 6 HAL implementation.
*
* \defgroup group_hal_utils_macros Macros
* \defgroup group_hal_utils_functions Functions
* \defgroup group_hal_utils_data_structures Data Structures
* \defgroup group_hal_utils_enums Enumerated Types
*/
#pragma once
#include "cyhal_hw_types.h"
#include "cy_utils.h"
#if defined(__cplusplus)
extern "C" {
#endif
/**
* \addtogroup group_hal_utils_macros
* \{
*/
#define CYHAL_GET_PIN(pin) ((uint8_t)(pin & 0xFFFFUL)) /**< Macro to extract the pin number */
#define CYHAL_GET_PORT(pin) ((uint8_t)((uint32_t)(pin >> 16) & 0xFFUL)) /**< Macro to extract the port number */
/** Looks up the resource block that connects to the specified pins from the provided resource pin mapping table.
* This is a convinience utility for cyhal_utils_get_resource() if the mappings is an array of known size.
*
* @param[in] pin The pin to lookup the hardware block for
* @param[in] mappings The mappings of pin to hardware block
* @return The entry for the specified pin if it exists, or null if it doesn't.
*/
#define CY_UTILS_GET_RESOURCE(pin, mappings) cyhal_utils_get_resource(pin, mappings, sizeof(mappings)/sizeof(cyhal_resource_pin_mapping_t))
/** \} group_hal_utils_macros */
/**
* \addtogroup group_hal_utils_functions
* \{
*/
/** Converts the provided gpio pin to a resource instance object
*
* @param[in] pin The pin to get a resource object for
* @return The equivilant resource instance object for the provided pin.
*/
static inline cyhal_resource_inst_t cyhal_utils_get_gpio_resource(cyhal_gpio_t pin)
{
cyhal_resource_inst_t rsc = { CYHAL_RSC_GPIO, CYHAL_GET_PORT(pin), CYHAL_GET_PIN(pin) };
return rsc;
}
/** Looks up the resource block that connects to the specified pins from the provided resource pin mapping table.
*
* @param[in] pin The pin to lookup the hardware block for
* @param[in] mappings The mappings of pin to hardware block
* @param[in] count The number of items in the mappings table
* @return The entry for the specified pin if it exists, or null if it doesn't.
*/
const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t* mappings, size_t count);
/** Disconnects any routing for the pin from the interconnect driver and then free's the pin from the hwmgr.
*
* @param[in] pin The pin to disconnect and free
*/
void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin);
/** \} group_hal_utils_functions */
#if defined(__cplusplus)
}
#endif
/** \} group_hal_utils */

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/***************************************************************************//**
* \file cyhal_psoc6_01_104_m_csp_ble.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_104_M_CSP_BLE_H_
#define _CYHAL_PSOC6_01_104_M_CSP_BLE_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_104_m_csp_ble_usb.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_104_M_CSP_BLE_USB_H_
#define _CYHAL_PSOC6_01_104_M_CSP_BLE_USB_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[66];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_USB_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_116_bga_ble.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 116-BGA-BLE package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_116_BGA_BLE_H_
#define _CYHAL_PSOC6_01_116_BGA_BLE_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_116_BGA_BLE_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_116_bga_usb.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 116-BGA-USB package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_116_BGA_USB_H_
#define _CYHAL_PSOC6_01_116_BGA_USB_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[76];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[70];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_116_BGA_USB_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_124_bga.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 124-BGA package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_124_BGA_H_
#define _CYHAL_PSOC6_01_124_BGA_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),
P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),
P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),
P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),
P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),
P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_124_BGA_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h Normal file
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@ -0,0 +1,222 @@
/***************************************************************************//**
* \file cyhal_psoc6_01_124_bga_sip.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 124-BGA-SIP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_124_BGA_SIP_H_
#define _CYHAL_PSOC6_01_124_BGA_SIP_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[82];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_124_BGA_SIP_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_43_smt.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 43-SMT package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_43_SMT_H_
#define _CYHAL_PSOC6_01_43_SMT_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_43_SMT_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_68_qfn_ble.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 68-QFN-BLE package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_68_QFN_BLE_H_
#define _CYHAL_PSOC6_01_68_QFN_BLE_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_68_QFN_BLE_H_ */
/* [] END OF FILE */

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/***************************************************************************//**
* \file cyhal_psoc6_01_80_wlcsp.h
*
* \brief
* PSoC6_01 device GPIO HAL header for 80-WLCSP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_01_80_WLCSP_H_
#define _CYHAL_PSOC6_01_80_WLCSP_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[60];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[60];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_01_80_WLCSP_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_02_100_wlcsp.h
*
* \brief
* PSoC6_02 device GPIO HAL header for 100-WLCSP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_02_100_WLCSP_H_
#define _CYHAL_PSOC6_02_100_WLCSP_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_02_100_WLCSP_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_02_124_bga.h
*
* \brief
* PSoC6_02 device GPIO HAL header for 124-BGA package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_02_124_BGA_H_
#define _CYHAL_PSOC6_02_124_BGA_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),
P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),
P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),
P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),
P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),
P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[18];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[18];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_02_124_BGA_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h Normal file
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@ -0,0 +1,244 @@
/***************************************************************************//**
* \file cyhal_psoc6_02_128_tqfp.h
*
* \brief
* PSoC6_02 device GPIO HAL header for 128-TQFP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_02_128_TQFP_H_
#define _CYHAL_PSOC6_02_128_TQFP_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0),
P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1),
P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2),
P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3),
P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4),
P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2),
P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3),
P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4),
P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5),
P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0),
P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1),
P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2),
P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2),
P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3),
P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4),
P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4),
P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5),
P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6),
P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4),
P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5),
P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6),
P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2),
P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3),
P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4),
P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0),
P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1),
P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2),
P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3),
P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4),
P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5),
P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6),
P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[17];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[100];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[100];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_02_128_TQFP_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_02_68_qfn.h
*
* \brief
* PSoC6_02 device GPIO HAL header for 68-QFN package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_02_68_QFN_H_
#define _CYHAL_PSOC6_02_68_QFN_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[52];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_02_68_QFN_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_03_100_tqfp.h
*
* \brief
* PSoC6_03 device GPIO HAL header for 100-TQFP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_03_100_TQFP_H_
#define _CYHAL_PSOC6_03_100_TQFP_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0),
P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5),
P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2),
P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6),
P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0),
P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[64];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[64];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_03_100_TQFP_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_03_49_wlcsp.h
*
* \brief
* PSoC6_03 device GPIO HAL header for 49-WLCSP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_03_49_WLCSP_H_
#define _CYHAL_PSOC6_03_49_WLCSP_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[36];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_03_49_WLCSP_H_ */
/* [] END OF FILE */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_03_68_qfn.h
*
* \brief
* PSoC6_03 device GPIO HAL header for 68-QFN package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#ifndef _CYHAL_PSOC6_03_68_QFN_H_
#define _CYHAL_PSOC6_03_68_QFN_H_
#include "cyhal_hw_resources.h"
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin))
/* Pin names */
typedef enum {
NC = (int)0xFFFFFFFF,
P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0),
P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1),
P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2),
P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3),
P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4),
P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5),
P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0),
P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1),
P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2),
P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3),
P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4),
P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5),
P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6),
P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7),
P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0),
P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1),
P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0),
P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1),
P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6),
P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7),
P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2),
P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3),
P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4),
P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5),
P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6),
P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7),
P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0),
P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1),
P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2),
P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3),
P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7),
P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0),
P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1),
P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0),
P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1),
P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2),
P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3),
P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0),
P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1),
P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2),
P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3),
P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4),
P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5),
P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0),
P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1),
P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2),
P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3),
P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4),
P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5),
P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6),
P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7),
P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6),
P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7),
USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0),
USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1),
} cyhal_gpio_t;
/* Connection type definition */
/** Represents an association between a pin and a resource */
typedef struct
{
cyhal_gpio_t pin; //!< The GPIO pin
const cyhal_resource_inst_t *inst; //!< The associated resource instance
cyhal_gpio_cfg_t cfg; //!< The DriveMode and HSIOM configuration value
} cyhal_resource_pin_mapping_t;
/* Pin connections */
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[52];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[54];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1];
extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1];
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _CYHAL_PSOC6_03_68_QFN_H_ */
/* [] END OF FILE */

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/***************************************************************************/ /**
* \file cyhal_adc.c
*
* \brief
* Provides a high level interface for interacting with the Cypress Analog/Digital
* convert. This interface abstracts out the chip specific details. If any chip
* specific functionality is necessary, or performance is critical the low level
* functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <cmsis_compiler.h>
#include "cyhal_adc.h"
#include "cyhal_analog_common.h"
#include "cyhal_gpio.h"
#include "cyhal_utils.h"
#if defined(CY_IP_MXS40PASS_SAR_INSTANCES)
#if defined(__cplusplus)
extern "C"
{
#endif
static SAR_Type *const cyhal_sar_base[] =
{
#if (CY_IP_MXS40PASS_SAR_INSTANCES == 1)
SAR,
#endif
#if (CY_IP_MXS40PASS_SAR_INSTANCES > 1)
#warning Unhandled SAR instance count
#endif
};
static const en_clk_dst_t cyhal_sar_clock[] =
{
#if (CY_IP_MXS40PASS_SAR_INSTANCES == 1)
PCLK_PASS_CLOCK_SAR,
#endif
#if (CY_IP_MXS40PASS_SAR_INSTANCES > 1)
#warning Unhandled SAR instance count
#endif
};
#define CYHAL_SAR_DEFAULT_CTRL ((uint32_t)CY_SAR_VREF_PWR_100 | (uint32_t)CY_SAR_VREF_SEL_BGR \
| (uint32_t)CY_SAR_BYPASS_CAP_DISABLE | (uint32_t)CY_SAR_NEG_SEL_VSSA_KELVIN \
| (uint32_t)CY_SAR_CTRL_NEGVREF_HW | (uint32_t)CY_SAR_CTRL_COMP_DLY_12 \
| (uint32_t)CY_SAR_COMP_PWR_100 | (uint32_t)CY_SAR_DEEPSLEEP_SARMUX_OFF \
| (uint32_t)CY_SAR_SARSEQ_SWITCH_ENABLE)
#define CYHAL_SAR_DEFAULT_SAMPLE ((uint32_t)CY_SAR_RIGHT_ALIGN | (uint32_t)CY_SAR_TRIGGER_MODE_FW_ONLY | (uint32_t)CY_SAR_SINGLE_ENDED_UNSIGNED)
#define CYHAL_SAR_DEFAULT_VREF_MV 1200UL
/** Default configuration for a generic channel; OR in a POS addr for the appropriate pin before configuring the channel */
#define CYHAL_SAR_DEFAULT_CH_CONFIG ((uint32_t)CY_SAR_POS_PORT_ADDR_SARMUX | (uint32_t)CY_SAR_CHAN_SINGLE_ENDED \
| (uint32_t)CY_SAR_CHAN_AVG_DISABLE | (uint32_t)CY_SAR_CHAN_SAMPLE_TIME_0)
const cy_stc_sar_config_t CYHAL_SAR_DEFAULT_CONFIG =
{
.ctrl = CYHAL_SAR_DEFAULT_CTRL,
.sampleCtrl = CYHAL_SAR_DEFAULT_SAMPLE,
.sampleTime01 = (10UL << CY_SAR_SAMPLE_TIME0_SHIFT), // Sample times 1, 2, and 3 are not used
.sampleTime23 = 0UL,
.rangeThres = (0UL << CY_SAR_RANGE_HIGH_SHIFT) | (0UL << CY_SAR_RANGE_LOW_SHIFT),
.rangeCond = CY_SAR_RANGE_COND_BELOW,
.chanEn = 0UL,
.chanConfig = { 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL, 0UL},
.intrMask = (uint32_t) CY_SAR_INTR_EOS_MASK,
.satIntrMask = 0UL,
.rangeIntrMask = 0UL,
.muxSwitch = 0UL,
.muxSwitchSqCtrl = 0UL,
.configRouting = true,
.vrefMvValue = CYHAL_SAR_DEFAULT_VREF_MV,
};
/*******************************************************************************
* Internal helper functions
*******************************************************************************/
static uint32_t cyhal_adc_get_mux_switch_control(cyhal_gpio_t gpio)
{
static const cy_en_sar_mux_switch_sq_ctrl_t mux_lookup[] =
{
CY_SAR_MUX_SQ_CTRL_P0,
CY_SAR_MUX_SQ_CTRL_P1,
CY_SAR_MUX_SQ_CTRL_P2,
CY_SAR_MUX_SQ_CTRL_P3,
CY_SAR_MUX_SQ_CTRL_P4,
CY_SAR_MUX_SQ_CTRL_P5,
CY_SAR_MUX_SQ_CTRL_P6,
CY_SAR_MUX_SQ_CTRL_P7
};
uint8_t pin = CYHAL_GET_PIN(gpio);
CY_ASSERT(pin < sizeof(mux_lookup)/sizeof(mux_lookup[0]));
return (uint32_t)mux_lookup[pin];
}
static uint32_t cyhal_adc_get_fw_switch_control(cyhal_gpio_t gpio, bool is_vplus)
{
static const cy_en_sar_mux_switch_fw_ctrl_t vplus_lookup[] =
{
CY_SAR_MUX_FW_P0_VPLUS,
CY_SAR_MUX_FW_P1_VPLUS,
CY_SAR_MUX_FW_P2_VPLUS,
CY_SAR_MUX_FW_P3_VPLUS,
CY_SAR_MUX_FW_P4_VPLUS,
CY_SAR_MUX_FW_P5_VPLUS,
CY_SAR_MUX_FW_P6_VPLUS,
CY_SAR_MUX_FW_P7_VPLUS
};
static const cy_en_sar_mux_switch_fw_ctrl_t vminus_lookup[] =
{
CY_SAR_MUX_FW_P0_VMINUS,
CY_SAR_MUX_FW_P1_VMINUS,
CY_SAR_MUX_FW_P2_VMINUS,
CY_SAR_MUX_FW_P3_VMINUS,
CY_SAR_MUX_FW_P4_VMINUS,
CY_SAR_MUX_FW_P5_VMINUS,
CY_SAR_MUX_FW_P6_VMINUS,
CY_SAR_MUX_FW_P7_VMINUS
};
uint8_t pin = CYHAL_GET_PIN(gpio);
CY_ASSERT(pin < sizeof(vplus_lookup)/sizeof(vplus_lookup[0]));
return (uint32_t)(is_vplus ? vplus_lookup[pin] : vminus_lookup[pin]);
}
static uint32_t cyhal_adc_get_pin_addr(cyhal_gpio_t gpio, bool is_vplus)
{
static const cy_en_sar_chan_config_pos_pin_addr_t vplus_lookup[] =
{
CY_SAR_CHAN_POS_PIN_ADDR_0,
CY_SAR_CHAN_POS_PIN_ADDR_1,
CY_SAR_CHAN_POS_PIN_ADDR_2,
CY_SAR_CHAN_POS_PIN_ADDR_3,
CY_SAR_CHAN_POS_PIN_ADDR_4,
CY_SAR_CHAN_POS_PIN_ADDR_5,
CY_SAR_CHAN_POS_PIN_ADDR_6,
CY_SAR_CHAN_POS_PIN_ADDR_7
};
static const cy_en_sar_chan_config_neg_pin_addr_t vminus_lookup[] =
{
CY_SAR_CHAN_NEG_PIN_ADDR_0,
CY_SAR_CHAN_NEG_PIN_ADDR_1,
CY_SAR_CHAN_NEG_PIN_ADDR_2,
CY_SAR_CHAN_NEG_PIN_ADDR_3,
CY_SAR_CHAN_NEG_PIN_ADDR_4,
CY_SAR_CHAN_NEG_PIN_ADDR_5,
CY_SAR_CHAN_NEG_PIN_ADDR_6,
CY_SAR_CHAN_NEG_PIN_ADDR_7
};
uint8_t pin = CYHAL_GET_PIN(gpio);
CY_ASSERT(pin < sizeof(vplus_lookup)/sizeof(vplus_lookup[0]));
return is_vplus ? (uint8_t)vplus_lookup[pin] : (uint8_t)vminus_lookup[pin];
}
/*******************************************************************************
* ADC HAL Functions
*******************************************************************************/
cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk)
{
const uint32_t DESIRED_DIVIDER = 8000000u; // 8 MHz. Required range is 1.7 - 18
if (NULL == obj || CYHAL_NC_PIN_VALUE == pin)
return CYHAL_ADC_RSLT_BAD_ARGUMENT;
memset(obj, 0, sizeof(cyhal_adc_t));
obj->base = NULL;
obj->channel_used = 0;
obj->clock.div_num = CYHAL_RSC_INVALID;
obj->resource.type = CYHAL_RSC_INVALID;
obj->dedicated_clock = false;
cy_rslt_t result;
const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_pass_sarmux_pads);
if (NULL == map)
return CYHAL_ADC_RSLT_BAD_ARGUMENT;
cyhal_resource_inst_t adc_inst = *map->inst;
if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&adc_inst)))
return result;
obj->resource = adc_inst;
obj->base = cyhal_sar_base[adc_inst.block_num];
en_clk_dst_t pclk = (en_clk_dst_t)(cyhal_sar_clock[adc_inst.block_num]);
if (NULL != clk)
{
obj->clock = *clk;
obj->dedicated_clock = false;
}
else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false)))
{
obj->dedicated_clock = true;
}
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num))
result = CYHAL_ADC_RSLT_FAILED_CLOCK;
if(obj->dedicated_clock)
{
uint32_t div = cy_PeriClkFreqHz / DESIRED_DIVIDER;
if (0 == div ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num))
{
result = CYHAL_ADC_RSLT_FAILED_CLOCK;
}
}
if (CY_RSLT_SUCCESS == result &&
!cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num))
{
cy_en_sar_status_t sar_rslt = Cy_SAR_Init(obj->base, &CYHAL_SAR_DEFAULT_CONFIG);
if(sar_rslt == CY_SAR_SUCCESS)
{
result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
}
else
{
result = CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, CY_RSLT_GET_CODE(sar_rslt));
}
}
if (result == CY_RSLT_SUCCESS)
{
Cy_SAR_SetVssaSarSeqCtrl(obj->base, CY_SAR_SWITCH_SEQ_CTRL_ENABLE);
Cy_SAR_SetVssaVminusSwitch(obj->base, CY_SAR_SWITCH_CLOSE);
cyhal_analog_init();
Cy_SAR_Enable(obj->base);
}
else
{
cyhal_adc_free(obj);
}
return result;
}
void cyhal_adc_free(cyhal_adc_t *obj)
{
if (NULL != obj && NULL != obj->base)
{
Cy_SAR_SetVssaSarSeqCtrl(obj->base, CY_SAR_SWITCH_SEQ_CTRL_DISABLE);
Cy_SAR_SetVssaVminusSwitch(obj->base, CY_SAR_SWITCH_OPEN);
Cy_SAR_Disable(obj->base);
if(obj->dedicated_clock)
{
Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
cyhal_hwmgr_free_clock(&obj->clock);
}
cyhal_analog_free();
cyhal_hwmgr_free(&obj->resource);
cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
obj->base = NULL;
}
}
/*******************************************************************************
* ADC Channel HAL Functions
*******************************************************************************/
cy_rslt_t cyhal_adc_channel_init(cyhal_adc_channel_t *obj, cyhal_adc_t* adc, cyhal_gpio_t pin)
{
if (NULL == obj || NULL == adc || CYHAL_NC_PIN_VALUE == pin)
return CYHAL_ADC_RSLT_BAD_ARGUMENT;
// Check for invalid pin or pin belonging to a different SAR
const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_pass_sarmux_pads);
if (NULL == map || map->inst->block_num != adc->resource.block_num)
return CYHAL_ADC_RSLT_BAD_ARGUMENT;
memset(obj, 0, sizeof(cyhal_adc_channel_t));
cy_rslt_t result;
// We don't need any special configuration of the pin, so just reserve it
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin);
if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&pinRsc)))
return result;
obj->pin = pin;
// Find the first available channel
uint8_t chosen_channel = __CLZ(__RBIT(~adc->channel_used));
if(chosen_channel >= CY_SAR_MAX_NUM_CHANNELS) // No channels available
result = CYHAL_ADC_RSLT_NO_CHANNELS;
else
{
// Don't set the ADC until here so that free knows whether we have allocated
// the channel on the parent ADC instance (and therefore doesn't try to free it if
// something fails further up)
obj->adc = adc;
obj->channel_idx = chosen_channel;
obj->adc->channel_used |= 1U << chosen_channel;
}
// The current version only supports single-ended channels, so always set the vplus switch
uint32_t fw_ctrl = cyhal_adc_get_fw_switch_control(pin, true);
uint32_t mux_ctrl = cyhal_adc_get_mux_switch_control(pin);
Cy_SAR_SetAnalogSwitch(obj->adc->base, CY_SAR_MUX_SWITCH0, fw_ctrl, CY_SAR_SWITCH_CLOSE);
Cy_SAR_SetSwitchSarSeqCtrl(obj->adc->base, mux_ctrl, CY_SAR_SWITCH_SEQ_CTRL_ENABLE);
uint8_t pin_select = cyhal_adc_get_pin_addr(pin, true);
uint32_t channel_config = CYHAL_SAR_DEFAULT_CH_CONFIG | pin_select;
obj->adc->base->CHAN_CONFIG[chosen_channel] = channel_config;
return result;
}
void cyhal_adc_channel_free(cyhal_adc_channel_t *obj)
{
if(obj->adc != NULL)
{
// Disable the channel, the unconfigure it
obj->adc->channel_used &= ~(1U << obj->channel_idx);
uint32_t fw_ctrl = cyhal_adc_get_fw_switch_control(obj->pin, true);
uint32_t mux_ctrl = cyhal_adc_get_mux_switch_control(obj->pin);
Cy_SAR_SetAnalogSwitch(obj->adc->base, CY_SAR_MUX_SWITCH0, fw_ctrl, CY_SAR_SWITCH_OPEN);
Cy_SAR_SetSwitchSarSeqCtrl(obj->adc->base, mux_ctrl, CY_SAR_SWITCH_SEQ_CTRL_DISABLE);
obj->adc->base->CHAN_CONFIG[obj->channel_idx] = 0;
cyhal_gpio_free(obj->pin);
obj->adc = NULL;
}
}
uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj)
{
const uint8_t RESULT_SCALING_FACTOR = UINT16_MAX / 0xFFF; // 12-bit SAR resolution
// Enable the selected channel only, then perform an on-demand conversion
Cy_SAR_SetChanMask(obj->adc->base, 1U << obj->channel_idx);
Cy_SAR_StartConvert(obj->adc->base, CY_SAR_START_CONVERT_SINGLE_SHOT);
Cy_SAR_IsEndConversion(obj->adc->base, CY_SAR_WAIT_FOR_RESULT);
// GetResult16 returns a signed value; it is safe to cast to unsigned because
// we always configure the channel in an unsigned mode. We also need to scale
// the value up because the SAR returns a 12-bit value (we don't configure averaging
// or summing) but our result is defined to fill the full 16-bit range.
uint16_t result = (uint16_t)Cy_SAR_GetResult16(obj->adc->base, obj->channel_idx);
uint16_t scaled_result = result * RESULT_SCALING_FACTOR;
return scaled_result;
}
#if defined(__cplusplus)
}
#endif
#endif /* defined(CY_IP_MXS40PASS_SAR_INSTANCES) */

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/***************************************************************************//**
* \file cyhal_analog_common.c
*
* \brief
* Provides common functionality that needs to be shared among all drivers that
* interact with the Programmable Analog Subsystem.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_pdl.h"
#if defined(CY_IP_MXS40PASS_INSTANCES)
#if defined(__cplusplus)
extern "C"
{
#endif
static uint16_t cyhal_analog_ref_count = 0;
void cyhal_analog_init()
{
if(cyhal_analog_ref_count == 0)
{
Cy_SysAnalog_Init(&Cy_SysAnalog_Fast_Local);
Cy_SysAnalog_Enable();
}
++cyhal_analog_ref_count;
}
void cyhal_analog_free()
{
CY_ASSERT(cyhal_analog_ref_count > 0);
--cyhal_analog_ref_count;
if(cyhal_analog_ref_count)
{
Cy_SysAnalog_Disable();
Cy_SysAnalog_DeInit();
}
}
#if defined(__cplusplus)
}
#endif
#endif /* defined(CY_IP_MXS40PASS_INSTANCES) */

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/*******************************************************************************
* File Name: cyhal_crc.c
*
* Description:
* Provides a high level interface for interacting with the Cypress CRC. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_crypto_core_crc.h"
#include "cyhal_crypto_common.h"
#include "cyhal_crc_impl.h"
#include "cyhal_hwmgr.h"
#if defined(CY_IP_MXCRYPTO)
/*******************************************************************************
* Functions
*******************************************************************************/
cy_rslt_t cyhal_crc_init(cyhal_crc_t *obj)
{
CY_ASSERT(NULL != obj);
memset(obj, 0, sizeof(cyhal_crc_t));
obj->resource.type = CYHAL_RSC_CRC;
return cyhal_crypto_reserve(&(obj->base), &(obj->resource));
}
void cyhal_crc_free(cyhal_crc_t *obj)
{
CY_ASSERT(NULL != obj || obj->resource.type != CYHAL_RSC_CRC);
if (obj->resource.type != CYHAL_RSC_INVALID)
{
cyhal_crypto_free(obj->base, &(obj->resource));
obj->resource.type = CYHAL_RSC_INVALID;
}
}
#endif /* defined(CY_IP_MXCRYPTO) */

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/*******************************************************************************
* File Name: cyhal_crypto_common.c
*
* Description:
* Provides a high level interface for interacting with the Cypress CRC. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_hwmgr.h"
#include "cy_crypto_core_crc.h"
#include "cyhal_crypto_common.h"
#if defined(CY_IP_MXCRYPTO)
CRYPTO_Type* CYHAL_CRYPTO_BASE_ADDRESSES[CYHAL_CRYPTO_INST_COUNT] =
{
#ifdef CRYPTO
CRYPTO,
#endif
};
cy_rslt_t cyhal_crypto_reserve(CRYPTO_Type** base, cyhal_resource_inst_t *resource)
{
cy_rslt_t result = CYHAL_HWMGR_RSLT_ERR_NONE_FREE;
for (uint32_t i = 0u; i < CYHAL_CRYPTO_INST_COUNT; i++)
{
resource->block_num = i;
result = cyhal_hwmgr_reserve(resource);
if (result == CY_RSLT_SUCCESS)
{
*base = CYHAL_CRYPTO_BASE_ADDRESSES[i];
Cy_Crypto_Core_Enable(*base);
result = cyhal_hwmgr_set_configured(resource->type, resource->block_num, resource->channel_num);
if (result == CY_RSLT_SUCCESS)
{
break;
}
else
{
cyhal_hwmgr_free(resource);
}
}
}
return result;
}
void cyhal_crypto_free(CRYPTO_Type* base, const cyhal_resource_inst_t *resource)
{
cyhal_hwmgr_set_unconfigured(resource->type, resource->block_num, resource->channel_num);
if (Cy_Crypto_Core_IsEnabled(base))
{
Cy_Crypto_Core_Disable(base);
}
cyhal_hwmgr_free(resource);
}
#endif /* defined(CY_IP_MXCRYPTO) */

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/***************************************************************************/ /**
* \file cyhal_adc.c
*
* \brief
* Provides a high level interface for interacting with the Cypress Digital/Analog converter.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <limits.h>
#include "cyhal_analog_common.h"
#include "cyhal_dac.h"
#include "cyhal_gpio.h"
#include "cyhal_utils.h"
#include "cy_pdl.h"
#if defined(CY_IP_MXS40PASS_CTDAC_INSTANCES)
#if defined(__cplusplus)
extern "C"
{
#endif
#define CYHAL_DAC_VALUE_SCALING_FACTOR (UINT16_MAX / CY_CTDAC_UNSIGNED_MAX_CODE_VALUE)
static CTDAC_Type *const cyhal_ctdac_base[] = {
#if (CY_IP_MXS40PASS_CTDAC_INSTANCES > 0)
CTDAC0,
#endif
#if (CY_IP_MXS40PASS_CTDAC_INSTANCES > 1)
CTDAC1,
#endif
#if (CY_IP_MXS40PASS_CTDAC_INSTANCES > 2)
#warning Unhandled CTDAC instance count
#endif
};
const cy_stc_ctdac_config_t CYHAL_CTDAC_DEFAULT_CONFIG =
{
.refSource = CY_CTDAC_REFSOURCE_VDDA,
.formatMode = CY_CTDAC_FORMAT_UNSIGNED,
.updateMode = CY_CTDAC_UPDATE_DIRECT_WRITE,
.deglitchMode = CY_CTDAC_DEGLITCHMODE_UNBUFFERED,
.outputMode = CY_CTDAC_OUTPUT_VALUE,
.outputBuffer = CY_CTDAC_OUTPUT_UNBUFFERED,
.deepSleep = CY_CTDAC_DEEPSLEEP_DISABLE,
.deglitchCycles = 0,
.value = 0,
.nextValue = 0,
.enableInterrupt = true,
.configClock = false,
// The following values are simply placeholders because configClock is false
.dividerType = CY_SYSCLK_DIV_8_BIT,
.dividerNum = 0,
.dividerIntValue = 0,
.dividerFracValue = 0,
};
/*******************************************************************************
* DAC HAL Functions
*******************************************************************************/
cy_rslt_t cyhal_dac_init(cyhal_dac_t *obj, cyhal_gpio_t pin)
{
if (NULL == obj || CYHAL_NC_PIN_VALUE == pin)
return CYHAL_DAC_RSLT_BAD_ARGUMENT;
obj->resource.type = CYHAL_RSC_INVALID;
obj->base = NULL;
obj->pin = CYHAL_NC_PIN_VALUE;
cy_rslt_t result;
const cyhal_resource_pin_mapping_t *map = CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_pass_ctdac_voutsw);
if (NULL == map)
return CYHAL_DAC_RSLT_BAD_ARGUMENT;
cyhal_resource_inst_t dac_inst = *map->inst;
if (CY_RSLT_SUCCESS != (result = cyhal_hwmgr_reserve(&dac_inst)))
return result;
obj->resource = dac_inst;
obj->base = cyhal_ctdac_base[dac_inst.block_num];
// We don't need any special configuration of the pin, so just reserve it
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin);
if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_reserve(&pinRsc)))
obj->pin = pin;
if (CY_RSLT_SUCCESS == result &&
!cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num))
{
cy_en_ctdac_status_t ctdac_rslt = Cy_CTDAC_Init(obj->base, &CYHAL_CTDAC_DEFAULT_CONFIG);
if(ctdac_rslt == CY_CTDAC_SUCCESS)
{
result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
}
else
{
if(ctdac_rslt == CY_CTDAC_BAD_PARAM)
result = CYHAL_DAC_RSLT_BAD_ARGUMENT;
else
result = CYHAL_DAC_RSLT_FAILED_INIT;
}
}
if (result == CY_RSLT_SUCCESS)
{
Cy_CTDAC_Enable(obj->base);
cyhal_analog_init();
}
else
{
cyhal_dac_free(obj);
}
return result;
}
void cyhal_dac_free(cyhal_dac_t *obj)
{
if (NULL != obj && NULL != obj->base)
{
Cy_CTDAC_Disable(obj->base);
cyhal_analog_free();
cyhal_hwmgr_free(&obj->resource);
cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
if(obj->pin != CYHAL_NC_PIN_VALUE)
{
cyhal_gpio_free(obj->pin);
obj->pin = CYHAL_NC_PIN_VALUE;
}
obj->base = NULL;
}
}
void cyhal_dac_write(const cyhal_dac_t *obj, uint16_t value)
{
uint16_t scaled_value = value / CYHAL_DAC_VALUE_SCALING_FACTOR;
Cy_CTDAC_SetValue(obj->base, scaled_value);
}
uint16_t cyhal_dac_read(cyhal_dac_t *obj)
{
uint16_t value = obj->base->CTDAC_VAL;
uint16_t scaled_value = value * CYHAL_DAC_VALUE_SCALING_FACTOR;
return scaled_value;
}
#if defined(__cplusplus)
}
#endif
#endif /* defined(CY_IP_MXS40PASS_CTDAC_INSTANCES) */

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/***************************************************************************//**
* \file cyhal_flash.c
*
* Description:
* Provides a high level interface for interacting with the Cypress Flash. This
* is wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_hwmgr.h"
#include "cyhal_hw_types.h"
#include "cyhal_flash.h"
#include <string.h>
#ifdef CY_IP_MXS40SRSS
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
typedef cy_en_flashdrv_status_t (*flash_operation)(uint32_t rowAddr, const uint32_t* data);
static uint8_t writeBuf[CY_FLASH_SIZEOF_ROW];
static inline bool is_in_flash(uint32_t address)
{
return (CY_FLASH_BASE <= address) && (address < (CY_FLASH_BASE + CY_FLASH_SIZE));
}
static inline bool is_in_sram(uint32_t address)
{
return (CY_SRAM_BASE <= address) && (address < (CY_SRAM_BASE + CY_SRAM_SIZE));
}
static cy_rslt_t run_flash_operation(
flash_operation operation, uint32_t address, const uint32_t* data, bool clearCache)
{
const uint32_t* buffer;
if (is_in_sram((uint32_t)data))
{
buffer = data;
}
else
{
memcpy(writeBuf, (const void *)data, CY_FLASH_SIZEOF_ROW);
buffer = (const uint32_t*)writeBuf;
}
cy_en_flashdrv_status_t status = operation(address, buffer);
if (clearCache)
{
Cy_SysLib_ClearFlashCacheAndBuffer();
}
return (cy_rslt_t)status;
}
cy_rslt_t cyhal_flash_init(cyhal_flash_t *obj)
{
return CY_RSLT_SUCCESS;
}
void cyhal_flash_free(cyhal_flash_t *obj)
{
CY_ASSERT(NULL != obj);
}
void cyhal_flash_get_info(const cyhal_flash_t *obj, cyhal_flash_info_t *info)
{
CY_ASSERT(NULL != obj);
info->start_address = CY_FLASH_BASE;
info->size = CY_FLASH_SIZE;
info->sector_size = CY_FLASH_SIZEOF_ROW;
info->page_size = CY_FLASH_SIZEOF_ROW;
info->erase_value = 0x00U;
}
cy_rslt_t cyhal_flash_read(cyhal_flash_t *obj, uint32_t address, uint8_t *data, size_t size)
{
CY_ASSERT(NULL != obj);
if (address < CY_FLASH_BASE || (address + size) > (CY_FLASH_BASE + CY_FLASH_SIZE))
{
return CYHAL_FLASH_RSLT_ERR_ADDRESS;
}
memmove(data, (void *)address, size);
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_flash_erase(cyhal_flash_t *obj, uint32_t address)
{
CY_ASSERT(NULL != obj);
cy_rslt_t status = CYHAL_FLASH_RSLT_ERR_ADDRESS;
if (is_in_flash(address))
{
status = Cy_Flash_EraseRow(address);
Cy_SysLib_ClearFlashCacheAndBuffer();
}
return (status);
}
cy_rslt_t cyhal_flash_write(cyhal_flash_t *obj, uint32_t address, const uint32_t* data)
{
CY_ASSERT(NULL != obj);
cy_rslt_t status = is_in_flash(address)
? run_flash_operation(Cy_Flash_WriteRow, address, data, true)
: CYHAL_FLASH_RSLT_ERR_ADDRESS;
return (status);
}
cy_rslt_t cyhal_flash_program(cyhal_flash_t *obj, uint32_t address, const uint32_t *data)
{
CY_ASSERT(NULL != obj);
cy_rslt_t status = is_in_flash(address)
? run_flash_operation(Cy_Flash_ProgramRow, address, data, true)
: CYHAL_FLASH_RSLT_ERR_ADDRESS;
return (status);
}
cy_rslt_t cyhal_flash_start_erase(cyhal_flash_t *obj, uint32_t address)
{
CY_ASSERT(NULL != obj);
cy_rslt_t status = is_in_flash(address)
? Cy_Flash_StartEraseRow(address)
: CYHAL_FLASH_RSLT_ERR_ADDRESS;
return (status);
}
cy_rslt_t cyhal_flash_start_write(cyhal_flash_t *obj, uint32_t address, const uint32_t* data)
{
CY_ASSERT(NULL != obj);
cy_rslt_t status = is_in_flash(address)
? run_flash_operation(Cy_Flash_StartWrite, address, data, false)
: CYHAL_FLASH_RSLT_ERR_ADDRESS;
return (status);
}
cy_rslt_t cyhal_flash_start_program(cyhal_flash_t *obj, uint32_t address, const uint32_t* data)
{
CY_ASSERT(NULL != obj);
cy_rslt_t status = is_in_flash(address)
? run_flash_operation(Cy_Flash_StartProgram, address, data, false)
: CYHAL_FLASH_RSLT_ERR_ADDRESS;
return (status);
}
bool cyhal_flash_is_operation_complete(cyhal_flash_t *obj)
{
CY_ASSERT(NULL != obj);
bool complete;
cy_rslt_t status = Cy_Flash_IsOperationComplete();
if (CY_FLASH_DRV_SUCCESS == status)
{
Cy_SysLib_ClearFlashCacheAndBuffer();
complete = true;
}
else
{
complete = false;
}
return complete;
}
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* CY_IP_MXS40SRSS */

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/***************************************************************************//**
* \file cyhal_gpio.c
*
* Description:
* Provides a high level interface for interacting with the Cypress GPIO. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_gpio_impl.h"
#include "cyhal_hwmgr.h"
#ifdef CY_IP_MXS40IOSS
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*******************************************************************************
* Internal
*******************************************************************************/
#define CYHAL_DIRECTION_INPUT_MASK (0x08UL) /**< Mask to enable the input buffer */
#define CYHAL_DIRECTION_OUTPUT_MASK (0x07UL) /**< Mask to disable the input buffer */
/* Callback array for GPIO interrupts */
static cyhal_gpio_irq_handler_t hal_gpio_callbacks[IOSS_GPIO_GPIO_PORT_NR][CY_GPIO_PINS_MAX];
static void *hal_gpio_callback_args[IOSS_GPIO_GPIO_PORT_NR][CY_GPIO_PINS_MAX];
/*******************************************************************************
* Dispatcher Interrrupt Service Routine
*******************************************************************************/
static void ioss_interrupts_dispatcher_IRQHandler(uint32_t port)
{
GPIO_PRT_Type *portAddr = Cy_GPIO_PortToAddr(port);
for (uint8_t cnt = 0u; cnt < CY_GPIO_PINS_MAX; cnt++)
{
if (Cy_GPIO_GetInterruptStatusMasked(portAddr, cnt))
{
if (hal_gpio_callbacks[port][cnt] != NULL)
{
/* Call registered callbacks here */
cyhal_gpio_irq_event_t event, edge = (cyhal_gpio_irq_event_t)Cy_GPIO_GetInterruptEdge(portAddr, cnt);
switch (edge)
{
case CYHAL_GPIO_IRQ_NONE:
case CYHAL_GPIO_IRQ_RISE:
case CYHAL_GPIO_IRQ_FALL:
event = edge;
break;
default:
event = Cy_GPIO_Read(portAddr, cnt) != 0 ? CYHAL_GPIO_IRQ_RISE : CYHAL_GPIO_IRQ_FALL;
break;
}
(void)(hal_gpio_callbacks[port][cnt])(hal_gpio_callback_args[port][cnt], event);
}
Cy_GPIO_ClearInterrupt(portAddr, cnt);
}
}
}
/*******************************************************************************
* (Internal) Interrrupt Service Routines
*******************************************************************************/
static void ioss_interrupts_gpio_0_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_1_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_2_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_3_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_4_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_5_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_6_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_7_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_8_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_9_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_10_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_11_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_12_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_13_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_14_IRQHandler (void) __attribute__((unused));
static void ioss_interrupts_gpio_0_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_0);
}
static void ioss_interrupts_gpio_1_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_1);
}
static void ioss_interrupts_gpio_2_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_2);
}
static void ioss_interrupts_gpio_3_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_3);
}
static void ioss_interrupts_gpio_4_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_4);
}
static void ioss_interrupts_gpio_5_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_5);
}
static void ioss_interrupts_gpio_6_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_6);
}
static void ioss_interrupts_gpio_7_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_7);
}
static void ioss_interrupts_gpio_8_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_8);
}
static void ioss_interrupts_gpio_9_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_9);
}
static void ioss_interrupts_gpio_10_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_10);
}
static void ioss_interrupts_gpio_11_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_11);
}
static void ioss_interrupts_gpio_12_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_12);
}
static void ioss_interrupts_gpio_13_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_13);
}
static void ioss_interrupts_gpio_14_IRQHandler (void)
{
ioss_interrupts_dispatcher_IRQHandler(CYHAL_PORT_14);
}
static void (*ioss_interrupts_dispatcher_table[IOSS_GPIO_GPIO_PORT_NR])(void) =
{
#if (IOSS_GPIO_GPIO_PORT_NR > 0)
ioss_interrupts_gpio_0_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 1)
ioss_interrupts_gpio_1_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 2)
ioss_interrupts_gpio_2_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 3)
ioss_interrupts_gpio_3_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 4)
ioss_interrupts_gpio_4_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 5)
ioss_interrupts_gpio_5_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 6)
ioss_interrupts_gpio_6_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 7)
ioss_interrupts_gpio_7_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 8)
ioss_interrupts_gpio_8_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 9)
ioss_interrupts_gpio_9_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 10)
ioss_interrupts_gpio_10_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 11)
ioss_interrupts_gpio_11_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 12)
ioss_interrupts_gpio_12_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 13)
ioss_interrupts_gpio_13_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 14)
ioss_interrupts_gpio_14_IRQHandler,
#endif
#if (IOSS_GPIO_GPIO_PORT_NR > 15)
#error "Unhandled port count"
#endif
};
/*******************************************************************************
* Functions
*******************************************************************************/
cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin);
/* Mbed creates GPIOs for pins that are dedicated to other peripherals in some cases. */
#ifndef __MBED__
cy_rslt_t status = cyhal_hwmgr_reserve(&pinRsc);
#else
cy_rslt_t status = CY_RSLT_SUCCESS;
#endif
if (status == CY_RSLT_SUCCESS)
{
/* Do not check for configured for resources we do not reserve. */
#ifndef __MBED__
bool configured = cyhal_hwmgr_is_configured(pinRsc.type, pinRsc.block_num, pinRsc.channel_num);
if (!configured)
#endif
{
Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), drvMode, initVal, HSIOM_SEL_GPIO);
cyhal_gpio_direction(pin, direction); //always returns success
status = cyhal_hwmgr_set_configured(pinRsc.type, pinRsc.block_num, pinRsc.channel_num);
}
}
return status;
}
void cyhal_gpio_free(cyhal_gpio_t pin)
{
if (pin != CYHAL_NC_PIN_VALUE)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin);
Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), CYHAL_GPIO_DRIVE_ANALOG, 0UL, HSIOM_SEL_GPIO);
cyhal_hwmgr_set_unconfigured(pinRsc.type, pinRsc.block_num, pinRsc.channel_num);
/* Do not attempt to free the resource we don't reserve in mbed. */
#ifndef __MBED__
cyhal_hwmgr_free(&pinRsc);
#endif
}
}
cy_rslt_t cyhal_gpio_direction(cyhal_gpio_t pin, cyhal_gpio_direction_t direction)
{
uint32_t drvMode = Cy_GPIO_GetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin));
if ((direction == CYHAL_GPIO_DIR_INPUT) | (direction == CYHAL_GPIO_DIR_BIDIRECTIONAL))
{
Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (drvMode | CYHAL_DIRECTION_INPUT_MASK));
}
else
{
Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (drvMode & CYHAL_DIRECTION_OUTPUT_MASK));
}
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_gpio_drivemode(cyhal_gpio_t pin, cyhal_gpio_drive_mode_t drvMode)
{
uint32_t inputBuf = Cy_GPIO_GetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin)) & CYHAL_DIRECTION_INPUT_MASK;
Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), drvMode | inputBuf);
return CY_RSLT_SUCCESS;
}
void cyhal_gpio_register_irq(cyhal_gpio_t pin, uint8_t intrPriority, cyhal_gpio_irq_handler_t handler, void *handler_arg)
{
IRQn_Type irqn = (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + CYHAL_GET_PORT(pin));
hal_gpio_callbacks[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = handler;
hal_gpio_callback_args[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = handler_arg;
/* Only enable if it's not already enabled */
if (NVIC_GetEnableIRQ(irqn) == 0)
{
cy_stc_sysint_t irqCfg = {irqn, intrPriority};
Cy_SysInt_Init(&irqCfg, ioss_interrupts_dispatcher_table[CYHAL_GET_PORT(pin)]);
NVIC_EnableIRQ(irqn);
}
else
{
NVIC_SetPriority(irqn, intrPriority);
}
}
void cyhal_gpio_irq_enable(cyhal_gpio_t pin, cyhal_gpio_irq_event_t event, bool enable)
{
Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)event);
Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)enable);
}
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* CY_IP_MXS40IOSS */

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/***************************************************************************//**
* \file cyhal_hwmgr.c
*
* \brief
* Provides a high level interface for managing hardware resources. This is
* used to track what hardware blocks are already being used so they are not over
* allocated.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_implementation.h"
#include "cmsis_compiler.h"
/*******************************************************************************
* Defines
*******************************************************************************/
#ifdef CY_IP_MXS40PASS_SAR_INSTANCES
#define CY_BLOCK_COUNT_ADC CY_IP_MXS40PASS_SAR_INSTANCES
#else
#define CY_BLOCK_COUNT_ADC 0
#endif
#ifdef CY_IP_MXBLESS_INSTANCES
#define CY_BLOCK_COUNT_BLE CY_IP_MXBLESS_INSTANCES
#else
#define CY_BLOCK_COUNT_BLE 0
#endif
#ifdef CY_IP_MXTTCANFD_INSTANCES
#define CY_BLOCK_COUNT_CAN CY_IP_MXTTCANFD_INSTANCES
#if (CY_IP_MXTTCANFD_INSTANCES == 0)
#define CY_CHANNEL_COUNT_CAN (0u)
#elif (CY_IP_MXTTCANFD_INSTANCES == 1)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 2)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 3)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 4)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 5)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 6)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 7)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 8)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 9)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES == 10)
#define CY_CHANNEL_COUNT_CAN (CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR + CANFD9_CAN_NR)
#elif (CY_IP_MXTTCANFD_INSTANCES > 10)
#warning Unhandled CAN instance count
#endif
#else
#define CY_BLOCK_COUNT_CAN 0
#define CY_CHANNEL_COUNT_CAN 0
#endif
#ifdef SRSS_NUM_CLKPATH
#define CY_BLOCK_COUNT_CLK_PATH SRSS_NUM_CLKPATH
#else
#define CY_BLOCK_COUNT_CLK_PATH 0
#endif
#define CY_BLOCK_COUNT_CLOCK 4
#define CY_CHANNEL_COUNT_CLOCK (PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR + PERI_DIV_24_5_NR)
#if defined(CY_IP_MXCRYPTO_INSTANCES)
#define CY_BLOCK_COUNT_CRC CY_IP_MXCRYPTO_INSTANCES
#elif defined(CPUSS_CRYPTO_PRESENT)
#define CY_BLOCK_COUNT_CRC 1
#else
#define CY_BLOCK_COUNT_CRC 0
#endif
#ifdef CY_IP_MXS40PASS_CTDAC_INSTANCES
#define CY_BLOCK_COUNT_DAC CY_IP_MXS40PASS_CTDAC_INSTANCES
#else
#define CY_BLOCK_COUNT_DAC 0
#endif
#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES)
#ifndef CPUSS_DMAC_CH_NR
#define CPUSS_DMAC_CH_NR (0u)
#endif
#define CY_BLOCK_COUNT_DMA 3
#define CY_CHANNEL_COUNT_DMA (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR + CPUSS_DMAC_CH_NR)
#endif
#ifdef IOSS_GPIO_GPIO_PORT_NR
#define CY_BLOCK_COUNT_GPIO IOSS_GPIO_GPIO_PORT_NR
#define CY_CHANNEL_COUNT_GPIO (8 * IOSS_GPIO_GPIO_PORT_NR)
#else
#define CY_BLOCK_COUNT_GPIO 0
#define CY_CHANNEL_COUNT_GPIO 0
#endif
#ifdef CY_IP_MXAUDIOSS_INSTANCES
#define CY_BLOCK_COUNT_I2S CY_IP_MXAUDIOSS_INSTANCES
#else
#define CY_BLOCK_COUNT_I2S 0
#endif
#ifdef CY_IP_MXLCD_INSTANCES
#define CY_BLOCK_COUNT_LCD CY_IP_MXLCD_INSTANCES
#else
#define CY_BLOCK_COUNT_LCD 0
#endif
#ifdef CY_IP_MXLPCOMP_INSTANCES
#define CY_BLOCK_COUNT_LPCOMP (2 * CY_IP_MXLPCOMP_INSTANCES)
#else
#define CY_BLOCK_COUNT_LPCOMP 0
#endif
#if defined(PASS_NR_CTBS)
#define CY_BLOCK_COUNT_OPAMP (2 * PASS_NR_CTBS)
#else
#define CY_BLOCK_COUNT_OPAMP 0
#endif
#ifdef CY_IP_MXAUDIOSS_INSTANCES
#define CY_BLOCK_COUNT_PDMPCM CY_IP_MXAUDIOSS_INSTANCES
#else
#define CY_BLOCK_COUNT_PDMPCM 0
#endif
#ifdef CY_IP_MXSMIF_INSTANCES
#define CY_BLOCK_COUNT_QSPI CY_IP_MXSMIF_INSTANCES
#else
#define CY_BLOCK_COUNT_QSPI 0
#endif
#if defined(CY_IP_MXCRYPTO_INSTANCES)
#define CY_BLOCK_COUNT_RNG CY_IP_MXCRYPTO_INSTANCES
#elif defined(CPUSS_CRYPTO_PRESENT)
#define CY_BLOCK_COUNT_RNG 1
#else
#define CY_BLOCK_COUNT_RNG 0
#endif
#ifdef CY_IP_MXS40SRSS_RTC_INSTANCES
#define CY_BLOCK_COUNT_RTC CY_IP_MXS40SRSS_RTC_INSTANCES
#else
#define CY_BLOCK_COUNT_RTC 0
#endif
#ifdef CY_IP_MXSCB_INSTANCES
#define CY_BLOCK_COUNT_SCB CY_IP_MXSCB_INSTANCES
#else
#define CY_BLOCK_COUNT_SCB 0
#endif
#ifdef CY_IP_MXSDHC_INSTANCES
#define CY_BLOCK_COUNT_SDHC CY_IP_MXSDHC_INSTANCES
#else
#define CY_BLOCK_COUNT_SDHC 0
#endif
#ifdef CY_IP_MXTCPWM_INSTANCES
#define CY_BLOCK_COUNT_TCPWM CY_IP_MXTCPWM_INSTANCES
#if (CY_IP_MXTCPWM_INSTANCES == 0)
#define CY_CHANNEL_COUNT_TCPWM (0u)
#elif (CY_IP_MXTCPWM_INSTANCES == 1)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 2)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 3)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 4)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 5)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 6)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 7)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 8)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 9)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 10)
#define CY_CHANNEL_COUNT_TCPWM (TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR + TCPWM9_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES > 10)
#warning Unhandled TCPWM instance count
#endif
#else
#define CY_BLOCK_COUNT_TCPWM 0
#define CY_CHANNEL_COUNT_TCPWM 0
#endif
#ifdef CY_IP_MXUDB_INSTANCES
#define CY_BLOCK_COUNT_UDB CY_IP_MXUDB_INSTANCES
#else
#define CY_BLOCK_COUNT_UDB 0
#endif
#ifdef CY_IP_MXUSBFS_INSTANCES
#define CY_BLOCK_COUNT_USB CY_IP_MXUSBFS_INSTANCES
#else
#define CY_BLOCK_COUNT_USB 0
#endif
#ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES
#define CY_BLOCK_COUNT_WDT CY_IP_MXS40SRSS_MCWDT_INSTANCES
#else
#define CY_BLOCK_COUNT_WDT 0
#endif
/*
All resources have an offset and a size, offsets are stored in an array
Subsequent resource offset equals the preceding offset + size
Offsets are bit indexes in the arrays that track used, configured etc.
Channel based resources have an extra array for block offsets
Note these are NOT offsets into the device's MMIO address space;
they are bit offsets into arrays that are internal to the HW mgr.
*/
#define CY_OFFSET_ADC 0
#define CY_SIZE_ADC CY_BLOCK_COUNT_ADC
#define CY_OFFSET_BLE (CY_OFFSET_ADC + CY_SIZE_ADC)
#define CY_SIZE_BLE CY_BLOCK_COUNT_BLE
#define CY_OFFSET_CAN (CY_OFFSET_BLE + CY_SIZE_BLE)
#define CY_SIZE_CAN CY_CHANNEL_COUNT_CAN
#define CY_OFFSET_CLK_PATH (CY_OFFSET_CAN + CY_SIZE_CAN)
#define CY_SIZE_CLK_PATH (CY_BLOCK_COUNT_CLK_PATH)
#define CY_OFFSET_CLOCK (CY_OFFSET_CLK_PATH + CY_SIZE_CLK_PATH)
#define CY_SIZE_CLOCK CY_CHANNEL_COUNT_CLOCK
#define CY_OFFSET_CRC (CY_OFFSET_CLOCK + CY_SIZE_CLOCK)
#define CY_SIZE_CRC CY_BLOCK_COUNT_CRC
#define CY_OFFSET_DAC (CY_OFFSET_CRC + CY_SIZE_CRC)
#define CY_SIZE_DAC CY_BLOCK_COUNT_DAC
#define CY_OFFSET_DMA (CY_OFFSET_DAC + CY_SIZE_DAC)
#define CY_SIZE_DMA CY_CHANNEL_COUNT_DMA
#define CY_OFFSET_GPIO (CY_OFFSET_DMA + CY_SIZE_DMA)
#define CY_SIZE_GPIO CY_CHANNEL_COUNT_GPIO
#define CY_OFFSET_I2S (CY_OFFSET_GPIO + CY_SIZE_GPIO)
#define CY_SIZE_I2S CY_BLOCK_COUNT_I2S
#define CY_OFFSET_LCD (CY_OFFSET_I2S + CY_SIZE_I2S)
#define CY_SIZE_LCD CY_BLOCK_COUNT_LCD
#define CY_OFFSET_LPCOMP (CY_OFFSET_LCD + CY_SIZE_LCD)
#define CY_SIZE_LPCOMP CY_BLOCK_COUNT_LPCOMP
#define CY_OFFSET_LPTIMER (CY_OFFSET_LPCOMP + CY_SIZE_LPCOMP)
#define CY_SIZE_LPTIMER CY_BLOCK_COUNT_WDT
#define CY_OFFSET_OPAMP (CY_OFFSET_LPTIMER + CY_SIZE_LPTIMER)
#define CY_SIZE_OPAMP CY_BLOCK_COUNT_OPAMP
#define CY_OFFSET_PDMPCM (CY_OFFSET_OPAMP + CY_SIZE_OPAMP)
#define CY_SIZE_PDMPCM CY_BLOCK_COUNT_PDMPCM
#define CY_OFFSET_QSPI (CY_OFFSET_PDMPCM + CY_SIZE_PDMPCM)
#define CY_SIZE_QSPI CY_BLOCK_COUNT_QSPI
#define CY_OFFSET_RNG (CY_OFFSET_QSPI + CY_SIZE_QSPI)
#define CY_SIZE_RNG CY_BLOCK_COUNT_RNG
#define CY_OFFSET_RTC (CY_OFFSET_RNG + CY_SIZE_RNG)
#define CY_SIZE_RTC CY_BLOCK_COUNT_RTC
#define CY_OFFSET_SCB (CY_OFFSET_RTC + CY_SIZE_RTC)
#define CY_SIZE_SCB CY_BLOCK_COUNT_SCB
#define CY_OFFSET_SDHC (CY_OFFSET_SCB + CY_SIZE_SCB)
#define CY_SIZE_SDHC CY_BLOCK_COUNT_SDHC
#define CY_OFFSET_TCPWM (CY_OFFSET_SDHC + CY_SIZE_SDHC)
#define CY_SIZE_TCPWM CY_CHANNEL_COUNT_TCPWM
#define CY_OFFSET_UDB (CY_OFFSET_TCPWM + CY_SIZE_TCPWM)
#define CY_SIZE_UDB CY_BLOCK_COUNT_UDB
#define CY_OFFSET_USB (CY_OFFSET_UDB + CY_SIZE_UDB)
#define CY_SIZE_USB CY_BLOCK_COUNT_USB
#define CY_TOTAL_ALLOCATABLE_ITEMS (CY_OFFSET_USB + CY_SIZE_USB)
#define CY_BYTE_NUM_SHIFT (3)
#define CY_BIT_NUM_MASK (0x07)
/*******************************************************************************
* Variables
*******************************************************************************/
static const uint8_t cyhal_block_offsets_clock[4] =
{
0, // 8-bit dividers
PERI_DIV_8_NR, // 16-bit dividers
PERI_DIV_8_NR + PERI_DIV_16_NR, // 16.5 bit dividers
PERI_DIV_8_NR + PERI_DIV_16_NR + PERI_DIV_16_5_NR, // 24.5 bit dividers
};
static const uint8_t cyhal_block_offsets_dma[] =
{
0,
CPUSS_DW0_CH_NR,
CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR,
};
static const uint8_t cyhal_block_offsets_gpio[] =
{
0, 8, 16, 24, 32, 40, 48, 56, 64, 72, 80, 88, 96, 104, 112, 120,
};
static const uint8_t cyhal_block_offsets_can[] =
{
#ifdef CY_IP_MXTTCANFD_INSTANCES
#if (CY_IP_MXTTCANFD_INSTANCES > 0)
0,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 1)
CANFD0_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 2)
CANFD0_CAN_NR + CANFD1_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 3)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 4)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 5)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 6)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 7)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 8)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 9)
CANFD0_CAN_NR + CANFD1_CAN_NR + CANFD2_CAN_NR + CANFD3_CAN_NR + CANFD4_CAN_NR + CANFD5_CAN_NR + CANFD6_CAN_NR + CANFD7_CAN_NR + CANFD8_CAN_NR,
#endif
#if (CY_IP_MXTTCANFD_INSTANCES > 10)
#warning Unhandled CAN instance count
#endif
#else
0
#endif
};
static const uint8_t cyhal_block_offsets_tcpwm[] =
{
#ifdef CY_IP_MXTCPWM_INSTANCES
#if (CY_IP_MXTCPWM_INSTANCES > 0)
0,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 1)
TCPWM0_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 2)
TCPWM0_CNT_NR + TCPWM1_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 3)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 4)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 5)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 6)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 7)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 8)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 9)
TCPWM0_CNT_NR + TCPWM1_CNT_NR + TCPWM2_CNT_NR + TCPWM3_CNT_NR + TCPWM4_CNT_NR + TCPWM5_CNT_NR + TCPWM6_CNT_NR + TCPWM7_CNT_NR + TCPWM8_CNT_NR,
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 10)
#warning Unhandled TCPWM instance count
#endif
#else
0
#endif
};
static uint8_t cyhal_used[(CY_TOTAL_ALLOCATABLE_ITEMS + 7) / 8] = {0};
static uint8_t cyhal_configured[(CY_TOTAL_ALLOCATABLE_ITEMS + 7) / 8] = {0};
/** Array of pin to resource mappings, provided by the BSP. Must be terminated with a CYHAL_RSC_INVALID entry */
extern cyhal_resource_pin_mapping_t* cyhal_resource_pin_mapping;
// Note: the ordering here needs to be parallel to that of cyhal_resource_t
static const uint16_t cyhal_resource_offsets[] =
{
CY_OFFSET_ADC,
CY_OFFSET_BLE,
CY_OFFSET_CAN,
CY_OFFSET_CLK_PATH,
CY_OFFSET_CLOCK,
CY_OFFSET_CRC,
CY_OFFSET_DAC,
CY_OFFSET_DMA,
CY_OFFSET_GPIO,
CY_OFFSET_I2S,
CY_OFFSET_LCD,
CY_OFFSET_LPCOMP,
CY_OFFSET_LPTIMER,
CY_OFFSET_OPAMP,
CY_OFFSET_PDMPCM,
CY_OFFSET_QSPI,
CY_OFFSET_RNG,
CY_OFFSET_RTC,
CY_OFFSET_SCB,
CY_OFFSET_SDHC,
CY_OFFSET_TCPWM,
CY_OFFSET_UDB,
CY_OFFSET_USB,
};
static const uint32_t cyhal_has_channels =
(1 << CYHAL_RSC_CAN) |
(1 << CYHAL_RSC_CLOCK) |
(1 << CYHAL_RSC_DMA) |
(1 << CYHAL_RSC_GPIO) |
(1 << CYHAL_RSC_TCPWM) ;
/*
* This function is designed to verify that the number of valid resources in the cyhal_resource_t
* enum and the number entries in the cyhal_resource_offsets array are identical. Any mismatch
* between the two will lead to runtime failures. This will produce a divide by 0 error if they
* get of of sync.
* NOTE: This function should never be called, it is only for a compile time error check
* NOTE: The Supress is to temporaraly disable the IAR warning about an uncalled function
*/
static inline void check_array_size() __attribute__ ((deprecated));
#if __ICCARM__
#pragma diag_suppress=Pe177
#endif
static inline void check_array_size()
{
uint32_t dummy = 1 / (sizeof(cyhal_resource_offsets) == (sizeof(uint16_t) * CYHAL_RSC_INVALID));
(void)dummy;
}
#if __ICCARM__
#pragma diag_default=Pe177
#endif
/*******************************************************************************
* Utility helper functions
*******************************************************************************/
static inline uint16_t cyhal_uses_channels(cyhal_resource_t type)
{
return (cyhal_has_channels & (1 << type)) > 0;
}
static inline uint16_t cyhal_get_resource_offset(cyhal_resource_t type)
{
return cyhal_resource_offsets[type];
}
static inline const uint8_t* cyhal_get_block_offsets(cyhal_resource_t type)
{
switch (type)
{
case CYHAL_RSC_CAN:
return cyhal_block_offsets_can;
case CYHAL_RSC_CLOCK:
return cyhal_block_offsets_clock;
case CYHAL_RSC_DMA:
return cyhal_block_offsets_dma;
case CYHAL_RSC_GPIO:
return cyhal_block_offsets_gpio;
case CYHAL_RSC_TCPWM:
return cyhal_block_offsets_tcpwm;
default:
CY_ASSERT(false);
return NULL;
}
}
// Gets the number of block offset entries, only valid for blocks which have channels.
static inline uint8_t cyhal_get_block_offset_length(cyhal_resource_t type)
{
switch (type)
{
case CYHAL_RSC_CAN:
return sizeof(cyhal_block_offsets_can)/sizeof(cyhal_block_offsets_can[0]);
case CYHAL_RSC_CLOCK:
return sizeof(cyhal_block_offsets_clock)/sizeof(cyhal_block_offsets_clock[0]);
case CYHAL_RSC_DMA:
return sizeof(cyhal_block_offsets_dma)/sizeof(cyhal_block_offsets_dma[0]);
case CYHAL_RSC_GPIO:
return sizeof(cyhal_block_offsets_gpio)/sizeof(cyhal_block_offsets_gpio[0]);
case CYHAL_RSC_TCPWM:
return sizeof(cyhal_block_offsets_tcpwm)/sizeof(cyhal_block_offsets_tcpwm[0]);
default:
CY_ASSERT(false);
return 0;
}
}
static cy_rslt_t cyhal_get_bit_position(cyhal_resource_t type, uint8_t block, uint8_t channel, uint16_t* bitPosition)
{
uint16_t offsetRsc = cyhal_get_resource_offset(type);
// Offset that is one past the beginning of the next resource (or one past the end of the array).
// Our offset must be strictly less than that
uint16_t offsetEndOfRsc = ((1u + type) < sizeof(cyhal_resource_offsets)/sizeof(cyhal_resource_offsets[0]))
? cyhal_get_resource_offset((cyhal_resource_t)(type + 1))
: CY_TOTAL_ALLOCATABLE_ITEMS;
if (cyhal_uses_channels(type))
{
const uint8_t* blockOffsets = cyhal_get_block_offsets(type);
*bitPosition = offsetEndOfRsc;
if (blockOffsets != NULL)
{
// Offset (from the beginning of the section for this block type) that is one past the end of
// the requested block index. The channel number must be strictly less than that.
uint16_t blocks = cyhal_get_block_offset_length(type);
if (block < blocks)
{
*bitPosition = offsetRsc + blockOffsets[block] + channel;
if ((block + 1) < blocks)
{
offsetEndOfRsc = offsetRsc + blockOffsets[block + 1];
}
}
}
}
else
{
*bitPosition = offsetRsc + block;
}
return (*bitPosition < offsetEndOfRsc)
? CY_RSLT_SUCCESS
: CYHAL_HWMGR_RSLT_ERR_INVALID;
}
static inline cy_rslt_t cyhal_is_set(const uint8_t* used, cyhal_resource_t type, uint8_t block, uint8_t channel, bool* isSet)
{
uint16_t bitPosition;
cy_rslt_t status = cyhal_get_bit_position(type, block, channel, &bitPosition);
if (status == CY_RSLT_SUCCESS)
{
uint8_t byte = bitPosition >> CY_BYTE_NUM_SHIFT;
uint8_t bit = bitPosition & CY_BIT_NUM_MASK;
*isSet = (used[byte] & (1 << bit));
}
return status;
}
static inline cy_rslt_t cyhal_set_bit(uint8_t* used, cyhal_resource_t type, uint8_t block, uint8_t channel)
{
uint16_t bitPosition;
cy_rslt_t status = cyhal_get_bit_position(type, block, channel, &bitPosition);
if (status == CY_RSLT_SUCCESS)
{
uint8_t byte = bitPosition >> CY_BYTE_NUM_SHIFT;
uint8_t bit = bitPosition & CY_BIT_NUM_MASK;
used[byte] |= (1 << bit);
}
return status;
}
static inline cy_rslt_t cyhal_clear_bit(uint8_t* used, cyhal_resource_t type, uint8_t block, uint8_t channel)
{
uint16_t bitPosition;
cy_rslt_t status = cyhal_get_bit_position(type, block, channel, &bitPosition);
if (status == CY_RSLT_SUCCESS)
{
uint8_t byte = bitPosition >> CY_BYTE_NUM_SHIFT;
uint8_t bit = bitPosition & CY_BIT_NUM_MASK;
used[byte] &= ~(1 << bit);
}
return status;
}
/*******************************************************************************
* Hardware Manager API
*******************************************************************************/
cy_rslt_t cyhal_hwmgr_init()
{
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_hwmgr_reserve(const cyhal_resource_inst_t* obj)
{
bool isSet;
uint32_t state = cyhal_system_critical_section_enter();
cy_rslt_t rslt = cyhal_is_set(cyhal_used, obj->type, obj->block_num, obj->channel_num, &isSet);
if (rslt == CY_RSLT_SUCCESS && isSet)
{
rslt = CYHAL_HWMGR_RSLT_ERR_INUSE;
}
if (rslt == CY_RSLT_SUCCESS)
{
rslt = cyhal_set_bit(cyhal_used, obj->type, obj->block_num, obj->channel_num);
}
cyhal_system_critical_section_exit(state);
return rslt;
}
void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj)
{
uint32_t state = cyhal_system_critical_section_enter();
cy_rslt_t rslt = cyhal_clear_bit(cyhal_used, obj->type, obj->block_num, obj->channel_num);
CY_ASSERT(CY_RSLT_SUCCESS == rslt);
cyhal_system_critical_section_exit(state);
}
cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj)
{
uint16_t offsetStartOfRsc = cyhal_get_resource_offset(type);
uint16_t offsetEndOfRsc = ((1u + type) < sizeof(cyhal_resource_offsets)/sizeof(cyhal_resource_offsets[0]))
? cyhal_get_resource_offset((cyhal_resource_t)(type + 1))
: CY_TOTAL_ALLOCATABLE_ITEMS;
bool usesChannels = cyhal_uses_channels(type);
uint16_t count = offsetEndOfRsc - offsetStartOfRsc;
uint8_t block = 0;
uint8_t channel = 0;
for (uint16_t i = 0; i < count; i++)
{
cyhal_resource_inst_t res = { type, block, channel };
if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(&res))
{
obj->type = type;
obj->block_num = block;
obj->channel_num = channel;
return CY_RSLT_SUCCESS;
}
else
{
if (usesChannels)
{
const uint8_t* blockOffsets = cyhal_get_block_offsets(type);
uint16_t blocks = cyhal_get_block_offset_length(type);
if ((block + 1) < blocks && blockOffsets[block + 1] == (i + 1))
{
block++;
channel = 0;
}
else
{
channel++;
}
}
else
{
block++;
}
}
}
return CYHAL_HWMGR_RSLT_ERR_NONE_FREE;
}
cy_rslt_t cyhal_hwmgr_allocate_clock(cyhal_clock_divider_t* obj, cyhal_clock_divider_types_t div, bool accept_larger)
{
static uint8_t counts[] = { PERI_DIV_8_NR, PERI_DIV_16_NR, PERI_DIV_16_5_NR, PERI_DIV_24_5_NR };
cyhal_clock_divider_types_t max_div_type = (accept_larger) ? (cyhal_clock_divider_types_t)(sizeof(counts) - 1) : div;
cy_rslt_t rslt = CYHAL_HWMGR_RSLT_ERR_NONE_FREE;
for(cyhal_clock_divider_types_t current_div = div; rslt != CY_RSLT_SUCCESS && current_div <= max_div_type; ++current_div)
{
uint8_t block = (uint8_t)current_div;
uint8_t count = counts[block];
for (int i = 0; rslt != CY_RSLT_SUCCESS && i < count; i++)
{
cyhal_resource_inst_t res = { CYHAL_RSC_CLOCK, block, i };
bool reserved = (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(&res));
if (reserved)
{
obj->div_type = current_div;
obj->div_num = i;
rslt = CY_RSLT_SUCCESS;
}
}
}
return rslt;
}
void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj)
{
cyhal_resource_inst_t res = { CYHAL_RSC_CLOCK, obj->div_type, obj->div_num };
cyhal_hwmgr_free(&res);
}
cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj)
{
return cyhal_hwmgr_allocate(CYHAL_RSC_DMA, obj);
}
cy_rslt_t cyhal_hwmgr_set_configured(cyhal_resource_t type, uint8_t block, uint8_t channel)
{
uint32_t state = cyhal_system_critical_section_enter();
cy_rslt_t status = cyhal_set_bit(cyhal_configured, type, block, channel);
cyhal_system_critical_section_exit(state);
return status;
}
cy_rslt_t cyhal_hwmgr_set_unconfigured(cyhal_resource_t type, uint8_t block, uint8_t channel)
{
uint32_t state = cyhal_system_critical_section_enter();
cy_rslt_t status = cyhal_clear_bit(cyhal_configured, type, block, channel);
cyhal_system_critical_section_exit(state);
return status;
}
bool cyhal_hwmgr_is_configured(cyhal_resource_t type, uint8_t block, uint8_t channel)
{
// This doesn't modify anything, so no need for a critical section
bool isConfigured = false;
cy_rslt_t status = cyhal_is_set(cyhal_configured, type, block, channel, &isConfigured);
CY_ASSERT(CY_RSLT_SUCCESS == status);
return isConfigured;
}

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/***************************************************************************//**
* \file cyhal_interconnect.c
*
* \brief
* Provides a high level interface for interacting with the internal digital
* routing on the chip. This is a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_interconnect.h"
#include "cyhal_hwmgr.h"
#include "cyhal_gpio_impl.h"
#ifdef CY_IP_MXPERI
/** Trigger type */
typedef enum
{
CY_TRIGGER_LEVEL, //!< Level triggered
CY_TRIGGER_EDGE, //!< Edge triggered
CY_TRIGGER_EITHER,//!< Level or edge triggered
} cyhal_trigger_type_t;
/** Number of muxes */
#define MUX_COUNT
/** Indicates that a mux output does not continue to another mux */
#define NOT_CONTINUATION 0xFF
/** Mux identiifer the one-to-one triggers */
#define ONE_TO_ONE_IDENT 0x80
/** Determines whether a mux is one-to-one */
#define IS_1TO1(muxId) (ONE_TO_ONE_IDENT == (muxId & ONE_TO_ONE_IDENT))
#define WRITE_REGISTER(muxIdx, sourceId, destId) /* TODO */
/* Maps each cyhal_destination_t to a mux index ~100b */
extern uint8_t* cyhal_dest_to_mux;
/* Maps each cyhal_destination_t to a specific output in its mux ~100b */
extern uint8_t* cyhal_mux_dest_index;
/* Number of sources for each mux ~30b */
extern uint8_t* cyhal_source_count_per_mux;
/* Mux index to a table of cyhal_source_t ~2400b (2b * 15muxes * 80sources_per_mux) (could be 1/2 the size if there are less than 255 sources) */
extern cyhal_source_t** cyhal_mux_to_sources;
/* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections ~80b*/
extern cyhal_dest_t* cyhal_intra_trigger_source;
/* Trigger type for each input ~400b */
cyhal_trigger_type_t cyhal_trigger_type_source;
/* Trigger type for each output ~100b */
cyhal_trigger_type_t cyhal_trigger_type_dest;
bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx)
{
// TODO
return false;
}
cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest)
{
uint8_t muxIdx = cyhal_dest_to_mux[dest];
uint8_t destId = dest - cyhal_mux_dest_index[dest];
uint8_t sourceCount = cyhal_source_count_per_mux[muxIdx];
if (cyhal_has_connection(muxIdx, destId))
{
return CYHAL_CONNECT_RSLT_ALREADY_CONNECTED;
}
for (uint8_t sourceId = 0; sourceId < sourceCount; sourceId++)
{
cyhal_source_t foundSource = cyhal_mux_to_sources[muxIdx][sourceId];
if (foundSource == source)
{
if (IS_1TO1(muxIdx) && sourceId != destId)
{
return CYHAL_CONNECT_RSLT_INVALID_1TO1_CONNECTION;
}
WRITE_REGISTER (muxIdx, sourceId, destId);
return CY_RSLT_SUCCESS;
}
else
{
cyhal_dest_t intraDest = cyhal_intra_trigger_source[foundSource];
if (NOT_CONTINUATION != intraDest)
{
cy_rslt_t result = cyhal_connect_trigger(source, intraDest);
if (result == CY_RSLT_SUCCESS)
{
WRITE_REGISTER (muxIdx, sourceId, destId);
return result;
}
}
}
}
return CYHAL_CONNECT_RSLT_NO_CONNECTION;
}
cy_rslt_t cyhal_connect_pin(const cyhal_resource_pin_mapping_t *pin_connection)
{
cyhal_gpio_t pin = pin_connection->pin;
GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYHAL_GET_PORT(pin));
en_hsiom_sel_t hsiom = CY_GPIO_CFG_GET_HSIOM(pin_connection->cfg);
uint8_t mode = CY_GPIO_CFG_GET_MODE(pin_connection->cfg);
Cy_GPIO_Pin_FastInit(port, CYHAL_GET_PIN(pin), mode, 1, hsiom);
// Force output to enable pulls.
switch (mode) {
case CY_GPIO_DM_PULLUP:
Cy_GPIO_Write(port, CYHAL_GET_PIN(pin), 1);
break;
case CY_GPIO_DM_PULLDOWN:
Cy_GPIO_Write(port, CYHAL_GET_PIN(pin), 0);
break;
default:
/* do nothing */
break;
}
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_disconnect_pin(cyhal_gpio_t pin)
{
GPIO_PRT_Type *port = Cy_GPIO_PortToAddr(CYHAL_GET_PORT(pin));
Cy_GPIO_Pin_FastInit(port, CYHAL_GET_PIN(pin), CY_GPIO_DM_HIGHZ, 1, HSIOM_SEL_GPIO);
return CY_RSLT_SUCCESS;
}
#endif /* CY_IP_MXPERI */

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c Normal file
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/***************************************************************************//**
* \file cy_hal_lptimer.c
*
* \brief
* Provides a high level interface for interacting with the Cypress Low-Power Timer.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cmsis_compiler.h"
#include "cy_wdt.h"
#include "cy_syslib.h"
#include "cy_sysint.h"
#include "cyhal_lptimer.h"
#include "cyhal_hwmgr.h"
#ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES
#if defined(__cplusplus)
extern "C" {
#endif
static MCWDT_STRUCT_Type * const cyhal_lptimer_base[] = {
#if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 1
MCWDT_STRUCT0,
#endif
#if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 2
MCWDT_STRUCT1,
#endif
#if CY_IP_MXS40SRSS_MCWDT_INSTANCES >= 3
#error "CY_IP_MXS40SRSS_MCWDT_INSTANCES > 2 not supported"
#endif
};
static const uint16_t CY_MCWDT_RESET_TIME_US = 62;
static const uint16_t CY_MCWDT_SETMATCH_TIME_US = 93;
typedef struct {
cyhal_lptimer_irq_handler_t handler;
void *handler_arg;
} cyhal_lptimer_irq_info_t;
static cyhal_lptimer_irq_info_t cyhal_lptimer_handlers[CY_IP_MXS40SRSS_MCWDT_INSTANCES];
static void cyhal_lptimer_dispatch(void)
{
// IPSR is numbered from 0 (0-15 are exceptions); IRQn_Type is numbered from -16
uint32_t instance = __get_IPSR() - 0x10 - (uint32_t)srss_interrupt_mcwdt_0_IRQn;
if (instance < CY_IP_MXS40SRSS_MCWDT_INSTANCES)
{
Cy_MCWDT_ClearInterrupt(cyhal_lptimer_base[instance], CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2);
cyhal_lptimer_irq_info_t *info = &cyhal_lptimer_handlers[instance];
if (NULL != info->handler)
(*info->handler)(info->handler_arg, CYHAL_LPTIMER_COMPARE_MATCH);
}
}
cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj)
{
cy_rslt_t rslt;
obj->resource.type = CYHAL_RSC_INVALID;
if (CY_RSLT_SUCCESS == (rslt = cyhal_hwmgr_allocate(CYHAL_RSC_LPTIMER, &(obj->resource))))
{
obj->base = cyhal_lptimer_base[obj->resource.block_num];
cyhal_lptimer_handlers[obj->resource.block_num].handler = NULL;
IRQn_Type irq = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
static const uint32_t CY_DEFAULT_WDT_PRIORITY = 3;
cy_stc_sysint_t irqCfg = { irq, CY_DEFAULT_WDT_PRIORITY };
if (NVIC_GetEnableIRQ(irq) ||
CY_RSLT_SUCCESS == (rslt = (cy_rslt_t)Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_dispatch)))
{
NVIC_EnableIRQ(irq);
bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
if (!configured)
{
static const cy_stc_mcwdt_config_t cfg = {
/* .c0Match = */ 0,
/* .c1Match = */ 0,
/* .c0Mode = */ CY_MCWDT_MODE_INT,
/* .c1Mode = */ CY_MCWDT_MODE_NONE,
/* .c2ToggleBit = */ 0,
/* .c2Mode = */ CY_MCWDT_MODE_NONE,
/* .c0ClearOnMatch = */ false,
/* .c1ClearOnMatch = */ false,
/* .c0c1Cascade = */ false,
/* .c1c2Cascade = */ false
};
if (CY_RSLT_SUCCESS == (rslt = (cy_rslt_t)Cy_MCWDT_Init(obj->base, &cfg)))
{
Cy_MCWDT_Enable(obj->base, CY_MCWDT_CTR0, CY_MCWDT_RESET_TIME_US);
rslt = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
}
}
}
}
if (CY_RSLT_SUCCESS != rslt)
cyhal_lptimer_free(obj);
return rslt;
}
void cyhal_lptimer_free(cyhal_lptimer_t *obj)
{
if (CYHAL_RSC_INVALID != obj->resource.type)
{
cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
cyhal_lptimer_handlers[obj->resource.block_num].handler = NULL;
obj->resource.type = CYHAL_RSC_INVALID;
}
if (NULL != obj->base)
{
Cy_MCWDT_DeInit(obj->base);
obj->base = NULL;
}
}
cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj)
{
Cy_MCWDT_ResetCounters(obj->base, CY_MCWDT_CTR0, CY_MCWDT_RESET_TIME_US);
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time)
{
Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, time, CY_MCWDT_SETMATCH_TIME_US);
Cy_MCWDT_SetClearOnMatch(obj->base, CY_MCWDT_COUNTER0, 1);
Cy_MCWDT_ResetCounters(obj->base, CY_MCWDT_CTR0, CY_MCWDT_RESET_TIME_US);
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value)
{
Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, value, 0);
return CY_RSLT_SUCCESS;
}
uint32_t cyhal_lptimer_read(const cyhal_lptimer_t *obj)
{
return Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0);
}
void cyhal_lptimer_register_irq(cyhal_lptimer_t *obj, cyhal_lptimer_irq_handler_t handler, void *handler_arg)
{
CY_ASSERT_L2(CYHAL_RSC_INVALID != obj->resource.block_num);
cyhal_lptimer_handlers[obj->resource.block_num].handler = NULL;
__DSB();
__ISB();
cyhal_lptimer_handlers[obj->resource.block_num].handler_arg = handler_arg;
__DSB();
__ISB();
cyhal_lptimer_handlers[obj->resource.block_num].handler = handler;
}
void cyhal_lptimer_irq_enable(cyhal_lptimer_t *obj, cyhal_lptimer_irq_event_t event, bool enable)
{
Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR0 : 0);
}
void cyhal_lptimer_irq_trigger(cyhal_lptimer_t *obj)
{
CY_ASSERT_L2(CYHAL_RSC_INVALID != obj->resource.block_num);
IRQn_Type irq = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num);
NVIC_SetPendingIRQ(irq);
}
#if defined(__cplusplus)
}
#endif
#endif /* CY_IP_MXS40SRSS_MCWDT_INSTANCES */

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/***************************************************************************//**
* \file cyhal_not_implemented.c
*
* \brief
* This file contains place holder functions for drivers that are not yet
* implemented but are referenced by mbed and cause build failures on some
* toolchains. As the drivers are implemented, these items need to be deleted.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_adc.h"
#include "cyhal_dac.h"
#include "cyhal_dma.h"
uint8_t* cyhal_dest_to_mux;
uint8_t* cyhal_mux_dest_index;
uint8_t* cyhal_source_count_per_mux;
cyhal_source_t** cyhal_mux_to_sources;
cyhal_dest_t* cyhal_intra_trigger_source;
cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction)
{
return CY_RSLT_SUCCESS;
}
void cyhal_dma_free(cyhal_dma_t *obj)
{
}
cy_rslt_t cyhal_dma_setup_transfer(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg)
{
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj)
{
return CY_RSLT_SUCCESS;
}
bool cyhal_dma_busy(cyhal_dma_t *obj)
{
return false;
}
void cyhal_dma_register_irq(cyhal_dma_t *obj, cyhal_dma_irq_handler_t handler, void *handler_arg)
{
}
void cyhal_dma_irq_enable(cyhal_dma_t *obj, cyhal_dma_irq_event_t event, bool enable)
{
}

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/***************************************************************************//**
* \file cyhal_pwm.c
*
* \brief
* Provides a high level interface for interacting with the Cypress PWM. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include <string.h>
#include "cyhal_pwm.h"
#include "cyhal_gpio.h"
#include "cyhal_interconnect.h"
#include "cyhal_utils.h"
#ifdef CY_IP_MXTCPWM
#if defined(__cplusplus)
extern "C" {
#endif
typedef struct {
TCPWM_Type *base;
en_clk_dst_t clock_dst;
uint32_t cnt_width;
} cyhal_internal_pwm_data_t;
static const cyhal_internal_pwm_data_t cyhal_internal_pwm_data[] = {
#ifdef TCPWM0
{TCPWM0, PCLK_TCPWM0_CLOCKS0, TCPWM0_CNT_CNT_WIDTH},
#endif
#ifdef TCPWM1
{TCPWM1, PCLK_TCPWM1_CLOCKS0, TCPWM1_CNT_CNT_WIDTH},
#endif
};
#if CY_IP_MXTCPWM_INSTANCES > 2
#error PWM driver must be updated to support more TCPWM instances
#endif
#define CYHAL_NC_PIN_VALUE_GPIO_VALUE ((cyhal_gpio_t)CYHAL_NC_PIN_VALUE)
#define CYHAL_TCPWM_MAX_WIDTH 32
static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count)
{
for (uint32_t i = 0; i < count; i++)
{
if (pin == pin_map[i].pin)
{
if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(pin_map[i].inst))
{
return &pin_map[i];
}
}
}
return NULL;
}
cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk)
{
CY_ASSERT(NULL != obj);
/* Explicitly marked not allocated resources as invalid to prevent freeing them. */
obj->resource.type = CYHAL_RSC_INVALID;
obj->pin = CYHAL_NC_PIN_VALUE_GPIO_VALUE;
obj->dedicated_clock = false;
const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t));
if (map == NULL)
{
map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line_compl, sizeof(cyhal_pin_map_tcpwm_line_compl) / sizeof(cyhal_resource_pin_mapping_t));
}
if (map == NULL)
{
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
}
obj->resource = *map->inst;
obj->base = cyhal_internal_pwm_data[obj->resource.block_num].base;
en_clk_dst_t pclk = (en_clk_dst_t)(cyhal_internal_pwm_data[obj->resource.block_num].clock_dst + obj->resource.channel_num);
cy_rslt_t result;
if (CY_RSLT_SUCCESS == (result = cyhal_gpio_init(pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true)))
{
obj->pin = pin;
if (CY_RSLT_SUCCESS == (result = cyhal_connect_pin(map)))
{
if (NULL != clk)
{
obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num));
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num))
result = CYHAL_PWM_RSLT_FAILED_CLOCK;
}
else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false)))
{
obj->dedicated_clock = true;
uint32_t div = (uint32_t)(1 << (CYHAL_TCPWM_MAX_WIDTH - cyhal_internal_pwm_data[obj->resource.block_num].cnt_width));
if (0 == div ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num))
result = CYHAL_PWM_RSLT_FAILED_CLOCK;
else
{
obj->clock_hz = cy_PeriClkFreqHz / div;
}
}
if (CY_RSLT_SUCCESS == result &&
!cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num))
{
static const cy_stc_tcpwm_pwm_config_t config =
{
/* .pwmMode = */ CY_TCPWM_PWM_MODE_PWM,
/* .clockPrescaler = */ CY_TCPWM_PWM_PRESCALER_DIVBY_1,
/* .pwmAlignment = */ CY_TCPWM_PWM_LEFT_ALIGN,
/* .deadTimeClocks = */ 0UL,
/* .runMode = */ CY_TCPWM_PWM_CONTINUOUS,
/* .period0 = */ 0UL,
/* .period1 = */ 0UL,
/* .enablePeriodSwap = */ false,
/* .compare0 = */ 0UL,
/* .compare1 = */ 0UL,
/* .enableCompareSwap = */ false,
/* .interruptSources = */ CY_TCPWM_INT_NONE,
/* .invertPWMOut = */ CY_TCPWM_PWM_INVERT_DISABLE,
/* .invertPWMOutN = */ CY_TCPWM_PWM_INVERT_ENABLE,
/* .killMode = */ CY_TCPWM_PWM_STOP_ON_KILL,
/* .swapInputMode = */ CY_TCPWM_INPUT_RISINGEDGE,
/* .swapInput = */ CY_TCPWM_INPUT_0,
/* .reloadInputMode = */ CY_TCPWM_INPUT_RISINGEDGE,
/* .reloadInput = */ CY_TCPWM_INPUT_0,
/* .startInputMode = */ CY_TCPWM_INPUT_RISINGEDGE,
/* .startInput = */ CY_TCPWM_INPUT_0,
/* .killInputMode = */ CY_TCPWM_INPUT_RISINGEDGE,
/* .killInput = */ CY_TCPWM_INPUT_0,
/* .countInputMode = */ CY_TCPWM_INPUT_LEVEL,
/* .countInput = */ CY_TCPWM_INPUT_1
};
result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config);
if (CY_TCPWM_SUCCESS == result)
{
result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
}
}
}
}
if (result == CY_RSLT_SUCCESS)
{
Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num);
}
else
{
cyhal_pwm_free(obj);
}
return result;
}
void cyhal_pwm_free(cyhal_pwm_t *obj)
{
CY_ASSERT(NULL != obj);
if (CYHAL_NC_PIN_VALUE != obj->pin)
{
cyhal_gpio_free(obj->pin);
obj->pin = CYHAL_NC_PIN_VALUE;
}
if (NULL != obj->base)
{
Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num);
cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
cyhal_hwmgr_free(&(obj->resource));
obj->base = NULL;
obj->resource.type = CYHAL_RSC_INVALID;
}
if (obj->dedicated_clock)
{
cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
CY_ASSERT(CY_SYSCLK_SUCCESS == rslt);
cyhal_hwmgr_free_clock(&(obj->clock));
obj->dedicated_clock = false;
}
}
static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare)
{
if (period < 1 || period > (uint32_t)((1 << cyhal_internal_pwm_data[obj->resource.block_num].cnt_width)) - 1)
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
if (compare > period)
compare = period;
Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, 0u);
Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->resource.channel_num, period - 1u);
Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, compare);
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_pwm_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us)
{
static const uint32_t US_PER_SEC = 1000000u;
if (NULL == obj)
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC);
uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC);
return cyhal_pwm_set_period_and_compare(obj, period, width);
}
cy_rslt_t cyhal_pwm_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz)
{
if (NULL == obj)
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1)
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
uint32_t period = obj->clock_hz / frequencyhal_hz;
uint32_t width = (uint32_t)(duty_cycle * 0.01f * period);
return cyhal_pwm_set_period_and_compare(obj, period, width);
}
cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj)
{
if (NULL == obj)
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj)
{
if (NULL == obj)
return CYHAL_PWM_RSLT_BAD_ARGUMENT;
Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
#if defined(__cplusplus)
}
#endif
#endif /* CY_IP_MXTCPWM */

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/***************************************************************************//**
* \file cyhal_rtc.c
*
* \brief
* Provides a high level interface for interacting with the Cypress Real-Time Clock.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_implementation.h"
#include "cy_rtc.h"
#ifdef CY_IP_MXS40SRSS_RTC_INSTANCES
#if defined(__cplusplus)
extern "C" {
#endif
#define CY_RTC_STATE_UNINITIALIZED 0
#define CY_RTC_STATE_ENABLED 1
#define CY_RTC_STATE_TIME_SET 2
#define CY_RTC_DEFAULT_PRIORITY 5
#define CY_TM_YEAR_BASE 1900
// Cy_RTC_DeepSleepCallback does not have a compatible signature
static cy_en_syspm_status_t cyhal_rtc_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode)
{
return Cy_RTC_DeepSleepCallback(params, mode);
}
static cy_stc_syspm_callback_params_t cyhal_rtc_pm_cb_params = {NULL, NULL};
static cy_stc_syspm_callback_t cyhal_rtc_pm_cb = {
.callback = &cyhal_rtc_syspm_callback,
.type = CY_SYSPM_DEEPSLEEP,
.callbackParams = &cyhal_rtc_pm_cb_params,
};
static cyhal_rtc_irq_handler_t cyhal_rtc_user_handler;
static void *cyhal_rtc_handler_arg;
#define CYHAL_RTC_INITIAL_CENTURY 1900
static uint16_t cyhal_rtc_century = CYHAL_RTC_INITIAL_CENTURY;
static uint8_t cyhal_rtc_initialized = CY_RTC_STATE_UNINITIALIZED;
static void cyhal_rtc_internal_handler(void)
{
Cy_RTC_Interrupt(NULL, false);
}
void Cy_RTC_Alarm1Interrupt(void)
{
if (NULL != cyhal_rtc_user_handler)
{
(*cyhal_rtc_user_handler)(cyhal_rtc_handler_arg, CYHAL_RTC_ALARM);
}
}
void Cy_RTC_CenturyInterrupt(void)
{
cyhal_rtc_century += 100;
}
cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj)
{
cy_rslt_t rslt = CY_RSLT_SUCCESS;
if (cyhal_rtc_initialized == CY_RTC_STATE_UNINITIALIZED)
{
if (Cy_RTC_IsExternalResetOccurred())
{
// Reset to default time
static const cy_stc_rtc_config_t defaultTime = {
.dayOfWeek = CY_RTC_THURSDAY,
.date = 1,
.month = 1,
.year = 70
};
Cy_RTC_SetDateAndTime(&defaultTime);
}
else
{
// Time is already set (possibly after sw reset). Assume century.
cyhal_rtc_century = 2000;
}
Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY);
Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY);
static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CY_RTC_DEFAULT_PRIORITY};
Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler);
NVIC_EnableIRQ(srss_interrupt_backup_IRQn);
Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb);
cyhal_rtc_initialized = CY_RTC_STATE_ENABLED;
}
return rslt;
}
void cyhal_rtc_free(cyhal_rtc_t *obj)
{
Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY);
}
bool cyhal_rtc_is_enabled(cyhal_rtc_t *obj)
{
return (cyhal_rtc_initialized == CY_RTC_STATE_TIME_SET);
}
cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time)
{
// The number of days that precede each month of the year, not including Fdb 29
static const uint16_t CUMULATIVE_DAYS[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334};
cy_stc_rtc_config_t dateTime;
uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
Cy_RTC_GetDateAndTime(&dateTime);
int year = dateTime.year + cyhal_rtc_century;
cyhal_system_critical_section_exit(savedIntrStatus);
time->tm_sec = dateTime.sec;
time->tm_min = dateTime.min;
time->tm_hour = dateTime.hour;
time->tm_mday = dateTime.date;
time->tm_mon = dateTime.month - 1u;
time->tm_year = year - CY_TM_YEAR_BASE;
time->tm_wday = dateTime.dayOfWeek - 1u;
time->tm_yday = CUMULATIVE_DAYS[time->tm_mon] + dateTime.date - 1u +
((dateTime.month >= 3 && Cy_RTC_IsLeapYear(year)) ? 1u : 0u);
time->tm_isdst = -1;
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time)
{
uint32_t year2digit = time->tm_year % 100;
cy_stc_rtc_config_t newtime = {
.sec = time->tm_sec,
.min = time->tm_min,
.hour = time->tm_hour,
.hrFormat = CY_RTC_24_HOURS,
.dayOfWeek = time->tm_wday + 1,
.date = time->tm_mday,
.month = time->tm_mon + 1,
.year = year2digit
};
cy_rslt_t rslt;
uint32_t retry = 0;
static const uint32_t MAX_RETRY = 10, RETRY_DELAY_MS = 1;
do {
if (retry != 0)
Cy_SysLib_Delay(RETRY_DELAY_MS);
uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
rslt = (cy_rslt_t)Cy_RTC_SetDateAndTime(&newtime);
if (rslt == CY_RSLT_SUCCESS)
cyhal_rtc_century = time->tm_year - year2digit + CY_TM_YEAR_BASE;
cyhal_system_critical_section_exit(savedIntrStatus);
++retry;
} while (rslt == CY_RTC_INVALID_STATE && retry < MAX_RETRY);
while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) { }
if (rslt == CY_RSLT_SUCCESS)
cyhal_rtc_initialized = CY_RTC_STATE_TIME_SET;
return rslt;
}
cy_rslt_t cyhal_rtc_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active)
{
// Note: the hardware does not support year matching
cy_stc_rtc_alarm_t alarm = {
.sec = time->tm_sec,
.secEn = active.en_sec ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
.min = time->tm_min,
.minEn = active.en_min ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
.hour = time->tm_hour,
.hourEn = active.en_hour ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
.dayOfWeek = time->tm_wday + 1,
.dayOfWeekEn = active.en_day ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
.date = time->tm_mday,
.dateEn = active.en_date ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
.month = time->tm_mon + 1,
.monthEn = active.en_month ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE,
.almEn = CY_RTC_ALARM_ENABLE
};
return (cy_rslt_t)Cy_RTC_SetAlarmDateAndTime(&alarm, CY_RTC_ALARM_1);
}
void cyhal_rtc_register_irq(cyhal_rtc_t *obj, cyhal_rtc_irq_handler_t handler, void *handler_arg)
{
uint32_t savedIntrStatus = cyhal_system_critical_section_enter();
cyhal_rtc_handler_arg = handler_arg;
cyhal_rtc_user_handler = handler;
cyhal_system_critical_section_exit(savedIntrStatus);
}
void cyhal_rtc_irq_enable(cyhal_rtc_t *obj, cyhal_rtc_irq_event_t event, bool enable)
{
Cy_RTC_ClearInterrupt(CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2);
Cy_RTC_SetInterruptMask((enable ? CY_RTC_INTR_ALARM1 : 0) | CY_RTC_INTR_CENTURY);
}
#if defined(__cplusplus)
}
#endif
#endif /* CY_IP_MXS40SRSS_RTC_INSTANCES */

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/***************************************************************************//**
* \file cyhal_scb_types.h
*
* \brief
* Provides a struct definitions for configuration resources in the SCB (UART, I2C, SPI).
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_scb_common.h"
#ifdef CY_IP_MXSCB
CySCB_Type* CY_SCB_BASE_ADDRESSES[CY_IP_MXSCB_INSTANCES] =
{
#ifdef SCB0
SCB0,
#endif
#ifdef SCB1
SCB1,
#endif
#ifdef SCB2
SCB2,
#endif
#ifdef SCB3
SCB3,
#endif
#ifdef SCB4
SCB4,
#endif
#ifdef SCB5
SCB5,
#endif
#ifdef SCB6
SCB6,
#endif
#ifdef SCB7
SCB7,
#endif
#ifdef SCB8
SCB8,
#endif
#ifdef SCB9
SCB9,
#endif
#ifdef SCB10
SCB10,
#endif
#ifdef SCB11
SCB11,
#endif
#ifdef SCB12
SCB12,
#endif
#ifdef SCB13
SCB13,
#endif
#ifdef SCB14
SCB14,
#endif
#ifdef SCB15
SCB15,
#endif
};
IRQn_Type CY_SCB_IRQ_N[CY_IP_MXSCB_INSTANCES] =
{
#ifdef SCB0
scb_0_interrupt_IRQn,
#endif
#ifdef SCB1
scb_1_interrupt_IRQn,
#endif
#ifdef SCB2
scb_2_interrupt_IRQn,
#endif
#ifdef SCB3
scb_3_interrupt_IRQn,
#endif
#ifdef SCB4
scb_4_interrupt_IRQn,
#endif
#ifdef SCB5
scb_5_interrupt_IRQn,
#endif
#ifdef SCB6
scb_6_interrupt_IRQn,
#endif
#ifdef SCB7
scb_7_interrupt_IRQn,
#endif
#ifdef SCB8
scb_8_interrupt_IRQn,
#endif
#ifdef SCB9
scb_9_interrupt_IRQn,
#endif
#ifdef SCB10
scb_10_interrupt_IRQn,
#endif
#ifdef SCB11
scb_11_interrupt_IRQn,
#endif
#ifdef SCB12
scb_12_interrupt_IRQn,
#endif
#ifdef SCB13
scb_13_interrupt_IRQn,
#endif
#ifdef SCB14
scb_14_interrupt_IRQn,
#endif
#ifdef SCB15
scb_15_interrupt_IRQn,
#endif
};
#endif /* CY_IP_MXSCB */

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/***************************************************************************//**
* \file cyhal_system.c
*
* \brief
* Provides a high level interface for interacting with the Cypress power
* management and system clock configuration. This interface abstracts out the
* chip specific details. If any chip specific functionality is necessary, or
* performance is critical the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_system.h"
#ifdef CY_IP_MXS40SRSS
#define HZ_PER_MHZ 1000000
cy_rslt_t cyhal_system_register_callback(cyhal_system_call_back_t *handler)
{
return Cy_SysPm_RegisterCallback(handler)
? CY_RSLT_SUCCESS
: CYHAL_SYSTEM_RSLT_ERROR;
}
cy_rslt_t cyhal_system_unregister_callback(cyhal_system_call_back_t const *handler)
{
return Cy_SysPm_UnregisterCallback(handler)
? CY_RSLT_SUCCESS
: CYHAL_SYSTEM_RSLT_ERROR;
}
uint32_t get_src_freq(cy_en_clkpath_in_sources_t source)
{
/* get the frequency of the source, i.e., the path mux input */
switch(source)
{
case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */
return CY_SYSCLK_IMO_FREQ;
case CY_SYSCLK_CLKPATH_IN_ILO: /* ILO, WCO and PILO frequencies are nominally 32.768 kHz */
case CY_SYSCLK_CLKPATH_IN_WCO:
case CY_SYSCLK_CLKPATH_IN_PILO:
return CY_SYSCLK_ILO_FREQ;
default:
return 0;
}
}
uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used)
{
*fll_pll_used = 0xff;
if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0)
{
cy_stc_fll_manual_config_t fll_config;
Cy_SysClk_FllGetConfiguration(&fll_config);
if (fll_config.outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
{
freq *= fll_config.fllMult;
freq /= fll_config.refDiv;
freq /= (fll_config.enableOutputDiv ? 2U : 1U);
*fll_pll_used = 0;
}
}
else if((uint32_t)path <= CY_SRSS_NUM_PLL)
{
cy_stc_pll_manual_config_t pll_config;
Cy_SysClk_PllGetConfiguration(path, &pll_config);
if (pll_config.outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
{
freq *= pll_config.feedbackDiv;
freq /= pll_config.referenceDiv;
freq /= pll_config.outputDiv;
*fll_pll_used = (uint8_t)path;
}
}
return freq;
}
cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq)
{
bool divider_found = false;
cy_en_clkhf_dividers_t divider;
if (target_freq == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_NO_DIVIDE;
}
else if (target_freq * 2 == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_DIVIDE_BY_2;
}
else if (target_freq * 4 == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_DIVIDE_BY_4;
}
else if (target_freq * 8 == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_DIVIDE_BY_8;
}
if (divider_found)
{
Cy_SysClk_ClkHfSetDivider(clock, divider);
Cy_SysClk_ClkHfEnable(clock);
return CY_RSLT_SUCCESS;
}
else
{
return CYHAL_SYSTEM_RSLT_NO_VALID_DIVIDER;
}
}
cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq)
{
Cy_SysClk_FllDisable();
Cy_SysClk_ClkHfSetSource(clock, CY_SYSCLK_CLKHF_IN_CLKPATH0);
Cy_SysClk_ClkPathSetSource(0, CY_SYSCLK_CLKPATH_IN_IMO);
cy_rslt_t rslt = Cy_SysClk_FllConfigure(CY_SYSCLK_IMO_FREQ, target_freq, CY_SYSCLK_FLLPLL_OUTPUT_AUTO);
if (rslt == CY_RSLT_SUCCESS)
{
// Wait up to 1 seconds for FLL to lock
rslt = Cy_SysClk_FllEnable(1000000);
}
if (rslt == CY_RSLT_SUCCESS)
{
Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE);
SystemCoreClockUpdate();
}
return rslt;
}
cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq)
{
Cy_SysClk_PllDisable(pll);
Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll));
cy_stc_pll_config_t cfg;
cfg.inputFreq = CY_SYSCLK_IMO_FREQ;
cfg.outputFreq = target_freq;
cfg.lfMode = false;
cfg.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO;
Cy_SysClk_ClkPathSetSource(pll, CY_SYSCLK_CLKPATH_IN_IMO);
cy_rslt_t rslt = Cy_SysClk_PllConfigure(pll, &cfg);
if (rslt == CY_RSLT_SUCCESS)
{
// Wait up to 1 seconds for PLL to lock
rslt = Cy_SysClk_PllEnable(pll, 1000000);
}
if (rslt == CY_RSLT_SUCCESS)
{
Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE);
SystemCoreClockUpdate();
}
return rslt;
}
/* This should be part of the PDL */
static inline bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf)
{
bool retVal = false;
if (clkHf < CY_SRSS_NUM_HFROOT)
{
retVal = _FLD2BOOL(SRSS_CLK_ROOT_SELECT_ENABLE, SRSS_CLK_ROOT_SELECT[clkHf]);
}
return (retVal);
}
cy_rslt_t cyhal_system_clock_frequency(uint8_t clock, uint32_t frequencyhal_hz)
{
cy_en_clkhf_in_sources_t path = Cy_SysClk_ClkHfGetSource((uint32_t)clock);
cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path);
uint32_t src_freq = get_src_freq(source);
if (src_freq == 0)
{
return CYHAL_SYSTEM_RSLT_SRC_CLK_DISABLED;
}
uint8_t fll_pll_used;
uint32_t clkpath_freq = get_clkpath_freq(path, src_freq, &fll_pll_used);
cy_rslt_t rslt = try_set_hf_divider(clock, clkpath_freq, frequencyhal_hz);
if (rslt == CY_RSLT_SUCCESS)
{
SystemCoreClockUpdate();
return rslt;
}
bool enabled = Cy_SysClk_ClkHfIsEnabled(clock);
if (enabled && fll_pll_used == 0)
{
return try_set_fll(clock, frequencyhal_hz);
}
else if (enabled && fll_pll_used <= SRSS_NUM_PLL)
{
return try_set_pll(clock, fll_pll_used, frequencyhal_hz);
}
else
{
// Cannot get the correct frequency. Try to allocate an FLL or PLL
cyhal_resource_inst_t inst;
rslt = cyhal_hwmgr_allocate(CYHAL_RSC_CLKPATH, &inst);
if (rslt == CY_RSLT_SUCCESS)
{
if (inst.block_num == 0)
{
rslt = try_set_fll(clock, frequencyhal_hz);
}
else if (inst.block_num <= SRSS_NUM_PLL)
{
rslt = try_set_pll(clock, inst.block_num, frequencyhal_hz);
}
else
{
// No FLL or PLL available.
rslt = CYHAL_SYSTEM_RSLT_UNABLE_TO_SET_CLK_FREQ;
}
if (!enabled && rslt == CY_RSLT_SUCCESS)
{
rslt = Cy_SysClk_ClkHfEnable(clock);
}
if (rslt != CY_RSLT_SUCCESS)
{
cyhal_hwmgr_free(&inst);
}
}
}
return rslt;
}
cy_rslt_t cyhal_system_clock_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider)
{
if (divider < 1 || divider > 0x100)
{
return CYHAL_SYSTEM_RSLT_INVALID_CLK_DIVIDER;
}
switch(clock)
{
case CYHAL_SYSTEM_CLOCK_CM4:
{
Cy_SysClk_ClkFastSetDivider(divider - 1);
break;
}
case CYHAL_SYSTEM_CLOCK_CM0:
{
Cy_SysClk_ClkSlowSetDivider(divider - 1);
break;
}
case CYHAL_SYSTEM_CLOCK_PERI:
{
Cy_SysClk_ClkPeriSetDivider(divider - 1);
break;
}
default:
{
return CYHAL_SYSTEM_RSLT_INVALID_CLK_DIVIDER;
}
}
SystemCoreClockUpdate();
return CY_RSLT_SUCCESS;
}
#endif /* CY_IP_MXS40SRSS */

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/***************************************************************************//**
* \file cyhal_timer.c
*
* \brief
* Provides a high level interface for interacting with the Cypress Timer/Counter.
* This interface abstracts out the chip specific details. If any chip specific
* functionality is necessary, or performance is critical the low level functions
* can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_timer.h"
#include "cyhal_hwmgr.h"
#include "cyhal_gpio.h"
#if defined(CY_IP_MXTCPWM_INSTANCES)
#if defined(__cplusplus)
extern "C" {
#endif
#define GET_ARRAY_INDEX(block, channel) (cyhal_internal_data[block].channel_offset + channel)
#if (CY_IP_MXTCPWM_INSTANCES == 0)
#define TCPWM_CHANNELS (0u)
#elif (CY_IP_MXTCPWM_INSTANCES == 1)
#define TCPWM_CHANNELS (TCPWM0_CNT_NR)
#elif (CY_IP_MXTCPWM_INSTANCES == 2)
#define TCPWM_CHANNELS (TCPWM0_CNT_NR + TCPWM1_CNT_NR)
#else
#warning Unhandled TCPWM instance count
#endif
/* Callback array for TCPWM interrupts */
static cyhal_timer_irq_handler_t callbacks[TCPWM_CHANNELS];
static void *callback_args[TCPWM_CHANNELS];
typedef struct {
TCPWM_Type *base;
en_clk_dst_t clock_dst;
uint32_t max_count;
uint8_t channel_offset;
uint8_t isr_offset;
} cyhal_internal_timer_data_t;
static const cyhal_internal_timer_data_t cyhal_internal_data[] = {
#if (CY_IP_MXTCPWM_INSTANCES > 0)
{TCPWM0, PCLK_TCPWM0_CLOCKS0, (uint32_t)((1ULL << TCPWM0_CNT_CNT_WIDTH) - 1ULL), 0, tcpwm_0_interrupts_0_IRQn },
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 1)
{TCPWM1, PCLK_TCPWM1_CLOCKS0, (uint32_t)((1ULL << TCPWM1_CNT_CNT_WIDTH) - 1ULL), TCPWM0_CNT_NR, tcpwm_1_interrupts_0_IRQn },
#endif
#if (CY_IP_MXTCPWM_INSTANCES > 2)
#warning Unhandled TCPWM instance count
#endif
};
const cy_stc_tcpwm_counter_config_t default_config =
{
.period = 32768,
.clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1,
.runMode = CY_TCPWM_COUNTER_CONTINUOUS,
.countDirection = CY_TCPWM_COUNTER_COUNT_UP,
.compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE,
.compare0 = 16384,
.compare1 = 16384,
.enableCompareSwap = false,
.interruptSources = CY_TCPWM_INT_NONE,
.captureInputMode = 0x3U,
.captureInput = CY_TCPWM_INPUT_0,
.reloadInputMode = 0x3U,
.reloadInput = CY_TCPWM_INPUT_0,
.startInputMode = 0x3U,
.startInput = CY_TCPWM_INPUT_0,
.stopInputMode = 0x3U,
.stopInput = CY_TCPWM_INPUT_0,
.countInputMode = 0x3U,
.countInput = CY_TCPWM_INPUT_1,
};
/*******************************************************************************
* Dispatcher Interrrupt Service Routine
*******************************************************************************/
static void isr_tcpwm_handler(uint8_t block, uint8_t channel)
{
TCPWM_Type *blockAddr = cyhal_internal_data[block].base;
uint32_t index = GET_ARRAY_INDEX(block, channel);
if (callbacks[index] != NULL)
{
/* Call registered callbacks here */
(void)(callbacks[index])(callback_args[index], (cyhal_timer_irq_event_t)Cy_TCPWM_GetInterruptStatus(blockAddr, channel));
}
Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC);
}
/*******************************************************************************
* (Internal) Interrrupt Service Routines
*******************************************************************************/
static void isr_tcpwm_0_00_handler(void) __attribute__((unused));
static void isr_tcpwm_0_01_handler(void) __attribute__((unused));
static void isr_tcpwm_0_02_handler(void) __attribute__((unused));
static void isr_tcpwm_0_03_handler(void) __attribute__((unused));
static void isr_tcpwm_0_04_handler(void) __attribute__((unused));
static void isr_tcpwm_0_05_handler(void) __attribute__((unused));
static void isr_tcpwm_0_06_handler(void) __attribute__((unused));
static void isr_tcpwm_0_07_handler(void) __attribute__((unused));
static void isr_tcpwm_0_08_handler(void) __attribute__((unused));
static void isr_tcpwm_0_09_handler(void) __attribute__((unused));
static void isr_tcpwm_0_10_handler(void) __attribute__((unused));
static void isr_tcpwm_0_11_handler(void) __attribute__((unused));
static void isr_tcpwm_0_12_handler(void) __attribute__((unused));
static void isr_tcpwm_0_13_handler(void) __attribute__((unused));
static void isr_tcpwm_0_14_handler(void) __attribute__((unused));
static void isr_tcpwm_0_15_handler(void) __attribute__((unused));
static void isr_tcpwm_0_16_handler(void) __attribute__((unused));
static void isr_tcpwm_0_17_handler(void) __attribute__((unused));
static void isr_tcpwm_0_18_handler(void) __attribute__((unused));
static void isr_tcpwm_0_19_handler(void) __attribute__((unused));
static void isr_tcpwm_0_20_handler(void) __attribute__((unused));
static void isr_tcpwm_0_21_handler(void) __attribute__((unused));
static void isr_tcpwm_0_22_handler(void) __attribute__((unused));
static void isr_tcpwm_0_23_handler(void) __attribute__((unused));
static void isr_tcpwm_0_24_handler(void) __attribute__((unused));
static void isr_tcpwm_0_25_handler(void) __attribute__((unused));
static void isr_tcpwm_0_26_handler(void) __attribute__((unused));
static void isr_tcpwm_0_27_handler(void) __attribute__((unused));
static void isr_tcpwm_0_28_handler(void) __attribute__((unused));
static void isr_tcpwm_0_29_handler(void) __attribute__((unused));
static void isr_tcpwm_0_30_handler(void) __attribute__((unused));
static void isr_tcpwm_0_31_handler(void) __attribute__((unused));
static void isr_tcpwm_1_00_handler(void) __attribute__((unused));
static void isr_tcpwm_1_01_handler(void) __attribute__((unused));
static void isr_tcpwm_1_02_handler(void) __attribute__((unused));
static void isr_tcpwm_1_03_handler(void) __attribute__((unused));
static void isr_tcpwm_1_04_handler(void) __attribute__((unused));
static void isr_tcpwm_1_05_handler(void) __attribute__((unused));
static void isr_tcpwm_1_06_handler(void) __attribute__((unused));
static void isr_tcpwm_1_07_handler(void) __attribute__((unused));
static void isr_tcpwm_1_08_handler(void) __attribute__((unused));
static void isr_tcpwm_1_09_handler(void) __attribute__((unused));
static void isr_tcpwm_1_10_handler(void) __attribute__((unused));
static void isr_tcpwm_1_11_handler(void) __attribute__((unused));
static void isr_tcpwm_1_12_handler(void) __attribute__((unused));
static void isr_tcpwm_1_13_handler(void) __attribute__((unused));
static void isr_tcpwm_1_14_handler(void) __attribute__((unused));
static void isr_tcpwm_1_15_handler(void) __attribute__((unused));
static void isr_tcpwm_1_16_handler(void) __attribute__((unused));
static void isr_tcpwm_1_17_handler(void) __attribute__((unused));
static void isr_tcpwm_1_18_handler(void) __attribute__((unused));
static void isr_tcpwm_1_19_handler(void) __attribute__((unused));
static void isr_tcpwm_1_20_handler(void) __attribute__((unused));
static void isr_tcpwm_1_21_handler(void) __attribute__((unused));
static void isr_tcpwm_1_22_handler(void) __attribute__((unused));
static void isr_tcpwm_1_23_handler(void) __attribute__((unused));
static void isr_tcpwm_1_24_handler(void) __attribute__((unused));
static void isr_tcpwm_1_25_handler(void) __attribute__((unused));
static void isr_tcpwm_1_26_handler(void) __attribute__((unused));
static void isr_tcpwm_1_27_handler(void) __attribute__((unused));
static void isr_tcpwm_1_28_handler(void) __attribute__((unused));
static void isr_tcpwm_1_29_handler(void) __attribute__((unused));
static void isr_tcpwm_1_30_handler(void) __attribute__((unused));
static void isr_tcpwm_1_31_handler(void) __attribute__((unused));
static void isr_tcpwm_0_00_handler (void)
{
isr_tcpwm_handler(0, 0);
}
static void isr_tcpwm_0_01_handler (void)
{
isr_tcpwm_handler(0, 1);
}
static void isr_tcpwm_0_02_handler (void)
{
isr_tcpwm_handler(0, 2);
}
static void isr_tcpwm_0_03_handler (void)
{
isr_tcpwm_handler(0, 3);
}
static void isr_tcpwm_0_04_handler (void)
{
isr_tcpwm_handler(0, 4);
}
static void isr_tcpwm_0_05_handler (void)
{
isr_tcpwm_handler(0, 5);
}
static void isr_tcpwm_0_06_handler (void)
{
isr_tcpwm_handler(0, 6);
}
static void isr_tcpwm_0_07_handler (void)
{
isr_tcpwm_handler(0, 7);
}
static void isr_tcpwm_0_08_handler (void)
{
isr_tcpwm_handler(0, 8);
}
static void isr_tcpwm_0_09_handler (void)
{
isr_tcpwm_handler(0, 9);
}
static void isr_tcpwm_0_10_handler (void)
{
isr_tcpwm_handler(0, 10);
}
static void isr_tcpwm_0_11_handler (void)
{
isr_tcpwm_handler(0, 11);
}
static void isr_tcpwm_0_12_handler (void)
{
isr_tcpwm_handler(0, 12);
}
static void isr_tcpwm_0_13_handler (void)
{
isr_tcpwm_handler(0, 13);
}
static void isr_tcpwm_0_14_handler (void)
{
isr_tcpwm_handler(0, 14);
}
static void isr_tcpwm_0_15_handler (void)
{
isr_tcpwm_handler(0, 15);
}
static void isr_tcpwm_0_16_handler (void)
{
isr_tcpwm_handler(0, 16);
}
static void isr_tcpwm_0_17_handler (void)
{
isr_tcpwm_handler(0, 17);
}
static void isr_tcpwm_0_18_handler (void)
{
isr_tcpwm_handler(0, 18);
}
static void isr_tcpwm_0_19_handler (void)
{
isr_tcpwm_handler(0, 19);
}
static void isr_tcpwm_0_20_handler (void)
{
isr_tcpwm_handler(0, 20);
}
static void isr_tcpwm_0_21_handler (void)
{
isr_tcpwm_handler(0, 21);
}
static void isr_tcpwm_0_22_handler (void)
{
isr_tcpwm_handler(0, 22);
}
static void isr_tcpwm_0_23_handler (void)
{
isr_tcpwm_handler(0, 23);
}
static void isr_tcpwm_0_24_handler (void)
{
isr_tcpwm_handler(0, 24);
}
static void isr_tcpwm_0_25_handler (void)
{
isr_tcpwm_handler(0, 25);
}
static void isr_tcpwm_0_26_handler (void)
{
isr_tcpwm_handler(0, 26);
}
static void isr_tcpwm_0_27_handler (void)
{
isr_tcpwm_handler(0, 27);
}
static void isr_tcpwm_0_28_handler (void)
{
isr_tcpwm_handler(0, 28);
}
static void isr_tcpwm_0_29_handler (void)
{
isr_tcpwm_handler(0, 29);
}
static void isr_tcpwm_0_30_handler (void)
{
isr_tcpwm_handler(0, 30);
}
static void isr_tcpwm_0_31_handler (void)
{
isr_tcpwm_handler(0, 31);
}
static void isr_tcpwm_1_00_handler (void)
{
isr_tcpwm_handler(1, 0);
}
static void isr_tcpwm_1_01_handler (void)
{
isr_tcpwm_handler(1, 1);
}
static void isr_tcpwm_1_02_handler (void)
{
isr_tcpwm_handler(1, 2);
}
static void isr_tcpwm_1_03_handler (void)
{
isr_tcpwm_handler(1, 3);
}
static void isr_tcpwm_1_04_handler (void)
{
isr_tcpwm_handler(1, 4);
}
static void isr_tcpwm_1_05_handler (void)
{
isr_tcpwm_handler(1, 5);
}
static void isr_tcpwm_1_06_handler (void)
{
isr_tcpwm_handler(1, 6);
}
static void isr_tcpwm_1_07_handler (void)
{
isr_tcpwm_handler(1, 7);
}
static void isr_tcpwm_1_08_handler (void)
{
isr_tcpwm_handler(1, 8);
}
static void isr_tcpwm_1_09_handler (void)
{
isr_tcpwm_handler(1, 9);
}
static void isr_tcpwm_1_10_handler (void)
{
isr_tcpwm_handler(1, 10);
}
static void isr_tcpwm_1_11_handler (void)
{
isr_tcpwm_handler(1, 11);
}
static void isr_tcpwm_1_12_handler (void)
{
isr_tcpwm_handler(1, 12);
}
static void isr_tcpwm_1_13_handler (void)
{
isr_tcpwm_handler(1, 13);
}
static void isr_tcpwm_1_14_handler (void)
{
isr_tcpwm_handler(1, 14);
}
static void isr_tcpwm_1_15_handler (void)
{
isr_tcpwm_handler(1, 15);
}
static void isr_tcpwm_1_16_handler (void)
{
isr_tcpwm_handler(1, 16);
}
static void isr_tcpwm_1_17_handler (void)
{
isr_tcpwm_handler(1, 17);
}
static void isr_tcpwm_1_18_handler (void)
{
isr_tcpwm_handler(1, 18);
}
static void isr_tcpwm_1_19_handler (void)
{
isr_tcpwm_handler(1, 19);
}
static void isr_tcpwm_1_20_handler (void)
{
isr_tcpwm_handler(1, 20);
}
static void isr_tcpwm_1_21_handler (void)
{
isr_tcpwm_handler(1, 21);
}
static void isr_tcpwm_1_22_handler (void)
{
isr_tcpwm_handler(1, 22);
}
static void isr_tcpwm_1_23_handler (void)
{
isr_tcpwm_handler(1, 23);
}
static void isr_tcpwm_1_24_handler (void)
{
isr_tcpwm_handler(1, 24);
}
static void isr_tcpwm_1_25_handler (void)
{
isr_tcpwm_handler(1, 25);
}
static void isr_tcpwm_1_26_handler (void)
{
isr_tcpwm_handler(1, 26);
}
static void isr_tcpwm_1_27_handler (void)
{
isr_tcpwm_handler(1, 27);
}
static void isr_tcpwm_1_28_handler (void)
{
isr_tcpwm_handler(1, 28);
}
static void isr_tcpwm_1_29_handler (void)
{
isr_tcpwm_handler(1, 29);
}
static void isr_tcpwm_1_30_handler (void)
{
isr_tcpwm_handler(1, 30);
}
static void isr_tcpwm_1_31_handler (void)
{
isr_tcpwm_handler(1, 31);
}
typedef void (*interrupt_dispatcher)(void);
static const interrupt_dispatcher interrupts_dispatcher_table[TCPWM_CHANNELS] =
{
#if (TCPWM0_CNT_NR > 0)
isr_tcpwm_0_00_handler,
#endif
#if (TCPWM0_CNT_NR > 1)
isr_tcpwm_0_01_handler,
#endif
#if (TCPWM0_CNT_NR > 2)
isr_tcpwm_0_02_handler,
#endif
#if (TCPWM0_CNT_NR > 3)
isr_tcpwm_0_03_handler,
#endif
#if (TCPWM0_CNT_NR > 4)
isr_tcpwm_0_04_handler,
#endif
#if (TCPWM0_CNT_NR > 5)
isr_tcpwm_0_05_handler,
#endif
#if (TCPWM0_CNT_NR > 6)
isr_tcpwm_0_06_handler,
#endif
#if (TCPWM0_CNT_NR > 7)
isr_tcpwm_0_07_handler,
#endif
#if (TCPWM0_CNT_NR > 8)
isr_tcpwm_0_08_handler,
#endif
#if (TCPWM0_CNT_NR > 9)
isr_tcpwm_0_09_handler,
#endif
#if (TCPWM0_CNT_NR > 10)
isr_tcpwm_0_10_handler,
#endif
#if (TCPWM0_CNT_NR > 11)
isr_tcpwm_0_11_handler,
#endif
#if (TCPWM0_CNT_NR > 12)
isr_tcpwm_0_12_handler,
#endif
#if (TCPWM0_CNT_NR > 13)
isr_tcpwm_0_13_handler,
#endif
#if (TCPWM0_CNT_NR > 14)
isr_tcpwm_0_14_handler,
#endif
#if (TCPWM0_CNT_NR > 15)
isr_tcpwm_0_15_handler,
#endif
#if (TCPWM0_CNT_NR > 16)
isr_tcpwm_0_16_handler,
#endif
#if (TCPWM0_CNT_NR > 17)
isr_tcpwm_0_17_handler,
#endif
#if (TCPWM0_CNT_NR > 18)
isr_tcpwm_0_18_handler,
#endif
#if (TCPWM0_CNT_NR > 19)
isr_tcpwm_0_19_handler,
#endif
#if (TCPWM0_CNT_NR > 20)
isr_tcpwm_0_20_handler,
#endif
#if (TCPWM0_CNT_NR > 21)
isr_tcpwm_0_21_handler,
#endif
#if (TCPWM0_CNT_NR > 22)
isr_tcpwm_0_22_handler,
#endif
#if (TCPWM0_CNT_NR > 23)
isr_tcpwm_0_23_handler,
#endif
#if (TCPWM0_CNT_NR > 24)
isr_tcpwm_0_24_handler,
#endif
#if (TCPWM0_CNT_NR > 25)
isr_tcpwm_0_25_handler,
#endif
#if (TCPWM0_CNT_NR > 26)
isr_tcpwm_0_26_handler,
#endif
#if (TCPWM0_CNT_NR > 27)
isr_tcpwm_0_27_handler,
#endif
#if (TCPWM0_CNT_NR > 28)
isr_tcpwm_0_28_handler,
#endif
#if (TCPWM0_CNT_NR > 29)
isr_tcpwm_0_29_handler,
#endif
#if (TCPWM0_CNT_NR > 30)
isr_tcpwm_0_30_handler,
#endif
#if (TCPWM0_CNT_NR > 31)
isr_tcpwm_0_31_handler,
#endif
#if (TCPWM0_CNT_NR > 32)
#error "Unhandled TCPWM 0 channel count"
#endif
#if (TCPWM1_CNT_NR > 0)
isr_tcpwm_1_00_handler,
#endif
#if (TCPWM1_CNT_NR > 1)
isr_tcpwm_1_01_handler,
#endif
#if (TCPWM1_CNT_NR > 2)
isr_tcpwm_1_02_handler,
#endif
#if (TCPWM1_CNT_NR > 3)
isr_tcpwm_1_03_handler,
#endif
#if (TCPWM1_CNT_NR > 4)
isr_tcpwm_1_04_handler,
#endif
#if (TCPWM1_CNT_NR > 5)
isr_tcpwm_1_05_handler,
#endif
#if (TCPWM1_CNT_NR > 6)
isr_tcpwm_1_06_handler,
#endif
#if (TCPWM1_CNT_NR > 7)
isr_tcpwm_1_07_handler,
#endif
#if (TCPWM1_CNT_NR > 8)
isr_tcpwm_1_08_handler,
#endif
#if (TCPWM1_CNT_NR > 9)
isr_tcpwm_1_09_handler,
#endif
#if (TCPWM1_CNT_NR > 10)
isr_tcpwm_1_10_handler,
#endif
#if (TCPWM1_CNT_NR > 11)
isr_tcpwm_1_11_handler,
#endif
#if (TCPWM1_CNT_NR > 12)
isr_tcpwm_1_12_handler,
#endif
#if (TCPWM1_CNT_NR > 13)
isr_tcpwm_1_13_handler,
#endif
#if (TCPWM1_CNT_NR > 14)
isr_tcpwm_1_14_handler,
#endif
#if (TCPWM1_CNT_NR > 15)
isr_tcpwm_1_15_handler,
#endif
#if (TCPWM1_CNT_NR > 16)
isr_tcpwm_1_16_handler,
#endif
#if (TCPWM1_CNT_NR > 17)
isr_tcpwm_1_17_handler,
#endif
#if (TCPWM1_CNT_NR > 18)
isr_tcpwm_1_18_handler,
#endif
#if (TCPWM1_CNT_NR > 19)
isr_tcpwm_1_19_handler,
#endif
#if (TCPWM1_CNT_NR > 20)
isr_tcpwm_1_20_handler,
#endif
#if (TCPWM1_CNT_NR > 21)
isr_tcpwm_1_21_handler,
#endif
#if (TCPWM1_CNT_NR > 22)
isr_tcpwm_1_22_handler,
#endif
#if (TCPWM1_CNT_NR > 23)
isr_tcpwm_1_23_handler,
#endif
#if (TCPWM1_CNT_NR > 24)
isr_tcpwm_1_24_handler,
#endif
#if (TCPWM1_CNT_NR > 25)
isr_tcpwm_1_25_handler,
#endif
#if (TCPWM1_CNT_NR > 26)
isr_tcpwm_1_26_handler,
#endif
#if (TCPWM1_CNT_NR > 27)
isr_tcpwm_1_27_handler,
#endif
#if (TCPWM1_CNT_NR > 28)
isr_tcpwm_1_28_handler,
#endif
#if (TCPWM1_CNT_NR > 29)
isr_tcpwm_1_29_handler,
#endif
#if (TCPWM1_CNT_NR > 30)
isr_tcpwm_1_30_handler,
#endif
#if (TCPWM1_CNT_NR > 31)
isr_tcpwm_1_31_handler,
#endif
#if (TCPWM1_CNT_NR > 32)
#error "Unhandled TCPWM 1 channel count"
#endif
};
static inline uint32_t convert_direction(cyhal_timer_direction_t direction)
{
switch (direction)
{
case CYHAL_TIMER_DIR_UP:
return CY_TCPWM_COUNTER_COUNT_UP;
case CYHAL_TIMER_DIR_DOWN:
return CY_TCPWM_COUNTER_COUNT_DOWN;
case CYHAL_TIMER_DIR_UP_DOWN:
return CY_TCPWM_COUNTER_COUNT_UP_DOWN_2;
}
return CY_TCPWM_COUNTER_COUNT_UP;
}
/*******************************************************************************
* Timer HAL Functions
*******************************************************************************/
cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk)
{
CY_ASSERT(NULL != obj);
//TODO: Handle Trigger mux pin assignments
if (CYHAL_NC_PIN_VALUE != pin)
return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT;
cy_rslt_t result = cyhal_hwmgr_allocate(CYHAL_RSC_TCPWM, &obj->resource);
if (CY_RSLT_SUCCESS == result)
{
cyhal_resource_inst_t *timer = &obj->resource;
obj->base = cyhal_internal_data[timer->block_num].base;
en_clk_dst_t pclk = (en_clk_dst_t)(cyhal_internal_data[timer->block_num].clock_dst + timer->channel_num);
if (NULL != clk)
{
obj->clock_hz = cy_PeriClkFreqHz / (1 + Cy_SysClk_PeriphGetDivider(obj->clock.div_type, obj->clock.div_num));
if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num))
{
result = CYHAL_TIMER_RSLT_ERR_CLOCK;
}
}
else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false)))
{
uint32_t div = cy_PeriClkFreqHz / 1000000u;
if (0 == div ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) ||
CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num))
{
result = CYHAL_TIMER_RSLT_ERR_CLOCK;
}
else
{
obj->clock_hz = cy_PeriClkFreqHz / div;
}
}
bool configured = cyhal_hwmgr_is_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
if (CY_RSLT_SUCCESS == result && !configured)
{
result = Cy_TCPWM_Counter_Init(obj->base, obj->resource.channel_num, &default_config);
if (CY_TCPWM_SUCCESS == result)
{
result = cyhal_hwmgr_set_configured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
}
}
if (result == CY_RSLT_SUCCESS)
{
Cy_TCPWM_Counter_Enable(obj->base, obj->resource.channel_num);
}
else
{
cyhal_timer_free(obj);
}
}
return result;
}
void cyhal_timer_free(cyhal_timer_t *obj)
{
CY_ASSERT(NULL != obj);
if (NULL != obj && NULL != obj->base)
{
cyhal_hwmgr_free(&obj->resource);
cyhal_hwmgr_set_unconfigured(obj->resource.type, obj->resource.block_num, obj->resource.channel_num);
obj->base = NULL;
}
}
cy_rslt_t cyhal_timer_set_config(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg)
{
cy_rslt_t rslt;
if (obj->is_continuous != cfg->is_continuous ||
obj->direction != cfg->direction ||
obj->is_compare != cfg->is_compare)
{
cy_stc_tcpwm_counter_config_t config = default_config;
config.period = cfg->period;
config.compare0 = cfg->compare_value;
config.runMode = cfg->is_continuous ? CY_TCPWM_COUNTER_CONTINUOUS : CY_TCPWM_COUNTER_ONESHOT;
config.compareOrCapture = cfg->is_compare ? CY_TCPWM_COUNTER_MODE_COMPARE : CY_TCPWM_COUNTER_MODE_CAPTURE;
config.countDirection = convert_direction(cfg->direction);
Cy_TCPWM_Counter_DeInit(obj->base, obj->resource.channel_num, &config);
rslt = (cy_rslt_t)Cy_TCPWM_Counter_Init(obj->base, obj->resource.channel_num, &config);
if (CY_TCPWM_SUCCESS == rslt)
{
obj->is_continuous = cfg->is_continuous;
obj->direction = cfg->direction;
obj->is_compare = cfg->is_compare;
}
}
else
{
Cy_TCPWM_Counter_SetCounter(obj->base, obj->resource.channel_num, cfg->value);
Cy_TCPWM_Counter_SetPeriod(obj->base, obj->resource.channel_num, cfg->period);
if (cfg->is_compare)
{
Cy_TCPWM_Counter_SetCompare0(obj->base, obj->resource.channel_num, cfg->compare_value);
}
rslt = CY_RSLT_SUCCESS;
}
return rslt;
}
cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj)
{
if (NULL == obj)
return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT;
Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj)
{
if (NULL == obj)
return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT;
Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num);
return CY_RSLT_SUCCESS;
}
void cyhal_timer_register_irq(cyhal_timer_t *obj, uint8_t priority, cyhal_timer_irq_handler_t handler, void *handler_arg)
{
uint8_t index = GET_ARRAY_INDEX(obj->resource.block_num, obj->resource.channel_num);
callbacks[index] = handler;
callback_args[index] = handler_arg;
IRQn_Type irqn = (IRQn_Type)(cyhal_internal_data[obj->resource.block_num].isr_offset + obj->resource.channel_num);
/* Only enable if it's not already enabled */
if (NVIC_GetEnableIRQ(irqn) == 0)
{
cy_stc_sysint_t irqCfg = {irqn, priority};
Cy_SysInt_Init(&irqCfg, interrupts_dispatcher_table[index]);
NVIC_EnableIRQ(irqn);
}
else
{
NVIC_SetPriority(irqn, priority);
}
}
void cyhal_timer_irq_enable(cyhal_timer_t *obj, cyhal_timer_irq_event_t event, bool enable)
{
Cy_TCPWM_SetInterruptMask(obj->base, obj->resource.channel_num, enable ? (uint32_t)event : 0);
}
#if defined(__cplusplus)
}
#endif
#endif /* defined(CY_IP_MXTCPWM_INSTANCES) */

55
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c Normal file
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@ -0,0 +1,55 @@
/*******************************************************************************
* File Name: cyhal_trng.c
*
* Description:
* Provides a high level interface for interacting with the Cypress TRNG. This is
* a wrapper around the lower level PDL API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_hwmgr.h"
#include "cyhal_crypto_common.h"
#include "cy_crypto_core_crc.h"
#include "cyhal_trng_impl.h"
#if defined(CY_IP_MXCRYPTO)
/*******************************************************************************
* Functions
*******************************************************************************/
cy_rslt_t cyhal_trng_init(cyhal_trng_t *obj)
{
CY_ASSERT(NULL != obj);
memset(obj, 0, sizeof(cyhal_trng_t));
obj->resource.type = CYHAL_RSC_TRNG;
return cyhal_crypto_reserve(&(obj->base), &(obj->resource));
}
void cyhal_trng_free(cyhal_trng_t *obj)
{
CY_ASSERT(NULL != obj || obj->resource.type != CYHAL_RSC_TRNG);
if (obj->resource.type != CYHAL_RSC_INVALID)
{
cyhal_crypto_free(obj->base, &(obj->resource));
obj->resource.type = CYHAL_RSC_INVALID;
}
}
#endif /* defined(CY_IP_MXCRYPTO) */

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/*******************************************************************************
* File Name: cyhal_udb_sdio.c
*
* Description:
* Provides a high level interface for interacting with the Cypress UDB SDIO.
* This is a wrapper around the lower level UDB SDIO API.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_hwmgr.h"
#if defined(CYHAL_UDB_SDIO)
#include <stdlib.h>
#include "SDIO_HOST_cfg.h"
#include "cyhal_utils.h"
#include "cyhal_sdio.h"
#include "cyhal_gpio.h"
#include "cyhal_interconnect.h"
#include "cyhal_implementation.h"
/* Not connected pin define */
#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE)
#define CY_HAL_SDIO_CLK_DIV_VALUE ((uint8_t) 0xFF)
/* Not configured clock divider define*/
#define CY_HAL_SDIO_CLK_DIV_NC ((cy_en_divider_types_t) CY_HAL_SDIO_CLK_DIV_VALUE)
/* Define for default SDIO frequency */
#define CY_HAL_SDIO_DEF_FREQ (400000U)
/* The 64b block transition mode define */
#define CY_HAL_SDIO_64B (64u)
/* The 1 byte transition mode define */
#define CY_HAL_SDIO_1B (1u)
/*******************************************************************************
* (Internal) Configuration structures for SDIO pins
*******************************************************************************/
const cy_stc_gpio_pin_config_t pin_cmd_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = HSIOM_SEL_DSI_DSI, /* DSI controls 'out' and 'output enable' */
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t pin_data_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG,
.hsiom = HSIOM_SEL_DSI_DSI, /* DSI controls 'out' and 'output enable' */
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
const cy_stc_gpio_pin_config_t pin_clk_config =
{
.outVal = 1,
.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
.hsiom = HSIOM_SEL_DSI_GPIO, /* DSI controls 'out', GPIO controls 'output enable' */
.intEdge = CY_GPIO_INTR_DISABLE,
.intMask = 0UL,
.vtrip = CY_GPIO_VTRIP_CMOS,
.slewRate = CY_GPIO_SLEW_FAST,
.driveSel = CY_GPIO_DRIVE_1_2,
.vregEn = 0UL,
.ibufMode = 0UL,
.vtripSel = 0UL,
.vrefSel = 0UL,
.vohSel = 0UL,
};
/* Callback pointers */
static cyhal_sdio_irq_handler_t cyhal_sdio_callback = NULL;
static cyhal_sdio_t *cyhal_sdio_config_struct = NULL;
static void *cyhal_sdio_callback_args = NULL;
/*******************************************************************************
* Dispatcher Interrupt Callbacks Service Routine
*******************************************************************************/
static void cyhal_sdio_interrupts_dispatcher_IRQHandler(void)
{
if ((cyhal_sdio_callback != NULL) && (cyhal_sdio_config_struct->irq_cause != 0U))
{
(void)(cyhal_sdio_callback)(cyhal_sdio_callback_args, (cyhal_sdio_irq_event_t) cyhal_sdio_config_struct->irq_cause);
}
}
/*******************************************************************************
* Internal functions
*******************************************************************************/
static void cyhal_free_pins(cyhal_sdio_t *obj);
static void cyhal_free_pins(cyhal_sdio_t *obj)
{
cyhal_gpio_free(obj->pin_clk);
obj->pin_clk = SDIO_PINS_NC;
cyhal_gpio_free(obj->pin_cmd);
obj->pin_cmd = SDIO_PINS_NC;
cyhal_gpio_free(obj->pin_data0);
obj->pin_data0 = SDIO_PINS_NC;
cyhal_gpio_free(obj->pin_data1);
obj->pin_data1 = SDIO_PINS_NC;
cyhal_gpio_free(obj->pin_data2);
obj->pin_data2 = SDIO_PINS_NC;
cyhal_gpio_free(obj->pin_data3);
obj->pin_data3 = SDIO_PINS_NC;
}
static void cyhal_free_clocks(cyhal_sdio_t *obj)
{
cyhal_resource_inst_t udbClkRsc;
udbClkRsc.type = CYHAL_RSC_CLOCK;
udbClkRsc.block_num = obj->clock.div_num;
udbClkRsc.channel_num = 0;
cyhal_hwmgr_free(&udbClkRsc);
}
static void cyhal_free_dmas(cyhal_sdio_t *obj)
{
cyhal_resource_inst_t dmaRsc;
dmaRsc.type = CYHAL_RSC_DMA;
dmaRsc.block_num = 0;
dmaRsc.channel_num = 0;
cyhal_hwmgr_free(&dmaRsc);
dmaRsc.block_num = 0;
dmaRsc.channel_num = 1;
cyhal_hwmgr_free(&dmaRsc);
dmaRsc.block_num = 1;
dmaRsc.channel_num = 1;
cyhal_hwmgr_free(&dmaRsc);
dmaRsc.block_num = 1;
dmaRsc.channel_num = 3;
cyhal_hwmgr_free(&dmaRsc);
}
cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, cyhal_gpio_t data0, cyhal_gpio_t data1, cyhal_gpio_t data2, cyhal_gpio_t data3)
{
CY_ASSERT(NULL != obj);
/* If something go wrong, any resource not marked as invalid will be freed.
* Explicitly marked not allocated resources as invalid to prevent freeing
* them.
*
* Before we reserve UDB at all we need try to reserve clock divider, then
* DMAs and pins. If all these resources are reserved only then reserve UDB
* SDIO.
*/
obj->resource.type = CYHAL_RSC_INVALID;
obj->pin_cmd = SDIO_PINS_NC;
obj->pin_clk = SDIO_PINS_NC;
obj->pin_data0 = SDIO_PINS_NC;
obj->pin_data1 = SDIO_PINS_NC;
obj->pin_data2 = SDIO_PINS_NC;
obj->pin_data3 = SDIO_PINS_NC;
obj->dma0Ch0.resource.type = CYHAL_RSC_INVALID;
obj->dma0Ch1.resource.type = CYHAL_RSC_INVALID;
obj->dma1Ch1.resource.type = CYHAL_RSC_INVALID;
obj->dma1Ch3.resource.type = CYHAL_RSC_INVALID;
cy_rslt_t retVal = CY_RSLT_SUCCESS;
obj->clock.div_type = CY_HAL_SDIO_CLK_DIV_NC;
/* Reserve clock */
cyhal_resource_inst_t udbClkRsc = { CYHAL_RSC_CLOCK, 0, 0 };
retVal = cyhal_hwmgr_reserve(&udbClkRsc);
if (retVal == CY_RSLT_SUCCESS)
{
/* Assign clock divider */
obj->clock.div_type = CY_SYSCLK_DIV_8_BIT;
obj->clock.div_num = 0;
retVal = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, 0U);
if (CY_SYSCLK_SUCCESS == retVal)
{
retVal = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num);
}
if (CY_SYSCLK_SUCCESS == retVal)
{
retVal = Cy_SysClk_PeriphAssignDivider(PCLK_UDB_CLOCKS0, obj->clock.div_type, obj->clock.div_num);
}
}
/* The DMAs are initialized in SDIO_Init() function, so only reserve */
if (retVal == CY_RSLT_SUCCESS)
{
/* Reserve DMA0 CH0 */
cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 0 };
retVal = cyhal_hwmgr_reserve(&dmaRsc);
}
if (retVal == CY_RSLT_SUCCESS)
{
/* Reserve DMA0 CH1 */
cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 1 };
retVal = cyhal_hwmgr_reserve(&dmaRsc);
}
if (retVal == CY_RSLT_SUCCESS)
{
/* Reserve DMA1 CH1 */
cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 1 };
retVal = cyhal_hwmgr_reserve(&dmaRsc);
}
if (retVal == CY_RSLT_SUCCESS)
{
/* Reserve DMA1 CH3 */
cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 3 };
retVal = cyhal_hwmgr_reserve(&dmaRsc);
}
/* Reserve the clk pin */
if (retVal == CY_RSLT_SUCCESS)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(clk);
retVal = cyhal_hwmgr_reserve(&pinRsc);
if (retVal == CY_RSLT_SUCCESS)
{
obj->pin_clk = clk;
Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(clk), CYHAL_GET_PIN(clk), &pin_clk_config);
}
}
/* Reserve the cmd pin */
if (retVal == CY_RSLT_SUCCESS)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(cmd);
retVal = cyhal_hwmgr_reserve(&pinRsc);
if (retVal == CY_RSLT_SUCCESS)
{
obj->pin_cmd = cmd;
Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(cmd), CYHAL_GET_PIN(cmd), &pin_cmd_config);
}
}
/* Reserve the data0 pin */
if (retVal == CY_RSLT_SUCCESS)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(data0);
retVal = cyhal_hwmgr_reserve(&pinRsc);
if (retVal == CY_RSLT_SUCCESS)
{
obj->pin_data0 = data0;
Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(data0), CYHAL_GET_PIN(data0), &pin_data_config);
}
}
/* Reserve the data1 pin */
if (retVal == CY_RSLT_SUCCESS)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(data1);
retVal = cyhal_hwmgr_reserve(&pinRsc);
if (retVal == CY_RSLT_SUCCESS)
{
obj->pin_data1 = data1;
Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(data1), CYHAL_GET_PIN(data1), &pin_data_config);
}
}
/* Reserve the data2 pin */
if (retVal == CY_RSLT_SUCCESS)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(data2);
retVal = cyhal_hwmgr_reserve(&pinRsc);
if (retVal == CY_RSLT_SUCCESS)
{
obj->pin_data2 = data2;
Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(data2), CYHAL_GET_PIN(data2), &pin_data_config);
}
}
/* Reserve the data3 pin */
if (retVal == CY_RSLT_SUCCESS)
{
cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(data3);
retVal = cyhal_hwmgr_reserve(&pinRsc);
if (retVal == CY_RSLT_SUCCESS)
{
obj->pin_data3 = data3;
Cy_GPIO_Pin_Init(CYHAL_GET_PORTADDR(data3), CYHAL_GET_PIN(data3), &pin_data_config);
}
}
/* Reserve UDB SDIO */
if (retVal == CY_RSLT_SUCCESS)
{
/* UDB SDIO resource */
cyhal_resource_inst_t udbRsc = { CYHAL_RSC_UDB, 0, 0 };
retVal = cyhal_hwmgr_reserve(&udbRsc);
if (retVal == CY_RSLT_SUCCESS)
{
/* Update SDIO object */
obj->resource.type = udbRsc.type;
obj->resource.block_num = udbRsc.block_num;
obj->resource.channel_num = udbRsc.channel_num;
/* Set default interrupt priority of 7 (lowest possible priority) */
cy_stc_sysint_t irqCfg = {udb_interrupts_0_IRQn, 7};
Cy_SysInt_Init(&irqCfg, &SDIO_IRQ);
NVIC_EnableIRQ(udb_interrupts_0_IRQn);
/* Setup write DMA interrupt handler */
cy_stc_sysint_t irqDma1_1 = {cpuss_interrupts_dw1_1_IRQn, 7};
Cy_SysInt_Init(&irqDma1_1, &SDIO_WRITE_DMA_IRQ);
NVIC_EnableIRQ(cpuss_interrupts_dw1_1_IRQn);
/* Setup read DMA interrupt handler */
cy_stc_sysint_t irqDma1_3 = {cpuss_interrupts_dw1_3_IRQn, 7};
Cy_SysInt_Init(&irqDma1_3, &SDIO_READ_DMA_IRQ);
NVIC_EnableIRQ(cpuss_interrupts_dw1_3_IRQn);
/* Connect UDB to DMA */
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT1, TRIG0_OUT_CPUSS_DW0_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG0_IN_TR_GROUP14_OUTPUT4, TRIG0_OUT_CPUSS_DW0_TR_IN0, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT0, TRIG1_OUT_CPUSS_DW1_TR_IN1, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG1_IN_TR_GROUP14_OUTPUT5, TRIG1_OUT_CPUSS_DW1_TR_IN3, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB0, TRIG14_OUT_TR_GROUP1_INPUT43, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB1, TRIG14_OUT_TR_GROUP0_INPUT44, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB3, TRIG14_OUT_TR_GROUP0_INPUT47, false, TRIGGER_TYPE_LEVEL);
Cy_TrigMux_Connect(TRIG14_IN_UDB_TR_UDB7, TRIG14_OUT_TR_GROUP1_INPUT48, false, TRIGGER_TYPE_LEVEL);
stc_sdio_irq_cb_t irq_cbs;
irq_cbs.pfnCardIntCb = cyhal_sdio_interrupts_dispatcher_IRQHandler;
SDIO_Init(&irq_cbs);
/* SDIO_Init() configures the SDIO to 40 kHz */
obj->frequencyhal_hz = CY_HAL_SDIO_DEF_FREQ;
obj->block_size = CY_HAL_SDIO_64B;
/* Initialize interrupt cause */
obj->irq_cause = 0u;
retVal = cyhal_hwmgr_set_configured(udbRsc.type, udbRsc.block_num, udbRsc.channel_num);
}
}
if (retVal != CY_RSLT_SUCCESS)
{
cyhal_sdio_free(obj);
}
return retVal;
}
void cyhal_sdio_free(cyhal_sdio_t *obj)
{
CY_ASSERT(NULL != obj);
cyhal_free_pins(obj);
cyhal_free_clocks(obj);
cyhal_free_dmas(obj);
}
cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config)
{
CY_ASSERT(NULL != obj);
/* Do not change frequency if requested value is zero */
if (config->frequencyhal_hz != 0)
{
SDIO_SetSdClkFrequency(config->frequencyhal_hz);
obj->frequencyhal_hz = config->frequencyhal_hz;
}
/* Do not change block size if requested value is zero */
if (config->block_size != 0)
{
SDIO_SetBlockSize(config->block_size);
obj->block_size = config->block_size;
}
return CY_RSLT_SUCCESS;
}
cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, cyhal_sdio_command_t command, uint32_t argument, uint32_t* response)
{
CY_ASSERT(NULL != obj);
if (command == CYHAL_SDIO_CMD_IO_RW_EXTENDED)
{
return CYHAL_SDIO_RSLT_ERR_BAD_PARAM;
}
uint32_t cmdResponse;
stc_sdio_cmd_t cmd;
en_sdio_result_t status;
cy_rslt_t retVal = CY_RSLT_SUCCESS;
if (response != NULL)
{
*response = 0;
}
cmd.u32CmdIdx = (uint32_t) command;
cmd.u32Arg = argument;
cmd.pu32Response = &cmdResponse;
cmd.pu8Data = NULL; /* Not used */
cmd.bRead = (direction != CYHAL_READ) ? false : true;
cmd.u16BlockCnt = 0U; /* Not used */
cmd.u16BlockSize = 0U; /* Not used */
status = SDIO_SendCommandAndWait(&cmd);
if (Ok != status)
{
retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
}
if (response != NULL)
{
*response = cmdResponse;
}
return retVal;
}
cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length, uint32_t* response)
{
CY_ASSERT(NULL != obj);
stc_sdio_cmd_t cmd;
en_sdio_result_t status;
uint32_t cmdResponse;
cy_rslt_t retVal = CY_RSLT_SUCCESS;
if (response != NULL)
{
*response = 0;
}
cmd.u32CmdIdx = (uint32_t) CYHAL_SDIO_CMD_IO_RW_EXTENDED;
cmd.u32Arg = argument;
cmd.pu32Response = &cmdResponse;
/* Note that this implementation uses 8b address */
cmd.pu8Data = (uint8_t *) data;
cmd.bRead = (direction != CYHAL_READ) ? false : true;
if (length >= obj->block_size)
{
cmd.u16BlockCnt = (uint16_t) ((length + obj->block_size - 1)/obj->block_size);
cmd.u16BlockSize = obj->block_size;
}
else
{
/* Data will be sent as one packet */
cmd.u16BlockCnt = CY_HAL_SDIO_1B;
cmd.u16BlockSize = length;
}
status = SDIO_SendCommandAndWait(&cmd);
if (Ok != status)
{
retVal = CYHAL_SDIO_RSLT_ERR_FUNC_RET(status);
}
if (response != NULL)
{
*response = cmdResponse;
}
return retVal;
}
cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t direction, uint32_t argument, const uint32_t* data, uint16_t length)
{
/* UDB SDIO implementation does not support async transfers */
/* Just add check to suppress warning about unused arguments */
if ((NULL == obj) && (data == NULL) && (length == 0) && (argument == 0) && (direction == ((cyhal_transfer_t) 0x3)))
{
return CYHAL_SDIO_RSLT_ERR_BAD_PARAM;
}
return CYHAL_SDIO_FUNC_NOT_SUPPORTED;
}
bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj)
{
/* UDB SDIO does not support async transfers */
return true;
}
cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj)
{
/* Reset UDB SDIO */
SDIO_Reset();
return CY_RSLT_SUCCESS;
}
void cyhal_sdio_register_irq(cyhal_sdio_t *obj, cyhal_sdio_irq_handler_t handler, void *handler_arg)
{
cyhal_sdio_config_struct = obj;
cyhal_sdio_callback = handler;
cyhal_sdio_callback_args = handler_arg;
}
void cyhal_sdio_irq_enable(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, bool enable)
{
/* Only CYHAL_SDIO_CARD_INTERRUPT event can be registered */
if (event == CYHAL_SDIO_CARD_INTERRUPT)
{
if (enable)
{
obj->irq_cause = event;
if (cyhal_sdio_config_struct != NULL)
{
cyhal_sdio_config_struct->irq_cause = event;
}
SDIO_EnableChipInt();
}
else
{
obj->irq_cause = 0U;
if (cyhal_sdio_config_struct != NULL)
{
cyhal_sdio_config_struct->irq_cause = 0U;
}
SDIO_DisableChipInt();
}
}
}
#endif /* defined(CYHAL_UDB_SDIO) */

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/*******************************************************************************
* File Name: cyhal_usb_dev.c
*
* \brief
* Provides a high level interface for interacting with the Cypress USB Device.
* This interface abstracts out the chip specific details.
* If any chip specific functionality is necessary, or performance is critical
* the low level functions can be used directly.
*
********************************************************************************
* \copyright
* Copyright 2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cyhal_usb_dev.h"
#include "cyhal_gpio.h"
#include "cyhal_interconnect.h"
#include "cyhal_utils.h"
#if defined(CY_IP_MXUSBFS)
/* Interrupt configuration and access */
#define CYHAL_USB_DEV_DEFAULT_IRQ_PRIORITY (3U)
/* Assign all interrupt sources to Low interrupt */
#define CYHAL_USB_DEV_IRQ_LVL (CY_USBFS_DEV_DRV_LVL_LOW)
#define CYHAL_USB_DEV_IRQ_LVL_DEFAULT (CY_USBFS_DEV_DRV_SET_SOF_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP0_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_LPM_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP1_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP2_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP3_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP4_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP5_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP6_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP7_LVL(CYHAL_USB_DEV_IRQ_LVL) | \
CY_USBFS_DEV_DRV_SET_EP8_LVL(CYHAL_USB_DEV_IRQ_LVL))
#define CYHAL_USB_DEV_IS_EVENT_VALID(event) ( ((event) == CYHAL_USB_DEV_EVENT_BUS_RESET) || \
((event) == CYHAL_USB_DEV_EVENT_EP0_SETUP) || \
((event) == CYHAL_USB_DEV_EVENT_EP0_IN) || \
((event) == CYHAL_USB_DEV_EVENT_EP0_OUT) )
#define CYHAL_USB_DEV_IS_EP_NUM_VALID(endpoint) CY_USBFS_DEV_DRV_IS_EP_VALID(endpoint)
#define CYHAL_USB_DEV_IS_EP0_SIZE_VALID(ep0_size) (ep0_size >= CY_USBFS_DEV_DRV_EP0_BUFFER_SIZE)
#define CYHAL_USB_DEV_EVENT_NUM (4)
#define CYHAL_USB_DEV_EP_EVENT_NUM (CY_USBFS_DEV_DRV_NUM_EPS_MAX)
/* Clock configuration constants */
#define CYHAL_USB_DEV_USB_CLK_HF (3U) /* USBFS block dedicated path clock: CLK_HF3 */
#define CYHAL_USB_DEV_USB_CLK_HF_FREQ (48000000U) /* CLK_HF3 required frequency, Hz */
#define CYHAL_USB_DEV_BUS_RESET_CLOCK_HZ (100000U) /* Bus Reset require frequency, Hz */
typedef enum
{
CYHAL_USB_DEV_EP1_IDX = 0, /* Callback number for Endpoint 1 completion interrupt */
CYHAL_USB_DEV_EP2_IDX = 1, /* Callback number for Endpoint 2 completion interrupt */
CYHAL_USB_DEV_EP3_IDX = 2, /* Callback number for Endpoint 3 completion interrupt */
CYHAL_USB_DEV_EP4_IDX = 3, /* Callback number for Endpoint 4 completion interrupt */
CYHAL_USB_DEV_EP5_IDX = 4, /* Callback number for Endpoint 5 completion interrupt */
CYHAL_USB_DEV_EP6_IDX = 5, /* Callback number for Endpoint 6 completion interrupt */
CYHAL_USB_DEV_EP7_IDX = 6, /* Callback number for Endpoint 7 completion interrupt */
CYHAL_USB_DEV_EP8_IDX = 7, /* Callback number for Endpoint 8 completion interrupt */
} cyhal_usb_dev_ep_cb_num_t;
static USBFS_Type* const CYHAL_USB_DEV_BASE_ADDRESSES[CY_IP_MXUSBFS_INSTANCES] =
{
#ifdef USBFS0
USBFS0,
#endif
};
static IRQn_Type CYHAL_USBDEV_IRQ_N[CY_IP_MXUSBFS_INSTANCES] =
{
#ifdef USBFS0
usb_interrupt_lo_IRQn,
#endif
};
static bool cyhal_usb_dev_set_hf_divider(uint32_t clock, uint32_t input_freq, uint32_t target_freq);
static cy_rslt_t cyhal_usb_dev_reseve_pll(cyhal_resource_inst_t *rsc);
static cy_rslt_t cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq);
static uint32_t cyhal_usb_dev_get_pll_freq(uint32_t path);
static cy_rslt_t cyhal_usb_dev_hf_clock_setup(cyhal_usb_dev_t *obj);
static cy_rslt_t cyhal_usb_dev_peri_clock_setup(cyhal_usb_dev_t *obj, const cyhal_clock_divider_t *clk);
static cy_rslt_t cyhal_usb_dev_pin_setup(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm);
static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj);
static void cyhal_usb_0_dev_bus_reset_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext);
static void cyhal_usb_0_dev_ep0_setup_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext);
static void cyhal_usb_0_dev_ep0_in_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext);
static void cyhal_usb_0_dev_ep0_out_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext);
static cyhal_usb_dev_event_handler_t cyhal_usb_dev_event_callback_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM];
static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_event_cb_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EVENT_NUM] =
{
/* USBFS0 */
{
&cyhal_usb_0_dev_bus_reset_callback, /* CY_USB_DEV_BUS_RESET = 0U */
&cyhal_usb_0_dev_ep0_setup_callback, /* CY_USB_DEV_EP0_SETUP = 1U */
&cyhal_usb_0_dev_ep0_in_callback, /* CY_USB_DEV_EP0_IN = 2U */
&cyhal_usb_0_dev_ep0_out_callback /* CY_USB_DEV_EP0_OUT = 3U */
},
};
static void cyhal_usb_0_dev_sof_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext);
static cyhal_usb_dev_sof_handler_t cyhal_usb_dev_sof_user_callback[CY_IP_MXUSBFS_INSTANCES];
static cy_cb_usbfs_dev_drv_callback_t cyhal_usb_dev_drv_sof_cb_table[CY_IP_MXUSBFS_INSTANCES]=
{
/* USBFS0 */
&cyhal_usb_0_dev_sof_callback,
};
static void cyhal_usb_0_dev_ep_callback(USBFS_Type *base, uint32_t ep_addr, uint32_t errorType, cy_stc_usbfs_dev_drv_context_t *drvContext);
static cyhal_usb_dev_endpoint_handler_t cyhal_usb_dev_ep_handler_table[CY_IP_MXUSBFS_INSTANCES][CYHAL_USB_DEV_EP_EVENT_NUM];
static cy_cb_usbfs_dev_drv_ep_callback_t cyhal_usb_dev_drv_ep_cb_table[CY_IP_MXUSBFS_INSTANCES] =
{
/* USBFS0 */
&cyhal_usb_0_dev_ep_callback,
};
static void cyhal_usb_0_dev_bus_reset_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext)
{
(void) base; (void) drvContext;
cyhal_usb_dev_event_callback_table[0][CYHAL_USB_DEV_EVENT_BUS_RESET]();
}
static void cyhal_usb_0_dev_ep0_setup_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext)
{
(void) base; (void) drvContext;
cyhal_usb_dev_event_callback_table[0][CYHAL_USB_DEV_EVENT_EP0_SETUP]();
}
static void cyhal_usb_0_dev_ep0_in_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext)
{
(void) base; (void) drvContext;
cyhal_usb_dev_event_callback_table[0][CYHAL_USB_DEV_EVENT_EP0_IN]();
}
static void cyhal_usb_0_dev_ep0_out_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext)
{
(void) base; (void) drvContext;
cyhal_usb_dev_event_callback_table[0][CYHAL_USB_DEV_EVENT_EP0_OUT]();
}
static void cyhal_usb_0_dev_sof_callback(USBFS_Type *base, struct cy_stc_usbfs_dev_drv_context *drvContext)
{
(void) drvContext;
if (NULL != cyhal_usb_dev_sof_user_callback[0])
{
uint32_t frame_number = Cy_USBFS_Dev_Drv_GetSofNubmer(base);
cyhal_usb_dev_sof_user_callback[0](frame_number);
}
}
static void cyhal_usb_0_dev_ep_callback(USBFS_Type *base, uint32_t ep_addr, uint32_t errorType, cy_stc_usbfs_dev_drv_context_t *drvContext)
{
(void) base; (void) errorType; (void) drvContext;
uint32_t endpoint_idx = CYHAL_USB_DEV_GET_EP_IDX(ep_addr);
cyhal_usb_dev_endpoint_handler_t ep_handler = cyhal_usb_dev_ep_handler_table[0U][endpoint_idx];
if (NULL != ep_handler)
{
ep_handler(ep_addr);
}
}
static bool cyhal_usb_dev_set_hf_divider(uint32_t clock, uint32_t input_freq, uint32_t target_freq)
{
bool divider_found;
cy_en_clkhf_dividers_t divider;
if (target_freq == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_NO_DIVIDE;
}
else if ((target_freq * 2U) == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_DIVIDE_BY_2;
}
else if ((target_freq * 4U) == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_DIVIDE_BY_4;
}
else if ((target_freq * 8U) == input_freq)
{
divider_found = true;
divider = CY_SYSCLK_CLKHF_DIVIDE_BY_8;
}
else
{
divider_found = false;
}
if (divider_found)
{
Cy_SysClk_ClkHfSetDivider(clock, divider);
}
return divider_found;
}
static cy_rslt_t cyhal_usb_dev_reseve_pll(cyhal_resource_inst_t *rsc)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR_CLK_CFG;
uint32_t i;
rsc->type = CYHAL_RSC_CLKPATH;
rsc->channel_num = 0U;
for (i = 1U; i <= SRSS_NUM_PLL; ++i)
{
/* Set block number to path number that belongs to PLL */
rsc->block_num = i;
if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(rsc))
{
result = CY_RSLT_SUCCESS;
break;
}
}
if (CY_RSLT_SUCCESS != result)
{
/* Reservation failed mark type invalid */
rsc->type = CYHAL_RSC_INVALID;
}
return result;
}
static cy_rslt_t cyhal_usb_dev_init_pll(uint32_t clock, uint32_t pll, uint32_t target_freq)
{
cy_stc_pll_config_t cfg;
Cy_SysClk_PllDisable(pll);
Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll));
cfg.inputFreq = CY_SYSCLK_IMO_FREQ;
cfg.outputFreq = target_freq;
cfg.lfMode = false;
cfg.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO;
Cy_SysClk_ClkPathSetSource(pll, CY_SYSCLK_CLKPATH_IN_IMO);
cy_rslt_t result = Cy_SysClk_PllConfigure(pll, &cfg);
if (result == CY_RSLT_SUCCESS)
{
/* Wait up to 1 seconds for PLL to lock */
result = Cy_SysClk_PllEnable(pll, 1000000);
}
if (result == CY_RSLT_SUCCESS)
{
Cy_SysClk_ClkHfSetDivider(clock, CY_SYSCLK_CLKHF_NO_DIVIDE);
}
return result;
}
static uint32_t cyhal_usb_dev_get_pll_freq(uint32_t path)
{
/* PLL sourced from the IMO */
uint32_t freq = CY_SYSCLK_IMO_FREQ;
cy_stc_pll_manual_config_t pll_config;
Cy_SysClk_PllGetConfiguration(path, &pll_config);
if (pll_config.outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
{
freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)pll_config.feedbackDiv),
((uint64_t)pll_config.referenceDiv * (uint64_t)pll_config.outputDiv));
}
return freq;
}
static cy_rslt_t cyhal_usb_dev_hf_clock_setup(cyhal_usb_dev_t *obj)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR_CLK_CFG;
uint32_t clock = CYHAL_USB_DEV_USB_CLK_HF;
uint32_t path;
/* Start CLK_HF3 configuration */
Cy_SysClk_ClkHfDisable(clock);
/* Loop through all enabled PLLs and find one that matches requirements:
* sourced from IMO and frequency in multiple of 48MHz.
*/
for (path = 1U; path <= SRSS_NUM_PLL; ++path)
{
if ( Cy_SysClk_PllIsEnabled(path) &&
(CY_SYSCLK_CLKPATH_IN_IMO == Cy_SysClk_ClkPathGetSource(path)) )
{
/* Get PLL frequency */
uint32_t clk_pll_freq = cyhal_usb_dev_get_pll_freq(path);
/* Try to adjust CLK_HF3 divider to meet frequency requirements (48 MHz) */
if (cyhal_usb_dev_set_hf_divider(clock, clk_pll_freq, CYHAL_USB_DEV_USB_CLK_HF_FREQ))
{
/* Change path if it does not match after successful divider update */
if (Cy_SysClk_ClkHfGetSource(clock) != path)
{
Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t) path);
}
/* The existing PLL is used, mark to not try clear it */
result = CY_RSLT_SUCCESS;
break;
}
}
}
/* None of existing PLLs do meet USB requirements, try to allocate free */
if (CY_RSLT_SUCCESS != result)
{
result = cyhal_usb_dev_reseve_pll(&(obj->pll_resource));
if (CY_RSLT_SUCCESS == result)
{
/* Sets PLL source IMO and clear CLK_HF3 divider */
result = cyhal_usb_dev_init_pll(clock, obj->pll_resource.block_num, CYHAL_USB_DEV_USB_CLK_HF_FREQ);
}
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_hwmgr_set_configured(obj->pll_resource.type,
obj->pll_resource.block_num,
obj->pll_resource.channel_num);
}
}
/* End CLK_HF3 configuration */
Cy_SysClk_ClkHfEnable(clock);
if (result == CY_RSLT_SUCCESS)
{
SystemCoreClockUpdate();
}
return result;
}
static cy_rslt_t cyhal_usb_dev_peri_clock_setup(cyhal_usb_dev_t *obj, const cyhal_clock_divider_t *clk)
{
cy_rslt_t result;
cy_en_sysclk_status_t status = CY_SYSCLK_BAD_PARAM;
if (NULL == clk)
{
obj->shared_clock = false;
/* USB bus reset clock must be 100KHz. Usual peri clock frequency is > 26 MHz, which requires 16-bit divider */
result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, true);
if (CY_RSLT_SUCCESS == result)
{
/* Get divider to provide 100kHz clock or less */
uint32_t div_value = (cy_PeriClkFreqHz / CYHAL_USB_DEV_BUS_RESET_CLOCK_HZ) - 1U;
(void) Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num);
status = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div_value);
(void) Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num);
}
}
else
{
obj->clock = *clk;
obj->shared_clock = true;
status = CY_SYSCLK_SUCCESS;
}
if (CY_SYSCLK_SUCCESS == status)
{
status = Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, obj->clock.div_type, obj->clock.div_num);
}
result = (CY_SYSCLK_SUCCESS == status) ? CY_RSLT_SUCCESS : CYHAL_USB_DEV_RSLT_ERR_CLK_CFG;
return result;
}
static cy_rslt_t cyhal_usb_dev_pin_setup(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
const cyhal_resource_pin_mapping_t *dp_map = CY_UTILS_GET_RESOURCE(dp, cyhal_pin_map_usb_usb_dp_pad);
const cyhal_resource_pin_mapping_t *dm_map = CY_UTILS_GET_RESOURCE(dm, cyhal_pin_map_usb_usb_dm_pad);
if((NULL != dp_map) && (NULL != dm_map) &&
(dp_map->inst->block_num == dm_map->inst->block_num))
{
cyhal_resource_inst_t pin_rsc;
obj->resource = *dp_map->inst;
/* reserve DM and DP pins */
pin_rsc = cyhal_utils_get_gpio_resource(dp);
result = cyhal_hwmgr_reserve(&pin_rsc);
if (CY_RSLT_SUCCESS == result)
{
obj->pin_dp = dp;
pin_rsc = cyhal_utils_get_gpio_resource(dm);
result = cyhal_hwmgr_reserve(&pin_rsc);
}
if (CY_RSLT_SUCCESS == result)
{
obj->pin_dm = dm;
result = cyhal_connect_pin(dp_map);
}
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_connect_pin(dm_map);
}
}
return result;
}
static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj)
{
/* The object set into the default state in the cyhal_usb_dev_init() */
if (CYHAL_RSC_INVALID != obj->resource.type)
{
cyhal_hwmgr_set_unconfigured(obj->resource.type,
obj->resource.block_num,
obj->resource.channel_num);
cyhal_hwmgr_free(&(obj->resource));
}
if (CYHAL_RSC_INVALID != obj->pll_resource.type)
{
cyhal_hwmgr_set_unconfigured(obj->pll_resource.type,
obj->pll_resource.block_num,
obj->pll_resource.channel_num);
cyhal_hwmgr_free(&(obj->pll_resource));
}
if (!obj->shared_clock)
{
cyhal_hwmgr_free_clock(&(obj->clock));
}
if (CYHAL_NC_PIN_VALUE != obj->pin_dp)
{
cyhal_utils_disconnect_and_free(obj->pin_dp);
}
if (CYHAL_NC_PIN_VALUE != obj->pin_dm)
{
cyhal_utils_disconnect_and_free(obj->pin_dm);
}
}
cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk)
{
cy_rslt_t result;
CY_ASSERT(NULL != obj);
/* Reset object into the default state to handle resource free */
obj->base = NULL;
obj->resource.type = CYHAL_RSC_INVALID;
obj->pll_resource.type = CYHAL_RSC_INVALID;
obj->shared_clock = true;
obj->pin_dp = CYHAL_NC_PIN_VALUE;
obj->pin_dm = CYHAL_NC_PIN_VALUE;
result = cyhal_usb_dev_pin_setup(obj, dp, dm);
if (CY_RSLT_SUCCESS == result)
{
/* Configure CLK_HF3 frequency and proper path */
result = cyhal_usb_dev_hf_clock_setup(obj);
if (CY_RSLT_SUCCESS == result)
{
/* Configure CLK_PERI divider */
result = cyhal_usb_dev_peri_clock_setup(obj, clk);
}
}
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_hwmgr_reserve(&(obj->resource));
obj->base = CYHAL_USB_DEV_BASE_ADDRESSES[obj->resource.block_num];
}
if (CY_RSLT_SUCCESS == result)
{
bool configured = cyhal_hwmgr_is_configured(obj->resource.type,
obj->resource.block_num,
obj->resource.channel_num);
if (configured)
{
/* Check driver configuration (CYHAL supports only CPU management mode) */
if (_FLD2VAL(USBFS_USBDEV_ARB_CFG_DMA_CFG, USBFS_DEV_ARB_CFG(obj->base)) ==
CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU)
{
/* Set context to select 16-bit register access read/write API implementation */
obj->context.useReg16 = false;
}
else
{
result = CYHAL_USB_DEV_RSLT_ERR_BAD_DRV_CFG;
}
}
else
{
/* Configure driver */
static cy_stc_usbfs_dev_drv_config_t default_cfg =
{
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
.dmaConfig[0] = NULL,
.dmaConfig[1] = NULL,
.dmaConfig[2] = NULL,
.dmaConfig[3] = NULL,
.dmaConfig[4] = NULL,
.dmaConfig[5] = NULL,
.dmaConfig[6] = NULL,
.dmaConfig[7] = NULL,
.epBuffer = NULL,
.epBufferSize = 0U,
.intrLevelSel = CYHAL_USB_DEV_IRQ_LVL_DEFAULT,
.enableLpm = false,
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR
};
if (CY_USBFS_DEV_DRV_SUCCESS != Cy_USBFS_Dev_Drv_Init(obj->base,
&default_cfg,
&(obj->context)))
{
result = CYHAL_USB_DEV_RSLT_ERR;
}
if (CY_RSLT_SUCCESS == result)
{
result = cyhal_hwmgr_set_configured(obj->resource.type,
obj->resource.block_num,
obj->resource.channel_num);
}
}
}
if (CY_RSLT_SUCCESS == result)
{
uint32_t instance = obj->resource.block_num;
uint32_t cb_num;
/* Register service callbacks */
Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_BUS_RESET,
cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_BUS_RESET],
&(obj->context));
Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_SETUP,
cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_SETUP],
&(obj->context));
Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_IN,
cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_IN],
&(obj->context));
Cy_USBFS_Dev_Drv_RegisterServiceCallback(obj->base, CY_USB_DEV_EP0_OUT,
cyhal_usb_dev_drv_event_cb_table[instance][CY_USB_DEV_EP0_OUT],
&(obj->context));
/* Register sof callback (it enables sof interrupt, so disable it after registration) */
Cy_USBFS_Dev_Drv_RegisterSofCallback(obj->base, cyhal_usb_dev_drv_sof_cb_table[instance],
&(obj->context));
cyhal_usb_dev_sof_enable(obj, false);
/* Register data endpoint handlers */
for (cb_num = 0; cb_num < CYHAL_USB_DEV_EP_EVENT_NUM; cb_num++)
{
Cy_USBFS_Dev_Drv_RegisterEndpointCallback(obj->base,
(cb_num + 1U),
cyhal_usb_dev_drv_ep_cb_table[instance],
&(obj->context));
}
}
if (CY_RSLT_SUCCESS != result)
{
cyhal_usb_dev_free_resources(obj);
}
return result;
}
void cyhal_usb_dev_free(cyhal_usb_dev_t *obj)
{
cyhal_usb_dev_irq_enable(obj, false);
cyhal_usb_dev_disconnect(obj);
cyhal_usb_dev_free_resources(obj);
}
void cyhal_usb_dev_connect(cyhal_usb_dev_t *obj)
{
Cy_USBFS_Dev_Drv_Enable(obj->base, &(obj->context));
}
void cyhal_usb_dev_disconnect(cyhal_usb_dev_t *obj)
{
Cy_USBFS_Dev_Drv_Disable(obj->base, &(obj->context));
}
void cyhal_usb_dev_configure(cyhal_usb_dev_t *obj)
{
Cy_USBFS_Dev_Drv_ConfigDevice(obj->base, &(obj->context));
}
void cyhal_usb_dev_unconfigure(cyhal_usb_dev_t *obj)
{
Cy_USBFS_Dev_Drv_UnConfigureDevice(obj->base, &(obj->context));
}
void cyhal_usb_dev_sof_enable(cyhal_usb_dev_t *obj, bool enable)
{
uint32_t mask = Cy_USBFS_Dev_Drv_GetSieInterruptMask(obj->base);
if (enable)
{
mask |= CY_USBFS_DEV_DRV_INTR_SIE_SOF;
Cy_USBFS_Dev_Drv_ClearSieInterrupt(obj->base, CY_USBFS_DEV_DRV_INTR_SIE_SOF);
}
else
{
mask &= ~CY_USBFS_DEV_DRV_INTR_SIE_SOF;
}
Cy_USBFS_Dev_Drv_SetSieInterruptMask(obj->base, mask);
}
void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address)
{
Cy_USBFS_Dev_Drv_SetAddress(obj->base, address, &(obj->context));
}
uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj)
{
return Cy_USBFS_Dev_Drv_GetEp0MaxPacket(obj->base);
}
void cyhal_usb_dev_ep0_setup_read_result(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size)
{
CY_ASSERT_L1(CYHAL_USB_DEV_IS_EP0_SIZE_VALID(size));
Cy_USBFS_Dev_Drv_Ep0GetSetup(obj->base, buffer, &(obj->context));
}
void cyhal_usb_dev_ep0_read(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size)
{
Cy_USBFS_Dev_Drv_Ep0Read(obj->base, buffer, size, &(obj->context));
}
uint32_t cyhal_usb_dev_ep0_read_result(cyhal_usb_dev_t *obj)
{
return Cy_USBFS_Dev_Drv_Ep0ReadResult(obj->base, &(obj->context));
}
uint32_t cyhal_usb_dev_ep0_write(cyhal_usb_dev_t *obj, uint8_t *buffer, uint32_t size)
{
return Cy_USBFS_Dev_Drv_Ep0Write(obj->base, buffer, size, &(obj->context));
}
void cyhal_usb_dev_ep0_stall(cyhal_usb_dev_t *obj)
{
Cy_USBFS_Dev_Drv_Ep0Stall(obj->base);
}
cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enable,
cyhal_usb_dev_ep_t endpoint, uint32_t max_packet, cyhal_usb_dev_ep_type_t type)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
cy_stc_usb_dev_ep_config_t ep_config;
/* Set parameters to allocate endpoint buffer */
ep_config.allocBuffer = alloc;
ep_config.bufferSize = (uint16_t) max_packet;
/* Set parameters to enable endpoint operation */
ep_config.enableEndpoint = enable;
ep_config.endpointAddr = (uint8_t) endpoint;
ep_config.attributes = (uint8_t) type;
ep_config.maxPacketSize = (uint16_t) max_packet;
if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_AddEndpoint(obj->base,
&ep_config,
&(obj->context)))
{
result = CY_RSLT_SUCCESS;
}
return result;
}
cy_rslt_t cyhal_usb_dev_endpoint_remove(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_RemoveEndpoint(obj->base,
endpoint,
&(obj->context)))
{
result = CY_RSLT_SUCCESS;
}
return result;
}
cy_rslt_t cyhal_usb_dev_endpoint_stall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_StallEndpoint(obj->base,
CYHAL_USB_DEV_GET_EP_NUM(endpoint),
&(obj->context)))
{
result = CY_RSLT_SUCCESS;
}
return result;
}
cy_rslt_t cyhal_usb_dev_endpoint_unstall(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_UnStallEndpoint(obj->base,
CYHAL_USB_DEV_GET_EP_NUM(endpoint),
&(obj->context)))
{
result = CY_RSLT_SUCCESS;
}
return result;
}
bool cyhal_usb_dev_endpoint_is_stalled(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint)
{
bool is_stalled = (CY_USB_DEV_EP_STALLED == Cy_USBFS_Dev_Drv_GetEndpointState(obj->base,
CYHAL_USB_DEV_GET_EP_NUM(endpoint),
&(obj->context)));
return is_stalled;
}
cy_rslt_t cyhal_usb_dev_endpoint_read(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint8_t *data, uint32_t size)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint);
/* Check if endpoint is read for a read operation */
cy_en_usb_dev_ep_state_t ep_state;
ep_state = Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, ep_num, &(obj->context));
if ((CY_USB_DEV_EP_IDLE == ep_state) || (CY_USB_DEV_EP_COMPLETED == ep_state))
{
/* Save pointer and size to use in cyhal_usb_dev_endpoint_read_result */
obj->rd_data[CYHAL_USB_DEV_GET_EP_IDX(endpoint)] = data;
obj->rd_size[CYHAL_USB_DEV_GET_EP_IDX(endpoint)] = size;
Cy_USBFS_Dev_Drv_EnableOutEndpoint(obj->base, ep_num, &obj->context);
result = CY_RSLT_SUCCESS;
}
return result;
}
cy_rslt_t cyhal_usb_dev_endpoint_read_result(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint32_t *actSize)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint);
/* Check if endpoint is read for a read result operation */
if (CY_USB_DEV_EP_COMPLETED == Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, ep_num, &(obj->context)))
{
cy_en_usbfs_dev_drv_status_t drvStatus;
drvStatus = Cy_USBFS_Dev_Drv_ReadOutEndpoint(obj->base,
ep_num,
obj->rd_data[CYHAL_USB_DEV_GET_EP_IDX(endpoint)],
obj->rd_size[CYHAL_USB_DEV_GET_EP_IDX(endpoint)],
actSize,
&(obj->context));
if (drvStatus == CY_USBFS_DEV_DRV_SUCCESS)
{
result = CY_RSLT_SUCCESS;
}
}
return result;
}
cy_rslt_t cyhal_usb_dev_endpoint_write(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, uint8_t const *data, uint32_t size)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint);
/* Check if endpoint is read for a write operation */
cy_en_usb_dev_ep_state_t ep_state;
ep_state = Cy_USBFS_Dev_Drv_GetEndpointState(obj->base, ep_num, &(obj->context));
if ((CY_USB_DEV_EP_IDLE == ep_state) || (CY_USB_DEV_EP_COMPLETED == ep_state))
{
cy_en_usbfs_dev_drv_status_t drvStatus;
drvStatus = Cy_USBFS_Dev_Drv_LoadInEndpoint(obj->base,
ep_num,
data,
size,
&(obj->context));
if (drvStatus == CY_USBFS_DEV_DRV_SUCCESS)
{
result = CY_RSLT_SUCCESS;
}
}
return result;
}
cy_rslt_t cyhal_usb_dev_endpoint_abort(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
uint32_t ep_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint);
if (CY_USBFS_DEV_DRV_SUCCESS == Cy_USBFS_Dev_Drv_Abort(obj->base, ep_num, &(obj->context)))
{
result = CY_RSLT_SUCCESS;
}
return result;
}
void cyhal_usb_dev_irq_enable(cyhal_usb_dev_t *obj, bool enable)
{
uint32_t instance = (uint32_t)obj->resource.block_num;
if (enable)
{
NVIC_ClearPendingIRQ(CYHAL_USBDEV_IRQ_N[instance]);
NVIC_EnableIRQ(CYHAL_USBDEV_IRQ_N[instance]);
}
else
{
NVIC_DisableIRQ(CYHAL_USBDEV_IRQ_N[instance]);
}
}
void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj)
{
Cy_USBFS_Dev_Drv_Interrupt(obj->base,
Cy_USBFS_Dev_Drv_GetInterruptCauseLo(obj->base),
&(obj->context));
}
cy_rslt_t cyhal_usb_dev_register_irq(cyhal_usb_dev_t *obj, cyhal_usb_dev_irq_handler_t handler)
{
cy_rslt_t result = CYHAL_USB_DEV_RSLT_ERR;
cy_stc_sysint_t config;
uint32_t instance = (uint32_t)obj->resource.block_num;
/* Configure NVIC parameters */
config.intrPriority = CYHAL_USB_DEV_DEFAULT_IRQ_PRIORITY;
config.intrSrc = CYHAL_USBDEV_IRQ_N[instance];
/* Setup interrupt in NVIC to trigger the handler */
if (CY_SYSINT_SUCCESS == Cy_SysInt_Init(&config, (cy_israddress)handler))
{
result = CY_RSLT_SUCCESS;
}
return result;
}
void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_event_t event, cyhal_usb_dev_event_handler_t handler)
{
CY_ASSERT_L1(CYHAL_USB_DEV_IS_EVENT_VALID(event));
uint32_t instance = (uint32_t)obj->resource.block_num;
cyhal_usb_dev_event_callback_table[instance][event] = handler;
}
void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_handler_t handler)
{
uint32_t instance = (uint32_t)obj->resource.block_num;
cyhal_usb_dev_sof_user_callback[instance] = handler;
}
void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_handler_t handler)
{
uint32_t endpoint_num = CYHAL_USB_DEV_GET_EP_NUM(endpoint);
uint32_t instance = (uint32_t)obj->resource.block_num;
CY_ASSERT_L1(CYHAL_USB_DEV_IS_EP_NUM_VALID(endpoint_num));
cyhal_usb_dev_ep_handler_table[instance][CYHAL_USB_DEV_GET_EP_IDX(endpoint_num)]= handler;
}
#endif /* CY_IP_MXUSBFS) */

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/***************************************************************************//**
* \file cyhal_utils.c
*
* \brief
* Provides utility functions for working with the PSoC 6 HAL implementation.
*
********************************************************************************
* \copyright
* Copyright 2018-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_result.h"
#include "cyhal_utils.h"
#include "cyhal_hwmgr.h"
#include "cyhal_interconnect.h"
const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t* mappings, size_t count)
{
for (uint32_t i = 0; i < count; i++)
{
if (pin == mappings[i].pin)
{
return &mappings[i];
}
}
return NULL;
}
void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin)
{
cy_rslt_t rslt = cyhal_disconnect_pin(pin);
CY_ASSERT(CY_RSLT_SUCCESS == rslt);
cyhal_resource_inst_t rsc = cyhal_utils_get_gpio_resource(pin);
cyhal_hwmgr_free(&rsc);
}

730
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_104_m_csp_ble.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_104_M_CSP_BLE_H_)
#include "pin_packages/cyhal_psoc6_01_104_m_csp_ble.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_19 = { CYHAL_RSC_TCPWM, 1, 19 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = {
{P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
{P10_7, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_7_PASS_SARMUX_PADS7)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P8_6, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_3, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)},
{P1_3, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P5_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_5, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P8_7, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P10_7, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
};
#endif

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_104_m_csp_ble_usb.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_104_M_CSP_BLE_USB_H_)
#include "pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_19 = { CYHAL_RSC_TCPWM, 1, 19 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = {
{P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
{P10_7, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_7_PASS_SARMUX_PADS7)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P8_6, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[66] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P5_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_5, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P8_7, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P10_7, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
};
/* Connections for: usb_usb_dm_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = {
{USBDM, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDM_USB_USB_DM_PAD)},
};
/* Connections for: usb_usb_dp_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = {
{USBDP, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDP_USB_USB_DP_PAD)},
};
#endif

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_116_bga_ble.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 116-BGA-BLE package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_116_BGA_BLE_H_)
#include "pin_packages/cyhal_psoc6_01_116_bga_ble.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_DAC_0 = { CYHAL_RSC_DAC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_19 = { CYHAL_RSC_TCPWM, 1, 19 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
{P12_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P12_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
{P9_4, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_4_PASS_CTB_PADS4)},
{P9_5, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_5_PASS_CTB_PADS5)},
{P9_6, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
{P9_7, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_7_PASS_CTB_PADS7)},
};
/* Connections for: pass_ctdac_voutsw */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = {
{P9_6, &CYHAL_DAC_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[10] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[10] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[10] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[10] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_2, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)},
{P1_2, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P8_6, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P9_6, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
{P9_6, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
{P13_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_3, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)},
{P1_3, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_5, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P8_7, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_5, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
{P9_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{P13_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
};
#endif

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_116_bga_usb.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 116-BGA-USB package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_116_BGA_USB_H_)
#include "pin_packages/cyhal_psoc6_01_116_bga_usb.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_DAC_0 = { CYHAL_RSC_DAC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_19 = { CYHAL_RSC_TCPWM, 1, 19 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
{P12_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P12_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
{P9_4, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_4_PASS_CTB_PADS4)},
{P9_5, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_5_PASS_CTB_PADS5)},
{P9_6, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
{P9_7, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_7_PASS_CTB_PADS7)},
};
/* Connections for: pass_ctdac_voutsw */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = {
{P9_6, &CYHAL_DAC_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[9] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[9] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[76] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_2, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)},
{P1_2, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P8_6, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P9_6, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
{P9_6, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
{P13_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[70] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_5, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P8_7, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_5, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
{P9_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{P13_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
};
/* Connections for: usb_usb_dm_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = {
{USBDM, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDM_USB_USB_DM_PAD)},
};
/* Connections for: usb_usb_dp_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = {
{USBDP, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDP_USB_USB_DP_PAD)},
};
#endif

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_124_bga.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 124-BGA package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_124_BGA_H_)
#include "pin_packages/cyhal_psoc6_01_124_bga.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_DAC_0 = { CYHAL_RSC_DAC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_19 = { CYHAL_RSC_TCPWM, 1, 19 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
{P12_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P12_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: bless_mxd_act_bpktctl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1] = {
{P3_3, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P3_3_BLESS_MXD_ACT_BPKTCTL)},
};
/* Connections for: bless_mxd_act_dbus_rx_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1] = {
{P3_1, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P3_1_BLESS_MXD_ACT_DBUS_RX_EN)},
};
/* Connections for: bless_mxd_act_dbus_tx_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1] = {
{P3_2, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P3_2_BLESS_MXD_ACT_DBUS_TX_EN)},
};
/* Connections for: bless_mxd_act_txd_rxd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1] = {
{P3_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P3_4_BLESS_MXD_ACT_TXD_RXD)},
};
/* Connections for: bless_mxd_dpslp_act_ldo_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1] = {
{P2_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_6_BLESS_MXD_DPSLP_ACT_LDO_EN)},
};
/* Connections for: bless_mxd_dpslp_buck_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1] = {
{P2_2, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_2_BLESS_MXD_DPSLP_BUCK_EN)},
};
/* Connections for: bless_mxd_dpslp_clk_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1] = {
{P2_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_4_BLESS_MXD_DPSLP_CLK_EN)},
};
/* Connections for: bless_mxd_dpslp_dig_ldo_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1] = {
{P3_0, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P3_0_BLESS_MXD_DPSLP_DIG_LDO_EN)},
};
/* Connections for: bless_mxd_dpslp_isolate_n */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1] = {
{P2_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_5_BLESS_MXD_DPSLP_ISOLATE_N)},
};
/* Connections for: bless_mxd_dpslp_rcb_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1] = {
{P4_0, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P4_0_BLESS_MXD_DPSLP_RCB_CLK)},
};
/* Connections for: bless_mxd_dpslp_rcb_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1] = {
{P3_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P3_5_BLESS_MXD_DPSLP_RCB_DATA)},
};
/* Connections for: bless_mxd_dpslp_rcb_le */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1] = {
{P4_1, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P4_1_BLESS_MXD_DPSLP_RCB_LE)},
};
/* Connections for: bless_mxd_dpslp_reset_n */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1] = {
{P2_3, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_3_BLESS_MXD_DPSLP_RESET_N)},
};
/* Connections for: bless_mxd_dpslp_ret_ldo_ol_hv */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1] = {
{P2_1, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_1_BLESS_MXD_DPSLP_RET_LDO_OL_HV)},
};
/* Connections for: bless_mxd_dpslp_ret_switch_hv */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1] = {
{P2_0, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_0_BLESS_MXD_DPSLP_RET_SWITCH_HV)},
};
/* Connections for: bless_mxd_dpslp_xtal_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1] = {
{P2_7, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P2_7_BLESS_MXD_DPSLP_XTAL_EN)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = {
{P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
{P9_4, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_4_PASS_CTB_PADS4)},
{P9_5, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_5_PASS_CTB_PADS5)},
{P9_6, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
{P9_7, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_7_PASS_CTB_PADS7)},
};
/* Connections for: pass_ctdac_voutsw */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = {
{P9_6, &CYHAL_DAC_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
{P10_7, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_7_PASS_SARMUX_PADS7)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)},
{P3_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)},
{P4_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)},
{P3_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)},
{P4_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P2_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)},
{P3_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)},
{P3_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)},
{P4_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)},
{P3_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)},
{P4_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P2_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
{P3_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P2_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_4_SCB1_SPI_SELECT1)},
{P3_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_4_SCB2_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
{P13_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P2_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB1_SPI_SELECT2)},
{P3_5, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_5_SCB2_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
{P13_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10] = {
{P2_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB1_SPI_SELECT3)},
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P2_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_2_SCB1_SPI_CLK)},
{P3_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_2_SCB2_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_SPI_MISO)},
{P3_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_SPI_MISO)},
{P4_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_SPI_MOSI)},
{P3_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_SPI_MOSI)},
{P4_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P2_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
{P3_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P2_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_4_SCB1_SPI_SELECT1)},
{P3_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_4_SCB2_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
{P13_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P2_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_5_SCB1_SPI_SELECT2)},
{P3_5, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_5_SCB2_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
{P13_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10] = {
{P2_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_6_SCB1_SPI_SELECT3)},
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
{P2_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)},
{P3_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[14] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
{P2_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)},
{P3_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)},
{P3_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)},
{P4_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)},
{P3_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)},
{P4_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_2, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)},
{P1_2, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P2_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)},
{P2_0, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)},
{P2_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)},
{P2_2, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)},
{P2_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)},
{P2_4, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)},
{P2_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)},
{P2_6, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)},
{P3_0, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)},
{P3_0, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)},
{P3_2, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)},
{P3_2, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)},
{P3_4, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)},
{P3_4, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)},
{P4_0, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)},
{P4_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P8_6, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P9_6, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
{P9_6, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)},
{P13_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)},
{P13_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)},
{P13_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)},
{P13_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
{P13_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_3, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)},
{P1_3, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P2_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)},
{P2_1, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)},
{P2_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)},
{P2_3, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)},
{P2_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)},
{P2_5, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)},
{P2_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)},
{P2_7, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)},
{P3_1, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)},
{P3_1, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)},
{P3_3, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)},
{P3_3, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)},
{P3_5, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)},
{P3_5, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)},
{P4_1, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)},
{P4_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P5_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_5, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P8_7, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_5, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
{P9_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P10_7, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)},
{P13_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)},
{P13_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)},
{P13_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)},
{P13_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{P13_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
};
/* Connections for: usb_usb_dm_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = {
{USBDM, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDM_USB_USB_DM_PAD)},
};
/* Connections for: usb_usb_dp_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = {
{USBDP, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDP_USB_USB_DP_PAD)},
};
#endif

805
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_124_bga_sip.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 124-BGA-SIP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_124_BGA_SIP_H_)
#include "pin_packages/cyhal_psoc6_01_124_bga_sip.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_DAC_0 = { CYHAL_RSC_DAC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_19 = { CYHAL_RSC_TCPWM, 1, 19 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
{P12_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P12_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = {
{P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
{P9_4, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_4_PASS_CTB_PADS4)},
{P9_5, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_5_PASS_CTB_PADS5)},
{P9_6, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
{P9_7, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_7_PASS_CTB_PADS7)},
};
/* Connections for: pass_ctdac_voutsw */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = {
{P9_6, &CYHAL_DAC_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
{P10_7, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_7_PASS_SARMUX_PADS7)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
{P13_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
{P13_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[9] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_2_SCB7_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
{P13_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P8_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_5_SCB4_SPI_SELECT2)},
{P8_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P8_7_SCB3_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
{P13_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[9] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P8_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_6_SCB4_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[12] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P1_3, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P1_2, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[82] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_2, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)},
{P1_2, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P8_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
{P8_6, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P9_6, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
{P9_6, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)},
{P13_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)},
{P13_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)},
{P13_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)},
{P13_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
{P13_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_3, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)},
{P1_3, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P5_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P8_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
{P8_5, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
{P8_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
{P8_7, &CYHAL_TCPWM_1_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_5, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
{P9_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P10_7, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)},
{P13_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)},
{P13_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)},
{P13_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)},
{P13_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{P13_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
};
/* Connections for: usb_usb_dm_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = {
{USBDM, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDM_USB_USB_DM_PAD)},
};
/* Connections for: usb_usb_dp_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = {
{USBDP, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDP_USB_USB_DP_PAD)},
};
#endif

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_43_smt.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 43-SMT package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_43_SMT_H_)
#include "pin_packages/cyhal_psoc6_01_43_smt.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_DAC_0 = { CYHAL_RSC_DAC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[7] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
{P9_4, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_4_PASS_CTB_PADS4)},
{P9_5, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_5_PASS_CTB_PADS5)},
{P9_6, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
};
/* Connections for: pass_ctdac_voutsw */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1] = {
{P9_6, &CYHAL_DAC_0, CYHAL_PIN_ANALOG_FUNCTION(P9_6_PASS_CTB_PADS6)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5] = {
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6] = {
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6] = {
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[5] = {
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6] = {
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[5] = {
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P9_5, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_5_SCB2_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P9_6, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_6_SCB2_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4] = {
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5] = {
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P9_6, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
{P9_6, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_5, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
{P9_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
};
#endif

489
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_68_qfn_ble.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 68-QFN-BLE package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_68_QFN_BLE_H_)
#include "pin_packages/cyhal_psoc6_01_68_qfn_ble.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_BLESS_0 = { CYHAL_RSC_BLESS, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
/* Pin connections */
/* Connections for: bless_ext_lna_rx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1] = {
{P7_4, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_4_BLESS_EXT_LNA_RX_CTL_OUT)},
};
/* Connections for: bless_ext_pa_lna_chip_en_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1] = {
{P7_6, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_6_BLESS_EXT_PA_LNA_CHIP_EN_OUT)},
};
/* Connections for: bless_ext_pa_tx_ctl_out */
const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1] = {
{P7_5, &CYHAL_BLESS_0, CYHAL_PIN_OUT_FUNCTION(P7_5_BLESS_EXT_PA_TX_CTL_OUT)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3] = {
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P7_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_4_SCB4_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P7_5, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_5_SCB4_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3] = {
{P7_6, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_6_SCB4_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P7_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
{P7_4, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
{P7_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
{P7_6, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
{P7_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
};
#endif

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targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_01_80_wlcsp.c
*
* \brief
* PSoC6_01 device GPIO HAL header for 80-WLCSP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_01_80_WLCSP_H_)
#include "pin_packages/cyhal_psoc6_01_80_wlcsp.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_OPAMP_0 = { CYHAL_RSC_OPAMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS_PDM_DATA)},
{P12_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P12_5_AUDIOSS_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS_TX_WS)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = {
{P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_ctb_oa0_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_OA0_OUT_10X)},
};
/* Connections for: pass_ctb_oa1_out_10x */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_OA1_OUT_10X)},
};
/* Connections for: pass_ctb_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6] = {
{P9_0, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_0_PASS_CTB_PADS0)},
{P9_1, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_1_PASS_CTB_PADS1)},
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_2_PASS_CTB_PADS2)},
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_3_PASS_CTB_PADS3)},
{P9_4, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_4_PASS_CTB_PADS4)},
{P9_7, &CYHAL_OPAMP_0, CYHAL_PIN_ANALOG_FUNCTION(P9_7_PASS_CTB_PADS7)},
};
/* Connections for: pass_dsi_ctb_cmp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1] = {
{P9_2, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_2_PASS_DSI_CTB_CMP0)},
};
/* Connections for: pass_dsi_ctb_cmp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1] = {
{P9_3, &CYHAL_OPAMP_0, CYHAL_PIN_OUT_FUNCTION(P9_3_PASS_DSI_CTB_CMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[13] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[13] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[13] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[11] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[13] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[11] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4] = {
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[9] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[60] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[60] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P5_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_7, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
};
/* Connections for: usb_usb_dm_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = {
{USBDM, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDM_USB_USB_DM_PAD)},
};
/* Connections for: usb_usb_dp_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = {
{USBDP, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDP_USB_USB_DP_PAD)},
};
#endif

853
targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c Normal file
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/***************************************************************************//**
* \file cyhal_psoc6_02_100_wlcsp.c
*
* \brief
* PSoC6_02 device GPIO HAL header for 100-WLCSP package
*
* \note
* Generator version: 1.4.7107.26790
*
********************************************************************************
* \copyright
* Copyright 2016-2019 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/
#include "cy_device_headers.h"
#include "cyhal_hw_types.h"
#if defined(_GPIO_PSOC6_02_100_WLCSP_H_)
#include "pin_packages/cyhal_psoc6_02_100_wlcsp.h"
/* Hardware Blocks */
static const cyhal_resource_inst_t CYHAL_I2S_0 = { CYHAL_RSC_I2S, 0, 0 };
static const cyhal_resource_inst_t CYHAL_PDM_0 = { CYHAL_RSC_PDM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_I2S_1 = { CYHAL_RSC_I2S, 1, 0 };
static const cyhal_resource_inst_t CYHAL_LPCOMP_0_0 = { CYHAL_RSC_LPCOMP, 0, 0 };
static const cyhal_resource_inst_t CYHAL_ADC_0 = { CYHAL_RSC_ADC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_0 = { CYHAL_RSC_SCB, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_1 = { CYHAL_RSC_SCB, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_10 = { CYHAL_RSC_SCB, 10, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_11 = { CYHAL_RSC_SCB, 11, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_12 = { CYHAL_RSC_SCB, 12, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_2 = { CYHAL_RSC_SCB, 2, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_3 = { CYHAL_RSC_SCB, 3, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_4 = { CYHAL_RSC_SCB, 4, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_5 = { CYHAL_RSC_SCB, 5, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_6 = { CYHAL_RSC_SCB, 6, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_7 = { CYHAL_RSC_SCB, 7, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_8 = { CYHAL_RSC_SCB, 8, 0 };
static const cyhal_resource_inst_t CYHAL_SCB_9 = { CYHAL_RSC_SCB, 9, 0 };
static const cyhal_resource_inst_t CYHAL_SDHC_0 = { CYHAL_RSC_SDHC, 0, 0 };
static const cyhal_resource_inst_t CYHAL_SDHC_1 = { CYHAL_RSC_SDHC, 1, 0 };
static const cyhal_resource_inst_t CYHAL_SMIF_0 = { CYHAL_RSC_SMIF, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_0 = { CYHAL_RSC_TCPWM, 0, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_1 = { CYHAL_RSC_TCPWM, 0, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_2 = { CYHAL_RSC_TCPWM, 0, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_3 = { CYHAL_RSC_TCPWM, 0, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_4 = { CYHAL_RSC_TCPWM, 0, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_5 = { CYHAL_RSC_TCPWM, 0, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_6 = { CYHAL_RSC_TCPWM, 0, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_0_7 = { CYHAL_RSC_TCPWM, 0, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_0 = { CYHAL_RSC_TCPWM, 1, 0 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_1 = { CYHAL_RSC_TCPWM, 1, 1 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_10 = { CYHAL_RSC_TCPWM, 1, 10 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_11 = { CYHAL_RSC_TCPWM, 1, 11 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_12 = { CYHAL_RSC_TCPWM, 1, 12 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_13 = { CYHAL_RSC_TCPWM, 1, 13 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_15 = { CYHAL_RSC_TCPWM, 1, 15 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_16 = { CYHAL_RSC_TCPWM, 1, 16 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_17 = { CYHAL_RSC_TCPWM, 1, 17 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_18 = { CYHAL_RSC_TCPWM, 1, 18 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_2 = { CYHAL_RSC_TCPWM, 1, 2 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_20 = { CYHAL_RSC_TCPWM, 1, 20 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_21 = { CYHAL_RSC_TCPWM, 1, 21 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_22 = { CYHAL_RSC_TCPWM, 1, 22 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_23 = { CYHAL_RSC_TCPWM, 1, 23 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_3 = { CYHAL_RSC_TCPWM, 1, 3 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_4 = { CYHAL_RSC_TCPWM, 1, 4 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_5 = { CYHAL_RSC_TCPWM, 1, 5 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_6 = { CYHAL_RSC_TCPWM, 1, 6 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_7 = { CYHAL_RSC_TCPWM, 1, 7 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_8 = { CYHAL_RSC_TCPWM, 1, 8 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_9 = { CYHAL_RSC_TCPWM, 1, 9 };
static const cyhal_resource_inst_t CYHAL_TCPWM_1_14 = { CYHAL_RSC_TCPWM, 1, 14 };
static const cyhal_resource_inst_t CYHAL_USB_0 = { CYHAL_RSC_USB, 0, 0 };
/* Pin connections */
/* Connections for: audioss_clk_i2s_if */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4] = {
{P5_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_0_AUDIOSS0_CLK_I2S_IF)},
{P9_0, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P9_0_AUDIOSS0_CLK_I2S_IF)},
{P11_0, &CYHAL_I2S_1, CYHAL_PIN_IN_FUNCTION(P11_0_AUDIOSS1_CLK_I2S_IF)},
{P13_0, &CYHAL_I2S_1, CYHAL_PIN_IN_FUNCTION(P13_0_AUDIOSS1_CLK_I2S_IF)},
};
/* Connections for: audioss_pdm_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2] = {
{P10_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P10_4_AUDIOSS0_PDM_CLK)},
{P12_4, &CYHAL_PDM_0, CYHAL_PIN_OUT_FUNCTION(P12_4_AUDIOSS0_PDM_CLK)},
};
/* Connections for: audioss_pdm_data */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2] = {
{P10_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P10_5_AUDIOSS0_PDM_DATA)},
{P12_5, &CYHAL_PDM_0, CYHAL_PIN_IN_FUNCTION(P12_5_AUDIOSS0_PDM_DATA)},
};
/* Connections for: audioss_rx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4] = {
{P5_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_4_AUDIOSS0_RX_SCK)},
{P9_4, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P9_4_AUDIOSS0_RX_SCK)},
{P11_4, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P11_4_AUDIOSS1_RX_SCK)},
{P13_4, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P13_4_AUDIOSS1_RX_SCK)},
};
/* Connections for: audioss_rx_sdi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3] = {
{P5_6, &CYHAL_I2S_0, CYHAL_PIN_IN_FUNCTION(P5_6_AUDIOSS0_RX_SDI)},
{P11_6, &CYHAL_I2S_1, CYHAL_PIN_IN_FUNCTION(P11_6_AUDIOSS1_RX_SDI)},
{P13_6, &CYHAL_I2S_1, CYHAL_PIN_IN_FUNCTION(P13_6_AUDIOSS1_RX_SDI)},
};
/* Connections for: audioss_rx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3] = {
{P5_5, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_5_AUDIOSS0_RX_WS)},
{P11_5, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P11_5_AUDIOSS1_RX_WS)},
{P13_5, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P13_5_AUDIOSS1_RX_WS)},
};
/* Connections for: audioss_tx_sck */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4] = {
{P5_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_1_AUDIOSS0_TX_SCK)},
{P9_1, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P9_1_AUDIOSS0_TX_SCK)},
{P11_1, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P11_1_AUDIOSS1_TX_SCK)},
{P13_1, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P13_1_AUDIOSS1_TX_SCK)},
};
/* Connections for: audioss_tx_sdo */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4] = {
{P5_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_3_AUDIOSS0_TX_SDO)},
{P9_3, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P9_3_AUDIOSS0_TX_SDO)},
{P11_3, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P11_3_AUDIOSS1_TX_SDO)},
{P13_3, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P13_3_AUDIOSS1_TX_SDO)},
};
/* Connections for: audioss_tx_ws */
const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4] = {
{P5_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P5_2_AUDIOSS0_TX_WS)},
{P9_2, &CYHAL_I2S_0, CYHAL_PIN_OUT_FUNCTION(P9_2_AUDIOSS0_TX_WS)},
{P11_2, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P11_2_AUDIOSS1_TX_WS)},
{P13_2, &CYHAL_I2S_1, CYHAL_PIN_OUT_FUNCTION(P13_2_AUDIOSS1_TX_WS)},
};
/* Connections for: lpcomp_dsi_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1] = {
{P8_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_2_LPCOMP_DSI_COMP0)},
};
/* Connections for: lpcomp_dsi_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1] = {
{P8_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_OUT_FUNCTION(P8_3_LPCOMP_DSI_COMP1)},
};
/* Connections for: lpcomp_inn_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1] = {
{P5_7, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_7_LPCOMP_INN_COMP0)},
};
/* Connections for: lpcomp_inn_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1] = {
{P6_3, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_3_LPCOMP_INN_COMP1)},
};
/* Connections for: lpcomp_inp_comp0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1] = {
{P5_6, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P5_6_LPCOMP_INP_COMP0)},
};
/* Connections for: lpcomp_inp_comp1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1] = {
{P6_2, &CYHAL_LPCOMP_0_0, CYHAL_PIN_ANALOG_FUNCTION(P6_2_LPCOMP_INP_COMP1)},
};
/* Connections for: pass_sarmux_pads */
const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8] = {
{P10_0, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_0_PASS_SARMUX_PADS0)},
{P10_1, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_1_PASS_SARMUX_PADS1)},
{P10_2, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_2_PASS_SARMUX_PADS2)},
{P10_3, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_3_PASS_SARMUX_PADS3)},
{P10_4, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_4_PASS_SARMUX_PADS4)},
{P10_5, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_5_PASS_SARMUX_PADS5)},
{P10_6, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_6_PASS_SARMUX_PADS6)},
{P10_7, &CYHAL_ADC_0, CYHAL_PIN_ANALOG_FUNCTION(P10_7_PASS_SARMUX_PADS7)},
};
/* Connections for: scb_i2c_scl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)},
{P2_4, &CYHAL_SCB_9, CYHAL_PIN_OD_FUNCTION(P2_4_SCB9_I2C_SCL)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
{P5_4, &CYHAL_SCB_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
{P8_4, &CYHAL_SCB_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
{P13_4, &CYHAL_SCB_12, CYHAL_PIN_OD_FUNCTION(P13_4_SCB12_I2C_SCL)},
};
/* Connections for: scb_i2c_sda */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)},
{P2_5, &CYHAL_SCB_9, CYHAL_PIN_OD_FUNCTION(P2_5_SCB9_I2C_SDA)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
{P5_5, &CYHAL_SCB_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
{P13_5, &CYHAL_SCB_12, CYHAL_PIN_OD_FUNCTION(P13_5_SCB12_I2C_SDA)},
};
/* Connections for: scb_spi_m_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P2_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_m_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[15] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_m_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_m_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P2_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_m_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P2_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_4_SCB1_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
{P13_4, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_m_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P2_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB1_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
{P13_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_m_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[7] = {
{P2_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB1_SPI_SELECT3)},
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_spi_s_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_4_SCB0_SPI_CLK)},
{P2_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_2_SCB1_SPI_CLK)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_2_SCB5_SPI_CLK)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_2_SCB3_SPI_CLK)},
{P6_2, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_2_SCB8_SPI_CLK)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_6_SCB6_SPI_CLK)},
{P6_6, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_6_SCB8_SPI_CLK)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_2_SCB4_SPI_CLK)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_2_SCB4_SPI_CLK)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_2_SCB2_SPI_CLK)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_2_SCB1_SPI_CLK)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_2_SCB5_SPI_CLK)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_2_SCB6_SPI_CLK)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_2_SCB6_SPI_CLK)},
};
/* Connections for: scb_spi_s_miso */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[15] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_SPI_MISO)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_SPI_MISO)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_SPI_MISO)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_SPI_MISO)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_SPI_MISO)},
{P6_1, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB8_SPI_MISO)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_SPI_MISO)},
{P6_5, &CYHAL_SCB_8, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB8_SPI_MISO)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_SPI_MISO)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_SPI_MISO)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_SPI_MISO)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_SPI_MISO)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_SPI_MISO)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_SPI_MISO)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_SPI_MISO)},
};
/* Connections for: scb_spi_s_mosi */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_SPI_MOSI)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_SPI_MOSI)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_SPI_MOSI)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_SPI_MOSI)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_SPI_MOSI)},
{P6_0, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_0_SCB8_SPI_MOSI)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_SPI_MOSI)},
{P6_4, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_4_SCB8_SPI_MOSI)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_SPI_MOSI)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_SPI_MOSI)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_SPI_MOSI)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_SPI_MOSI)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_SPI_MOSI)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_SPI_MOSI)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_SPI_MOSI)},
};
/* Connections for: scb_spi_s_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
{P2_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
{P6_3, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
{P6_7, &CYHAL_SCB_8, CYHAL_PIN_IN_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_SPI_SELECT0)},
};
/* Connections for: scb_spi_s_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11] = {
{P0_0, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_0_SCB0_SPI_SELECT1)},
{P1_4, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_4_SCB7_SPI_SELECT1)},
{P2_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_4_SCB1_SPI_SELECT1)},
{P5_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_4_SCB5_SPI_SELECT1)},
{P7_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P7_7_SCB3_SPI_SELECT1)},
{P8_4, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_4_SCB4_SPI_SELECT1)},
{P9_4, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_4_SCB2_SPI_SELECT1)},
{P10_4, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_4_SCB1_SPI_SELECT1)},
{P11_4, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_4_SCB5_SPI_SELECT1)},
{P12_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_4_SCB6_SPI_SELECT1)},
{P13_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_4_SCB6_SPI_SELECT1)},
};
/* Connections for: scb_spi_s_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8] = {
{P0_1, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_1_SCB0_SPI_SELECT2)},
{P1_5, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_5_SCB7_SPI_SELECT2)},
{P2_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_5_SCB1_SPI_SELECT2)},
{P5_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_5_SCB5_SPI_SELECT2)},
{P10_5, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_5_SCB1_SPI_SELECT2)},
{P11_5, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_5_SCB5_SPI_SELECT2)},
{P12_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_5_SCB6_SPI_SELECT2)},
{P13_5, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_5_SCB6_SPI_SELECT2)},
};
/* Connections for: scb_spi_s_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[7] = {
{P2_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_6_SCB1_SPI_SELECT3)},
{P5_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_6_SCB5_SPI_SELECT3)},
{P5_7, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P5_7_SCB3_SPI_SELECT3)},
{P10_6, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_6_SCB1_SPI_SELECT3)},
{P11_6, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_6_SCB5_SPI_SELECT3)},
{P12_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_6_SCB6_SPI_SELECT3)},
{P13_6, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_6_SCB6_SPI_SELECT3)},
};
/* Connections for: scb_uart_cts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15] = {
{P0_5, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
{P2_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)},
{P2_7, &CYHAL_SCB_9, CYHAL_PIN_IN_FUNCTION(P2_7_SCB9_UART_CTS)},
{P5_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
{P5_7, &CYHAL_SCB_10, CYHAL_PIN_IN_FUNCTION(P5_7_SCB10_UART_CTS)},
{P6_3, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
{P6_7, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
{P7_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
{P8_3, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
{P9_3, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
{P10_3, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
{P11_3, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
{P12_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
{P13_3, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)},
{P13_7, &CYHAL_SCB_12, CYHAL_PIN_IN_FUNCTION(P13_7_SCB12_UART_CTS)},
};
/* Connections for: scb_uart_rts */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15] = {
{P0_4, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
{P2_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)},
{P2_6, &CYHAL_SCB_9, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB9_UART_RTS)},
{P5_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
{P5_6, &CYHAL_SCB_10, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB10_UART_RTS)},
{P6_2, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
{P6_6, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
{P7_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
{P8_2, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
{P9_2, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
{P10_2, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
{P11_2, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
{P12_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
{P13_2, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)},
{P13_6, &CYHAL_SCB_12, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB12_UART_RTS)},
};
/* Connections for: scb_uart_rx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17] = {
{P0_2, &CYHAL_SCB_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
{P1_0, &CYHAL_SCB_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
{P2_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)},
{P2_4, &CYHAL_SCB_9, CYHAL_PIN_IN_FUNCTION(P2_4_SCB9_UART_RX)},
{P5_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
{P5_4, &CYHAL_SCB_10, CYHAL_PIN_IN_FUNCTION(P5_4_SCB10_UART_RX)},
{P6_0, &CYHAL_SCB_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
{P6_4, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
{P7_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
{P8_0, &CYHAL_SCB_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
{P8_4, &CYHAL_SCB_11, CYHAL_PIN_IN_FUNCTION(P8_4_SCB11_UART_RX)},
{P9_0, &CYHAL_SCB_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
{P10_0, &CYHAL_SCB_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
{P11_0, &CYHAL_SCB_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
{P12_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
{P13_0, &CYHAL_SCB_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
{P13_4, &CYHAL_SCB_12, CYHAL_PIN_IN_FUNCTION(P13_4_SCB12_UART_RX)},
};
/* Connections for: scb_uart_tx */
const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16] = {
{P0_3, &CYHAL_SCB_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
{P1_1, &CYHAL_SCB_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
{P2_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)},
{P2_5, &CYHAL_SCB_9, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB9_UART_TX)},
{P5_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
{P5_5, &CYHAL_SCB_10, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB10_UART_TX)},
{P6_1, &CYHAL_SCB_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
{P6_5, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
{P7_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
{P8_1, &CYHAL_SCB_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
{P9_1, &CYHAL_SCB_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
{P10_1, &CYHAL_SCB_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
{P11_1, &CYHAL_SCB_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
{P12_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
{P13_1, &CYHAL_SCB_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
{P13_5, &CYHAL_SCB_12, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB12_UART_TX)},
};
/* Connections for: sdhc_card_cmd */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2] = {
{P2_4, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_4_SDHC0_CARD_CMD)},
{P12_4, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P12_4_SDHC1_CARD_CMD)},
};
/* Connections for: sdhc_card_dat_3to0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8] = {
{P2_0, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_0_SDHC0_CARD_DAT_3TO00)},
{P2_1, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_1_SDHC0_CARD_DAT_3TO01)},
{P2_2, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_2_SDHC0_CARD_DAT_3TO02)},
{P2_3, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_3_SDHC0_CARD_DAT_3TO03)},
{P13_0, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_0_SDHC1_CARD_DAT_3TO00)},
{P13_1, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_1_SDHC1_CARD_DAT_3TO01)},
{P13_2, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_2_SDHC1_CARD_DAT_3TO02)},
{P13_3, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_3_SDHC1_CARD_DAT_3TO03)},
};
/* Connections for: sdhc_card_dat_7to4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4] = {
{P13_4, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_4_SDHC1_CARD_DAT_7TO40)},
{P13_5, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_5_SDHC1_CARD_DAT_7TO41)},
{P13_6, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_6_SDHC1_CARD_DAT_7TO42)},
{P13_7, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P13_7_SDHC1_CARD_DAT_7TO43)},
};
/* Connections for: sdhc_card_detect_n */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2] = {
{P2_6, &CYHAL_SDHC_0, CYHAL_PIN_IN_FUNCTION(P2_6_SDHC0_CARD_DETECT_N)},
{P12_1, &CYHAL_SDHC_1, CYHAL_PIN_IN_FUNCTION(P12_1_SDHC1_CARD_DETECT_N)},
};
/* Connections for: sdhc_card_emmc_reset_n */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1] = {
{P12_0, &CYHAL_SDHC_1, CYHAL_PIN_OUT_FUNCTION(P12_0_SDHC1_CARD_EMMC_RESET_N)},
};
/* Connections for: sdhc_card_if_pwr_en */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1] = {
{P12_6, &CYHAL_SDHC_1, CYHAL_PIN_OUT_FUNCTION(P12_6_SDHC1_CARD_IF_PWR_EN)},
};
/* Connections for: sdhc_card_mech_write_prot */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2] = {
{P2_7, &CYHAL_SDHC_0, CYHAL_PIN_IN_FUNCTION(P2_7_SDHC0_CARD_MECH_WRITE_PROT)},
{P12_2, &CYHAL_SDHC_1, CYHAL_PIN_IN_FUNCTION(P12_2_SDHC1_CARD_MECH_WRITE_PROT)},
};
/* Connections for: sdhc_clk_card */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2] = {
{P2_5, &CYHAL_SDHC_0, CYHAL_PIN_OUT_BUF_FUNCTION(P2_5_SDHC0_CLK_CARD)},
{P12_5, &CYHAL_SDHC_1, CYHAL_PIN_OUT_BUF_FUNCTION(P12_5_SDHC1_CLK_CARD)},
};
/* Connections for: sdhc_io_volt_sel */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1] = {
{P12_7, &CYHAL_SDHC_1, CYHAL_PIN_OUT_FUNCTION(P12_7_SDHC1_IO_VOLT_SEL)},
};
/* Connections for: sdhc_led_ctrl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1] = {
{P12_3, &CYHAL_SDHC_1, CYHAL_PIN_OUT_FUNCTION(P12_3_SDHC1_LED_CTRL)},
};
/* Connections for: smif_spi_clk */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1] = {
{P11_7, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_7_SMIF_SPI_CLK)},
};
/* Connections for: smif_spi_data0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1] = {
{P11_6, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_6_SMIF_SPI_DATA0)},
};
/* Connections for: smif_spi_data1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1] = {
{P11_5, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_5_SMIF_SPI_DATA1)},
};
/* Connections for: smif_spi_data2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1] = {
{P11_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_4_SMIF_SPI_DATA2)},
};
/* Connections for: smif_spi_data3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1] = {
{P11_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P11_3_SMIF_SPI_DATA3)},
};
/* Connections for: smif_spi_data4 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1] = {
{P12_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_0_SMIF_SPI_DATA4)},
};
/* Connections for: smif_spi_data5 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1] = {
{P12_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_1_SMIF_SPI_DATA5)},
};
/* Connections for: smif_spi_data6 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1] = {
{P12_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_2_SMIF_SPI_DATA6)},
};
/* Connections for: smif_spi_data7 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1] = {
{P12_3, &CYHAL_SMIF_0, CYHAL_PIN_OUT_BUF_FUNCTION(P12_3_SMIF_SPI_DATA7)},
};
/* Connections for: smif_spi_select0 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1] = {
{P11_2, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_2_SMIF_SPI_SELECT0)},
};
/* Connections for: smif_spi_select1 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1] = {
{P11_1, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_1_SMIF_SPI_SELECT1)},
};
/* Connections for: smif_spi_select2 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1] = {
{P11_0, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P11_0_SMIF_SPI_SELECT2)},
};
/* Connections for: smif_spi_select3 */
const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1] = {
{P12_4, &CYHAL_SMIF_0, CYHAL_PIN_OUT_FUNCTION(P12_4_SMIF_SPI_SELECT3)},
};
/* Connections for: tcpwm_line */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80] = {
{P0_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
{P0_0, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
{P0_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
{P0_2, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
{P0_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
{P0_4, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
{P1_0, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
{P1_0, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
{P1_4, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
{P1_4, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
{P2_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)},
{P2_0, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)},
{P2_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)},
{P2_2, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)},
{P2_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)},
{P2_4, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)},
{P2_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)},
{P2_6, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)},
{P5_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
{P5_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
{P5_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
{P5_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
{P5_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
{P5_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
{P5_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
{P5_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
{P6_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
{P6_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
{P6_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
{P6_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
{P6_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
{P6_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
{P6_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
{P6_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
{P7_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
{P7_0, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
{P7_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
{P7_2, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
{P8_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
{P8_0, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
{P8_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
{P8_2, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
{P8_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
{P8_4, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
{P9_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
{P9_0, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
{P9_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
{P9_2, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
{P9_4, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
{P9_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
{P10_0, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
{P10_0, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
{P10_2, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
{P10_2, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
{P10_4, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
{P10_4, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
{P10_6, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
{P10_6, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
{P11_0, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
{P11_0, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
{P11_2, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
{P11_2, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
{P11_4, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
{P11_4, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
{P12_0, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
{P12_0, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
{P12_2, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
{P12_2, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
{P12_4, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
{P12_4, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
{P12_6, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
{P12_6, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
{P13_0, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
{P13_0, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
{P13_2, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)},
{P13_2, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)},
{P13_4, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)},
{P13_4, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)},
{P13_6, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
{P13_6, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
};
/* Connections for: tcpwm_line_compl */
const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80] = {
{P0_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
{P0_1, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
{P0_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
{P0_3, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
{P0_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
{P0_5, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
{P1_1, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
{P1_1, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
{P1_5, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
{P1_5, &CYHAL_TCPWM_1_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
{P2_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)},
{P2_1, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)},
{P2_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)},
{P2_3, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)},
{P2_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)},
{P2_5, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)},
{P2_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)},
{P2_7, &CYHAL_TCPWM_1_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)},
{P5_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
{P5_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
{P5_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
{P5_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
{P5_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
{P5_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
{P5_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
{P5_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
{P6_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
{P6_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
{P6_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
{P6_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
{P6_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
{P6_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
{P6_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
{P6_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
{P7_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
{P7_1, &CYHAL_TCPWM_1_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
{P7_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
{P7_3, &CYHAL_TCPWM_1_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
{P7_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
{P7_7, &CYHAL_TCPWM_1_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
{P8_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
{P8_1, &CYHAL_TCPWM_1_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
{P8_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
{P8_3, &CYHAL_TCPWM_1_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
{P9_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
{P9_1, &CYHAL_TCPWM_1_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
{P9_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
{P9_3, &CYHAL_TCPWM_1_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
{P9_7, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
{P9_7, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
{P10_1, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
{P10_1, &CYHAL_TCPWM_1_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
{P10_3, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
{P10_3, &CYHAL_TCPWM_1_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
{P10_5, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
{P10_5, &CYHAL_TCPWM_1_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
{P10_7, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
{P10_7, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
{P11_1, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
{P11_1, &CYHAL_TCPWM_1_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
{P11_3, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
{P11_3, &CYHAL_TCPWM_1_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
{P11_5, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
{P11_5, &CYHAL_TCPWM_1_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
{P12_1, &CYHAL_TCPWM_0_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
{P12_1, &CYHAL_TCPWM_1_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
{P12_3, &CYHAL_TCPWM_0_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
{P12_3, &CYHAL_TCPWM_1_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
{P12_5, &CYHAL_TCPWM_0_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
{P12_5, &CYHAL_TCPWM_1_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
{P12_7, &CYHAL_TCPWM_0_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
{P12_7, &CYHAL_TCPWM_1_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
{P13_1, &CYHAL_TCPWM_0_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
{P13_1, &CYHAL_TCPWM_1_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
{P13_3, &CYHAL_TCPWM_0_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)},
{P13_3, &CYHAL_TCPWM_1_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)},
{P13_5, &CYHAL_TCPWM_0_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)},
{P13_5, &CYHAL_TCPWM_1_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)},
{P13_7, &CYHAL_TCPWM_0_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
{P13_7, &CYHAL_TCPWM_1_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
};
/* Connections for: usb_usb_dm_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1] = {
{USBDM, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDM_USB_USB_DM_PAD)},
};
/* Connections for: usb_usb_dp_pad */
const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1] = {
{USBDP, &CYHAL_USB_0, CYHAL_PIN_AUX_FUNCTION(USBDP_USB_USB_DP_PAD)},
};
#endif

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