fix mbed-ci build error L6216E
* (.ARM.exidx) and *(.init_array) must be placed explicitly, otherwise it is shared between two regions, and the linker is unable to decide where to place it.
This patch changes the linker files and defines to use the ZBT SSRAM
instead of the FPGA Block RAM for code and data.
The section 4.1.1, Code and RAM memory map, of the CM3DS Eval RTL and
testbench user guide explains the available memories.
This switch improves code memory from 256 kB to 4 MB and data memory
from 128 kB to 4 MB.
However, the ZBT SSRAM1 for code memory begins at 0x00400000 while the
processor can only boot at address 0x00000000 which means that it
expects the vector table to be at that address. That is why we have to
create 2 load regions in the linker scripts: one with only the vector
table at address 0x0 and one with code + data at address 0x00400000.
Because of these two load regions, linker will produce different
behaviours:
* GCC_ARM and IAR will only create 1 binary with both load regions
padding with 0 in between. The binary will then be very large (at least
4 MB) and the flash process will take longer.
* ARM and ARMC6 will create 2 binaries for the two load regions. The
load addresses of the two binaries can be written in the images.txt file
on the MPS2 board. You can also use the --bincombined option of fromelf
utility to produce only 1 large binary.
This patch also adds the memory_zones.h file to try to put in common all
the memory addresses that were previously hard coded in the linker
scripts / startup files.
With that patch in, the simplest option is to directly use the .elf file
with the MPS2, which is only possible with mbb_v225.ebf and more recent
firmwares. It will now be the default for CM3DS.
This commit works with greentea thanks to the now merged pull request
ARMmbed/htrun#181 in order to copy .elf file to the MPS2 board.
Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
Ameba has two memory blocks: SDRAM(2M) and SRAM(512KB). SRAM has better access performance than SDRAM. So some timing critical codes must be moved to SRAM.
fix for mbed-os issue #5778
rebase for #6289
1. Start function: Issue repeat start when bus is busy
2. Byte write function: Do not call SDK function as this does
not work for some of the Kinetis device
3. Byte read function: Do not call SDK function as this would
issue a START and STOP signal which is not required for
I2C byte functions
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
I2C3 clock define was missing. I2C3 is connected to the Arduino
connector which is used by the ci-test shield
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
fix section error, ARM compiler uses IRAM1.bss to calculate the heap size
fix conflict of _memset between Ameba's library and ARM compiler's library, use standard memset() instead of _memset() in case of ARM compiler
Originally, we use 2 H/W timers for us_ticker/lp_ticker, one for counting and the other for alarm.
With H/W timer running in continuous mode, we could use just one H/W timer for counting/alarm simultaneously.
Few targets need more than just pending IRQ set. They include some flags to be
set that are checked in IRQ handler. This is the case for targets in this
commit.
This commit adds the UART driver and updates the UART HAL implementation
to use this driver.
It also removes legacy definitions.
Change-Id: Ie8e7a7bb64c763a2d97bc66d949fab3596736bbc
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
This commit adds the SPI driver which is now called by the SPI HAL
implementation.
It also removes legacy definitions.
Change-Id: Iadb20dda9dfa571db3de66c3a1ce45d80d8b81b6
Signed-off-by: Tamas Kaman <tamas.kaman@arm.com>
This commit adds the GPIO drivers. The HAL implementations
(gpio_api.c, gpio_irq_api.c, port_api.c) now call these drivers.
Legacy definitions have been removed.
Serial HAL implementation has been changed to compile at this stage.
Change-Id: Ib76a3186358f5029ed350da671132e8aa11194f7
Signed-off-by: Galanakis, Minos <minos.galanakis@arm.com>
The HAL implementation (us_ticker.c and lp_ticker.c) now calls function
in cmsdk_ticker.c file. This file contains the necessary logic to be
able to only use one hardware timer (CMSDK timer) per mbed ticker.
This commit also updates the timer driver and removes legacy definition.
Change-Id: If40413822832117f9b78f38d2cdda7847284b035
Signed-off-by: Galanakis, Minos <minos.galanakis@arm.com>
Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
This patch changes the way data is put in the TX_DATA_PORT register when
sending packet over Ethernet.
When this driver is compiled with release compilation profile
(space optimization compiler options) with Arm compiler version 5,
the line:
SMSC9220->TX_DATA_PORT = *pktptr;
generates the assembly instruction to get the pktptr pointed value:
LDM r2!, {r3}
with pktptr = r2
However, the code does not prevent the pktptr value from being unaligned
(to a 32 bits boundary) in that zone and the LDM instruction causes a
HardFault if this is the case. When the compiler option is not activated
(debug and develop compilation profiles), the compiler generates LDR
instruction instead which does not cause a HardFault.
The ARM v7-M states page B3-601: "Unaligned load-store multiples and
word or halfword exclusive accesses always fault."
To face that problem, we check if the data pointer is aligned or not. If
it is, we apply the same algorithm than before. If not, a local variable
is created and we copy in it, byte per byte, the contents at the
unaligned pointer. However, it will impact performances adding 8
instructions (one LD and one ST for each copied byte).
Change-Id: I11f6e82ce5521960d2ecf499f718f76fec29c0b0
Signed-off-by: Hugues de Valon <hugues.devalon@arm.com>
How you write and ersae the flash on the NRF52 changes depending on
whether the SoftDevice is enabled or not.
This change does a runtime check before erasing and writing, and
then chooses the correct function to perform the action.
zzw
Cruz Monrreal
jeromecoutant
Martin Kojtal
Amanda Butler
Hugues de Valon
bcostm
amq
Mahesh Mahadevan
Evan Hosseini
Juha Ylinen
TomoYamanaka
Ashok Rao
Marcus Chang
paul-szczepanek-arm
Rob Meades
Bartek Szatkowski
Anna Bridge
gorazd
daid
cyliangtw
Keyur Hariya
ccli8
adustm
Maciej Bocianski
Avinash Mehta
Tamas Kaman
Galanakis, Minos
Fahim Alavi
Bilal