mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #5956 from marcuschangarm/feature-hal-swo
[feature-hal-itm] Instrumented Trace Macrocell HAL API for SWO debug outputpull/6134/merge
Cruz Monrreal
GitHub
commit
0ceecb946d
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@ -0,0 +1,71 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined(DEVICE_ITM)
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#include "hal/itm_api.h"
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#include "platform/FileHandle.h"
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class SerialWireOutput : public FileHandle {
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public:
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SerialWireOutput(void)
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{
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/* Initialize ITM using internal init function. */
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mbed_itm_init();
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}
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virtual ssize_t write(const void *buffer, size_t size)
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{
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const unsigned char *buf = static_cast<const unsigned char *>(buffer);
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/* Send buffer one character at a time over the ITM SWO port */
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for (size_t i = 0; i < size; i++) {
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mbed_itm_send(ITM_PORT_SWO, buf[i]);
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}
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return size;
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}
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virtual ssize_t read(void *buffer, size_t size)
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{
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/* Reading is not supported by this file handle */
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return -EBADF;
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}
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virtual off_t seek(off_t offset, int whence = SEEK_SET)
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{
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/* Seeking is not support by this file handler */
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return -ESPIPE;
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}
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virtual off_t size()
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{
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/* Size is not defined for this file handle */
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return -EINVAL;
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}
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virtual int isatty()
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{
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/* File handle is used for terminal output */
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return true;
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}
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virtual int close()
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{
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return 0;
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}
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};
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#endif
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@ -0,0 +1,91 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_ITM_API_H
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#define MBED_ITM_API_H
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#if defined(DEVICE_ITM)
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup hal_itm_port ITM Stimulus Ports
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*
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* @{
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*/
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enum {
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ITM_PORT_SWO = 0
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};
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/**@}*/
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/**
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* \defgroup itm_hal Instrumented Trace Macrocell HAL API
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* @{
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*/
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/**
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* @brief Target specific initialization function.
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* This function is responsible for initializing and configuring
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* the debug clock for the ITM and setting up the SWO pin for
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* debug output.
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*
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* The only Cortex-M register that should be modified is the clock
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* prescaler in TPI->ACPR.
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*
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* The generic mbed_itm_init initialization function will setup:
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*
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* ITM->LAR
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* ITM->TPR
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* ITM->TCR
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* ITM->TER
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* TPI->SPPR
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* TPI->FFCR
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* DWT->CTRL
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*
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* for SWO output on stimulus port 0.
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*/
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void itm_init(void);
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/**
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* @brief Initialization function for both generic registers and target specific clock and pin.
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*/
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void mbed_itm_init(void);
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/**
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* @brief Send data over ITM stimulus port.
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*
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* @param[in] port The stimulus port to send data over.
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* @param[in] data The data to send.
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*
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* @return value of data sent.
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*/
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uint32_t mbed_itm_send(uint32_t port, uint32_t data);
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/**@}*/
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* MBED_ITM_API_H */
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@ -0,0 +1,87 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined(DEVICE_ITM)
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#include "hal/itm_api.h"
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#include "cmsis.h"
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#include <stdbool.h>
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#define ITM_ENABLE_WRITE 0xC5ACCE55
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#define SWO_NRZ 0x02
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#define SWO_STIMULUS_PORT 0x01
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void mbed_itm_init(void)
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{
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static bool do_init = true;
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if (do_init) {
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do_init = false;
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itm_init();
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/* Enable write access to ITM registers. */
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ITM->LAR = ITM_ENABLE_WRITE;
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/* Trace Port Interface Selected Pin Protocol Register. */
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TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos);
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/* Trace Port Interface Formatter and Flush Control Register */
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TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos);
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/* Data Watchpoint and Trace Control Register */
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DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos) |
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(0xF << DWT_CTRL_POSTINIT_Pos) |
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(0xF << DWT_CTRL_POSTPRESET_Pos) |
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(1 << DWT_CTRL_CYCCNTENA_Pos);
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/* Trace Privilege Register.
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* Disable access to trace channel configuration from non-privileged mode.
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*/
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ITM->TPR = 0x0;
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/* Trace Control Register */
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ITM->TCR = (1 << ITM_TCR_TraceBusID_Pos) |
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(1 << ITM_TCR_DWTENA_Pos) |
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(1 << ITM_TCR_SYNCENA_Pos) |
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(1 << ITM_TCR_ITMENA_Pos);
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/* Trace Enable Register */
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ITM->TER = SWO_STIMULUS_PORT;
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}
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}
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uint32_t mbed_itm_send(uint32_t port, uint32_t data)
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{
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/* Check if ITM and port is enabled */
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if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
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((ITM->TER & (1UL << port) ) != 0UL) ) /* ITM Port enabled */
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{
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/* write data to port */
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ITM->PORT[port].u32 = data;
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/* Wait until data has been clocked out */
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while (ITM->PORT[port].u32 == 0UL) {
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__NOP();
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}
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}
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return data;
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}
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#endif // defined(DEVICE_ITM)
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/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined(DEVICE_ITM)
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#include "hal/itm_api.h"
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#include "nrf.h"
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#include "nrf5x_lf_clk_helper.h"
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/* SWO frequency: 4000 kHz */
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void itm_init(void)
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{
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/* Enable SWO trace functionality */
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
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/* set SWO clock speed to 4 MHz */
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NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) |
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(CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
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/* set SWO pin */
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NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) |
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(GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) |
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(GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
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/* set prescaler */
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TPI->ACPR = 0;
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}
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#endif
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@ -0,0 +1,107 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined(DEVICE_ITM)
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#include "hal/itm_api.h"
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#include "cmsis.h"
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#include "em_cmu.h"
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#include <stdbool.h>
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/* SWO frequency: 875 kHz */
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static void setupSWOForPrint(void)
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{
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#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
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// Enable GPIO clock.
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#if defined( _CMU_HFPERCLKEN0_GPIO_MASK )
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CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
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#elif defined( _CMU_HFBUSCLKEN0_GPIO_MASK )
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CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
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#endif
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// Enable Serial wire output pin
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#if defined( _GPIO_ROUTE_SWOPEN_MASK )
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GPIO->ROUTE |= GPIO_ROUTE_SWOPEN;
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#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
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GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN;
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#endif
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#endif
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#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_LEOPARD_FAMILY) || defined(_EFM32_WONDER_FAMILY) || defined(_EFM32_PEARL_FAMILY)
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// Set location 0
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#if defined( _GPIO_ROUTE_SWOPEN_MASK )
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GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC0;
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#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
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GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~(_GPIO_ROUTELOC0_SWVLOC_MASK)) | GPIO_ROUTELOC0_SWVLOC_LOC0;
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#endif
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// Enable output on pin - GPIO Port F, Pin 2
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GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK);
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GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL;
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#else
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// Set location 1
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GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC1;
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// Enable output on pin
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GPIO->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
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GPIO->P[2].MODEH |= GPIO_P_MODEH_MODE15_PUSHPULL;
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#endif
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// Enable debug clock AUXHFRCO
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CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
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// Wait until clock is ready
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while (!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY));
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// Enable trace in core debug
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
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/* Set TPIU prescaler for the current debug clock frequency. Target frequency
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is 875 kHz so we choose a divider that gives us the closest match.
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Actual divider is TPI->ACPR + 1. */
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uint32_t freq = CMU_ClockFreqGet(cmuClock_DBG) + (875000 / 2);
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uint32_t div = freq / 875000;
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TPI->ACPR = div - 1;
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}
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static bool swoIsInitd()
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{
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#if defined( _CMU_HFPERCLKEN0_GPIO_MASK )
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return ((CMU->HFPERCLKEN0 & CMU_HFPERCLKEN0_GPIO) &&
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(GPIO->ROUTE & GPIO_ROUTE_SWOPEN) &&
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(CMU->STATUS & CMU_STATUS_AUXHFRCORDY) &&
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(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk));
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#elif defined( _CMU_HFBUSCLKEN0_GPIO_MASK )
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return ((CMU->HFBUSCLKEN0 & CMU_HFBUSCLKEN0_GPIO) &&
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(GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN) &&
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(CMU->STATUS & CMU_STATUS_AUXHFRCORDY) &&
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(CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk));
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#endif
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}
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// As SWO has to be accessible everywhere, including ISRs, we can't easily
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// communicate the dependency on clocks etc. to other components - so this
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// function checks that things appear to be set up, and if not re-configures
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// everything
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void itm_init(void)
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{
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if(!swoIsInitd()) {
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setupSWOForPrint();
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}
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}
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#endif
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@ -2773,7 +2773,7 @@
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"EFM32GG_STK3700": {
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"inherits": ["EFM32GG990F1024"],
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"progen": {"target": "efm32gg-stk"},
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"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
|
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"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH", "ITM"],
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"forced_reset_timeout": 2,
|
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"config": {
|
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"hf_clock_src": {
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@ -3443,7 +3443,7 @@
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"inherits": ["Target"],
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"core": "Cortex-M4F",
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"macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
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"device_has": ["STCLK_OFF_DURING_SLEEP"],
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"device_has": ["STCLK_OFF_DURING_SLEEP", "ITM"],
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"extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"],
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"OUTPUT_EXT": "hex",
|
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"is_disk_virtual": true,
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@ -3546,7 +3546,7 @@
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"inherits": ["Target"],
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"core": "Cortex-M4F",
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"macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
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"device_has": ["STCLK_OFF_DURING_SLEEP"],
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"device_has": ["STCLK_OFF_DURING_SLEEP", "ITM"],
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"extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
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"OUTPUT_EXT": "hex",
|
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"is_disk_virtual": true,
|
||||
|
|
|
|||
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