Merge pull request #13122 from romanjoe/pr/add_cy8ckit_064b0b2_4343w

Cypress: Add target CY8CKIT_064B0S2_4343W, update psoc6pdl, psoc6cm0p

TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

@@ -67,7 +67,7 @@
         defined(TARGET_CY8CKIT_062S2_43012) ||      \
         defined(TARGET_CY8CKIT_062S2_4343W) ||      \
         defined(TARGET_CY8CKIT_064S2_4343W) ||      \
-        defined(TARGET_CYESKIT_064B0S2_4343W) ||    \
+        defined(TARGET_CY8CKIT_064B0S2_4343W) ||    \
         defined(TARGET_CY8CPROTO_062_4343W) ||      \
         defined(TARGET_CY8CPROTO_062S2_43012) ||    \
         defined(TARGET_CY8CPROTO_062S3_4343W) ||    \
@@ -78,9 +78,6 @@
 #elif   defined(TARGET_CYW9P62S1_43012EVB_01)
 #include "S25FS512S_config.h"
 
-#elif   defined(TARGET_CY8CPROTO_064_SB)
-#include "S25FL128S_config.h"
-
 #endif
 
 #endif // MBED_FLASH_CONFIGS_H

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -4,8 +4,8 @@
 * Description:
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -4,8 +4,8 @@
 * Description:
 * Simple wrapper header containing all generated files.
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -1,26 +1,26 @@
-/*******************************************************************************
+/*******************************************************************************
-* File Name: cycfg.timestamp
+* File Name: cycfg.timestamp
-*
+*
-* Description:
+* Description:
-* Sentinel file for determining if generated source is up to date.
+* Sentinel file for determining if generated source is up to date.
-* This file was automatically generated and should not be modified.
+* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
-*
+*
-********************************************************************************
+********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
+* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
+* SPDX-License-Identifier: Apache-2.0
-*
+*
-* Licensed under the Apache License, Version 2.0 (the "License");
+* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
+* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
+* You may obtain a copy of the License at
-*
+*
-*     http://www.apache.org/licenses/LICENSE-2.0
+*     http://www.apache.org/licenses/LICENSE-2.0
-*
+*
-* Unless required by applicable law or agreed to in writing, software
+* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
+* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
+* See the License for the specific language governing permissions and
-* limitations under the License.
+* limitations under the License.
-********************************************************************************/
+********************************************************************************/
-
+

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -4,8 +4,8 @@
 * Description:
 * Clock configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -27,7 +27,7 @@
 #include "cycfg_clocks.h"
 
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj = 
+	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
 	{
 		.type = CYHAL_RSC_CLOCK,
 		.block_num = CYBSP_CSD_CLK_DIV_HW,

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -4,8 +4,8 @@
 * Description:
 * Clock configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -5,8 +5,8 @@
 * Contains warnings and errors that occurred while generating code for the
 * design.
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -4,8 +4,8 @@
 * Description:
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -34,5 +34,5 @@ cy_stc_csd_context_t cy_csd_0_context =
 
 void init_cycfg_peripherals(void)
 {
-	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
+	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -4,8 +4,8 @@
 * Description:
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -37,8 +37,8 @@ extern "C" {
 
 #define CYBSP_CSD_ENABLED 1U
 #define CY_CAPSENSE_CORE 4u
-#define CY_CAPSENSE_CPU_CLK 96000000u
+#define CY_CAPSENSE_CPU_CLK 100000000u
-#define CY_CAPSENSE_PERI_CLK 48000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
 #define CY_CAPSENSE_VDDA_MV 3300u
 #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
 #define CY_CAPSENSE_PERI_DIV_INDEX 0u

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -4,8 +4,8 @@
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -74,11 +74,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
 		.channel_num = CYBSP_WCO_OUT_PIN,
 	};
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
+const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
 {
 	.outVal = 1,
 	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_TX_HSIOM,
+	.hsiom = CYBSP_CSD_RX_HSIOM,
 	.intEdge = CY_GPIO_INTR_DISABLE,
 	.intMask = 0UL,
 	.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -91,11 +91,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
 	.vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
+	const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
 	{
 		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_TX_PORT_NUM,
+		.block_num = CYBSP_CSD_RX_PORT_NUM,
-		.channel_num = CYBSP_CSD_TX_PIN,
+		.channel_num = CYBSP_CSD_RX_PIN,
 	};
 #endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
@@ -425,7 +425,7 @@ void init_cycfg_pins(void)
 #endif //defined (CY_USING_HAL)
 
 #if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
+	cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
 #endif //defined (CY_USING_HAL)
 
 	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -4,8 +4,8 @@
 * Description:
 * Pin configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -53,6 +53,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_IN P0_0
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -77,6 +80,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_WCO_OUT P0_1
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -86,29 +92,32 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_TX_ENABLED 1U
+#define CYBSP_CSD_RX_ENABLED 1U
-#define CYBSP_CSD_TX_PORT GPIO_PRT1
+#define CYBSP_CSD_RX_PORT GPIO_PRT1
-#define CYBSP_CSD_TX_PORT_NUM 1U
+#define CYBSP_CSD_RX_PORT_NUM 1U
-#define CYBSP_CSD_TX_PIN 0U
+#define CYBSP_CSD_RX_PIN 0U
-#define CYBSP_CSD_TX_NUM 0U
+#define CYBSP_CSD_RX_NUM 0U
-#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
+#define CYBSP_CSD_RX_INIT_DRIVESTATE 1
 #ifndef ioss_0_port_1_pin_0_HSIOM
 	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn
 #if defined (CY_USING_HAL)
-	#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
+	#define CYBSP_CSD_RX_HAL_PORT_PIN P1_0
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+	#define CYBSP_CSD_RX P1_0
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
+	#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
-	#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+	#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
 #define CYBSP_SWO_ENABLED 1U
 #define CYBSP_SWO_PORT GPIO_PRT6
@@ -125,6 +134,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_SWO_HAL_PORT_PIN P6_4
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWO P6_4
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -149,6 +161,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDIO P6_6
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -173,6 +188,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_SWDCK P6_7
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -197,6 +215,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CINA_HAL_PORT_PIN P7_1
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINA P7_1
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -221,6 +242,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CINB_HAL_PORT_PIN P7_2
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CINB P7_2
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -245,6 +269,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CMOD P7_7
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -269,6 +296,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN0 P8_1
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -293,6 +323,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_BTN1 P8_2
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -317,6 +350,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD0 P8_3
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -341,6 +377,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD1 P8_4
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -365,6 +404,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD2 P8_5
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -389,6 +431,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD3 P8_6
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -413,6 +458,9 @@ extern "C" {
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
 #endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+	#define CYBSP_CSD_SLD4 P8_7
+#endif //defined (CY_USING_HAL)
 #if defined (CY_USING_HAL)
 	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
 #endif //defined (CY_USING_HAL)
@@ -431,9 +479,9 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
 #if defined (CY_USING_HAL)
 	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
 #if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
+	extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
 #endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
 #if defined (CY_USING_HAL)

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -4,8 +4,8 @@
 * Description:
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -4,8 +4,8 @@
 * Description:
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -40,15 +40,15 @@ void init_cycfg_routing(void);
 #define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
 #define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
 #define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
 #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
 #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
 
 #if defined(__cplusplus)

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -4,8 +4,8 @@
 * Description:
 * System configuration
 * This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
+* cfg-backend-cli: 1.2.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
+* Device Support Library (libs/psoc6pdl): 1.6.0.4266
 *
 ********************************************************************************
 * Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -29,7 +29,8 @@
 
 #include "cycfg_notices.h"
 #include "cy_sysclk.h"
-#include "cy_systick.h"
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
 #if defined (CY_USING_HAL)
 	#include "cyhal_hwmgr.h"
 #endif //defined (CY_USING_HAL)
@@ -42,22 +43,26 @@ extern "C" {
 
 #define cpuss_0_dap_0_ENABLED 1U
 #define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
 #define srss_0_clock_0_bakclk_0_ENABLED 1U
 #define srss_0_clock_0_fastclk_0_ENABLED 1U
 #define srss_0_clock_0_fll_0_ENABLED 1U
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
 #define srss_0_clock_0_hfclk_2_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF2 2UL
+#define CY_CFG_SYSCLK_CLKHF2_CLKPATH_NUM 0UL
 #define srss_0_clock_0_hfclk_3_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF3 3UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL
 #define srss_0_clock_0_hfclk_4_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF4 4UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
 #define srss_0_clock_0_imo_0_ENABLED 1U
 #define srss_0_clock_0_lfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
 #define srss_0_clock_0_pathmux_0_ENABLED 1U
 #define srss_0_clock_0_pathmux_1_ENABLED 1U
 #define srss_0_clock_0_pathmux_2_ENABLED 1U

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -1,5 +1,5 @@
-[Device=CYB0644ABZI-D44]
+[Device=CYB0644ABZI-S2D44]
- 
+
 [Blocks]
 # WIFI
 # CYBSP_WIFI_SDIO

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
-<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0 build 1105-->
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
 <Configuration app="QSPI" major="2" minor="0">
     <DevicePath>PSoC 6.xml</DevicePath>
     <SlotConfigs>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
+<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
     <ToolInfo version="1.0.0"/>
     <Devices>
         <Device mpn="CYB0644ABZI-S2D44">
@@ -268,11 +268,6 @@
                 <Block location="srss[0].clock[0]">
                     <Personality template="mxs40sysclocks" version="1.2"/>
                 </Block>
-                <Block location="srss[0].clock[0].altsystickclk[0]">
-                    <Personality template="mxs40altsystick" version="1.0">
-                        <Param id="sourceClock" value="lfclk"/>
-                    </Personality>
-                </Block>
                 <Block location="srss[0].clock[0].bakclk[0]">
                     <Personality template="mxs40bakclk" version="1.0">
                         <Param id="sourceClock" value="lfclk"/>
@@ -286,7 +281,7 @@
                 <Block location="srss[0].clock[0].fll[0]">
                     <Personality template="mxs40fll" version="1.0">
                         <Param id="configuration" value="auto"/>
-                        <Param id="desiredFrequency" value="96.000"/>
+                        <Param id="desiredFrequency" value="100.000"/>
                     </Personality>
                 </Block>
                 <Block location="srss[0].clock[0].hfclk[0]">
@@ -345,7 +340,7 @@
                 </Block>
                 <Block location="srss[0].clock[0].periclk[0]">
                     <Personality template="mxs40periclk" version="1.0">
-                        <Param id="divider" value="2"/>
+                        <Param id="divider" value="1"/>
                     </Personality>
                 </Block>
                 <Block location="srss[0].clock[0].pll[0]">
@@ -386,7 +381,7 @@
                     </Personality>
                 </Block>
                 <Block location="srss[0].power[0]">
-                    <Personality template="mxs40power" version="1.2">
+                    <Personality template="mxs40power" version="1.3">
                         <Param id="pwrMode" value="LDO_1_1"/>
                         <Param id="actPwrMode" value="LP"/>
                         <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/cybsp_types.h

@@ -1,9 +1,9 @@
 /***************************************************************************//**
-* \file CY8CKIT-064S2-4343W/cybsp_types.h
+* \file CY8CKIT-064B0S2-4343W/cybsp_types.h
 *
 * Description:
 * Provides APIs for interacting with the hardware contained on the Cypress
-* CY8CKIT-064S2-4343W pioneer kit.
+* CY8CKIT-064B0S2-4343W pioneer kit.
 *
 ********************************************************************************
 * \copyright
@@ -100,32 +100,32 @@ extern "C" {
 * \{
 */
 
-/** LED 8; User LED1 */
+/** LED 8; User LED1 (orange) */
 #ifndef CYBSP_LED8
 #define CYBSP_LED8                  (P1_5)
 #endif
-/** LED 9; User LED2 */
+/** LED 9; User LED2 (red) */
 #ifndef CYBSP_LED9
-#define CYBSP_LED9                  (P13_7)
+#define CYBSP_LED9                  (P11_1)
 #endif
 /** LED 5: RGB LED - Red; User LED3 */
 #ifndef CYBSP_LED_RGB_RED
-#define CYBSP_LED_RGB_RED           (P0_3)
+#define CYBSP_LED_RGB_RED           (P1_1)
 #endif
 /** LED 5: RGB LED - Green; User LED4 */
 #ifndef CYBSP_LED_RGB_GREEN
-#define CYBSP_LED_RGB_GREEN         (P1_1)
+#define CYBSP_LED_RGB_GREEN         (P0_5)
 #endif
 /** LED 5: RGB LED - Blue; User LED5 */
 #ifndef CYBSP_LED_RGB_BLUE
-#define CYBSP_LED_RGB_BLUE          (P11_1)
+#define CYBSP_LED_RGB_BLUE          (P7_3)
 #endif
 
-/** LED 8; User LED1 */
+/** LED 8; User LED1 (orange) */
 #ifndef CYBSP_USER_LED1
 #define CYBSP_USER_LED1             (CYBSP_LED8)
 #endif
-/** LED 9; User LED2 */
+/** LED 9; User LED2 (red) */
 #ifndef CYBSP_USER_LED2
 #define CYBSP_USER_LED2             (CYBSP_LED9)
 #endif
@@ -141,7 +141,7 @@ extern "C" {
 #ifndef CYBSP_USER_LED5
 #define CYBSP_USER_LED5             (CYBSP_LED_RGB_BLUE)
 #endif
-/** LED 8; User LED1 */
+/** LED 8; User LED1 (orange) */
 #ifndef CYBSP_USER_LED
 #define CYBSP_USER_LED              (CYBSP_USER_LED1)
 #endif
@@ -158,11 +158,19 @@ extern "C" {
 #ifndef CYBSP_SW2
 #define CYBSP_SW2                   (P0_4)
 #endif
+/** Switch 4; User Button 2 */
+#ifndef CYBSP_SW4
+#define CYBSP_SW4                   (P1_4)
+#endif
 
 /** Switch 2; User Button 1 */
 #ifndef CYBSP_USER_BTN1
 #define CYBSP_USER_BTN1             (CYBSP_SW2)
 #endif
+/** Switch 4; User Button 2 */
+#ifndef CYBSP_USER_BTN2
+#define CYBSP_USER_BTN2             (CYBSP_SW4)
+#endif
 /** Switch 2; User Button 1 */
 #ifndef CYBSP_USER_BTN
 #define CYBSP_USER_BTN              (CYBSP_USER_BTN1)
@@ -206,7 +214,7 @@ extern "C" {
 #endif
 /** Pin: WIFI Host Wakeup */
 #ifndef CYBSP_WIFI_HOST_WAKE
-#define CYBSP_WIFI_HOST_WAKE        (P2_7)
+#define CYBSP_WIFI_HOST_WAKE        (P4_1)
 #endif
 
 /** Pin: BT UART RX */
@@ -232,11 +240,11 @@ extern "C" {
 #endif
 /** Pin: BT Host Wakeup */
 #ifndef CYBSP_BT_HOST_WAKE
-#define CYBSP_BT_HOST_WAKE          (P3_5)
+#define CYBSP_BT_HOST_WAKE          (P4_0)
 #endif
 /** Pin: BT Device Wakeup */
 #ifndef CYBSP_BT_DEVICE_WAKE
-#define CYBSP_BT_DEVICE_WAKE        (P4_0)
+#define CYBSP_BT_DEVICE_WAKE        (P3_5)
 #endif
 
 /** Pin: UART RX */
@@ -247,6 +255,14 @@ extern "C" {
 #ifndef CYBSP_DEBUG_UART_TX
 #define CYBSP_DEBUG_UART_TX         (P5_1)
 #endif
+/** Pin: UART RX */
+#ifndef CYBSP_DEBUG_UART_RTS
+#define CYBSP_DEBUG_UART_RTS        (P5_2)
+#endif
+/** Pin: UART TX */
+#ifndef CYBSP_DEBUG_UART_CTS
+#define CYBSP_DEBUG_UART_CTS        (P5_3)
+#endif
 
 /** Pin: I2C SCL */
 #ifndef CYBSP_I2C_SCL
@@ -295,6 +311,11 @@ extern "C" {
 #define CYBSP_QSPI_SCK              (P11_7)
 #endif
 
+/** Host-wake GPIO drive mode */
+#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
+/** Host-wake IRQ event */
+#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
+
 /** Pin: SPI MOSI */
 #ifndef CYBSP_SPI_MOSI
 #define CYBSP_SPI_MOSI              (P12_0)
@@ -312,11 +333,6 @@ extern "C" {
 #define CYBSP_SPI_CS                (P12_4)
 #endif
 
-/** Host-wake GPIO drive mode */
-#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
-/** Host-wake IRQ event */
-#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
-
 /** \} group_bsp_pins_comm */
 
 
@@ -379,15 +395,15 @@ extern "C" {
 #endif
 /** Arduino D7 */
 #ifndef CYBSP_D7
-#define CYBSP_D7                    (P0_2)
+#define CYBSP_D7                    (P5_7)
 #endif
 /** Arduino D8 */
 #ifndef CYBSP_D8
-#define CYBSP_D8                    (P13_0)
+#define CYBSP_D8                    (P7_5)
 #endif
 /** Arduino D9 */
 #ifndef CYBSP_D9
-#define CYBSP_D9                    (P13_1)
+#define CYBSP_D9                    (P7_6)
 #endif
 /** Arduino D10 */
 #ifndef CYBSP_D10
@@ -476,31 +492,15 @@ extern "C" {
 #endif
 /** Cypress J2 Header pin 14 */
 #ifndef CYBSP_J2_14
-#define CYBSP_J2_14                 (NC)
+#define CYBSP_J2_14                 (P9_6)
 #endif
 /** Cypress J2 Header pin 15 */
 #ifndef CYBSP_J2_15
-#define CYBSP_J2_15                 (P6_2)
+#define CYBSP_J2_15                 (P10_7)
 #endif
 /** Cypress J2 Header pin 16 */
 #ifndef CYBSP_J2_16
-#define CYBSP_J2_16                 (P9_6)
+#define CYBSP_J2_16                 (P9_7)
-#endif
-/** Cypress J2 Header pin 17 */
-#ifndef CYBSP_J2_17
-#define CYBSP_J2_17                 (P6_3)
-#endif
-/** Cypress J2 Header pin 18 */
-#ifndef CYBSP_J2_18
-#define CYBSP_J2_18                 (P9_7)
-#endif
-/** Cypress J2 Header pin 19 */
-#ifndef CYBSP_J2_19
-#define CYBSP_J2_19                 (P13_6)
-#endif
-/** Cypress J2 Header pin 20 */
-#ifndef CYBSP_J2_20
-#define CYBSP_J2_20                 (P13_7)
 #endif
 
 /** \} group_bsp_pins_j2 */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xxa_cm0plus.sct

@@ -4,7 +4,7 @@
 
 ;*******************************************************************************
 ;* \file cyb06xxa_cm0plus.sct
-;* \version 2.70.1
+;* \version 2.80
 ;*
 ;* Linker file for the ARMCC.
 ;*
@@ -55,7 +55,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
+  #define MBED_ROM_SIZE     0x00010000
 #endif
 
 ;* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -67,11 +67,11 @@
 #endif
 
 #if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
+  #define MBED_RAM_START    0x080E0000
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
+  #define MBED_RAM_SIZE     0x0000C000
 #endif
 
 #if !defined(MBED_PUBLIC_RAM_SIZE)
@@ -186,11 +186,11 @@ LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x800
 
     ; Application heap area (HEAP)
     ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
+    {
     }
-    
+
     ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
+    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE
     {
     }
 }

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S

@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.S
+; * @file     startup_psoc6_02_cm0plus.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM0plus Device Series
 ; * @version  V5.00
@@ -32,9 +32,12 @@
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
 
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
+                
+__Vectors       DCD    |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
+
                 DCD     Reset_Handler             ; Reset Handler
 
                 DCD     0x0000000D                ; NMI Handler located at ROM code
@@ -101,6 +104,9 @@ Reset_Handler   PROC
                 ; Define strong function for startup customization
                 BL      Cy_OnResetUser
 
+                ; Disable global interrupts
+                CPSID I
+
                 ; Copy vectors from ROM to RAM
                 LDR r1, =__Vectors
                 LDR r0, =__ramVectors
@@ -207,6 +213,10 @@ Internal7_IRQHandler
 
                 ALIGN
 
+
+; User Initial Stack & Heap
+                IMPORT   __use_two_region_memory
+
                 END
 
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xxa_cm0plus.ld

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file cyb06xxa_cm0plus.ld
-* \version 2.70.1
+* \version 2.80
 *
 * Linker file for the GNU C compiler.
 *
@@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
+  #define MBED_ROM_SIZE     0x00010000
 #endif
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -65,11 +65,11 @@ ENTRY(Reset_Handler)
 #endif
 
 #if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
+  #define MBED_RAM_START    0x080E0000
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
+  #define MBED_RAM_SIZE     0x0000C000
 #endif
 
 #if !defined(MBED_PUBLIC_RAM_SIZE)

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S

@@ -148,6 +148,7 @@ Cy_OnResetUser:
 
 Reset_Handler:
     bl Cy_OnResetUser
+    cpsid i
 
 /*  Firstly it copies data from read only memory to RAM. There are two schemes
  *  to copy. One can copy more than one sections. Another can only copy
@@ -282,7 +283,11 @@ Reset_Handler:
     str r0, [r1]
     dsb 0xF
 
-    bl  _start
+#ifndef __NO_SYSTEM_INIT
+    bl    SystemInit
+#endif
+
+    bl    main
 
     /* Should never get here */
     b   .

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xxa_cm0plus.icf

@@ -1,6 +1,6 @@
 /*******************************************************************************
 * \file cyb06xxa_cm0plus.icf
-* \version 2.70.1
+* \version 2.80
 *
 * Linker file for the IAR compiler.
 *
@@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
 }
 
 if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x80000;
+  define symbol MBED_ROM_SIZE = 0x00010000;
 }
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -66,11 +66,11 @@ if (!isdefinedsymbol(MBED_APP_SIZE)) {
 }
 
 if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
+  define symbol MBED_RAM_START = 0x080E0000;
 }
 
 if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x00010000;
+  define symbol MBED_RAM_SIZE = 0x0000C000;
 }
 
 /*-Sizes-*/

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S

@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.S
+; * @file     startup_psoc6_02_cm0plus.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM0plus Device Series
 ; * @version  V5.00
@@ -49,6 +49,7 @@
         EXTERN  __iar_program_start
         EXTERN  SystemInit
         EXTERN __iar_data_init3
+        EXTERN __iar_dynamic_initialization        
         PUBLIC  __vector_table
         PUBLIC  __vector_table_0x1c
         PUBLIC  __Vectors
@@ -157,6 +158,9 @@ Reset_Handler
         LDR     R0, =Cy_OnResetUser
         BLX     R0
 
+        ; Disable global interrupts
+        CPSID I
+
         ; Copy vectors from ROM to RAM
         LDR r1, =__vector_table
         LDR r0, =__ramVectors
@@ -176,6 +180,16 @@ intvec_copy
         STR r0, [r1]
         dsb
 
+        ; Initialize data sections
+        LDR     R0, =__iar_data_init3
+        BLX     R0
+
+        ; --manual_dynamic_initialization
+        BL      __iar_dynamic_initialization
+
+        LDR     R0, =SystemInit
+        BLX     R0
+
         LDR     R0, =__iar_program_start
         BLX     R0
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4_dual.sct

@@ -3,8 +3,8 @@
 ; to pass a scatter file through a C preprocessor.
 
 ;*******************************************************************************
-;* \file cyb06xx7_cm4.sct
+;* \file cyb06xxa_cm4_dual.sct
-;* \version 2.70.1
+;* \version 2.80
 ;*
 ;* Linker file for the ARMCC.
 ;*
@@ -42,36 +42,46 @@
 ;* limitations under the License.
 ;******************************************************************************/
 
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE     0x10000
+
 #if !defined(MBED_ROM_START)
   #define MBED_ROM_START    0x10000000
 #endif
 
 ;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
+;* will be calculate by the system. In case if MBED_APP_START address is
-;* is equal to MBED_ROM_START
+;* customized by the bootloader config, the application image should not
+;* include CM0p prebuilt image.
 ;*
+
 #if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
+  #define MBED_APP_START    (MBED_ROM_START + FLASH_CM0P_SIZE)
 #endif
 
+; The size of the MCU boot header area at the start of FLASH
+#define BOOT_HEADER_SIZE        0x00000400
+
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x000D0000
+  #define MBED_ROM_SIZE     0x00E8000
 #endif
 
 ;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+;* will be calculate by the system.
-;* is equal to MBED_ROM_SIZE
 ;*
 #if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
+  #define MBED_APP_SIZE     (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
 #endif
 
 #if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
+  #define MBED_RAM_START    0x08001800
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0002A000
+  #define MBED_RAM_SIZE     0x000DE800
 #endif
 
 #if !defined(MBED_BOOT_STACK_SIZE)
@@ -85,6 +95,11 @@
 ; Use these defines to specify the memory regions available for allocation.
 
 ; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
 ; RAM
 #define RAM_START               MBED_RAM_START
 #define RAM_SIZE                MBED_RAM_SIZE
@@ -92,9 +107,6 @@
 #define FLASH_START             MBED_APP_START
 #define FLASH_SIZE              MBED_APP_SIZE
 
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
 ; The following defines describe a 32K flash region used for EEPROM emulation.
 ; This region can also be used as the general purpose flash.
 ; You can assign sections to this memory region for only one of the cores.
@@ -133,8 +145,17 @@
 #define EFUSE_SIZE              0x100000
 
 
+; Cortex-M0+ application flash image area
+LR_IROM (MBED_ROM_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
 ; Cortex-M4 application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
+LR_IROM1 FLASH_START FLASH_SIZE
 {
     ER_FLASH_VECTORS +0
     {
@@ -173,12 +194,12 @@ LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
     ; Stack region growing down
     ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
     {
-    }    
+    }
-    
+
     ; Used for the digital signature of the secure application and the
     ; Bootloader SDK application. The size of the section depends on the required
     ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256
     {
         * (.cy_app_signature)
     }
@@ -269,7 +290,7 @@ CYMETA 0x90500000
 /* The following symbols used by the cymcuelftool. */
 /* Flash */
 #define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x000D0000
+#define __cy_memory_0_length  0x00200000
 #define __cy_memory_0_row_size 0x200
 
 /* Emulated EEPROM Flash area */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S

@@ -1,5 +1,5 @@
 ;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm4.S
+; * @file     startup_psoc6_02_cm4.s
 ; * @brief    CMSIS Core Device Startup File for
 ; *           ARMCM4 Device Series
 ; * @version  V5.00
@@ -32,9 +32,12 @@
                 EXPORT  __Vectors
                 EXPORT  __Vectors_End
                 EXPORT  __Vectors_Size
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
 
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
+                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
+                
+__Vectors       DCD    |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length| ; Top of Stack
+
                 DCD     Reset_Handler             ; Reset Handler
 
                 DCD     0x0000000D                            ; NMI Handler located at ROM code
@@ -279,7 +282,7 @@ Vectors_Copy
                 ; Enable the FPU if used
                 LDR     R0, =Cy_SystemInitFpuEnable
                 BLX     R0
-
+                
                 LDR     R0, =__main
                 BLX     R0
 
@@ -695,6 +698,10 @@ sdhc_1_interrupt_general_IRQHandler
 
                 ALIGN
 
+
+; User Initial Stack & Heap
+                IMPORT   __use_two_region_memory
+
                 END
 
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4_dual.ld

@@ -1,6 +1,6 @@
 /***************************************************************************//**
-* \file cyb06xxa_cm4.ld
+* \file cyb06xxa_cm4_dual.ld
-* \version 2.70
+* \version 2.80
 *
 * Linker file for the GNU C compiler.
 *
@@ -19,7 +19,7 @@
 *
 ********************************************************************************
 * \copyright
-* Copyright 2016-2019 Cypress Semiconductor Corporation
+* Copyright 2016-2020 Cypress Semiconductor Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
@@ -40,36 +40,46 @@ SEARCH_DIR(.)
 GROUP(-lgcc -lc -lnosys)
 ENTRY(Reset_Handler)
 
+/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core.
+* More about CM0+ prebuilt images, see here:
+* https://github.com/cypresssemiconductorco/psoc6cm0p
+*/
+/* The size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE = 0x10000;
+
+/* The size of the MCU boot header area at the start of FLASH */
+BOOT_HEADER_SIZE = 0x400;
+
 #if !defined(MBED_ROM_START)
   #define MBED_ROM_START    0x10000000
 #endif
 
-/* MBED_APP_START is being  used by the bootloader build script and
+/* MBED_APP_START is being used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
+* will be calculate by the system. In case if MBED_APP_START address is
-* is equal to MBED_ROM_START
+* customized by the bootloader config, the application image should not
+* include CM0p prebuilt image.
 */
 #if !defined(MBED_APP_START)
-  #define MBED_APP_START MBED_ROM_START
+  #define MBED_APP_START (MBED_ROM_START + FLASH_CM0P_SIZE)
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x001D0000
+  #define MBED_ROM_SIZE     0xE8000
 #endif
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
+* will be calculate by the system.
-* is equal to MBED_ROM_SIZE
 */
 #if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE MBED_ROM_SIZE
+  #define MBED_APP_SIZE (MBED_ROM_SIZE - FLASH_CM0P_SIZE)
 #endif
 
 #if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
+  #define MBED_RAM_START    0x08001800
 #endif
 
 #if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x000EA000
+  #define MBED_RAM_SIZE     0x000DE800
 #endif
 
 #if !defined(MBED_BOOT_STACK_SIZE)
@@ -79,9 +89,6 @@ ENTRY(Reset_Handler)
 /* The size of the stack section at the end of CM4 SRAM */
 STACK_SIZE = MBED_BOOT_STACK_SIZE;
 
-/* The size of the MCU boot header area at the start of FLASH */
-BOOT_HEADER_SIZE = 0x400;
-
 /* Force symbol to be entered in the output file as an undefined symbol. Doing
 * this may, for example, trigger linking of additional modules from standard
 * libraries. You may list several symbols for each EXTERN, and you may use
@@ -96,8 +103,13 @@ EXTERN(Reset_Handler)
 MEMORY
 {
     /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+     * Using this memory region for other purposes will lead to unexpected behavior.
+     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
+     * where 'xx' is the device group; for example, 'cyb06xxa_cm0plus.ld'.
      */
     ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
+    cm0p_image        (rx)    : ORIGIN = (MBED_ROM_START + BOOT_HEADER_SIZE), LENGTH = FLASH_CM0P_SIZE
     flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
 
     /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
@@ -156,10 +168,18 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
 
 SECTIONS
 {
-    /* Cortex-M4 application flash area */
+     /* Cortex-M0+ application flash image area */
-    .text ORIGIN(flash) + BOOT_HEADER_SIZE :
+    .cy_m0p_image ORIGIN(cm0p_image) :
+    {
+        . = ALIGN(4);
+        __cy_m0p_code_start = . ;
+        KEEP(*(.cy_m0p_image))
+        __cy_m0p_code_end = . ;
+    } > cm0p_image
+
+    /* Cortex-M4 application flash area */
+    .text ORIGIN(flash) :
     {
-        /* Cortex-M4 flash vector table */
         . = ALIGN(4);
         __Vectors = . ;
         KEEP(*(.vectors))

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4_dual.icf

@@ -1,6 +1,6 @@
 /*******************************************************************************
-* \file cyb06xx7_cm4.icf
+* \file cyb06xxa_cm4_dual.icf
-* \version 2.70.1
+* \version 2.80
 *
 * Linker file for the IAR compiler.
 *
@@ -41,52 +41,77 @@
 /*-Specials-*/
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 
+/* By default, the COMPONENT_CM0P_SECURE prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE = 0x10000;
+
+/* The size of the MCU boot header area at the start of FLASH */
+define symbol BOOT_HEADER_SIZE = 0x00000400;
+
 if (!isdefinedsymbol(MBED_ROM_START)) {
   define symbol MBED_ROM_START = 0x10000000;
 }
 
-/* MBED_APP_START is being  used by the bootloader build script and
+/* MBED_APP_START is being used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_START
+ * will be calculate by the system. In case if MBED_APP_START address is
- * is equal to MBED_ROM_START
+ * customized by the bootloader config, the application image should not
+ * include CM0p prebuilt image.
  */
 if (!isdefinedsymbol(MBED_APP_START)) {
-  define symbol MBED_APP_START = MBED_ROM_START;
+  define symbol MBED_APP_START = (MBED_ROM_START + FLASH_CM0P_SIZE);
 }
 
 if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x000D0000;
+  define symbol MBED_ROM_SIZE = 0x00E8000;
 }
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_SIZE
+ * will be calculate by the system.
- * is equal to MBED_ROM_SIZE
  */
 if (!isdefinedsymbol(MBED_APP_SIZE)) {
-  define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+  define symbol MBED_APP_SIZE = (MBED_ROM_SIZE - FLASH_CM0P_SIZE);
 }
 
 if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
+  define symbol MBED_RAM_START = 0x08001800;
 }
 
 if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x0002A000;
+  define symbol MBED_RAM_SIZE = 0x000DE800;
 }
 
 if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
-    define symbol MBED_BOOT_STACK_SIZE = 0x400;
+
+    if (!isdefinedsymbol(__STACK_SIZE)) {
+      define symbol MBED_BOOT_STACK_SIZE = 0x0400;
+    } else {
+      define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
+    }
 }
 
+define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
+
 /* The symbols below define the location and size of blocks of memory in the target.
  * Use these symbols to specify the memory regions available for allocation.
  */
 
 /* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'.
  */
 /* RAM */
 define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
 define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE - 1);
 /* Flash */
+define symbol __ICFEDIT_region_IROM0_start__ = MBED_ROM_START + BOOT_HEADER_SIZE;
+define symbol __ICFEDIT_region_IROM0_end__   = (MBED_ROM_START + FLASH_CM0P_SIZE - 1);
+
 define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
 define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 1);
 
@@ -143,12 +168,6 @@ define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
 define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
 define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
 /*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-
 /* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
 if (!isdefinedsymbol(__HEAP_SIZE)) {
     define symbol __ICFEDIT_size_heap__ = 0x0400;
@@ -157,11 +176,8 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
 }
 /**** End of ICF editor section. ###ICF###*/
 
-/* The size of the MCU boot header area at the start of FLASH */
-define symbol BOOT_HEADER_SIZE  = 0x400;
-
-
 define memory mem with size = 4G;
+define region IROM0_region = mem:[from __ICFEDIT_region_IROM0_start__ to __ICFEDIT_region_IROM0_end__];
 define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
 define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
 define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
@@ -182,6 +198,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
 define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__ { };
 define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
 
+define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)  { readonly section .cy_m0p_image };
 define block RO     {first section .intvec, readonly};
 
 /*-Initializations-*/
@@ -190,8 +207,11 @@ do not initialize  { section .noinit, section .intvec_ram };
 
 /*-Placement-*/
 
+/* Flash - Cortex-M0+ application image */
+place at start of IROM0_region  { block CM0P_RO };
+
 /* Flash - Cortex-M4 application */
-place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO };
+place at start of IROM1_region  { block RO };
 
 /* Used for the digital signature of the secure application and the Bootloader SDK application. */
 ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
@@ -230,7 +250,8 @@ place at end   of IRAM1_region  { block CSTACK };
 ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
 
 
-keep {  section .cy_app_signature,
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
         section .cy_em_eeprom,
         section .cy_sflash_user_data,
         section .cy_sflash_nar,
@@ -246,7 +267,7 @@ keep {  section .cy_app_signature,
 /* The following symbols used by the cymcuelftool. */
 /* Flash */
 define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x000D0000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
 define exported symbol __cy_memory_0_row_size = 0x200;
 
 /* Emulated EEPROM Flash area */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.70.1
+* \version 2.80
 *
 * The device system-source file.
 *
@@ -40,6 +40,10 @@
     #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
+#if defined(CY_DEVICE_SECURE)
+    #include "cy_pra.h"
+#endif /* defined(CY_DEVICE_SECURE) */
+
 
 /*******************************************************************************
 * SystemCoreClockUpdate()
@@ -160,7 +164,7 @@ void SystemInit(void)
 #ifdef __CM0P_PRESENT
     #if (__CM0P_PRESENT == 0)
         /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
+        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE <<
                                                                     CY_STARTUP_IPC7_DP_OFFSET);
 
         /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
@@ -233,6 +237,11 @@ void SystemInit(void)
 #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
 
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
+
+#if defined(CY_DEVICE_SECURE)
+    /* Initialize Protected Register Access driver */
+    Cy_PRA_Init();
+#endif /* defined(CY_DEVICE_SECURE) */
 }
 
 

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064B0S2_4343W/device/system_psoc6.h

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.70.1
+* \version 2.80
 *
 * \brief Device system header file.
 *
@@ -321,6 +321,16 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*       <td rowspan="2">2.80</td>
+*       <td>Updated linker scripts for PSoC 64 Secure MCU devices.</td>
+*       <td>Updated FLASH and SRAM memory area definitions in cyb0xxx linker script templates
+*           in accordance with the PSoC 64 Secure Boot SDK policies.</td>
+*   </tr>
+*   <tr>
+*       <td>Added \ref Cy_PRA_Init() function call to \ref SystemInit() API for CM0+ core of PSoC 64 Secure MCU.</td>
+*       <td>Updated PSoC 64 Secure MCU startup sequence to initialize the Protected Register Access driver.</td>
+*   </tr>
+*   <tr>
 *     <td>2.70.1</td>
 *     <td>Updated documentation for the better description of the existing startup implementation.</td>
 *     <td>User experience enhancement.</td>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -1,26 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg.timestamp
-*
-* Description:
-* Sentinel file for determining if generated source is up to date.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -1,47 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_clocks.c
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_clocks.h"
-
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
-	{
-		.type = CYHAL_RSC_CLOCK,
-		.block_num = CYBSP_CSD_CLK_DIV_HW,
-		.channel_num = CYBSP_CSD_CLK_DIV_NUM,
-	};
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_clocks(void)
-{
-	Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
-	Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
-	Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
-#endif //defined (CY_USING_HAL)
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -1,55 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_clocks.h
-*
-* Description:
-* Clock configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_CLOCKS_H)
-#define CYCFG_CLOCKS_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_CSD_CLK_DIV_ENABLED 1U
-#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
-#define CYBSP_CSD_CLK_DIV_NUM 3U
-
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_clocks(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_CLOCKS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -1,32 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_notices.h
-*
-* Description:
-* Contains warnings and errors that occurred while generating code for the
-* design.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_NOTICES_H)
-#define CYCFG_NOTICES_H
-
-
-#endif /* CYCFG_NOTICES_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -1,84 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_peripherals.h
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PERIPHERALS_H)
-#define CYCFG_PERIPHERALS_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_csd.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_CSD_ENABLED 1U
-#define CY_CAPSENSE_CORE 4u
-#define CY_CAPSENSE_CPU_CLK 100000000u
-#define CY_CAPSENSE_PERI_CLK 100000000u
-#define CY_CAPSENSE_VDDA_MV 3300u
-#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
-#define CY_CAPSENSE_PERI_DIV_INDEX 3u
-#define Cmod_PORT GPIO_PRT7
-#define CintA_PORT GPIO_PRT7
-#define CintB_PORT GPIO_PRT7
-#define Button0_Rx0_PORT GPIO_PRT8
-#define Button0_Tx_PORT GPIO_PRT1
-#define Button1_Rx0_PORT GPIO_PRT8
-#define Button1_Tx_PORT GPIO_PRT1
-#define LinearSlider0_Sns0_PORT GPIO_PRT8
-#define LinearSlider0_Sns1_PORT GPIO_PRT8
-#define LinearSlider0_Sns2_PORT GPIO_PRT8
-#define LinearSlider0_Sns3_PORT GPIO_PRT8
-#define LinearSlider0_Sns4_PORT GPIO_PRT8
-#define Cmod_PIN 7u
-#define CintA_PIN 1u
-#define CintB_PIN 2u
-#define Button0_Rx0_PIN 1u
-#define Button0_Tx_PIN 0u
-#define Button1_Rx0_PIN 2u
-#define Button1_Tx_PIN 0u
-#define LinearSlider0_Sns0_PIN 3u
-#define LinearSlider0_Sns1_PIN 4u
-#define LinearSlider0_Sns2_PIN 5u
-#define LinearSlider0_Sns3_PIN 6u
-#define LinearSlider0_Sns4_PIN 7u
-#define Cmod_PORT_NUM 7u
-#define CintA_PORT_NUM 7u
-#define CintB_PORT_NUM 7u
-#define CYBSP_CSD_HW CSD0
-#define CYBSP_CSD_IRQ csd_interrupt_IRQn
-
-extern cy_stc_csd_context_t cy_csd_0_context;
-
-void init_cycfg_peripherals(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PERIPHERALS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -1,59 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_routing.h
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_ROUTING_H)
-#define CYCFG_ROUTING_H
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#include "cycfg_notices.h"
-void init_cycfg_routing(void);
-#define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
-#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
-#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
-#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
-#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
-#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXB
-#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXB
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_ROUTING_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -1,598 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_system.h"
-
-#define CY_CFG_SYSCLK_ECO_ERROR 1
-#define CY_CFG_SYSCLK_ALTHF_ERROR 2
-#define CY_CFG_SYSCLK_PLL_ERROR 3
-#define CY_CFG_SYSCLK_FLL_ERROR 4
-#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
-#define CY_CFG_SYSCLK_FLL_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 48UL
-#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
-#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
-#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
-#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_ILO_ENABLED 1
-#define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
-#define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
-#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
-#define CY_CFG_SYSCLK_WCO_ENABLED 1
-#define CY_CFG_PWR_ENABLED 1
-#define CY_CFG_PWR_INIT 1
-#define CY_CFG_PWR_USING_PMIC 0
-#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
-#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
-#define CY_CFG_PWR_USING_ULP 0
-
-static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
-{
-	.fllMult = 500U,
-	.refDiv = 20U,
-	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
-	.enableOutputDiv = true,
-	.lockTolerance = 10U,
-	.igain = 9U,
-	.pgain = 5U,
-	.settlingCount = 8U,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
-	.cco_Freq = 355U,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 0U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 1U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 2U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 3U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 4U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
-{
-	.feedbackDiv = 30,
-	.referenceDiv = 1,
-	.outputDiv = 5,
-	.lfMode = false,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-};
-
-__WEAK void cycfg_ClockStartupError(uint32_t error)
-{
-    (void)error; /* Suppress the compiler warning */
-    while(1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
-{
-    Cy_SysTick_SetClockSource(CY_SYSTICK_CLOCK_SOURCE_CLK_LF);
-}
-__STATIC_INLINE void Cy_SysClk_ClkBakInit()
-{
-    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkFastInit()
-{
-    Cy_SysClk_ClkFastSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_FllInit()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
-{
-    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf1Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf4Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
-}
-__STATIC_INLINE void Cy_SysClk_IloInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_IloEnable();
-    Cy_SysClk_IloHibernateOn(true);
-}
-__STATIC_INLINE void Cy_SysClk_ClkLfInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
-{
-    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
-{
-    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
-{
-    Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath3Init()
-{
-    Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath4Init()
-{
-    Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
-{
-    Cy_SysClk_ClkPeriSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_Pll0Init()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
-{
-    Cy_SysClk_ClkSlowSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_ClkTimerInit()
-{
-    Cy_SysClk_ClkTimerDisable();
-     Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
-    Cy_SysClk_ClkTimerSetDivider(0U);
-    Cy_SysClk_ClkTimerEnable();
-}
-__STATIC_INLINE void Cy_SysClk_WcoInit()
-{
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-    }
-}
-__STATIC_INLINE void init_cycfg_power(void)
-{
-     /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
-     #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
-     #ifdef CY_CFG_SYSCLK_ILO_ENABLED
-     if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
-     {
-         Cy_SysLib_ResetBackupDomain();
-         Cy_SysClk_IloDisable();
-         Cy_SysClk_IloInit();
-     }
-     #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
-     #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
-
-     /* Configure core regulator */
-     #if CY_CFG_PWR_USING_LDO
-     Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
-     Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
-     #else
-     Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
-     #endif /* CY_CFG_PWR_USING_LDO */
-     /* Configure PMIC */
-     Cy_SysPm_UnlockPmic();
-     #if CY_CFG_PWR_USING_PMIC
-     Cy_SysPm_PmicEnableOutput();
-     #else
-     Cy_SysPm_PmicDisableOutput();
-     #endif /* CY_CFG_PWR_USING_PMIC */
-}
-
-
-void init_cycfg_system(void)
-{
-	/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
-	Cy_SysLib_SetWaitStates(false, 150UL);
-	#ifdef CY_CFG_PWR_ENABLED
-	    #ifdef CY_CFG_PWR_INIT
-	    init_cycfg_power();
-	    #else
-	    #warning Power system will not be configured. Update power personality to v1.20 or later.
-	    #endif /* CY_CFG_PWR_INIT */
-	#endif /* CY_CFG_PWR_ENABLED */
-
-	/* Reset the core clock path to default and disable all the FLLs/PLLs */
-	Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-	Cy_SysClk_ClkFastSetDivider(0U);
-	Cy_SysClk_ClkPeriSetDivider(1U);
-	Cy_SysClk_ClkSlowSetDivider(0U);
-	for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
-	{
-	    (void)Cy_SysClk_PllDisable(pll);
-	}
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-
-	if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
-	    (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
-	{
-	    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	}
-
-	Cy_SysClk_FllDisable();
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
-	Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
-	#ifdef CY_IP_MXBLESS
-	(void)Cy_BLE_EcoReset();
-	#endif
-
-
-	/* Enable all source clocks */
-	#ifdef CY_CFG_SYSCLK_PILO_ENABLED
-	Cy_SysClk_PiloInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_WCO_ENABLED
-	Cy_SysClk_WcoInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
-	Cy_SysClk_ClkLfInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
-	Cy_SysClk_AltHfInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_ECO_ENABLED
-	Cy_SysClk_EcoInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
-	Cy_SysClk_ExtClkInit();
-	#endif
-
-	/* Configure CPU clock dividers */
-	#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
-	Cy_SysClk_ClkFastInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
-	Cy_SysClk_ClkPeriInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
-	Cy_SysClk_ClkSlowInit();
-	#endif
-
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
-	    Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
-	    Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	#else
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-
-	/* Configure Path Clocks */
-	#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
-	Cy_SysClk_ClkPath0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
-	Cy_SysClk_ClkPath2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
-	Cy_SysClk_ClkPath3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
-	Cy_SysClk_ClkPath4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
-	Cy_SysClk_ClkPath5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
-	Cy_SysClk_ClkPath6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
-	Cy_SysClk_ClkPath7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
-	Cy_SysClk_ClkPath8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
-	Cy_SysClk_ClkPath9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
-	Cy_SysClk_ClkPath10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
-	Cy_SysClk_ClkPath11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
-	Cy_SysClk_ClkPath12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
-	Cy_SysClk_ClkPath13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
-	Cy_SysClk_ClkPath14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
-	Cy_SysClk_ClkPath15Init();
-	#endif
-
-	/* Configure and enable FLL */
-	#ifdef CY_CFG_SYSCLK_FLL_ENABLED
-	Cy_SysClk_FllInit();
-	#endif
-
-	Cy_SysClk_ClkHf0Init();
-
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        /* Apply the ClkPath1 user setting */
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-
-	/* Configure and enable PLLs */
-	#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
-	Cy_SysClk_Pll0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
-	Cy_SysClk_Pll1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
-	Cy_SysClk_Pll2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
-	Cy_SysClk_Pll3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
-	Cy_SysClk_Pll4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
-	Cy_SysClk_Pll5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
-	Cy_SysClk_Pll6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
-	Cy_SysClk_Pll7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
-	Cy_SysClk_Pll8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
-	Cy_SysClk_Pll9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
-	Cy_SysClk_Pll10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
-	Cy_SysClk_Pll11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
-	Cy_SysClk_Pll12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
-	Cy_SysClk_Pll13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
-	Cy_SysClk_Pll14Init();
-	#endif
-
-	/* Configure HF clocks */
-	#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
-	Cy_SysClk_ClkHf1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
-	Cy_SysClk_ClkHf2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
-	Cy_SysClk_ClkHf3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
-	Cy_SysClk_ClkHf4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
-	Cy_SysClk_ClkHf5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
-	Cy_SysClk_ClkHf6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
-	Cy_SysClk_ClkHf7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
-	Cy_SysClk_ClkHf8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
-	Cy_SysClk_ClkHf9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
-	Cy_SysClk_ClkHf10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
-	Cy_SysClk_ClkHf11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
-	Cy_SysClk_ClkHf12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
-	Cy_SysClk_ClkHf13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
-	Cy_SysClk_ClkHf14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
-	Cy_SysClk_ClkHf15Init();
-	#endif
-
-	/* Configure miscellaneous clocks */
-	#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
-	Cy_SysClk_ClkTimerInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
-	Cy_SysClk_ClkAltSysTickInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
-	Cy_SysClk_ClkPumpInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
-	Cy_SysClk_ClkBakInit();
-	#endif
-
-	/* Configure default enabled clocks */
-	#ifdef CY_CFG_SYSCLK_ILO_ENABLED
-	Cy_SysClk_IloInit();
-	#else
-	Cy_SysClk_IloDisable();
-	Cy_SysClk_IloHibernateOn(false);
-	#endif
-
-	#ifndef CY_CFG_SYSCLK_IMO_ENABLED
-	#error the IMO must be enabled for proper chip operation
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_MFO_ENABLED
-	Cy_SysClk_MfoInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
-	Cy_SysClk_ClkMfInit();
-	#endif
-
-	/* Set accurate flash wait states */
-	#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
-	Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
-	#endif
-
-	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
-	SystemCoreClockUpdate();
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
-#endif //defined (CY_USING_HAL)
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -1,113 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.h
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_SYSTEM_H)
-#define CYCFG_SYSTEM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#include "cy_systick.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-#include "cy_gpio.h"
-#include "cy_syspm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define cpuss_0_dap_0_ENABLED 1U
-#define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
-#define srss_0_clock_0_bakclk_0_ENABLED 1U
-#define srss_0_clock_0_fastclk_0_ENABLED 1U
-#define srss_0_clock_0_fll_0_ENABLED 1U
-#define srss_0_clock_0_hfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_1_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF1 1UL
-#define srss_0_clock_0_hfclk_2_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF2 2UL
-#define srss_0_clock_0_hfclk_3_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF3 3UL
-#define srss_0_clock_0_hfclk_4_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF4 4UL
-#define srss_0_clock_0_ilo_0_ENABLED 1U
-#define srss_0_clock_0_imo_0_ENABLED 1U
-#define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define srss_0_clock_0_pathmux_0_ENABLED 1U
-#define srss_0_clock_0_pathmux_1_ENABLED 1U
-#define srss_0_clock_0_pathmux_2_ENABLED 1U
-#define srss_0_clock_0_pathmux_3_ENABLED 1U
-#define srss_0_clock_0_pathmux_4_ENABLED 1U
-#define srss_0_clock_0_periclk_0_ENABLED 1U
-#define srss_0_clock_0_pll_0_ENABLED 1U
-#define srss_0_clock_0_slowclk_0_ENABLED 1U
-#define srss_0_clock_0_timerclk_0_ENABLED 1U
-#define srss_0_clock_0_wco_0_ENABLED 1U
-#define srss_0_power_0_ENABLED 1U
-#define CY_CFG_PWR_MODE_LP 0x01UL
-#define CY_CFG_PWR_MODE_ULP 0x02UL
-#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
-#define CY_CFG_PWR_MODE_SLEEP 0x08UL
-#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
-#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
-#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
-#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
-#define CY_CFG_PWR_USING_LDO 1
-#define CY_CFG_PWR_VDDA_MV 3300
-#define CY_CFG_PWR_VDDD_MV 3300
-#define CY_CFG_PWR_VBACKUP_MV 3300
-#define CY_CFG_PWR_VDD_NS_MV 3300
-#define CY_CFG_PWR_VDDIO0_MV 3300
-#define CY_CFG_PWR_VDDIO1_MV 3300
-
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_system(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_SYSTEM_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -1,63 +0,0 @@
-<?xml version="1.0"?>
-<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
-<Configuration app="QSPI" major="2" minor="0">
-    <DevicePath>PSoC 6.xml</DevicePath>
-    <SlotConfigs>
-        <SlotConfig>
-            <SlaveSlot>0</SlaveSlot>
-            <PartNumber>S25FL512S-4byteaddr</PartNumber>
-            <MemoryMapped>true</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18000000</StartAddress>
-            <Size>0x4000000</Size>
-            <EndAddress>0x1BFFFFFF</EndAddress>
-            <WriteEnable>true</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
-            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
-            <ConfigDataInFlash>true</ConfigDataInFlash>
-        </SlotConfig>
-        <SlotConfig>
-            <SlaveSlot>1</SlaveSlot>
-            <PartNumber>Not used</PartNumber>
-            <MemoryMapped>false</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18010000</StartAddress>
-            <Size>0x10000</Size>
-            <EndAddress>0x1801FFFF</EndAddress>
-            <WriteEnable>false</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
-            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
-            <ConfigDataInFlash>true</ConfigDataInFlash>
-        </SlotConfig>
-        <SlotConfig>
-            <SlaveSlot>2</SlaveSlot>
-            <PartNumber>Not used</PartNumber>
-            <MemoryMapped>false</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18020000</StartAddress>
-            <Size>0x10000</Size>
-            <EndAddress>0x1802FFFF</EndAddress>
-            <WriteEnable>false</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
-            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
-            <ConfigDataInFlash>true</ConfigDataInFlash>
-        </SlotConfig>
-        <SlotConfig>
-            <SlaveSlot>3</SlaveSlot>
-            <PartNumber>Not used</PartNumber>
-            <MemoryMapped>false</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18030000</StartAddress>
-            <Size>0x10000</Size>
-            <EndAddress>0x1803FFFF</EndAddress>
-            <WriteEnable>false</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
-            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
-            <ConfigDataInFlash>true</ConfigDataInFlash>
-        </SlotConfig>
-    </SlotConfigs>
-</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -1,486 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
-    <ToolInfo version="1.0.0"/>
-    <Devices>
-        <Device mpn="CYB0644ABZI-S2D44">
-            <BlockConfig>
-                <Block location="cpuss[0].dap[0]">
-                    <Personality template="mxs40dap" version="1.0">
-                        <Param id="dbgMode" value="SWD"/>
-                        <Param id="traceEnable" value="false"/>
-                    </Personality>
-                </Block>
-                <Block location="csd[0].csd[0]">
-                    <Alias value="CYBSP_CSD"/>
-                    <Personality template="mxs40csd" version="2.0">
-                        <Param id="CapSenseEnable" value="true"/>
-                        <Param id="CapSenseCore" value="4"/>
-                        <Param id="SensorCount" value="12"/>
-                        <Param id="CapacitorCount" value="3"/>
-                        <Param id="SensorName0" value="Cmod"/>
-                        <Param id="SensorName1" value="CintA"/>
-                        <Param id="SensorName2" value="CintB"/>
-                        <Param id="SensorName3" value="Button0_Rx0"/>
-                        <Param id="SensorName4" value="Button0_Tx"/>
-                        <Param id="SensorName5" value="Button1_Rx0"/>
-                        <Param id="SensorName6" value="Button1_Tx"/>
-                        <Param id="SensorName7" value="LinearSlider0_Sns0"/>
-                        <Param id="SensorName8" value="LinearSlider0_Sns1"/>
-                        <Param id="SensorName9" value="LinearSlider0_Sns2"/>
-                        <Param id="SensorName10" value="LinearSlider0_Sns3"/>
-                        <Param id="SensorName11" value="LinearSlider0_Sns4"/>
-                        <Param id="CapSenseConfigurator" value="0"/>
-                        <Param id="CapSenseTuner" value="0"/>
-                        <Param id="CsdAdcEnable" value="false"/>
-                        <Param id="numChannels" value="1"/>
-                        <Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
-                        <Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
-                        <Param id="acqTime" value="10"/>
-                        <Param id="autoCalibrInterval" value="30"/>
-                        <Param id="vref" value="-1"/>
-                        <Param id="operClkDivider" value="1"/>
-                        <Param id="azTime" value="5"/>
-                        <Param id="csdInitTime" value="25"/>
-                        <Param id="inFlash" value="true"/>
-                        <Param id="CsdIdacEnable" value="false"/>
-                        <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
-                        <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
-                        <Param id="csdIdacInitTime" value="25"/>
-                        <Param id="idacInFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[0].pin[0]">
-                    <Alias value="CYBSP_WCO_IN"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[0].pin[1]">
-                    <Alias value="CYBSP_WCO_OUT"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[1].pin[0]">
-                    <Alias value="CYBSP_CSD_TX"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[6].pin[4]">
-                    <Alias value="CYBSP_SWO"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[6].pin[6]">
-                    <Alias value="CYBSP_SWDIO"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[6].pin[7]">
-                    <Alias value="CYBSP_SWDCK"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[7].pin[1]">
-                    <Alias value="CYBSP_CINA"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[7].pin[2]">
-                    <Alias value="CYBSP_CINB"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[7].pin[7]">
-                    <Alias value="CYBSP_CMOD"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[1]">
-                    <Alias value="CYBSP_CSD_BTN0"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[2]">
-                    <Alias value="CYBSP_CSD_BTN1"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[3]">
-                    <Alias value="CYBSP_CSD_SLD0"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[4]">
-                    <Alias value="CYBSP_CSD_SLD1"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[5]">
-                    <Alias value="CYBSP_CSD_SLD2"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[6]">
-                    <Alias value="CYBSP_CSD_SLD3"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[8].pin[7]">
-                    <Alias value="CYBSP_CSD_SLD4"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="peri[0].div_8[3]">
-                    <Alias value="CYBSP_CSD_CLK_DIV"/>
-                    <Personality template="mxs40peripheralclock" version="1.0">
-                        <Param id="intDivider" value="256"/>
-                        <Param id="fracDivider" value="0"/>
-                        <Param id="startOnReset" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0]">
-                    <Personality template="mxs40sysclocks" version="1.2"/>
-                </Block>
-                <Block location="srss[0].clock[0].altsystickclk[0]">
-                    <Personality template="mxs40altsystick" version="1.0">
-                        <Param id="sourceClock" value="lfclk"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].bakclk[0]">
-                    <Personality template="mxs40bakclk" version="1.0">
-                        <Param id="sourceClock" value="wco"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].fastclk[0]">
-                    <Personality template="mxs40fastclk" version="1.0">
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].fll[0]">
-                    <Personality template="mxs40fll" version="1.0">
-                        <Param id="configuration" value="auto"/>
-                        <Param id="desiredFrequency" value="100.000"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[0]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="0"/>
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[1]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="1"/>
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[2]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="0"/>
-                        <Param id="divider" value="2"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[3]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="1"/>
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[4]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="0"/>
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].ilo[0]">
-                    <Personality template="mxs40ilo" version="1.0">
-                        <Param id="hibernate" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].imo[0]">
-                    <Personality template="mxs40imo" version="1.0">
-                        <Param id="trim" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].lfclk[0]">
-                    <Personality template="mxs40lfclk" version="1.1">
-                        <Param id="sourceClock" value="wco"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[0]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[1]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[2]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[3]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[4]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].periclk[0]">
-                    <Personality template="mxs40periclk" version="1.0">
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pll[0]">
-                    <Personality template="mxs40pll" version="1.0">
-                        <Param id="lowFrequencyMode" value="false"/>
-                        <Param id="configuration" value="auto"/>
-                        <Param id="desiredFrequency" value="48.000"/>
-                        <Param id="optimization" value="MinPower"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].slowclk[0]">
-                    <Personality template="mxs40slowclk" version="1.0">
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].timerclk[0]">
-                    <Personality template="mxs40timerclk" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                        <Param id="timerDivider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].wco[0]">
-                    <Personality template="mxs40wco" version="1.0">
-                        <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
-                        <Param id="clockLostDetection" value="false"/>
-                        <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
-                        <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
-                        <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
-                        <Param id="accuracyPpm" value="150"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].power[0]">
-                    <Personality template="mxs40power" version="1.2">
-                        <Param id="pwrMode" value="LDO_1_1"/>
-                        <Param id="actPwrMode" value="LP"/>
-                        <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
-                        <Param id="pmicEnable" value="false"/>
-                        <Param id="backupSrc" value="VDDD"/>
-                        <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
-                        <Param id="deepsleepLatency" value="0"/>
-                        <Param id="vddaMv" value="3300"/>
-                        <Param id="vdddMv" value="3300"/>
-                        <Param id="vBackupMv" value="3300"/>
-                        <Param id="vddNsMv" value="3300"/>
-                        <Param id="vddio0Mv" value="3300"/>
-                        <Param id="vddio1Mv" value="3300"/>
-                    </Personality>
-                </Block>
-            </BlockConfig>
-            <Netlist>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
-                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
-                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
-                    <Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
-                </Net>
-                <Net>
-                    <Port name="csd[0].csd[0].clock[0]"/>
-                    <Port name="peri[0].div_8[3].clk[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
-                </Net>
-                <Mux name="sense" location="csd[0].csd[0]">
-                    <Arm>
-                        <Port name="ioss[0].port[7].pin[7].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[1].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[2].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[3].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[4].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[5].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[6].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[8].pin[7].analog[0]"/>
-                    </Arm>
-                </Mux>
-            </Netlist>
-        </Device>
-        <Device mpn="CYW4343WKUBG">
-            <BlockConfig/>
-            <Netlist/>
-        </Device>
-    </Devices>
-    <Libraries/>
-    <ConfiguratorData/>
-</Design>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S

@@ -1,213 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     0x0000000D                ; NMI Handler located at ROM code
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External interrupts                           Description
-                DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0 
-                DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1 
-                DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2 
-                DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3 
-                DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4 
-                DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5 
-                DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6 
-                DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7 
-                DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0 
-                DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1 
-                DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2 
-                DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3 
-                DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4 
-                DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5 
-                DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6 
-                DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7 
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-                EXPORT __ramVectors
-                AREA    RESET_RAM, READWRITE, NOINIT
-__ramVectors    SPACE   __Vectors_Size
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Weak function for startup customization
-;
-; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
-; because this function is executed as the first instruction in the ResetHandler.
-; The PDL is also not initialized to use the proper register offsets.
-; The user of this function is responsible for initializing the PDL and resources before using them.
-;
-Cy_OnResetUser  PROC
-                EXPORT  Cy_OnResetUser            [WEAK]
-                BX      LR
-                ENDP
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-
-                ; Define strong function for startup customization
-                BL      Cy_OnResetUser
-
-                ; Copy vectors from ROM to RAM
-                LDR r1, =__Vectors
-                LDR r0, =__ramVectors
-                LDR r2, =__Vectors_Size
-Vectors_Copy
-                LDR r3, [r1]
-                STR r3, [r0]
-                ADDS r0, r0, #4
-                ADDS r1, r1, #4
-                SUBS r2, r2, #1
-                CMP r2, #0
-                BNE Vectors_Copy
-
-                ; Update Vector Table Offset Register. */
-                LDR r0, =__ramVectors
-                LDR r1, =0xE000ED08
-                STR r0, [r1]
-                dsb 0xF
-
-                LDR     R0, =__main
-                BLX     R0
-
-                ; Should never get here
-                B       .
-
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler         PROC
-                    EXPORT  NMI_Handler               [WEAK]
-                    B       .
-                    ENDP
-
-Cy_SysLib_FaultHandler PROC
-                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
-                    B       .
-                    ENDP
-
-HardFault_Handler   PROC
-                    EXPORT HardFault_Handler          [WEAK]
-                    movs r0, #4
-                    mov r1, LR
-                    tst r0, r1
-                    beq L_MSP
-                    mrs r0, PSP
-                    bl L_API_call
-L_MSP
-                    mrs r0, MSP
-L_API_call
-                    bl Cy_SysLib_FaultHandler
-                    ENDP
-
-SVC_Handler         PROC
-                    EXPORT  SVC_Handler               [WEAK]
-                    B       .
-                    ENDP
-PendSV_Handler      PROC
-                    EXPORT  PendSV_Handler            [WEAK]
-                    B       .
-                    ENDP
-SysTick_Handler     PROC
-                    EXPORT  SysTick_Handler           [WEAK]
-                    B       .
-                    ENDP
-
-Default_Handler     PROC
-                    EXPORT  Default_Handler                       [WEAK]
-                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
-                    EXPORT  Internal0_IRQHandler                  [WEAK]
-                    EXPORT  Internal1_IRQHandler                  [WEAK]
-                    EXPORT  Internal2_IRQHandler                  [WEAK]
-                    EXPORT  Internal3_IRQHandler                  [WEAK]
-                    EXPORT  Internal4_IRQHandler                  [WEAK]
-                    EXPORT  Internal5_IRQHandler                  [WEAK]
-                    EXPORT  Internal6_IRQHandler                  [WEAK]
-                    EXPORT  Internal7_IRQHandler                  [WEAK]
-
-NvicMux0_IRQHandler
-NvicMux1_IRQHandler
-NvicMux2_IRQHandler
-NvicMux3_IRQHandler
-NvicMux4_IRQHandler
-NvicMux5_IRQHandler
-NvicMux6_IRQHandler
-NvicMux7_IRQHandler
-Internal0_IRQHandler
-Internal1_IRQHandler
-Internal2_IRQHandler
-Internal3_IRQHandler
-Internal4_IRQHandler
-Internal5_IRQHandler
-Internal6_IRQHandler
-Internal7_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-                END
-
-
-; [] END OF FILE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S

@@ -1,317 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_02_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     08. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-        SECTION .intvec_ram:DATA:NOROOT(2)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        EXTERN __iar_data_init3
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-        PUBLIC  __ramVectors
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External interrupts                           Description
-        DCD     NvicMux0_IRQHandler                   ; CPU User Interrupt #0
-        DCD     NvicMux1_IRQHandler                   ; CPU User Interrupt #1
-        DCD     NvicMux2_IRQHandler                   ; CPU User Interrupt #2
-        DCD     NvicMux3_IRQHandler                   ; CPU User Interrupt #3
-        DCD     NvicMux4_IRQHandler                   ; CPU User Interrupt #4
-        DCD     NvicMux5_IRQHandler                   ; CPU User Interrupt #5
-        DCD     NvicMux6_IRQHandler                   ; CPU User Interrupt #6
-        DCD     NvicMux7_IRQHandler                   ; CPU User Interrupt #7
-        DCD     Internal0_IRQHandler                  ; Internal SW Interrupt #0
-        DCD     Internal1_IRQHandler                  ; Internal SW Interrupt #1
-        DCD     Internal2_IRQHandler                  ; Internal SW Interrupt #2
-        DCD     Internal3_IRQHandler                  ; Internal SW Interrupt #3
-        DCD     Internal4_IRQHandler                  ; Internal SW Interrupt #4
-        DCD     Internal5_IRQHandler                  ; Internal SW Interrupt #5
-        DCD     Internal6_IRQHandler                  ; Internal SW Interrupt #6
-        DCD     Internal7_IRQHandler                  ; Internal SW Interrupt #7
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
-
-        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
-__ramVectors
-        DS32     __Vectors_Size
-
-
-        THUMB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default handlers
-;;
-        PUBWEAK Default_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Default_Handler
-        B Default_Handler
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Weak function for startup customization
-;;
-;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-;; because this function is executed as the first instruction in the ResetHandler.
-;; The PDL is also not initialized to use the proper register offsets.
-;; The user of this function is responsible for initializing the PDL and resources before using them.
-;;
-        PUBWEAK Cy_OnResetUser
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Cy_OnResetUser
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Define strong version to return zero for
-;; __iar_program_start to skip data sections
-;; initialization.
-;;
-        PUBLIC __low_level_init
-        SECTION .text:CODE:REORDER:NOROOT(2)
-__low_level_init
-        MOVS R0, #0
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        ; Define strong function for startup customization
-        LDR     R0, =Cy_OnResetUser
-        BLX     R0
-
-        ; Copy vectors from ROM to RAM
-        LDR r1, =__vector_table
-        LDR r0, =__ramVectors
-        LDR r2, =__Vectors_Size
-intvec_copy
-        LDR r3, [r1]
-        STR r3, [r0]
-        ADDS r0, r0, #4
-        ADDS r1, r1, #4
-        SUBS r2, r2, #1
-        CMP r2, #0
-        BNE intvec_copy
-
-        ; Update Vector Table Offset Register
-        LDR r0, =__ramVectors
-        LDR r1, =0xE000ED08
-        STR r0, [r1]
-        dsb
-
-        LDR     R0, =__iar_program_start
-        BLX     R0
-
-; Should never get here
-Cy_Main_Exited
-        B Cy_Main_Exited
-
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-
-        PUBWEAK Cy_SysLib_FaultHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Cy_SysLib_FaultHandler
-        B Cy_SysLib_FaultHandler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        IMPORT Cy_SysLib_FaultHandler
-        movs r0, #4
-        mov r1, LR
-        tst r0, r1
-        beq L_MSP
-        mrs r0, PSP
-        b L_API_call
-L_MSP
-        mrs r0, MSP
-L_API_call
-        ; Storing LR content for Creator call stack trace
-        push {LR}
-        bl Cy_SysLib_FaultHandler
-
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-
-        ; External interrupts
-        PUBWEAK NvicMux0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux0_IRQHandler
-        B       NvicMux0_IRQHandler
-
-        PUBWEAK NvicMux1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux1_IRQHandler
-        B       NvicMux1_IRQHandler
-
-        PUBWEAK NvicMux2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux2_IRQHandler
-        B       NvicMux2_IRQHandler
-
-        PUBWEAK NvicMux3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux3_IRQHandler
-        B       NvicMux3_IRQHandler
-
-        PUBWEAK NvicMux4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux4_IRQHandler
-        B       NvicMux4_IRQHandler
-
-        PUBWEAK NvicMux5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux5_IRQHandler
-        B       NvicMux5_IRQHandler
-
-        PUBWEAK NvicMux6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux6_IRQHandler
-        B       NvicMux6_IRQHandler
-
-        PUBWEAK NvicMux7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux7_IRQHandler
-        B       NvicMux7_IRQHandler
-
-        PUBWEAK Internal0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal0_IRQHandler
-        B       Internal0_IRQHandler
-
-        PUBWEAK Internal1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal1_IRQHandler
-        B       Internal1_IRQHandler
-
-        PUBWEAK Internal2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal2_IRQHandler
-        B       Internal2_IRQHandler
-
-        PUBWEAK Internal3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal3_IRQHandler
-        B       Internal3_IRQHandler
-
-        PUBWEAK Internal4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal4_IRQHandler
-        B       Internal4_IRQHandler
-
-        PUBWEAK Internal5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal5_IRQHandler
-        B       Internal5_IRQHandler
-
-        PUBWEAK Internal6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal6_IRQHandler
-        B       Internal6_IRQHandler
-
-        PUBWEAK Internal7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Internal7_IRQHandler
-        B       Internal7_IRQHandler
-
-
-        END
-
-
-; [] END OF FILE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct

@@ -1,308 +0,0 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xxa_cm4.sct
-;* \version 2.70.1
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2020 Cypress Semiconductor Corporation
-;* Copyright 2020 Arm Limited
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#include "../../../partition/region_defs.h"
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    NS_CODE_START
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     NS_CODE_SIZE
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    NS_DATA_START
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     NS_DATA_SIZE
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE
-#endif
-
-; Shared memory area between Non-secure and Secure
-#define MBED_DATA_SHARED_SIZE  NS_DATA_SHARED_SIZE
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM4 core.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M4 application flash area
-LR_IROM1 FLASH_START FLASH_SIZE
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 ALIGN 4 EMPTY RAM_START+RAM_SIZE-MBED_BOOT_STACK_SIZE-MBED_DATA_SHARED_SIZE-ImageLimit(RW_IRAM1)
-    {
-    }
-
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY -MBED_BOOT_STACK_SIZE
-    {
-    }
-
-    ; Stack area overflowed within RAM
-    ScatterAssert(ImageBase(ARM_LIB_STACK) + ImageLength(ARM_LIB_STACK) == RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE)
-
-    ; Shared region
-    ARM_LIB_SHARED RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY MBED_DATA_SHARED_SIZE
-    {
-    }
-
-    ; Shared area overflowed within RAM
-    ScatterAssert(ImageBase(ARM_LIB_SHARED) + ImageLength(ARM_LIB_SHARED) == RAM_START+RAM_SIZE)
-
-
-    ; Used for the digital signature of the secure application and the
-    ; Bootloader SDK application. The size of the section depends on the required
-    ; data size.
-    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
-    {
-        * (.cy_app_signature)
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    .cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x001D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld

@@ -1,454 +0,0 @@
-/***************************************************************************//**
-* \file cyb06xxa_cm4.ld
-* \version 2.70.1
-*
-* Linker file for the GNU C compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* Copyright 2020 Arm Limited
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-ENTRY(Reset_Handler)
-
-#include "../../../partition/region_defs.h"
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    NS_CODE_START
-#endif
-
-/* MBED_APP_START is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
-* is equal to MBED_ROM_START
-*/
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     NS_CODE_SIZE
-#endif
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-* is equal to MBED_ROM_SIZE
-*/
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    NS_DATA_START
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     NS_DATA_SIZE
-#endif
-
-/* Size of the stack section in CM4 SRAM area */
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE
-#endif
-
-/* Shared memory area between Non-Secure and Secure */
-#define MBED_DATA_SHARED_SIZE  NS_DATA_SHARED_SIZE
-
-/* Force symbol to be entered in the output file as an undefined symbol. Doing
-* this may, for example, trigger linking of additional modules from standard
-* libraries. You may list several symbols for each EXTERN, and you may use
-* EXTERN multiple times. This command has the same effect as the -u command-line
-* option.
-*/
-EXTERN(Reset_Handler)
-
-/* The MEMORY section below describes the location and size of blocks of memory in the target.
-* Use this section to specify the memory regions available for allocation.
-*/
-MEMORY
-{
-    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
-     */
-    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
-
-    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
-     * You can assign sections to this memory region for only one of the cores.
-     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-     * Therefore, repurposing this memory region will prevent such middleware from operation.
-     */
-    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
-
-    /* The following regions define device specific memory regions and must not be changed. */
-    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
-    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
-    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
-    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
-    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
-    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
-    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-
-
-SECTIONS
-{
-    /* Cortex-M4 application flash area */
-    .text ORIGIN(flash) :
-    {
-        /* Cortex-M4 flash vector table */
-        . = ALIGN(4);
-        __Vectors = . ;
-        KEEP(*(.vectors))
-        . = ALIGN(4);
-        __Vectors_End = .;
-        __Vectors_Size = __Vectors_End - __Vectors;
-        __end__ = .;
-
-        . = ALIGN(4);
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* Read-only code (constants). */
-        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
-
-        KEEP(*(.eh_frame*))
-    } > flash
-
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    __exidx_start = .;
-
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > flash
-    __exidx_end = .;
-
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-
-        /* Copy interrupt vectors from flash to RAM */
-        LONG (__Vectors)                                    /* From */
-        LONG (__ram_vectors_start__)                        /* To   */
-        LONG (__Vectors_End - __Vectors)                    /* Size */
-
-        /* Copy data section to RAM */
-        LONG (__etext)                                      /* From */
-        LONG (__data_start__)                               /* To   */
-        LONG (__data_end__ - __data_start__)                /* Size */
-
-        __copy_table_end__ = .;
-    } > flash
-
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        __zero_table_end__ = .;
-    } > flash
-
-    __etext =  . ;
-
-
-    .ramVectors (NOLOAD) : ALIGN(8)
-    {
-        __ram_vectors_start__ = .;
-        KEEP(*(.ram_vectors))
-        __ram_vectors_end__   = .;
-    } > ram
-
-
-    .data __ram_vectors_end__ : AT (__etext)
-    {
-        __data_start__ = .;
-
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        KEEP(*(.cy_ramfunc*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > ram
-
-
-    /* Place variables in the section that should not be initialized during the
-    *  device startup.
-    */
-    .noinit (NOLOAD) : ALIGN(8)
-    {
-      KEEP(*(.noinit))
-    } > ram
-
-
-    /* The uninitialized global or static variables are placed in this section.
-    *
-    * The NOLOAD attribute tells linker that .bss section does not consume
-    * any space in the image. The NOLOAD attribute changes the .bss type to
-    * NOBITS, and that  makes linker to A) not allocate section in memory, and
-    * A) put information to clear the section with all zeros during application
-    * loading.
-    *
-    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
-    * This  makes linker to A) allocate zeroed section in memory, and B) copy
-    * this section to RAM during application loading.
-    */
-    .bss (NOLOAD):
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram
-
-
-    .heap (NOLOAD):
-    {
-        __HeapBase = .;
-        __end__ = .;
-        end = __end__;
-        KEEP(*(.heap*))
-        . = ORIGIN(ram) + LENGTH(ram) - MBED_BOOT_STACK_SIZE - MBED_DATA_SHARED_SIZE;
-        . = ALIGN(4);
-        __StackLimit = .;
-        __HeapLimit = .;
-    } > ram
-
-
-    __StackTop = (__StackLimit + MBED_BOOT_STACK_SIZE + 3) & 0xFFFFFFFC;
-    PROVIDE(__stack = __StackTop);
-
-    .shared __StackTop (NOLOAD):
-    {
-        __SharedStart = .;
-        . += MBED_DATA_SHARED_SIZE;
-        KEEP(*(.shared*))
-        __SharedLimit = .;
-    } > ram
-
-    /* Check if Shared area overflowed within RAM */
-    ASSERT(__SharedLimit == ORIGIN(ram) + LENGTH(ram), "Shared area overflowed within RAM")
-
-    /* Used for the digital signature of the secure application and the Bootloader SDK application.
-    * The size of the section depends on the required data size. */
-    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
-    {
-        KEEP(*(.cy_app_signature))
-    } > flash
-
-
-    /* Emulated EEPROM Flash area */
-    .cy_em_eeprom :
-    {
-        KEEP(*(.cy_em_eeprom))
-    } > em_eeprom
-
-
-    /* Supervisory Flash: User data */
-    .cy_sflash_user_data :
-    {
-        KEEP(*(.cy_sflash_user_data))
-    } > sflash_user_data
-
-
-    /* Supervisory Flash: Normal Access Restrictions (NAR) */
-    .cy_sflash_nar :
-    {
-        KEEP(*(.cy_sflash_nar))
-    } > sflash_nar
-
-
-    /* Supervisory Flash: Public Key */
-    .cy_sflash_public_key :
-    {
-        KEEP(*(.cy_sflash_public_key))
-    } > sflash_public_key
-
-
-    /* Supervisory Flash: Table of Content # 2 */
-    .cy_toc_part2 :
-    {
-        KEEP(*(.cy_toc_part2))
-    } > sflash_toc_2
-
-
-    /* Supervisory Flash: Table of Content # 2 Copy */
-    .cy_rtoc_part2 :
-    {
-        KEEP(*(.cy_rtoc_part2))
-    } > sflash_rtoc_2
-
-
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
-    /* eFuse */
-    .cy_efuse :
-    {
-        KEEP(*(.cy_efuse))
-    } > efuse
-
-
-    /* These sections are used for additional metadata (silicon revision,
-    *  Silicon/JTAG ID, etc.) storage.
-    */
-    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
-}
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x001D0000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start    = 0x14000000;
-__cy_memory_1_length   = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start    = 0x16000000;
-__cy_memory_2_length   = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start    = 0x18000000;
-__cy_memory_3_length   = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start    = 0x90700000;
-__cy_memory_4_length   = 0x100000;
-__cy_memory_4_row_size = 1;
-
-/* EOF */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cyb06xxa_cm4.icf

@@ -1,272 +0,0 @@
-/*******************************************************************************
-* \file cyb06xxa_cm4.icf
-* \version 2.70.1
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-if (!isdefinedsymbol(MBED_ROM_START)) {
-  define symbol MBED_ROM_START = 0x10000000;
-}
-
-/* MBED_APP_START is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_START
- * is equal to MBED_ROM_START
- */
-if (!isdefinedsymbol(MBED_APP_START)) {
-  define symbol MBED_APP_START = MBED_ROM_START;
-}
-
-if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x001D0000;
-}
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_SIZE
- * is equal to MBED_ROM_SIZE
- */
-if (!isdefinedsymbol(MBED_APP_SIZE)) {
-  define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
-}
-
-if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
-}
-
-if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x000EA000;
-}
-
-if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
-    define symbol MBED_BOOT_STACK_SIZE = 0x400;
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM4 core.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE - 1);
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
-define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 1);
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/*-Sizes-*/
-if (!isdefinedsymbol(__STACK_SIZE)) {
-  define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
-} else {
-  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
-}
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-/**** End of ICF editor section. ###ICF###*/
-
-/* The size of the MCU boot header area at the start of FLASH */
-define symbol BOOT_HEADER_SIZE  = 0x400;
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-
-define block RAM_DATA {readwrite section .data};
-define block RAM_OTHER {readwrite section * };
-define block RAM_NOINIT {readwrite section .noinit};
-define block RAM_BSS {readwrite section .bss};
-define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
-
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-
-define block RO     {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M4 application */
-place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO };
-
-/* Used for the digital signature of the secure application and the Bootloader SDK application. */
-".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region  { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in IRAM1_region  { block RAM};
-place in IRAM1_region  { block HEAP};
-place at end   of IRAM1_region  { block CSTACK };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_app_signature,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x001D0000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c

@@ -1,390 +0,0 @@
-/***************************************************************************//**
-* \file system_psoc6_cm4.c
-* \version 2.70.1
-*
-* The device system-source file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdbool.h>
-#include "system_psoc6.h"
-#include "cy_device.h"
-#include "cy_device_headers.h"
-#include "cy_syslib.h"
-#include "cy_sysclk.h"
-#include "cy_wdt.h"
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    #include "cy_ipc_sema.h"
-    #include "cy_ipc_pipe.h"
-    #include "cy_ipc_drv.h"
-
-    #if defined(CY_DEVICE_PSOC6ABLE2)
-        #include "cy_flash.h"
-    #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate()
-*******************************************************************************/
-
-/** Default HFClk frequency in Hz */
-#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
-
-/** Default PeriClk frequency in Hz */
-#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (4000000UL)
-
-/** Default FastClk system core frequency in Hz */
-#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (8000000UL)
-
-
-/**
-* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
-* which is the system clock frequency supplied to the SysTick timer and the
-* processor core clock.
-* This variable implements CMSIS Core global variable.
-* Refer to the [CMSIS documentation]
-* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
-* for more details.
-* This variable can be used by debuggers to query the frequency
-* of the debug timer or to configure the trace clock speed.
-*
-* \attention Compilers must be configured to avoid removing this variable in case
-* the application program is not using it. Debugging systems require the variable
-* to be physically present in memory so that it can be examined to configure the debugger. */
-uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
-
-/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
-
-/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
-uint32_t cy_BleEcoClockFreqHz = 0UL;
-
-/* SCB->CPACR */
-#define SCB_CPACR_CP10_CP11_ENABLE      (0xFUL << 20u)
-
-
-/*******************************************************************************
-* SystemInit()
-*******************************************************************************/
-
-/* CLK_FLL_CONFIG default values */
-#define CY_FB_CLK_FLL_CONFIG_VALUE      (0x01000000u)
-#define CY_FB_CLK_FLL_CONFIG2_VALUE     (0x00020001u)
-#define CY_FB_CLK_FLL_CONFIG3_VALUE     (0x00002800u)
-#define CY_FB_CLK_FLL_CONFIG4_VALUE     (0x000000FFu)
-
-/* IPC_STRUCT7->DATA configuration */
-#define CY_STARTUP_CM0_DP_STATE         (0x2uL)
-#define CY_STARTUP_IPC7_DP_OFFSET       (0x28u)
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate (void)
-*******************************************************************************/
-
-/* Do not use these definitions directly in your application */
-#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
-#define CY_DELAY_1K_THRESHOLD           (1000u)
-#define CY_DELAY_1M_THRESHOLD           (1000000u)
-
-uint32_t cy_delayFreqKhz  = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
-
-uint8_t cy_delayFreqMhz  = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
-
-uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
-                            CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
-
-
-/*******************************************************************************
-* Function Name: SystemInit
-****************************************************************************//**
-* \cond
-* Initializes the system:
-* - Restores FLL registers to the default state for single core devices.
-* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
-* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
-* - Calls \ref SystemCoreClockUpdate().
-* \endcond
-*******************************************************************************/
-void SystemInit(void)
-{
-    Cy_PDL_Init(CY_DEVICE_CFG);
-
-#ifdef __CM0P_PRESENT
-    #if (__CM0P_PRESENT == 0)
-        /* Restore FLL registers to the default state as they are not restored by the ROM code */
-        uint32_t copy = SRSS->CLK_FLL_CONFIG;
-        copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
-        SRSS->CLK_FLL_CONFIG = copy;
-
-        copy = SRSS->CLK_ROOT_SELECT[0u];
-        copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
-        SRSS->CLK_ROOT_SELECT[0u] = copy;
-
-        SRSS->CLK_FLL_CONFIG  = CY_FB_CLK_FLL_CONFIG_VALUE;
-        SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
-        SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
-        SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
-
-        /* Unlock and disable WDT */
-        Cy_WDT_Unlock();
-        Cy_WDT_Disable();
-    #endif /* (__CM0P_PRESENT == 0) */
-#endif /* __CM0P_PRESENT */
-
-    Cy_SystemInit();
-    SystemCoreClockUpdate();
-
-#ifdef __CM0P_PRESENT
-    #if (__CM0P_PRESENT == 0)
-        /* Configure data register (as CM0p in deep sleep state) of IPC structure #7, reserved for the Deep-Sleep operations. */
-        REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = (CY_STARTUP_CM0_DP_STATE << 
-                                                                    CY_STARTUP_IPC7_DP_OFFSET);
-
-        /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
-        REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
-    #endif /* (__CM0P_PRESENT == 0) */
-#endif /* __CM0P_PRESENT */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-
-#ifdef __CM0P_PRESENT
-    #if (__CM0P_PRESENT == 0)
-        /* Allocate and initialize semaphores for the system operations. */
-        static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
-        (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
-    #else
-        (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
-    #endif /* (__CM0P_PRESENT) */
-#else
-    (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL);
-#endif /* __CM0P_PRESENT */
-
-
-    /********************************************************************************
-    *
-    * Initializes the system pipes. The system pipes are used by BLE and Flash.
-    *
-    * If the default startup file is not used, or SystemInit() is not called in your
-    * project, call the following three functions prior to executing any flash or
-    * EmEEPROM write or erase operation:
-    *  -# Cy_IPC_Sema_Init()
-    *  -# Cy_IPC_Pipe_Config()
-    *  -# Cy_IPC_Pipe_Init()
-    *  -# Cy_Flash_Init()
-    *
-    *******************************************************************************/
-    /* Create an array of endpoint structures */
-    static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
-    Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
-    static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
-    static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 =
-    {
-    /* .ep0ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP0,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP0,
-            /* .ipcNotifierMuxNumber */  CY_SYS_INTR_CYPIPE_MUX_EP0,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM0_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP0
-        },
-    /* .ep1ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP1,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP1,
-            /* .ipcNotifierMuxNumber */  0u,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM4_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP1
-        },
-    /* .endpointClientsCount     */  CY_SYS_CYPIPE_CLIENT_CNT,
-    /* .endpointsCallbacksArray  */  systemIpcPipeSysCbArray,
-    /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm4
-    };
-
-    Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4);
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
-    Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SystemInit
-****************************************************************************//**
-*
-* The function is called during device startup. Once project compiled as part of
-* the PSoC Creator project, the Cy_SystemInit() function is generated by the
-* PSoC Creator.
-*
-* The function generated by PSoC Creator performs all of the necessary device
-* configuration based on the design settings.  This includes settings from the
-* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
-* configuration that is necessary.
-*
-*******************************************************************************/
-__WEAK void Cy_SystemInit(void)
-{
-     /* Empty weak function. The actual implementation to be in the PSoC Creator
-      * generated strong function.
-     */
-}
-
-
-/*******************************************************************************
-* Function Name: SystemCoreClockUpdate
-****************************************************************************//**
-*
-* Gets core clock frequency and updates \ref SystemCoreClock, \ref
-* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz.
-*
-* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
-* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
-*
-*******************************************************************************/
-void SystemCoreClockUpdate (void)
-{
-    uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
-
-    if (0UL != locHf0Clock)
-    {
-        cy_Hfclk0FreqHz = locHf0Clock;
-        cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
-        SystemCoreClock = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkFastGetDivider());
-
-        /* Sets clock frequency for Delay API */
-        cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
-        cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
-        cy_delay32kMs   = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
-    }
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SystemInitFpuEnable
-****************************************************************************//**
-*
-* Enables the FPU if it is used. The function is called from the startup file.
-*
-*******************************************************************************/
-void Cy_SystemInitFpuEnable(void)
-{
-    #if defined (__FPU_USED) && (__FPU_USED == 1U)
-        uint32_t  interruptState;
-        interruptState = Cy_SysLib_EnterCriticalSection();
-        SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE;
-        __DSB();
-        __ISB();
-        Cy_SysLib_ExitCriticalSection(interruptState);
-    #endif /* (__FPU_USED) && (__FPU_USED == 1U) */
-}
-
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-/*******************************************************************************
-* Function Name: Cy_SysIpcPipeIsrCm4
-****************************************************************************//**
-*
-* This is the interrupt service routine for the system pipe.
-*
-*******************************************************************************/
-void Cy_SysIpcPipeIsrCm4(void)
-{
-    Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR);
-}
-#endif
-
-
-/*******************************************************************************
-* Function Name: Cy_MemorySymbols
-****************************************************************************//**
-*
-* The intention of the function is to declare boundaries of the memories for the
-* MDK compilers. For the rest of the supported compilers, this is done using
-* linker configuration files. The following symbols used by the cymcuelftool.
-*
-*******************************************************************************/
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
-__asm void Cy_MemorySymbols(void)
-{
-    /* Flash */
-    EXPORT __cy_memory_0_start
-    EXPORT __cy_memory_0_length
-    EXPORT __cy_memory_0_row_size
-
-    /* Working Flash */
-    EXPORT __cy_memory_1_start
-    EXPORT __cy_memory_1_length
-    EXPORT __cy_memory_1_row_size
-
-    /* Supervisory Flash */
-    EXPORT __cy_memory_2_start
-    EXPORT __cy_memory_2_length
-    EXPORT __cy_memory_2_row_size
-
-    /* XIP */
-    EXPORT __cy_memory_3_start
-    EXPORT __cy_memory_3_length
-    EXPORT __cy_memory_3_row_size
-
-    /* eFuse */
-    EXPORT __cy_memory_4_start
-    EXPORT __cy_memory_4_length
-    EXPORT __cy_memory_4_row_size
-
-    /* Flash */
-__cy_memory_0_start     EQU __cpp(CY_FLASH_BASE)
-__cy_memory_0_length    EQU __cpp(CY_FLASH_SIZE)
-__cy_memory_0_row_size  EQU 0x200
-
-    /* Flash region for EEPROM emulation */
-__cy_memory_1_start     EQU __cpp(CY_EM_EEPROM_BASE)
-__cy_memory_1_length    EQU __cpp(CY_EM_EEPROM_SIZE)
-__cy_memory_1_row_size  EQU 0x200
-
-    /* Supervisory Flash */
-__cy_memory_2_start     EQU __cpp(CY_SFLASH_BASE)
-__cy_memory_2_length    EQU __cpp(CY_SFLASH_SIZE)
-__cy_memory_2_row_size  EQU 0x200
-
-    /* XIP */
-__cy_memory_3_start     EQU __cpp(CY_XIP_BASE)
-__cy_memory_3_length    EQU __cpp(CY_XIP_SIZE)
-__cy_memory_3_row_size  EQU 0x200
-
-    /* eFuse */
-__cy_memory_4_start     EQU __cpp(0x90700000)
-__cy_memory_4_length    EQU __cpp(0x100000)
-__cy_memory_4_row_size  EQU __cpp(1)
-}
-#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/system_psoc6.h

@@ -1,664 +0,0 @@
-/***************************************************************************//**
-* \file system_psoc6.h
-* \version 2.70.1
-*
-* \brief Device system header file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-
-#ifndef _SYSTEM_PSOC6_H_
-#define _SYSTEM_PSOC6_H_
-
-/**
-* \addtogroup group_system_config
-* \{
-* Provides device startup, system configuration, and linker script files.
-* The system startup provides the followings features:
-* - See \ref group_system_config_device_initialization for the:
-*   * \ref group_system_config_dual_core_device_initialization
-*   * \ref group_system_config_single_core_device_initialization
-* - \ref group_system_config_device_memory_definition
-* - \ref group_system_config_heap_stack_config
-* - \ref group_system_config_default_handlers
-* - \ref group_system_config_device_vector_table
-* - \ref group_system_config_cm4_functions
-*
-* \section group_system_config_configuration Configuration Considerations
-*
-* \subsection group_system_config_device_memory_definition Device Memory Definition
-* The flash and RAM allocation for each CPU is defined by the linker scripts.
-* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
-* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
-* For Single-Core devices the system reserves additional 80 bytes of RAM.
-* Using the reserved memory area for other purposes will lead to unexpected behavior.
-*
-* \note The linker files provided with the PDL are generic and handle all common
-* use cases. Your project may not use every section defined in the linker files.
-* In that case you may see warnings during the build process. To eliminate build
-* warnings in your project, you can simply comment out or remove the relevant
-* code in the linker file.
-*
-* \note For the PSoC 64 Secure MCUs devices, refer to the following page:
-* https://www.cypress.com/documentation/software-and-drivers/psoc-64-secure-mcu-secure-boot-sdk-user-guide
-*
-*
-* <b>ARM GCC</b>\n
-* The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
-* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
-* \note If the start of the Cortex-M4 application image is changed, the value
-* of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
-* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
-* Cy_SysEnableCM4() function call.
-* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
-*
-* Change the flash and RAM sizes by editing the macros value in the
-* linker files for both CPUs:
-* - 'xx_cm0plus.ld', where 'xx' is the device group:
-* \code
-* flash       (rx)  : ORIGIN = 0x10000000, LENGTH = 0x2000
-* ram         (rwx) : ORIGIN = 0x08000000, LENGTH = 0x2000
-* \endcode
-* - 'xx_cm4_dual.ld', where 'xx' is the device group:
-* \code
-* flash       (rx)  : ORIGIN = 0x10000000, LENGTH = 0x100000
-* ram         (rwx) : ORIGIN = 0x08002000, LENGTH = 0x45800
-* \endcode
-*
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the ROM ORIGIN's
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the flash LENGTH in 
-* 'xx_cm0plus.ld') in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. 
-* Do this by either:
-* - Passing the following commands to the compiler:\n
-* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
-* or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 
-* 'xx' is the device family:\n
-* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
-*
-* <b>ARM Compiler</b>\n
-* The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.sct', where 'xx' is the device group, and 'yy' is the target CPU; for 
-* example 'cy8c6xx7_cm0plus.sct' and 'cy8c6xx7_cm4_dual.sct'.
-* \note If the start of the Cortex-M4 application image is changed, the value
-* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
-* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
-* Cy_SysEnableCM4() function call.
-* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
-*
-* \note The linker files provided with the PDL are generic and handle all common
-* use cases. Your project may not use every section defined in the linker files.
-* In that case you may see the warnings during the build process:
-* L6314W (no section matches pattern) and/or L6329W
-* (pattern only matches removed unused sections). In your project, you can
-* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-* the linker. You can also comment out or remove the relevant code in the linker
-* file.
-*
-* Change the flash and RAM sizes by editing the macros value in the
-* linker files for both CPUs:
-* - 'xx_cm0plus.sct', where 'xx' is the device group:
-* \code
-* #define FLASH_START 0x10000000
-* #define FLASH_SIZE  0x00002000
-* #define RAM_START   0x08000000
-* #define RAM_SIZE    0x00002000
-* \endcode
-* - 'xx_cm4_dual.sct', where 'xx' is the device group:
-* \code
-* #define FLASH_START 0x10000000
-* #define FLASH_SIZE  0x00100000
-* #define RAM_START   0x08002000
-* #define RAM_SIZE    0x00045800
-* \endcode
-*
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
-* value (0x10000000) + FLASH_CM0P_SIZE value (0x2000, the size of a flash image 
-* of the Cortex-M0+ application should be the same value as the FLASH_SIZE in the 
-* 'xx_cm0plus.sct') in the 'xx_cm4_dual.sct' file, where 'xx' is the device group. 
-* Do this by either:
-* - Passing the following commands to the compiler:\n
-* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
-* or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
-* 'xx' is the device family:\n
-* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
-*
-* <b>IAR</b>\n
-* The flash and RAM sections for the CPU are defined in the linker files:
-* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
-* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
-* \note If the start of the Cortex-M4 application image is changed, the value
-* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
-* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
-* Cy_SysEnableCM4() function call.
-* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
-* More about CM0+ prebuilt images, see here:
-* https://github.com/cypresssemiconductorco/psoc6cm0p
-*
-* Change the flash and RAM sizes by editing the macros value in the
-* linker files for both CPUs:
-* - 'xx_cm0plus.icf', where 'xx' is the device group:
-* \code
-* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-* define symbol __ICFEDIT_region_IROM1_end__   = 0x10001FFF;
-* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
-* define symbol __ICFEDIT_region_IRAM1_end__   = 0x08001FFF;
-* \endcode
-* - 'xx_cm4_dual.icf', where 'xx' is the device group:
-* \code
-* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
-* define symbol __ICFEDIT_region_IROM1_end__   = 0x100FFFFF;
-* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
-* define symbol __ICFEDIT_region_IRAM1_end__   = 0x080477FF;
-* \endcode
-*
-* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the 
-* __ICFEDIT_region_IROM1_start__ value (0x10000000) + FLASH_CM0P_SIZE value 
-* (0x2000, the size of a flash image of the Cortex-M0+ application) in the 
-* 'xx_cm4_dual.icf' file, where 'xx' is the device group. The sum result
-* should be the same as (__ICFEDIT_region_IROM1_end__ + 1) value in the 
-* 'xx_cm0plus.icf'. Do this by either:
-* - Passing the following commands to the compiler:\n
-* \code -D CY_CORTEX_M4_APPL_ADDR=0x10002000 \endcode
-* or
-* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
-* 'xx' is the device family:\n
-* \code #define CY_CORTEX_M4_APPL_ADDR (0x10002000u) \endcode
-*
-* \subsection group_system_config_device_initialization Device Initialization
-* After a power-on-reset (POR), the boot process is handled by the boot code
-* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
-* code passes the control to the Cortex-M0+ startup code located in flash.
-*
-* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
-* The Cortex-M0+ startup code performs the device initialization by a call to
-* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
-* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
-* See \ref group_system_config_cm4_functions for more details.
-* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
-* The function has a separate implementation on each core.
-* Both function implementations unlock and disable the WDT.
-* Therefore enable the WDT after both cores have been initialized.
-*
-* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
-* The Cortex-M0+ core is not user-accessible on these devices. In this case the
-* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
-*
-* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
-* There are two ways to adjust heap and stack configurations:
-* -# Editing source code files
-* -# Specifying via command line
-*
-* By default, the stack size is set to 0x00001000 and the heap size is allocated 
-* dynamically to the whole available free memory up to stack memory and it 
-* is set to the 0x00000400 (for ARM GCC and IAR compilers) as minimal value.
-*
-* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
-* - <b>Editing source code files</b>\n
-* The heap and stack sizes are defined in the assembler startup files
-* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
-* Change the heap and stack sizes by modifying the following lines:\n
-* \code .equ  Stack_Size, 0x00001000 \endcode
-* \code .equ  Heap_Size,  0x00000400 \endcode
-* Also, the stack size is defined in the linker script files: 'xx_yy.ld',
-* where 'xx' is the device family, and 'yy' is the target CPU; for example,
-* cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
-* Change the stack size by modifying the following line:\n
-* \code STACK_SIZE = 0x1000; \endcode
-*
-* \subsubsection group_system_config_heap_stack_config_mdk ARM Compiler
-* - <b>Editing source code files</b>\n
-* The stack size is defined in the linker script files: 'xx_yy.sct',
-* where 'xx' is the device family, and 'yy' is the target CPU; for example,
-* cy8c6xx7_cm0plus.sct and cy8c6xx7_cm4_dual.sct.
-* Change the stack size by modifying the following line:\n
-* \code STACK_SIZE = 0x1000; \endcode
-*
-* \subsubsection group_system_config_heap_stack_config_iar IAR
-* - <b>Editing source code files</b>\n
-* The heap and stack sizes are defined in the linker script files: 'xx_yy.icf',
-* where 'xx' is the device family, and 'yy' is the target CPU; for example,
-* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
-* Change the heap and stack sizes by modifying the following lines:\n
-* \code Stack_Size      EQU     0x00001000 \endcode
-* \code Heap_Size       EQU     0x00000400 \endcode
-*
-* - <b>Specifying via command line</b>\n
-* Change the heap and stack sizes passing the following commands to the
-* linker (including quotation marks):\n
-* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
-* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
-*
-* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
-* The default interrupt handler functions are defined as weak functions to a dummy
-* handler in the startup file. The naming convention for the interrupt handler names
-* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
-* user code by defining the handler function using the same name. For example:
-* \code
-* void scb_0_interrupt_IRQHandler(void)
-*{
-*    ...
-*}
-* \endcode
-*
-* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
-* This process uses memory sections defined in the linker script. The startup
-* code actually defines the contents of the vector table and performs the copy.
-* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
-* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
-* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
-* It defines sections and locations in memory.\n
-*       Copy interrupt vectors from flash to RAM: \n
-*       From: \code LONG (__Vectors) \endcode
-*       To:   \code LONG (__ram_vectors_start__) \endcode
-*       Size: \code LONG (__Vectors_End - __Vectors) \endcode
-* The vector table address (and the vector table itself) are defined in the
-* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
-* The code in these files copies the vector table from Flash to RAM.
-* \subsubsection group_system_config_device_vector_table_mdk ARM Compiler
-* The linker script file is 'xx_yy.sct', where 'xx' is the device family,
-* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.sct and
-* cy8c6xx7_cm4_dual.sct. The linker script specifies that the vector table
-* (RESET_RAM) shall be first in the RAM section.\n
-* RESET_RAM represents the vector table. It is defined in the assembler startup
-* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
-* The code in these files copies the vector table from Flash to RAM.
-*
-* \subsubsection group_system_config_device_vector_table_iar IAR
-* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
-* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
-* This file defines the .intvec_ram section and its location.
-* \code place at start of IRAM1_region  { readwrite section .intvec_ram}; \endcode
-* The vector table address (and the vector table itself) are defined in the
-* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
-* The code in these files copies the vector table from Flash to RAM.
-*
-* \section group_system_config_MISRA MISRA Compliance
-*
-* <table class="doxtable">
-*   <tr>
-*     <th>MISRA Rule</th>
-*     <th>Rule Class (Required/Advisory)</th>
-*     <th>Rule Description</th>
-*     <th>Description of Deviation(s)</th>
-*   </tr>
-*   <tr>
-*     <td>2.3</td>
-*     <td>R</td>
-*     <td>The character sequence // shall not be used within a comment.</td>
-*     <td>The comments provide a useful WEB link to the documentation.</td>
-*   </tr>
-* </table>
-*
-* \section group_system_config_changelog Changelog
-*   <table class="doxtable">
-*   <tr>
-*       <th>Version</th>
-*       <th>Changes</th>
-*       <th>Reason for Change</th>
-*   </tr>
-*   <tr>
-*     <td>2.70.1</td>
-*     <td>Updated documentation for the better description of the existing startup implementation.</td>
-*     <td>User experience enhancement.</td>
-*   </tr>
-*   <tr>
-*       <td rowspan="5">2.70</td>
-*       <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
-*       <td>Code optimization.</td>
-*   </tr>
-*   <tr>
-*       <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
-*       <td>Provided support for SysPM driver updates.</td>
-*   </tr>
-*   <tr>
-*       <td>Updated the linker scripts.</td>
-*       <td>Reserved FLASH area for the MCU boot headers.</td>
-*   </tr>
-*   <tr>
-*       <td>Added System Pipe initialization for all devices. </td>
-*       <td>Improved PDL usability according to user experience.</td>
-*   </tr>
-*   <tr>
-*       <td>Removed redundant legacy macros: CY_CLK_EXT_FREQ_HZ, CY_CLK_ECO_FREQ_HZ and CY_CLK_ALTHF_FREQ_HZ.
-*           Use \ref Cy_SysClk_ExtClkSetFrequency, \ref Cy_SysClk_EcoConfigure and \ref Cy_BLE_EcoConfigure functions instead them. </td>
-*       <td>Defect fixing.</td>
-*   </tr>
-*   <tr>
-*       <td>2.60</td>
-*       <td>Updated linker scripts.</td>
-*       <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
-*   </tr>
-*   <tr>
-*       <td>2.50</td>
-*       <td>Updated assembler files, C files, linker scripts.</td>
-*       <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
-*   </tr>
-*   <tr>
-*       <td>2.40</td>
-*       <td>Updated assembler files, C files, linker scripts.</td>
-*       <td>Added Arm Compiler 6 support.</td>
-*   </tr>
-*   <tr>
-*       <td rowspan="2">2.30</td>
-*       <td>Added assembler files, linker scripts for Mbed OS.</td>
-*       <td>Added Arm Mbed OS embedded operating system support.</td>
-*   </tr>
-*   <tr>
-*       <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
-*       <td>Enhanced PDL usability.</td>
-*   </tr>
-*   <tr>
-*       <td>2.20</td>
-*       <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
-*       <td>Changed the IPC driver configuration method from compile time to run time.</td>
-*   </tr>
-*   <tr>
-*     <td rowspan="2"> 2.10</td>
-*     <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
-*         Removed $Sub$$main symbol for ARM MDK compiler.
-*     </td>
-*     <td>uVision Debugger support.</td>
-*   </tr>
-*   <tr>
-*     <td>Updated description of the Startup behavior for Single-Core Devices. \n
-*         Added note about WDT disabling by SystemInit() function.
-*     </td>
-*     <td>Documentation improvement.</td>
-*   </tr>
-*   <tr>
-*     <td rowspan="4"> 2.0</td>
-*     <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
-*         Single core device support.
-*     </td>
-*     <td></td>
-*   </tr>
-*   <tr>
-*     <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
-*         Renamed 'wflash' memory region to 'em_eeprom'.
-*     </td>
-*     <td>Linker scripts usability improvement.</td>
-*   </tr>
-*   <tr>
-*     <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
-*     <td>Reserved system resources for internal operations.</td>
-*   </tr>
-*   <tr>
-*     <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
-*     <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
-*   </tr>
-*   <tr>
-*       <td>1.0</td>
-*       <td>Initial version</td>
-*       <td></td>
-*   </tr>
-* </table>
-*
-*
-* \defgroup group_system_config_macro Macro
-* \{
-*   \defgroup group_system_config_system_macro            System
-*   \defgroup group_system_config_cm4_status_macro        Cortex-M4 Status
-*   \defgroup group_system_config_user_settings_macro     User Settings
-* \}
-* \defgroup group_system_config_functions Functions
-* \{
-*   \defgroup group_system_config_system_functions        System
-*   \defgroup group_system_config_cm4_functions           Cortex-M4 Control
-* \}
-* \defgroup group_system_config_globals Global Variables
-*
-* \}
-*/
-
-/**
-* \addtogroup group_system_config_system_functions
-* \{
-*   \details
-*   The following system functions implement CMSIS Core functions.
-*   Refer to the [CMSIS documentation]
-*   (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
-*   for more details.
-* \}
-*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/*******************************************************************************
-* Include files
-*******************************************************************************/
-#include <stdint.h>
-
-
-/*******************************************************************************
-* Global preprocessor symbols/macros ('define')
-*******************************************************************************/
-#if ((defined(__GNUC__)        &&  (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
-     (defined (__ICCARM__)     &&  (__CORE__ == __ARM6M__))  || \
-     (defined(__ARMCC_VERSION) &&  (__TARGET_ARCH_THUMB == 3)))
-    #define CY_SYSTEM_CPU_CM0P          1UL
-#else
-    #define CY_SYSTEM_CPU_CM0P          0UL
-#endif
-
-
-/*******************************************************************************
-*
-*                      START OF USER SETTINGS HERE
-*                      ===========================
-*
-*                 All lines with '<<<' can be set by user.
-*
-*******************************************************************************/
-
-/**
-* \addtogroup group_system_config_user_settings_macro
-* \{
-*/
-
-
-/***************************************************************************//**
-* \brief Start address of the Cortex-M4 application ([address]UL)
-*        <i>(USER SETTING)</i>
-*******************************************************************************/
-#if !defined (CY_CORTEX_M4_APPL_ADDR)
-    #define CY_CORTEX_M4_APPL_ADDR          (CY_FLASH_BASE + 0x2000U)   /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
-#endif /* (CY_CORTEX_M4_APPL_ADDR) */
-
-
-/***************************************************************************//**
-* \brief IPC Semaphores allocation ([value]UL).
-*        <i>(USER SETTING)</i>
-*******************************************************************************/
-#define CY_IPC_SEMA_COUNT               (128UL)  /* <<< This will allow 128 (4*32) semaphores */
-
-
-/***************************************************************************//**
-* \brief IPC Pipe definitions ([value]UL).
-*        <i>(USER SETTING)</i>
-*******************************************************************************/
-#define CY_IPC_MAX_ENDPOINTS            (8UL) /* <<< 8 endpoints */
-
-
-/*******************************************************************************
-*
-*                         END OF USER SETTINGS HERE
-*                         =========================
-*
-*******************************************************************************/
-
-/** \} group_system_config_user_settings_macro */
-
-
-/**
-* \addtogroup group_system_config_system_macro
-* \{
-*/
-
-#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
-    /** The Cortex-M0+ startup driver identifier */
-    #define CY_STARTUP_M0P_ID               ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
-#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
-
-#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
-    /** The Cortex-M4 startup driver identifier */
-    #define CY_STARTUP_M4_ID        ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
-#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
-
-/** \} group_system_config_system_macro */
-
-
-/**
-* \addtogroup group_system_config_system_functions
-* \{
-*/
-extern void SystemInit(void);
-
-extern void SystemCoreClockUpdate(void);
-/** \} group_system_config_system_functions */
-
-
-/**
-* \addtogroup group_system_config_cm4_functions
-* \{
-*/
-extern uint32_t Cy_SysGetCM4Status(void);
-extern void     Cy_SysEnableCM4(uint32_t vectorTableOffset);
-extern void     Cy_SysDisableCM4(void);
-extern void     Cy_SysRetainCM4(void);
-extern void     Cy_SysResetCM4(void);
-/** \} group_system_config_cm4_functions */
-
-
-/** \cond */
-extern void     Default_Handler (void);
-
-void Cy_SysIpcPipeIsrCm0(void);
-void Cy_SysIpcPipeIsrCm4(void);
-
-extern void     Cy_SystemInit(void);
-extern void     Cy_SystemInitFpuEnable(void);
-
-extern uint32_t cy_delayFreqKhz;
-extern uint8_t  cy_delayFreqMhz;
-extern uint32_t cy_delay32kMs;
-/** \endcond */
-
-
-#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
-/**
-* \addtogroup group_system_config_cm4_status_macro
-* \{
-*/
-#define CY_SYS_CM4_STATUS_ENABLED   (3U)    /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
-#define CY_SYS_CM4_STATUS_DISABLED  (0U)    /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
-#define CY_SYS_CM4_STATUS_RETAINED  (2U)    /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
-#define CY_SYS_CM4_STATUS_RESET     (1U)    /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
-/** \} group_system_config_cm4_status_macro */
-
-#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
-
-
-/*******************************************************************************
-*                             IPC Configuration
-*                         =========================
-*******************************************************************************/
-/* IPC CY_PIPE default configuration */
-#define CY_SYS_CYPIPE_CLIENT_CNT        (8UL)
-
-#define CY_SYS_INTR_CYPIPE_MUX_EP0      (1UL)   /* IPC CYPRESS PIPE */
-#define CY_SYS_INTR_CYPIPE_PRIOR_EP0    (1UL)   /* Notifier Priority */
-#define CY_SYS_INTR_CYPIPE_PRIOR_EP1    (1UL)   /* Notifier Priority */
-
-#define CY_SYS_CYPIPE_CHAN_MASK_EP0     (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
-#define CY_SYS_CYPIPE_CHAN_MASK_EP1     (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
-
-
-/******************************************************************************/
-/*
- * The System pipe configuration defines the IPC channel number, interrupt
- * number, and the pipe interrupt mask for the endpoint.
- *
- * The format of the endPoint configuration
- *    Bits[31:16] Interrupt Mask
- *    Bits[15:8 ] IPC interrupt
- *    Bits[ 7:0 ] IPC channel
- */
-
-/* System Pipe addresses */
-/* CyPipe defines */
-
-#define CY_SYS_CYPIPE_INTR_MASK   ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
-
-#define CY_SYS_CYPIPE_CONFIG_EP0  ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
-                                   | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
-                                    | CY_IPC_CHAN_CYPIPE_EP0)
-#define CY_SYS_CYPIPE_CONFIG_EP1  ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
-                                   | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
-                                    | CY_IPC_CHAN_CYPIPE_EP1)
-
-/******************************************************************************/
-
-
-/** \addtogroup group_system_config_globals
-* \{
-*/
-
-extern uint32_t SystemCoreClock;
-extern uint32_t cy_BleEcoClockFreqHz;
-extern uint32_t cy_Hfclk0FreqHz;
-extern uint32_t cy_PeriClkFreqHz;
-
-/** \} group_system_config_globals */
-
-
-
-/** \cond INTERNAL */
-/*******************************************************************************
-* Backward compatibility macros. The following code is DEPRECATED and must
-* not be used in new projects
-*******************************************************************************/
-
-/* BWC defines for functions related to enter/exit critical section */
-#define Cy_SaveIRQ      Cy_SysLib_EnterCriticalSection
-#define Cy_RestoreIRQ   Cy_SysLib_ExitCriticalSection
-#define CY_SYS_INTR_CYPIPE_EP0          (CY_IPC_INTR_CYPIPE_EP0)
-#define CY_SYS_INTR_CYPIPE_EP1          (CY_IPC_INTR_CYPIPE_EP1)
-#define cy_delayFreqHz                  (SystemCoreClock)
-
-/** \endcond */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SYSTEM_PSOC6_H_ */
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/flash_layout.h

@@ -1,185 +0,0 @@
-/*
- * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
- * Copyright (c) 2019, Cypress Semiconductor Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __FLASH_LAYOUT_H__
-#define __FLASH_LAYOUT_H__
-
-/* Flash layout with BL2:
- *
- * Not supported
- *
- * Flash layout if BL2 not defined:
- *
- * 0x1000_0000 Secure     image primary (320 KB)
- * 0x1005_0000 Non-secure image primary (1152 KB)
- * 0x1017_0000 Secure     image secondary (320 KB)
- * 0x101c_0000 - 0x101f_ffff Reserved
- *  0x101c_0000 Secure Storage Area (20 KB)
- *  0x101c_5000 Internal Trusted Storage Area (16 KB)
- *  0x101c_9000 NV counters area (512 Bytes)
- *  0x101c_9200 Scratch area (27.5 KB)
- *  0x101d_0000 Reserved (192 KB)
- * 0x101f_ffff End of Flash
- *
- */
-
-#define MAX(X, Y)                       (((X) > (Y)) ? (X) : (Y))
-
-/* This header file is included from linker scatter file as well, where only a
- * limited C constructs are allowed. Therefore it is not possible to include
- * here the platform_base_address.h to access flash related defines. To resolve
- * this some of the values are redefined here with different names, these are
- * marked with comment.
- */
-
-/* The size of S partition */
-#define FLASH_S_PARTITION_SIZE          0x50000      /* 320 KB */
-/* The size of NS partition */
-#define FLASH_NS_PARTITION_SIZE         0x120000     /* 1152 KB */
-
-/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */
-#define FLASH_AREA_IMAGE_SECTOR_SIZE    (0x200)      /* 512 B */
-/* Same as FLASH0_SIZE */
-#define FLASH_TOTAL_SIZE                (0x00200000) /* 2 MB */
-
-/* Flash layout info for BL2 bootloader */
-#define FLASH_BASE_ADDRESS              (0x10000000U) /* same as FLASH0_BASE */
-
-/* Reserved areas */
-#define FLASH_RESERVED_AREA_OFFSET      (SECURE_IMAGE_OFFSET + \
-                                         2*SECURE_IMAGE_MAX_SIZE + \
-                                         NON_SECURE_IMAGE_MAX_SIZE)
-
-/* FixMe: implement proper mcuboot partitioning for CYBL */
-
-/* Reserved for Secure Storage Area */
-#define FLASH_SST_AREA_OFFSET           (FLASH_RESERVED_AREA_OFFSET)
-#define FLASH_SST_AREA_SIZE             (0x5000)   /* 20 KB */
-
-/* Internal Trusted Storage Area */
-#define FLASH_ITS_AREA_OFFSET           (FLASH_SST_AREA_OFFSET + \
-                                         FLASH_SST_AREA_SIZE)
-#define FLASH_ITS_AREA_SIZE             (0x4000)    /* 16 KB */
-
-#define FLASH_NV_COUNTERS_AREA_OFFSET   (FLASH_ITS_AREA_OFFSET + \
-                                         FLASH_ITS_AREA_SIZE)
-#define FLASH_NV_COUNTERS_AREA_SIZE     (FLASH_AREA_IMAGE_SECTOR_SIZE)
-
-#ifdef BL2
-#error "BL2 configuration is not supported"
-#else /* BL2 */
-
-#define FLASH_AREA_SCRATCH_OFFSET       (FLASH_NV_COUNTERS_AREA_OFFSET + \
-                                         FLASH_NV_COUNTERS_AREA_SIZE)
-#define FLASH_AREA_SCRATCH_SIZE         (0x6e00)   /* 27.5 KB */
-#endif /* BL2 */
-
-#define FLASH_AREA_SYSTEM_RESERVED_SIZE (0x30000) /* 192 KB */
-
-
-/* Secure and non-secure images definition in flash area */
-
-#define SECURE_IMAGE_OFFSET             0x0
-
-#define SECURE_IMAGE_MAX_SIZE           FLASH_S_PARTITION_SIZE
-
-#define NON_SECURE_IMAGE_OFFSET         (SECURE_IMAGE_OFFSET + \
-                                         SECURE_IMAGE_MAX_SIZE)
-
-#define NON_SECURE_IMAGE_MAX_SIZE       FLASH_NS_PARTITION_SIZE
-
-/* Check if it fits into available Flash*/
-
-#define FLASH_RESERVED_AREA_SIZE        (FLASH_SST_AREA_SIZE + \
-                                         FLASH_ITS_AREA_SIZE + \
-                                         FLASH_NV_COUNTERS_AREA_SIZE + \
-                                         FLASH_AREA_SCRATCH_SIZE + \
-                                         FLASH_AREA_SYSTEM_RESERVED_SIZE)
-
-#if (FLASH_RESERVED_AREA_OFFSET + FLASH_RESERVED_AREA_SIZE) > (FLASH_TOTAL_SIZE)
-#error "Out of Flash memory"
-#endif
-
-/* Flash device name used by BL2 and SST
- * Name is defined in flash driver file: Driver_Flash.c
- */
-#define FLASH_DEV_NAME Driver_FLASH0
-
-/* Secure Storage (SST) Service definitions
- * Note: Further documentation of these definitions can be found in the
- * TF-M SST Integration Guide.
- */
-#define SST_FLASH_DEV_NAME Driver_FLASH0
-
-/* In this target the CMSIS driver requires only the offset from the base
- * address instead of the full memory address.
- */
-#define SST_FLASH_AREA_ADDR     FLASH_SST_AREA_OFFSET
-/* Dedicated flash area for SST */
-#define SST_FLASH_AREA_SIZE     FLASH_SST_AREA_SIZE
-#define SST_SECTOR_SIZE         FLASH_AREA_IMAGE_SECTOR_SIZE
-/* Number of SST_SECTOR_SIZE per block */
-#define SST_SECTORS_PER_BLOCK   0x8
-/* Specifies the smallest flash programmable unit in bytes */
-#define SST_FLASH_PROGRAM_UNIT  0x1
-/* The maximum asset size to be stored in the SST area */
-#define SST_MAX_ASSET_SIZE      2048
-/* The maximum number of assets to be stored in the SST area */
-#define SST_NUM_ASSETS          10
-
-/* Internal Trusted Storage (ITS) Service definitions
- * Note: Further documentation of these definitions can be found in the
- * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is
- * allocated in the external flash just for development platforms that don't
- * have internal flash available.
- */
-#define ITS_FLASH_DEV_NAME Driver_FLASH0
-
-/* In this target the CMSIS driver requires only the offset from the base
- * address instead of the full memory address.
- */
-#define ITS_FLASH_AREA_ADDR     FLASH_ITS_AREA_OFFSET
-/* Dedicated flash area for ITS */
-#define ITS_FLASH_AREA_SIZE     FLASH_ITS_AREA_SIZE
-#define ITS_SECTOR_SIZE         FLASH_AREA_IMAGE_SECTOR_SIZE
-/* Number of ITS_SECTOR_SIZE per block */
-#define ITS_SECTORS_PER_BLOCK   (0x8)
-/* Specifies the smallest flash programmable unit in bytes */
-#define ITS_FLASH_PROGRAM_UNIT  (0x1)
-/* The maximum asset size to be stored in the ITS area */
-#define ITS_MAX_ASSET_SIZE      (512)
-/* The maximum number of assets to be stored in the ITS area */
-#define ITS_NUM_ASSETS          (10)
-
-/* NV Counters definitions */
-#define TFM_NV_COUNTERS_AREA_ADDR    FLASH_NV_COUNTERS_AREA_OFFSET
-#define TFM_NV_COUNTERS_AREA_SIZE    FLASH_NV_COUNTERS_AREA_SIZE
-#define TFM_NV_COUNTERS_SECTOR_ADDR  FLASH_NV_COUNTERS_AREA_OFFSET
-#define TFM_NV_COUNTERS_SECTOR_SIZE  MAX(FLASH_NV_COUNTERS_AREA_SIZE, \
-                                         FLASH_AREA_IMAGE_SECTOR_SIZE)
-
-/* Use Flash to store Code data */
-#define S_ROM_ALIAS_BASE  (0x10000000)
-#define NS_ROM_ALIAS_BASE (0x10000000)
-
-/* Use SRAM to store RW data */
-#define S_RAM_ALIAS_BASE  (0x08000000)
-#define NS_RAM_ALIAS_BASE (0x08000000)
-
-#endif /* __FLASH_LAYOUT_H__ */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/partition/region_defs.h

@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2017-2019 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __REGION_DEFS_H__
-#define __REGION_DEFS_H__
-
-#include "flash_layout.h"
-
-#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE
-/* 2KB of RAM (at the end of the SRAM) are reserved for system use. Using
- * this memory region for other purposes will lead to unexpected behavior.
- * 94KB of RAM (just before the memory reserved for system use) are
- * allocated and protected by Cypress Bootloader */
-/* FixMe: confirm exact available amount of RAM based on the actual
-   system allocation */
-#define TOTAL_RAM_SIZE (0x000E8000) /* CY_SRAM_SIZE - 96KB */
-
-#define BL2_HEAP_SIZE           0x0001000
-#define BL2_MSP_STACK_SIZE      0x0001000
-
-#define S_HEAP_SIZE             0x0001000
-#define S_MSP_STACK_SIZE_INIT   0x0000400
-#define S_MSP_STACK_SIZE        0x0000800
-#define S_PSP_STACK_SIZE        0x0000800
-
-#define NS_HEAP_SIZE            0x0001000
-#define NS_MSP_STACK_SIZE       0x0000400
-#define NS_PSP_STACK_SIZE       0x0000C00
-
-/* Relocation of vectors to RAM support */
-/* #define RAM_VECTORS_SUPPORT */
-
-/*
- * This size of buffer is big enough to store an attestation
- * token produced by initial attestation service
- */
-#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE   0x250
-
-/*
- * MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment
- * of partitions is defined in accordance with this constraint.
- */
-
-#ifdef BL2
-#error "BL2 configuration is not supported"
-#else
-#define S_IMAGE_PRIMARY_PARTITION_OFFSET  SECURE_IMAGE_OFFSET
-#define NS_IMAGE_PRIMARY_PARTITION_OFFSET NON_SECURE_IMAGE_OFFSET
-#endif /* BL2 */
-
-/* TFM PSoC6 CY8CKIT_064 RAM layout:
- *
- * 0x0800_0000 - 0x0802_FFFF Secure (192KB)
- *    0x0800_0000 - 0x0800_FFFF Secure unprivileged data (S_UNPRIV_DATA_SIZE, 64KB)
- *    0x0801_0000 - 0x0802_EFFF Secure priviliged data (S_PRIV_DATA_SIZE, 124KB)
- *    0x0802_F000 - 0x0802_FFFF Secure priv code executable from RAM (S_RAM_CODE_SIZE, 4KB)
- *
- * 0x0803_0000 - 0x080E_7FFF Non-secure (736KB)
- *    0x0803_0000 - 0x080E_6FFF Non-secure OS/App (732KB)
- *    0x080E_7000 - 0x080E_7FFF Shared memory (NS_DATA_SHARED_SIZE, 4KB)
- * 0x080E_8000 - 0x080F_FFFF System reserved memory (96KB)
- * 0x0810_0000 End of RAM
- */
-
-/*
- * Boot partition structure if MCUBoot is used:
- * 0x0_0000 Bootloader header
- * 0x0_0400 Image area
- * 0x1_FC00 Trailer
- */
-/* Image code size is the space available for the software binary image.
- * It is less than the FLASH_S_PARTITION_SIZE and FLASH_NS_PARTITION_SIZE
- * because we reserve space for the image header and trailer introduced by the
- * bootloader.
- */
-#ifdef BL2
-#error "BL2 configuration is not supported"
-#else
-/* Even though TFM BL2 is excluded from the build,
- * CY BL built externally is used and it needs offsets for header and trailer
- * to be taken in account.
- * */
-#define BL2_HEADER_SIZE      (0x400)
-#define BL2_TRAILER_SIZE     (0x400)
-
-#endif /* BL2 */
-
-#define IMAGE_S_CODE_SIZE \
-            (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-#define IMAGE_NS_CODE_SIZE \
-            (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
-
-/* Alias definitions for secure and non-secure areas*/
-#define S_ROM_ALIAS(x)  (S_ROM_ALIAS_BASE + (x))
-#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x))
-
-#define S_RAM_ALIAS(x)  (S_RAM_ALIAS_BASE + (x))
-#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
-
-/* Secure regions */
-#define S_IMAGE_PRIMARY_AREA_OFFSET \
-             (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
-#define S_CODE_START    (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
-#define S_CODE_SIZE     IMAGE_S_CODE_SIZE
-#define S_CODE_LIMIT    (S_CODE_START + S_CODE_SIZE - 1)
-
-#define S_DATA_START    (S_RAM_ALIAS(0))
-#define S_UNPRIV_DATA_SIZE  0x10000
-#define S_PRIV_DATA_SIZE    0x1F000
-/* Reserve 4KB for RAM-based executable code */
-#define S_RAM_CODE_SIZE     0x1000
-
-/* Secure data area */
-#define S_DATA_SIZE  (S_UNPRIV_DATA_SIZE + S_PRIV_DATA_SIZE + S_RAM_CODE_SIZE)
-#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
-
-/* We need the privileged data area to be aligned so that an SMPU
- * region can cover it.
- */
-/* TODO It would be nice to figure this out automatically.
- * In theory, in the linker script, we could determine the amount
- * of secure data space available after all the unprivileged data,
- * round that down to a power of 2 to get the actual size we want
- * to use for privileged data, and then determine this value from
- * that. We'd also potentially have to update the configs for SMPU9
- * and SMPU10.
- * Leave the SMPU alignment check in SMPU configuration file.
- */
-#define S_DATA_UNPRIV_OFFSET (0)
-#define S_DATA_UNPRIV_START  S_RAM_ALIAS(S_DATA_UNPRIV_OFFSET)
-
-#define S_DATA_PRIV_OFFSET   (S_DATA_UNPRIV_OFFSET + S_UNPRIV_DATA_SIZE)
-#define S_DATA_PRIV_START    S_RAM_ALIAS(S_DATA_PRIV_OFFSET)
-
-/* Reserve area for RAM-based executable code right after secure unprivilaged
- * and privilaged data areas*/
-#define S_RAM_CODE_OFFSET    (S_DATA_PRIV_OFFSET + S_PRIV_DATA_SIZE)
-#define S_RAM_CODE_START     S_RAM_ALIAS(S_RAM_CODE_OFFSET)
-
-/* Non-secure regions */
-#define NS_IMAGE_PRIMARY_AREA_OFFSET \
-                        (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
-#define NS_CODE_START   (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
-#define NS_CODE_SIZE    IMAGE_NS_CODE_SIZE
-#define NS_CODE_LIMIT   (NS_CODE_START + NS_CODE_SIZE - 1)
-
-#define NS_DATA_START   (S_RAM_ALIAS(S_DATA_SIZE))
-#define NS_DATA_SIZE    (TOTAL_RAM_SIZE - S_DATA_SIZE)
-#define NS_DATA_LIMIT   (NS_DATA_START + NS_DATA_SIZE - 1)
-
-/* Shared memory */
-#define NS_DATA_SHARED_SIZE  0x1000
-#define NS_DATA_SHARED_START (NS_DATA_START + NS_DATA_SIZE - \
-                              NS_DATA_SHARED_SIZE)
-#define NS_DATA_SHARED_LIMIT (NS_DATA_SHARED_START + NS_DATA_SHARED_SIZE - 1)
-
-/* Shared variables addresses */
-/* ipcWaitMessageStc, cy_flash.c */
-#define IPC_WAIT_MESSAGE_STC_SIZE 4
-#define IPC_WAIT_MESSAGE_STC_ADDR (NS_DATA_SHARED_START + \
-                                   NS_DATA_SHARED_SIZE - \
-                                   IPC_WAIT_MESSAGE_STC_SIZE)
-
-/* NS partition information is used for MPC and SAU configuration */
-#define NS_PARTITION_START \
-            (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
-
-#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
-
-#ifdef BL2
-#error "BL2 configuration is not supported"
-#endif /* BL2 */
-
-/* Shared data area between bootloader and runtime firmware.
- * Shared data area is allocated at the beginning of the privileged data area,
- * it is overlapping with TF-M Secure code's MSP stack
- */
-#define BOOT_TFM_SHARED_DATA_BASE (S_RAM_ALIAS(S_DATA_PRIV_OFFSET))
-#define BOOT_TFM_SHARED_DATA_SIZE 0x400
-
-#endif /* __REGION_DEFS_H__ */
-

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/secure_image_parameters.json

@@ -1,17 +0,0 @@
-{   
-    "boot0" : { 
-        "VERSION" : "0.1",
-        "ROLLBACK_COUNTER" : "0"
-    },
-    
-    "boot1" : {
-        "VERSION" : "0.1",
-        "ROLLBACK_COUNTER" : "0"
-    },
-    
-    "sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/",
-    "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem",
-    "aes_key_file": "keys/image-aes-128.key",
-    "dev_pub_key_file": "keys/dev_pub_key.pem",
-    "policy_file": "policy/policy_single_stage_CM4_2m.json"
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -1,34 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg.c
-*
-* Description:
-* Wrapper function to initialize all generated code.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg.h"
-
-void init_cycfg_all(void)
-{
-	init_cycfg_system();
-	init_cycfg_routing();
-	init_cycfg_pins();
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -1,47 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg.h
-*
-* Description:
-* Simple wrapper header containing all generated files.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_H)
-#define CYCFG_H
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#include "cycfg_notices.h"
-#include "cycfg_system.h"
-#include "cycfg_routing.h"
-#include "cycfg_pins.h"
-
-void init_cycfg_all(void);
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -1,235 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.c
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_pins.h"
-
-const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_WCO_IN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_WCO_IN_PORT_NUM,
-		.channel_num = CYBSP_WCO_IN_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_WCO_OUT_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_WCO_OUT_PORT_NUM,
-		.channel_num = CYBSP_WCO_OUT_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_ECO_IN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_ECO_IN_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_ECO_IN_PORT_NUM,
-		.channel_num = CYBSP_ECO_IN_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_ECO_OUT_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_ECO_OUT_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_ECO_OUT_PORT_NUM,
-		.channel_num = CYBSP_ECO_OUT_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_SWO_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SWO_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_SWO_PORT_NUM,
-		.channel_num = CYBSP_SWO_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_SWDIO_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SWDIO_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_SWDIO_PORT_NUM,
-		.channel_num = CYBSP_SWDIO_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config =
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLDOWN,
-	.hsiom = CYBSP_SWCLK_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SWCLK_obj =
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_SWCLK_PORT_NUM,
-		.channel_num = CYBSP_SWCLK_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_pins(void)
-{
-	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_ECO_IN_PORT, CYBSP_ECO_IN_PIN, &CYBSP_ECO_IN_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_ECO_IN_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_ECO_OUT_PORT, CYBSP_ECO_OUT_PIN, &CYBSP_ECO_OUT_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_ECO_OUT_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_SWCLK_PORT, CYBSP_SWCLK_PIN, &CYBSP_SWCLK_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_SWCLK_obj);
-#endif //defined (CY_USING_HAL)
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -1,246 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PORT_NUM 0U
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PORT_NUM 0U
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_ECO_IN_ENABLED 1U
-#define CYBSP_ECO_IN_PORT GPIO_PRT12
-#define CYBSP_ECO_IN_PORT_NUM 12U
-#define CYBSP_ECO_IN_PIN 6U
-#define CYBSP_ECO_IN_NUM 6U
-#define CYBSP_ECO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_ECO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_6_HSIOM
-	#define ioss_0_port_12_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_ECO_IN_HSIOM ioss_0_port_12_pin_6_HSIOM
-#define CYBSP_ECO_IN_IRQ ioss_interrupts_gpio_12_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_IN_HAL_PORT_PIN P12_6
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_ECO_OUT_ENABLED 1U
-#define CYBSP_ECO_OUT_PORT GPIO_PRT12
-#define CYBSP_ECO_OUT_PORT_NUM 12U
-#define CYBSP_ECO_OUT_PIN 7U
-#define CYBSP_ECO_OUT_NUM 7U
-#define CYBSP_ECO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_ECO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_12_pin_7_HSIOM
-	#define ioss_0_port_12_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_ECO_OUT_HSIOM ioss_0_port_12_pin_7_HSIOM
-#define CYBSP_ECO_OUT_IRQ ioss_interrupts_gpio_12_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_OUT_HAL_PORT_PIN P12_7
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_ECO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PORT_NUM 6U
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_PORT_PIN P6_4
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PORT_NUM 6U
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
-#endif //defined (CY_USING_HAL)
-#define CYBSP_SWCLK_ENABLED 1U
-#define CYBSP_SWCLK_PORT GPIO_PRT6
-#define CYBSP_SWCLK_PORT_NUM 6U
-#define CYBSP_SWCLK_PIN 7U
-#define CYBSP_SWCLK_NUM 7U
-#define CYBSP_SWCLK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWCLK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWCLK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWCLK_IRQ ioss_interrupts_gpio_6_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWCLK_HAL_PORT_PIN P6_7
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWCLK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWCLK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWCLK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
-#endif //defined (CY_USING_HAL)
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_ECO_IN_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_ECO_IN_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_ECO_OUT_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_ECO_OUT_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_SWCLK_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SWCLK_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -1,266 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_qspi_memslot.c
-*
-* Description:
-* Provides definitions of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* QSPI Configurator: 2.0.0.1483
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_qspi_memslot.h"
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xEBU,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_QUAD,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0x01U,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_QUAD,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 4U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_QUAD
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x06U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x04U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x20U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x60U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x38U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_QUAD,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_QUAD
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x35U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x05U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x01U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0 =
-{
-    /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x03U,
-    /* The size of the memory. */
-    .memSize = 0x1000000U,
-    /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readCmd,
-    /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeEnCmd,
-    /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeDisCmd,
-    /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_eraseCmd,
-    /* Specifies the sector size of each erase. */
-    .eraseSize = 0x0001000U,
-    /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_chipEraseCmd,
-    /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_programCmd,
-    /* Specifies the page size for programming. */
-    .programSize = 0x0000200U,
-    /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegQeCmd,
-    /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_readStsRegWipCmd,
-    /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL128S_SlaveSlot_0_writeStsRegQeCmd,
-    /* The mask for the status register. */
-    .stsRegBusyMask = 0x01U,
-    /* The mask for the status register. */
-    .stsRegQuadEnableMask = 0x02U,
-    /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 650U,
-    /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 165000U,
-    /* The max time for the page-program cycle-time in us. */
-    .programTime = 750U
-};
-
-const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0 =
-{
-    /* Determines the slot number where the memory device is placed. */
-    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
-    /* Flags. */
-    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
-    /* The data-line selection options for a slave device. */
-    .dataSelect = CY_SMIF_DATA_SEL0,
-    /* The base address the memory slave is mapped to in the PSoC memory map.
-    Valid when the memory-mapped mode is enabled. */
-    .baseAddress = 0x18000000U,
-    /* The size allocated in the PSoC memory map, for the memory slave device.
-    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x1000000U,
-    /* If this memory device is one of the devices in the dual quad SPI configuration.
-    Valid when the memory mapped mode is enabled. */
-    .dualQuadSlots = 0,
-    /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL128S_SlaveSlot_0
-};
-
-const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL128S_SlaveSlot_0
-};
-
-const cy_stc_smif_block_config_t smifBlockConfig =
-{
-    /* The number of SMIF memories defined. */
-    .memCount = CY_SMIF_DEVICE_NUM,
-    /* The pointer to the array of memory config structures of size memCount. */
-    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
-    /* The version of the SMIF driver. */
-    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
-    /* The version of the SMIF driver. */
-    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
-};
-

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -1,51 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_qspi_memslot.h
-*
-* Description:
-* Provides declarations of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* QSPI Configurator: 2.0.0.1483
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#ifndef CYCFG_QSPI_MEMSLOT_H
-#define CYCFG_QSPI_MEMSLOT_H
-#include "cy_smif_memslot.h"
-
-#define CY_SMIF_DEVICE_NUM 1
-
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeEnCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeDisCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_eraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_chipEraseCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_programCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegQeCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_readStsRegWipCmd;
-extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd;
-
-extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0;
-
-extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0;
-extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
-
-extern const cy_stc_smif_block_config_t smifBlockConfig;
-
-
-#endif /*CY_SMIF_MEMCONFIG_H*/
-

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -1,31 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_routing.c
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_routing.h"
-
-void init_cycfg_routing(void)
-{
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -1,48 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_routing.h
-*
-* Description:
-* Establishes all necessary connections between hardware elements.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_ROUTING_H)
-#define CYCFG_ROUTING_H
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#include "cycfg_notices.h"
-void init_cycfg_routing(void);
-#define init_cycfg_connectivity() init_cycfg_routing()
-#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
-#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
-#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
-#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
-#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_ROUTING_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -1,567 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.c
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_system.h"
-
-#define CY_CFG_SYSCLK_ECO_ERROR 1
-#define CY_CFG_SYSCLK_ALTHF_ERROR 2
-#define CY_CFG_SYSCLK_PLL_ERROR 3
-#define CY_CFG_SYSCLK_FLL_ERROR 4
-#define CY_CFG_SYSCLK_WCO_ERROR 5
-#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
-#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
-#define CY_CFG_SYSCLK_FLL_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
-#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ 50UL
-#define CY_CFG_SYSCLK_CLKHF2_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
-#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 48UL
-#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH1
-#define CY_CFG_SYSCLK_ILO_ENABLED 1
-#define CY_CFG_SYSCLK_IMO_ENABLED 1
-#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
-#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
-#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
-#define CY_CFG_SYSCLK_PLL0_ENABLED 1
-#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
-#define CY_CFG_SYSCLK_WCO_ENABLED 1
-#define CY_CFG_PWR_ENABLED 1
-#define CY_CFG_PWR_INIT 1
-#define CY_CFG_PWR_USING_PMIC 0
-#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
-#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
-#define CY_CFG_PWR_USING_ULP 0
-
-static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
-{
-	.fllMult = 500U,
-	.refDiv = 20U,
-	.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
-	.enableOutputDiv = true,
-	.lockTolerance = 10U,
-	.igain = 9U,
-	.pgain = 5U,
-	.settlingCount = 8U,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
-	.cco_Freq = 355U,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 0U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 1U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 2U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 3U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
-	{
-		.type = CYHAL_RSC_CLKPATH,
-		.block_num = 4U,
-		.channel_num = 0U,
-	};
-#endif //defined (CY_USING_HAL)
-static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
-{
-	.feedbackDiv = 30,
-	.referenceDiv = 1,
-	.outputDiv = 5,
-	.lfMode = false,
-	.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
-};
-
-__WEAK void cycfg_ClockStartupError(uint32_t error)
-{
-    (void)error; /* Suppress the compiler warning */
-    while(1);
-}
-__STATIC_INLINE void Cy_SysClk_ClkBakInit()
-{
-    Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_WCO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkFastInit()
-{
-    Cy_SysClk_ClkFastSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_FllInit()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf0Init()
-{
-    Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf2Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF2, CY_CFG_SYSCLK_CLKHF2_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF2, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF2);
-}
-__STATIC_INLINE void Cy_SysClk_ClkHf3Init()
-{
-    Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
-    Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
-    Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
-}
-__STATIC_INLINE void Cy_SysClk_IloInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_IloEnable();
-    Cy_SysClk_IloHibernateOn(true);
-}
-__STATIC_INLINE void Cy_SysClk_ClkLfInit()
-{
-    /* The WDT is unlocked in the default startup code */
-    Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath0Init()
-{
-    Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath1Init()
-{
-    Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath2Init()
-{
-    Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath3Init()
-{
-    Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPath4Init()
-{
-    Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
-}
-__STATIC_INLINE void Cy_SysClk_ClkPeriInit()
-{
-    Cy_SysClk_ClkPeriSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_Pll0Init()
-{
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
-    }
-}
-__STATIC_INLINE void Cy_SysClk_ClkSlowInit()
-{
-    Cy_SysClk_ClkSlowSetDivider(0U);
-}
-__STATIC_INLINE void Cy_SysClk_WcoInit()
-{
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
-    if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
-    {
-        cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
-    }
-}
-__STATIC_INLINE void init_cycfg_power(void)
-{
-     /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
-     #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
-     #ifdef CY_CFG_SYSCLK_ILO_ENABLED
-     if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
-     {
-         Cy_SysLib_ResetBackupDomain();
-         Cy_SysClk_IloDisable();
-         Cy_SysClk_IloInit();
-     }
-     #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
-     #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
-
-     /* Configure core regulator */
-     #if CY_CFG_PWR_USING_LDO
-     Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
-     Cy_SysPm_LdoSetMode(CY_SYSPM_LDO_MODE_NORMAL);
-     #else
-     Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
-     #endif /* CY_CFG_PWR_USING_LDO */
-     /* Configure PMIC */
-     Cy_SysPm_UnlockPmic();
-     #if CY_CFG_PWR_USING_PMIC
-     Cy_SysPm_PmicEnableOutput();
-     #else
-     Cy_SysPm_PmicDisableOutput();
-     #endif /* CY_CFG_PWR_USING_PMIC */
-}
-
-
-void init_cycfg_system(void)
-{
-	/* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
-	Cy_SysLib_SetWaitStates(false, 150UL);
-	#ifdef CY_CFG_PWR_ENABLED
-	    #ifdef CY_CFG_PWR_INIT
-	    init_cycfg_power();
-	    #else
-	    #warning Power system will not be configured. Update power personality to v1.20 or later.
-	    #endif /* CY_CFG_PWR_INIT */
-	#endif /* CY_CFG_PWR_ENABLED */
-
-	/* Reset the core clock path to default and disable all the FLLs/PLLs */
-	Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
-	Cy_SysClk_ClkFastSetDivider(0U);
-	Cy_SysClk_ClkPeriSetDivider(1U);
-	Cy_SysClk_ClkSlowSetDivider(0U);
-	for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
-	{
-	    (void)Cy_SysClk_PllDisable(pll);
-	}
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
-
-	if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
-	    (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
-	{
-	    Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	}
-
-	Cy_SysClk_FllDisable();
-	Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
-	Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
-	#ifdef CY_IP_MXBLESS
-	(void)Cy_BLE_EcoReset();
-	#endif
-
-
-	/* Enable all source clocks */
-	#ifdef CY_CFG_SYSCLK_PILO_ENABLED
-	Cy_SysClk_PiloInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_WCO_ENABLED
-	Cy_SysClk_WcoInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
-	Cy_SysClk_ClkLfInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
-	Cy_SysClk_AltHfInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_ECO_ENABLED
-	Cy_SysClk_EcoInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
-	Cy_SysClk_ExtClkInit();
-	#endif
-
-	/* Configure CPU clock dividers */
-	#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
-	Cy_SysClk_ClkFastInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
-	Cy_SysClk_ClkPeriInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
-	Cy_SysClk_ClkSlowInit();
-	#endif
-
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
-	    Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
-	    Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
-	#else
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-
-	/* Configure Path Clocks */
-	#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
-	Cy_SysClk_ClkPath0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
-	Cy_SysClk_ClkPath2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
-	Cy_SysClk_ClkPath3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
-	Cy_SysClk_ClkPath4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
-	Cy_SysClk_ClkPath5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
-	Cy_SysClk_ClkPath6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
-	Cy_SysClk_ClkPath7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
-	Cy_SysClk_ClkPath8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
-	Cy_SysClk_ClkPath9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
-	Cy_SysClk_ClkPath10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
-	Cy_SysClk_ClkPath11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
-	Cy_SysClk_ClkPath12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
-	Cy_SysClk_ClkPath13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
-	Cy_SysClk_ClkPath14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
-	Cy_SysClk_ClkPath15Init();
-	#endif
-
-	/* Configure and enable FLL */
-	#ifdef CY_CFG_SYSCLK_FLL_ENABLED
-	Cy_SysClk_FllInit();
-	#endif
-
-	Cy_SysClk_ClkHf0Init();
-
-	#if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE == CY_SYSCLK_CLKPATH_IN_WCO) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH == CY_SYSCLK_CLKHF_IN_CLKPATH0))
-	    #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
-	        /* Apply the ClkPath1 user setting */
-	        Cy_SysClk_ClkPath1Init();
-	    #endif
-	#endif
-
-	/* Configure and enable PLLs */
-	#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
-	Cy_SysClk_Pll0Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
-	Cy_SysClk_Pll1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
-	Cy_SysClk_Pll2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
-	Cy_SysClk_Pll3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
-	Cy_SysClk_Pll4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
-	Cy_SysClk_Pll5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
-	Cy_SysClk_Pll6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
-	Cy_SysClk_Pll7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
-	Cy_SysClk_Pll8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
-	Cy_SysClk_Pll9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
-	Cy_SysClk_Pll10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
-	Cy_SysClk_Pll11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
-	Cy_SysClk_Pll12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
-	Cy_SysClk_Pll13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
-	Cy_SysClk_Pll14Init();
-	#endif
-
-	/* Configure HF clocks */
-	#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
-	Cy_SysClk_ClkHf1Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
-	Cy_SysClk_ClkHf2Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
-	Cy_SysClk_ClkHf3Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
-	Cy_SysClk_ClkHf4Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
-	Cy_SysClk_ClkHf5Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
-	Cy_SysClk_ClkHf6Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
-	Cy_SysClk_ClkHf7Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
-	Cy_SysClk_ClkHf8Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
-	Cy_SysClk_ClkHf9Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
-	Cy_SysClk_ClkHf10Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
-	Cy_SysClk_ClkHf11Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
-	Cy_SysClk_ClkHf12Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
-	Cy_SysClk_ClkHf13Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
-	Cy_SysClk_ClkHf14Init();
-	#endif
-	#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
-	Cy_SysClk_ClkHf15Init();
-	#endif
-
-	/* Configure miscellaneous clocks */
-	#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
-	Cy_SysClk_ClkTimerInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
-	Cy_SysClk_ClkAltSysTickInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
-	Cy_SysClk_ClkPumpInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
-	Cy_SysClk_ClkBakInit();
-	#endif
-
-	/* Configure default enabled clocks */
-	#ifdef CY_CFG_SYSCLK_ILO_ENABLED
-	Cy_SysClk_IloInit();
-	#else
-	Cy_SysClk_IloDisable();
-	Cy_SysClk_IloHibernateOn(false);
-	#endif
-
-	#ifndef CY_CFG_SYSCLK_IMO_ENABLED
-	#error the IMO must be enabled for proper chip operation
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_MFO_ENABLED
-	Cy_SysClk_MfoInit();
-	#endif
-
-	#ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
-	Cy_SysClk_ClkMfInit();
-	#endif
-
-	/* Set accurate flash wait states */
-	#if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
-	Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
-	#endif
-
-	/* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
-	SystemCoreClockUpdate();
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
-#endif //defined (CY_USING_HAL)
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -1,106 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_system.h
-*
-* Description:
-* System configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (libs/psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_SYSTEM_H)
-#define CYCFG_SYSTEM_H
-
-#include "cycfg_notices.h"
-#include "cy_sysclk.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-#include "cy_gpio.h"
-#include "cy_syspm.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define cpuss_0_dap_0_ENABLED 1U
-#define srss_0_clock_0_ENABLED 1U
-#define srss_0_clock_0_bakclk_0_ENABLED 1U
-#define srss_0_clock_0_fastclk_0_ENABLED 1U
-#define srss_0_clock_0_fll_0_ENABLED 1U
-#define srss_0_clock_0_hfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF0 0UL
-#define srss_0_clock_0_hfclk_2_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF2 2UL
-#define srss_0_clock_0_hfclk_3_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKHF3 3UL
-#define srss_0_clock_0_ilo_0_ENABLED 1U
-#define srss_0_clock_0_imo_0_ENABLED 1U
-#define srss_0_clock_0_lfclk_0_ENABLED 1U
-#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
-#define srss_0_clock_0_pathmux_0_ENABLED 1U
-#define srss_0_clock_0_pathmux_1_ENABLED 1U
-#define srss_0_clock_0_pathmux_2_ENABLED 1U
-#define srss_0_clock_0_pathmux_3_ENABLED 1U
-#define srss_0_clock_0_pathmux_4_ENABLED 1U
-#define srss_0_clock_0_periclk_0_ENABLED 1U
-#define srss_0_clock_0_pll_0_ENABLED 1U
-#define srss_0_clock_0_slowclk_0_ENABLED 1U
-#define srss_0_clock_0_wco_0_ENABLED 1U
-#define srss_0_power_0_ENABLED 1U
-#define CY_CFG_PWR_MODE_LP 0x01UL
-#define CY_CFG_PWR_MODE_ULP 0x02UL
-#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
-#define CY_CFG_PWR_MODE_SLEEP 0x08UL
-#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
-#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
-#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
-#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
-#define CY_CFG_PWR_USING_LDO 1
-#define CY_CFG_PWR_VDDA_MV 3300
-#define CY_CFG_PWR_VDDD_MV 3300
-#define CY_CFG_PWR_VBACKUP_MV 3300
-#define CY_CFG_PWR_VDD_NS_MV 3300
-#define CY_CFG_PWR_VDDIO0_MV 3300
-#define CY_CFG_PWR_VDDIO1_MV 3300
-
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_system(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_SYSTEM_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -1,3 +0,0 @@
-set SMIF_BANKS {
-  0 {addr 0x18000000 size 0x1000000 psize 0x0000200 esize 0x0001000}
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -1,4 +0,0 @@
-[Device=CYB06447BZI-D54]
- 
-[Blocks]
-# Nothing needs to be reserved for this board

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -1,63 +0,0 @@
-<?xml version="1.0"?>
-<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.0.0.1483-->
-<Configuration app="QSPI" major="2" minor="0">
-    <DevicePath>PSoC 6.xml</DevicePath>
-    <SlotConfigs>
-        <SlotConfig>
-            <SlaveSlot>0</SlaveSlot>
-            <PartNumber>S25FL128S</PartNumber>
-            <MemoryMapped>true</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18000000</StartAddress>
-            <Size>0x1000000</Size>
-            <EndAddress>0x18FFFFFF</EndAddress>
-            <WriteEnable>true</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
-            <MemoryConfigsPath>S25FL128S</MemoryConfigsPath>
-            <ConfigDataInFlash>true</ConfigDataInFlash>
-        </SlotConfig>
-        <SlotConfig>
-            <SlaveSlot>1</SlaveSlot>
-            <PartNumber>Not used</PartNumber>
-            <MemoryMapped>false</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18010000</StartAddress>
-            <Size>0x10000</Size>
-            <EndAddress>0x1801FFFF</EndAddress>
-            <WriteEnable>false</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
-            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
-            <ConfigDataInFlash>false</ConfigDataInFlash>
-        </SlotConfig>
-        <SlotConfig>
-            <SlaveSlot>2</SlaveSlot>
-            <PartNumber>Not used</PartNumber>
-            <MemoryMapped>false</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18020000</StartAddress>
-            <Size>0x10000</Size>
-            <EndAddress>0x1802FFFF</EndAddress>
-            <WriteEnable>false</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
-            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
-            <ConfigDataInFlash>false</ConfigDataInFlash>
-        </SlotConfig>
-        <SlotConfig>
-            <SlaveSlot>3</SlaveSlot>
-            <PartNumber>Not used</PartNumber>
-            <MemoryMapped>false</MemoryMapped>
-            <DualQuad>None</DualQuad>
-            <StartAddress>0x18030000</StartAddress>
-            <Size>0x10000</Size>
-            <EndAddress>0x1803FFFF</EndAddress>
-            <WriteEnable>false</WriteEnable>
-            <Encrypt>false</Encrypt>
-            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
-            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
-            <ConfigDataInFlash>false</ConfigDataInFlash>
-        </SlotConfig>
-    </SlotConfigs>
-</Configuration>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -1,253 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<Design version="12" device_library_hint_path="../../psoc6pdl/devicesupport.xml" xmlns="http://cypress.com/xsd/cydesignfile_v3">
-    <ToolInfo version="1.0.0"/>
-    <Devices>
-        <Device mpn="CYB06447BZI-D54">
-            <BlockConfig>
-                <Block location="cpuss[0].dap[0]">
-                    <Personality template="mxs40dap" version="1.0">
-                        <Param id="dbgMode" value="SWD"/>
-                        <Param id="traceEnable" value="false"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[0].pin[0]">
-                    <Alias value="CYBSP_WCO_IN"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[0].pin[1]">
-                    <Alias value="CYBSP_WCO_OUT"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[12].pin[6]">
-                    <Alias value="CYBSP_ECO_IN"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[12].pin[7]">
-                    <Alias value="CYBSP_ECO_OUT"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[6].pin[4]">
-                    <Alias value="CYBSP_SWO"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[6].pin[6]">
-                    <Alias value="CYBSP_SWDIO"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="ioss[0].port[6].pin[7]">
-                    <Alias value="CYBSP_SWCLK"/>
-                    <Personality template="mxs40pin" version="1.1">
-                        <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0]">
-                    <Personality template="mxs40sysclocks" version="1.2"/>
-                </Block>
-                <Block location="srss[0].clock[0].bakclk[0]">
-                    <Personality template="mxs40bakclk" version="1.0">
-                        <Param id="sourceClock" value="wco"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].fastclk[0]">
-                    <Personality template="mxs40fastclk" version="1.0">
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].fll[0]">
-                    <Personality template="mxs40fll" version="1.0">
-                        <Param id="configuration" value="auto"/>
-                        <Param id="desiredFrequency" value="100.000"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[0]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="0"/>
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[2]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="0"/>
-                        <Param id="divider" value="2"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].hfclk[3]">
-                    <Personality template="mxs40hfclk" version="1.1">
-                        <Param id="sourceClockNumber" value="1"/>
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].ilo[0]">
-                    <Personality template="mxs40ilo" version="1.0">
-                        <Param id="hibernate" value="true"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].imo[0]">
-                    <Personality template="mxs40imo" version="1.0">
-                        <Param id="trim" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].lfclk[0]">
-                    <Personality template="mxs40lfclk" version="1.1">
-                        <Param id="sourceClock" value="wco"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[0]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[1]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[2]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[3]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pathmux[4]">
-                    <Personality template="mxs40pathmux" version="1.0">
-                        <Param id="sourceClock" value="imo"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].periclk[0]">
-                    <Personality template="mxs40periclk" version="1.0">
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].pll[0]">
-                    <Personality template="mxs40pll" version="1.0">
-                        <Param id="lowFrequencyMode" value="false"/>
-                        <Param id="configuration" value="auto"/>
-                        <Param id="desiredFrequency" value="48.000"/>
-                        <Param id="optimization" value="MinPower"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].slowclk[0]">
-                    <Personality template="mxs40slowclk" version="1.0">
-                        <Param id="divider" value="1"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].clock[0].wco[0]">
-                    <Personality template="mxs40wco" version="1.0">
-                        <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
-                        <Param id="clockLostDetection" value="false"/>
-                        <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
-                        <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
-                        <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
-                        <Param id="accuracyPpm" value="150"/>
-                    </Personality>
-                </Block>
-                <Block location="srss[0].power[0]">
-                    <Personality template="mxs40power" version="1.2">
-                        <Param id="pwrMode" value="LDO_1_1"/>
-                        <Param id="actPwrMode" value="LP"/>
-                        <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
-                        <Param id="pmicEnable" value="false"/>
-                        <Param id="backupSrc" value="VDDD"/>
-                        <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
-                        <Param id="deepsleepLatency" value="0"/>
-                        <Param id="vddaMv" value="3300"/>
-                        <Param id="vdddMv" value="3300"/>
-                        <Param id="vBackupMv" value="3300"/>
-                        <Param id="vddNsMv" value="3300"/>
-                        <Param id="vddio0Mv" value="3300"/>
-                        <Param id="vddio1Mv" value="3300"/>
-                    </Personality>
-                </Block>
-            </BlockConfig>
-            <Netlist>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
-                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
-                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
-                </Net>
-                <Net>
-                    <Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
-                    <Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
-                </Net>
-                <Net>
-                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
-                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
-                </Net>
-            </Netlist>
-        </Device>
-    </Devices>
-    <Libraries/>
-    <ConfiguratorData/>
-</Design>

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/PeripheralPins.c

@@ -1,474 +0,0 @@
-/*
- * mbed Microcontroller Library
- * Copyright (c) 2017-2018 Future Electronics
- * Copyright (c) 2019 Cypress Semiconductor Corporation
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "PeripheralNames.h"
-#include "PeripheralPins.h"
-#include "pinmap.h"
-
-#if DEVICE_SERIAL
-//*** SERIAL ***
-const PinMap PinMap_UART_RX[] = {
-    {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)},
-    {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)},
-    {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)},
-    {P3_0, UART_2, CYHAL_PIN_IN_FUNCTION(P3_0_SCB2_UART_RX)},
-    {P4_0, UART_7, CYHAL_PIN_IN_FUNCTION(P4_0_SCB7_UART_RX)},
-    {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)},
-    {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)},
-    {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)},
-    {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)},
-    {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)},
-    {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)},
-    {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)},
-    {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)},
-    {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)},
-    {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)},
-    {NC,    NC,     0}
-};
-const PinMap PinMap_UART_TX[] = {
-    {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)},
-    {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)},
-    {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)},
-    {P3_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_1_SCB2_UART_TX)},
-    {P4_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P4_1_SCB7_UART_TX)},
-    {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)},
-    {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)},
-    {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)},
-    {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)},
-    {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)},
-    {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)},
-    {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)},
-    {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)},
-    {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)},
-    {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)},
-    {NC,    NC,     0}
-};
-const PinMap PinMap_UART_RTS[] = {
-    {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)},
-    {P1_2, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_UART_RTS)},
-    {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)},
-    {P3_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_UART_RTS)},
-    {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)},
-    {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)},
-    {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)},
-    {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)},
-    {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)},
-    {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)},
-    {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)},
-    {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)},
-    {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)},
-    {NC,    NC,     0}
-};
-const PinMap PinMap_UART_CTS[] = {
-    {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)},
-    {P1_3, UART_7, CYHAL_PIN_IN_FUNCTION(P1_3_SCB7_UART_CTS)},
-    {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)},
-    {P3_3, UART_2, CYHAL_PIN_IN_FUNCTION(P3_3_SCB2_UART_CTS)},
-    {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)},
-    {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)},
-    {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)},
-    {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)},
-    {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)},
-    {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)},
-    {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)},
-    {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)},
-    {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)},
-    {NC,    NC,     0}
-};
-#endif // DEVICE_SERIAL
-
-
-#if DEVICE_I2C
-//*** I2C ***
-const PinMap PinMap_I2C_SCL[] = {
-    {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)},
-    {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)},
-    {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)},
-    {P3_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_0_SCB2_I2C_SCL)},
-    {P4_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_0_SCB7_I2C_SCL)},
-    {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)},
-    {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)},
-    {P6_0, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_0_SCB8_I2C_SCL)},
-    {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)},
-    {P6_4, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_4_SCB8_I2C_SCL)},
-    {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)},
-    {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)},
-    {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)},
-    {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)},
-    {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)},
-    {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)},
-    {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)},
-    {NC,    NC,    0}
-};
-const PinMap PinMap_I2C_SDA[] = {
-    {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)},
-    {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)},
-    {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)},
-    {P3_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P3_1_SCB2_I2C_SDA)},
-    {P4_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P4_1_SCB7_I2C_SDA)},
-    {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)},
-    {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)},
-    {P6_1, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_1_SCB8_I2C_SDA)},
-    {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)},
-    {P6_5, I2C_8, CYHAL_PIN_OD_FUNCTION(P6_5_SCB8_I2C_SDA)},
-    {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)},
-    {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)},
-    {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)},
-    {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)},
-    {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)},
-    {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)},
-    {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)},
-    {NC,    NC,    0}
-};
-#endif // DEVICE_I2C
-
-#if DEVICE_SPI
-//*** SPI ***
-const PinMap PinMap_SPI_MOSI[] = {
-    {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)},
-    {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)},
-    {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)},
-    {P3_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_0_SCB2_SPI_MOSI)},
-    {P4_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P4_0_SCB7_SPI_MOSI)},
-    {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)},
-    {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)},
-    {P6_0, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB8_SPI_MOSI)},
-    {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)},
-    {P6_4, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB8_SPI_MOSI)},
-    {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)},
-    {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)},
-    {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)},
-    {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)},
-    {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)},
-    {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)},
-    {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)},
-    {NC,    NC,    0}
-};
-const PinMap PinMap_SPI_MISO[] = {
-    {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)},
-    {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)},
-    {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)},
-    {P3_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P3_1_SCB2_SPI_MISO)},
-    {P4_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P4_1_SCB7_SPI_MISO)},
-    {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)},
-    {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)},
-    {P6_1, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_1_SCB8_SPI_MISO)},
-    {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)},
-    {P6_5, SPI_8, CYHAL_PIN_IN_FUNCTION(P6_5_SCB8_SPI_MISO)},
-    {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)},
-    {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)},
-    {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)},
-    {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)},
-    {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)},
-    {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)},
-    {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)},
-    {NC,    NC,    0}
-};
-const PinMap PinMap_SPI_SCLK[] = {
-    {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)},
-    {P1_2, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_2_SCB7_SPI_CLK)},
-    {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)},
-    {P3_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_2_SCB2_SPI_CLK)},
-    {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)},
-    {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)},
-    {P6_2, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB8_SPI_CLK)},
-    {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)},
-    {P6_6, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB8_SPI_CLK)},
-    {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)},
-    {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)},
-    {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)},
-    {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)},
-    {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)},
-    {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)},
-    {NC,    NC,    0}
-};
-const PinMap PinMap_SPI_SSEL[] = {
-    {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)},
-    {P1_3, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_3_SCB7_SPI_SELECT0)},
-    {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)},
-    {P3_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P3_3_SCB2_SPI_SELECT0)},
-    {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)},
-    {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)},
-    {P6_3, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB8_SPI_SELECT0)},
-    {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)},
-    {P6_7, SPI_8, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB8_SPI_SELECT0)},
-    {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)},
-    {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)},
-    {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)},
-    {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)},
-    {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)},
-    {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)},
-    {NC,    NC,    0}
-};
-#endif // DEVICE_SPI
-
-#if DEVICE_PWMOUT
-//*** PWM ***
-const PinMap PinMap_PWM_OUT[] = {
-    // 16-bit PWM outputs
-    {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)},
-    {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)},
-    {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)},
-    {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)},
-    {P1_2, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM1_LINE12)},
-    {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)},
-    {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)},
-    {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)},
-    {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)},
-    {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)},
-    {P3_0, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM1_LINE19)},
-    {P3_2, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM1_LINE20)},
-    {P3_4, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM1_LINE21)},
-    {P4_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM1_LINE22)},
-    {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)},
-    {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)},
-    {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)},
-    {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)},
-    {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)},
-    {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)},
-    {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)},
-    {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)},
-    {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)},
-    {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)},
-    {P7_4, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM1_LINE14)},
-    {P7_6, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM1_LINE15)},
-    {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)},
-    {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)},
-    {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)},
-    {P8_6, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM1_LINE19)},
-    {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)},
-    {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)},
-    {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)},
-    {P9_6, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM1_LINE1)},
-    {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)},
-    {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)},
-    {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)},
-    {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)},
-    {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)},
-    {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)},
-    {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)},
-    {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)},
-    {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)},
-    {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)},
-    {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)},
-    {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)},
-    {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)},
-    {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)},
-    {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)},
-    // 16-bit PWM inverted outputs
-    {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)},
-    {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)},
-    {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)},
-    {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)},
-    {P1_3, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM1_LINE_COMPL12)},
-    {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)},
-    {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)},
-    {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)},
-    {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)},
-    {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)},
-    {P3_1, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM1_LINE_COMPL19)},
-    {P3_3, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM1_LINE_COMPL20)},
-    {P3_5, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM1_LINE_COMPL21)},
-    {P4_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM1_LINE_COMPL22)},
-    {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)},
-    {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)},
-    {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)},
-    {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)},
-    {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)},
-    {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)},
-    {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)},
-    {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)},
-    {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)},
-    {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)},
-    {P7_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM1_LINE_COMPL14)},
-    {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)},
-    {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)},
-    {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)},
-    {P8_5, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM1_LINE_COMPL18)},
-    {P8_7, PWM_16b_19, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM1_LINE_COMPL19)},
-    {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)},
-    {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)},
-    {P9_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM1_LINE_COMPL0)},
-    {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)},
-    {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)},
-    {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)},
-    {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)},
-    {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)},
-    {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)},
-    {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)},
-    {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)},
-    {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)},
-    {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)},
-    {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)},
-    {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)},
-    {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)},
-    {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)},
-    {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)},
-    {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)},
-    // 32-bit PWM outputs
-    {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)},
-    {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)},
-    {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)},
-    {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)},
-    {P1_2, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_2_TCPWM0_LINE4)},
-    {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)},
-    {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)},
-    {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)},
-    {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)},
-    {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)},
-    {P3_0, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_0_TCPWM0_LINE2)},
-    {P3_2, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_2_TCPWM0_LINE3)},
-    {P3_4, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_4_TCPWM0_LINE4)},
-    {P4_0, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_0_TCPWM0_LINE5)},
-    {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)},
-    {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)},
-    {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)},
-    {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)},
-    {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)},
-    {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)},
-    {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)},
-    {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)},
-    {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)},
-    {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)},
-    {P7_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_4_TCPWM0_LINE6)},
-    {P7_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_6_TCPWM0_LINE7)},
-    {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)},
-    {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)},
-    {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)},
-    {P8_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_6_TCPWM0_LINE3)},
-    {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)},
-    {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)},
-    {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)},
-    {P9_6, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_6_TCPWM0_LINE0)},
-    {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)},
-    {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)},
-    {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)},
-    {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)},
-    {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)},
-    {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)},
-    {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)},
-    {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)},
-    {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)},
-    {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)},
-    {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)},
-    {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)},
-    {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)},
-    {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)},
-    {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)},
-    // 32-bit PWM inverted outputs
-    {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)},
-    {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)},
-    {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)},
-    {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)},
-    {P1_3, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P1_3_TCPWM0_LINE_COMPL4)},
-    {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)},
-    {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)},
-    {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)},
-    {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)},
-    {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)},
-    {P3_1, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P3_1_TCPWM0_LINE_COMPL2)},
-    {P3_3, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P3_3_TCPWM0_LINE_COMPL3)},
-    {P3_5, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P3_5_TCPWM0_LINE_COMPL4)},
-    {P4_1, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P4_1_TCPWM0_LINE_COMPL5)},
-    {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)},
-    {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)},
-    {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)},
-    {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)},
-    {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)},
-    {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)},
-    {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)},
-    {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)},
-    {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)},
-    {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)},
-    {P7_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P7_5_TCPWM0_LINE_COMPL6)},
-    {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)},
-    {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)},
-    {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)},
-    {P8_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_5_TCPWM0_LINE_COMPL2)},
-    {P8_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P8_7_TCPWM0_LINE_COMPL3)},
-    {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)},
-    {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)},
-    {P9_5, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_5_TCPWM0_LINE_COMPL7)},
-    {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)},
-    {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)},
-    {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)},
-    {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)},
-    {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)},
-    {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)},
-    {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)},
-    {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)},
-    {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)},
-    {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)},
-    {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)},
-    {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)},
-    {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)},
-    {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)},
-    {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)},
-    {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)},
-    {NC,    NC,     0}
-};
-#endif // DEVICE_PWMOUT
-
-#if DEVICE_ANALOGIN
-const PinMap PinMap_ADC[] = {
-    {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {NC,    NC,     0}
-};
-#endif // DEVICE_ANALOGIN
-
-#if DEVICE_ANALOGOUT
-const PinMap PinMap_DAC[] = {
-    {P9_6,  DAC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)},
-    {NC,    NC,     0}
-};
-#endif // DEVICE_ANALOGIN
-
-#if DEVICE_QSPI
-const PinMap PinMap_QSPI_SCLK[] = {
-    {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)},
-    {NC, NC, 0},
-};
-const PinMap PinMap_QSPI_SSEL[] = {
-    {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)},
-    {NC, NC, 0},
-};
-const PinMap PinMap_QSPI_DATA0[] = {
-    {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)},
-    {NC, NC, 0},
-};
-const PinMap PinMap_QSPI_DATA1[] = {
-    {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)},
-    {NC, NC, 0},
-};
-const PinMap PinMap_QSPI_DATA2[] = {
-    {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)},
-    {NC, NC, 0},
-};
-const PinMap PinMap_QSPI_DATA3[] = {
-    {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)},
-    {NC, NC, 0},
-};
-#endif // DEVICE_QSPI

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.c

@@ -1,134 +0,0 @@
-/***************************************************************************//**
-* \file cybsp.c
-*
-* Description:
-* Provides initialization code for starting up the hardware contained on the
-* Cypress board.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdlib.h>
-#include "cy_syspm.h"
-#include "cy_sysclk.h"
-#include "cybsp.h"
-#if defined(CY_USING_HAL)
-#include "cyhal_hwmgr.h"
-#include "cyhal_syspm.h"
-#endif
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/* The sysclk deep sleep callback is recommended to be the last callback that
-* is executed before entry into deep sleep mode and the first one upon
-* exit the deep sleep mode.
-* Doing so minimizes the time spent on low power mode entry and exit.
-*/
-#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER
-    #define CYBSP_SYSCLK_PM_CALLBACK_ORDER  (255u)
-#endif
-
-#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
-static cyhal_sdio_t sdio_obj;
-
-cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void)
-{
-    return &sdio_obj;
-}
-#endif
-
-/**
- * Registers a power management callback that prepares the clock system
- * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep.
- * NOTE: This is called automatically as part of \ref cybsp_init
- */
-static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
-{
-    cy_rslt_t result = CY_RSLT_SUCCESS;
-    static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL};
-    static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = {
-        .callback = &Cy_SysClk_DeepSleepCallback,
-        .type = CY_SYSPM_DEEPSLEEP,
-        .callbackParams = &cybsp_sysclk_pm_callback_param,
-        .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER
-    };
-
-    if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback))
-    {
-        result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK;
-    }
-    return result;
-}
-
-cy_rslt_t cybsp_init(void)
-{
-    /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */
-#if defined(CY_USING_HAL)
-    cy_rslt_t result = cyhal_hwmgr_init();
-
-    if (CY_RSLT_SUCCESS == result)
-    {
-        result = cyhal_syspm_init();
-    }
-#else
-    cy_rslt_t result = CY_RSLT_SUCCESS;
-#endif
-
-#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
-    init_cycfg_all();
-#endif
-
-    if (CY_RSLT_SUCCESS == result)
-    {
-        result = cybsp_register_sysclk_pm_callback();
-    }
-
-#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
-    /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require
-     * specific peripheral instances.
-     * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically
-     * done when starting up WiFi.
-     */
-    if (CY_RSLT_SUCCESS == result)
-    {
-        /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3
-         * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK.
-         */
-        result = cyhal_sdio_init(
-                &sdio_obj,
-                CYBSP_WIFI_SDIO_CMD,
-                CYBSP_WIFI_SDIO_CLK,
-                CYBSP_WIFI_SDIO_D0,
-                CYBSP_WIFI_SDIO_D1,
-                CYBSP_WIFI_SDIO_D2,
-                CYBSP_WIFI_SDIO_D3);
-    }
-#endif /* defined(CYBSP_WIFI_CAPABLE) */
-
-    /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by
-     * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list
-     * (cyreservedresources.list) to make sure no resources are reserved by both.
-     */
-    return result;
-}
-
-#if defined(__cplusplus)
-}
-#endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp.h

@@ -1,73 +0,0 @@
-/***************************************************************************//**
-* \file cybsp.h
-*
-* \brief
-* Basic API for setting up boards containing a Cypress MCU.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#pragma once
-
-#include "cy_result.h"
-#include "cybsp_types.h"
-#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
-#include "cyhal_sdio.h"
-#endif
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/**
-* \addtogroup group_bsp_macros Macros
-* \{
-*/
-
-/** Failed to configure sysclk power management callback */
-#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK  (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
-
-/** \} group_bsp_macros */
-
-/**
-* \addtogroup group_bsp_functions Functions
-* \{
-*/
-
-/**
- * \brief Initialize all hardware on the board
- * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is
- *          a problem initializing any hardware it returns an error code specific
- *          to the hardware module that had a problem.
- */
-cy_rslt_t cybsp_init(void);
-
-#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL)
-/**
- * \brief Get the initialized sdio object used for communicating with the WiFi Chip.
- * \note This function should only be called after cybsp_init();
- * \returns The initialized sdio object.
- */
-cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void);
-#endif /* defined(CYBSP_WIFI_CAPABLE) */
-
-/** \} group_bsp_functions */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/cybsp_types.h

@@ -1,227 +0,0 @@
-/***************************************************************************//**
-* \file CY8CPROTO-064-SB/cybsp_types.h
-*
-* Description:
-* Provides APIs for interacting with the hardware contained on the Cypress
-* CY8CPROTO-064-SB kit.
-*
-********************************************************************************
-* \copyright
-* Copyright 2018-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#pragma once
-
-#if defined(CY_USING_HAL)
-#include "cyhal_pin_package.h"
-#endif
-#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS)
-#include "cycfg.h"
-#endif
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/**
-* \addtogroup group_bsp_settings BSP Settings
-* \{
-*
-* <div class="category">Peripheral Default HAL Settings:</div>
-* | Resource | Parameter | Value | Remarks |
-* | :------: | :-------: | :---: | :------ |
-* | ADC      | VREF      | 1.2 V | |
-* | ^        | Measurement type | Single Ended | |
-* | ^        | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | |
-* | ^        | Output range | 0x000 to 0x7FF | |
-* | DAC      | Reference source | VDDA | |
-* | ^        | Input range | 0x000 to 0xFFF | |
-* | ^        | Output range | 0 to VDDA | |
-* | ^        | Output type | Unbuffered output | |
-* | I2C      | Role | Master | Configurable to slave mode through HAL function |
-* | ^        | Data rate | 100 kbps | Configurable through HAL function |
-* | ^        | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required |
-* | LpTimer  | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. |||
-* | SPI      | Data rate | 100 kpbs | Configurable through HAL function |
-* | ^        | Slave select polarity | Active low | |
-* | UART     | Flow control | No flow control | Configurable through HAL function |
-* | ^        | Data format | 8N1 | Configurable through HAL function |
-* | ^        | Baud rate | 115200 | Configurable through HAL function |
-*/
-/** \} group_bsp_settings */
-
-/**
-* \addtogroup group_bsp_pin_state Pin States
-* \{
-*/
-
-/** Pin state for the LED on. */
-#ifndef CYBSP_LED_STATE_ON
-#define CYBSP_LED_STATE_ON          (0U)
-#endif
-/** Pin state for the LED off. */
-#ifndef CYBSP_LED_STATE_OFF
-#define CYBSP_LED_STATE_OFF         (1U)
-#endif
-
-/** Pin state for when a button is pressed. */
-#ifndef CYBSP_BTN_PRESSED
-#define CYBSP_BTN_PRESSED           (0U)
-#endif
-/** Pin state for when a button is released. */
-#ifndef CYBSP_BTN_OFF
-#define CYBSP_BTN_OFF               (1U)
-#endif
-
-/** \} group_bsp_pin_state */
-
-#if defined(CY_USING_HAL)
-
-/**
-* \addtogroup group_bsp_pins Pin Mappings
-* \{
-*/
-
-/**
-* \addtogroup group_bsp_pins_led LED Pins
-* \{
-*/
-
-/** LED 3; User LED1 */
-#ifndef CYBSP_LED3
-#define CYBSP_LED3                  (P13_7)
-#endif
-/** LED 4; User LED2 */
-#ifndef CYBSP_LED4
-#define CYBSP_LED4                  (P1_5)
-#endif
-
-/** LED 3; User LED1 */
-#ifndef CYBSP_USER_LED1
-#define CYBSP_USER_LED1             (CYBSP_LED3)
-#endif
-/** LED 4; User LED2 */
-#ifndef CYBSP_USER_LED2
-#define CYBSP_USER_LED2             (CYBSP_LED4)
-#endif
-/** LED 3; User LED1 */
-#ifndef CYBSP_USER_LED
-#define CYBSP_USER_LED              (CYBSP_USER_LED1)
-#endif
-
-/** \} group_bsp_pins_led */
-
-/**
-* \addtogroup group_bsp_pins_btn Button Pins
-* \{
-*/
-
-/** Switch 2; User Button 1 */
-#ifndef CYBSP_SW2
-#define CYBSP_SW2                   (P0_4)
-#endif
-
-/** Switch 2; User Button 1 */
-#ifndef CYBSP_USER_BTN1
-#define CYBSP_USER_BTN1             (CYBSP_SW2)
-#endif
-/** Switch 2; User Button 1 */
-#ifndef CYBSP_USER_BTN
-#define CYBSP_USER_BTN              (CYBSP_USER_BTN1)
-#endif
-
-/** \} group_bsp_pins_btn */
-
-
-/**
-* \addtogroup group_bsp_pins_comm Communication Pins
-* \{
-*/
-
-/** Pin: UART RX */
-#ifndef CYBSP_UART_RX
-#define CYBSP_UART_RX               (P5_0)
-#endif
-/** Pin: UART TX */
-#ifndef CYBSP_UART_TX
-#define CYBSP_UART_TX               (P5_1)
-#endif
-
-/** Pin: UART RX */
-#ifndef CYBSP_DEBUG_UART_RX
-#define CYBSP_DEBUG_UART_RX         (P5_0)
-#endif
-/** Pin: UART TX */
-#ifndef CYBSP_DEBUG_UART_TX
-#define CYBSP_DEBUG_UART_TX         (P5_1)
-#endif
-
-/** Pin: I2C SCL */
-#ifndef CYBSP_I2C_SCL
-#define CYBSP_I2C_SCL               (P6_0)
-#endif
-/** Pin: I2C SDA */
-#ifndef CYBSP_I2C_SDA
-#define CYBSP_I2C_SDA               (P6_1)
-#endif
-
-/** Pin: SWDIO */
-#ifndef CYBSP_SWDIO
-#define CYBSP_SWDIO                 (P6_6)
-#endif
-/** Pin: SWDCK */
-#ifndef CYBSP_SWDCK
-#define CYBSP_SWDCK                 (P6_7)
-#endif
-/** Pin: SWO */
-#ifndef CYBSP_SWO
-#define CYBSP_SWO                   (P6_4)
-#endif
-
-/** Pin: QUAD SPI SS */
-#ifndef CYBSP_QSPI_SS
-#define CYBSP_QSPI_SS               (P11_2)
-#endif
-/** Pin: QUAD SPI D3 */
-#ifndef CYBSP_QSPI_D3
-#define CYBSP_QSPI_D3               (P11_3)
-#endif
-/** Pin: QUAD SPI D2 */
-#ifndef CYBSP_QSPI_D2
-#define CYBSP_QSPI_D2               (P11_4)
-#endif
-/** Pin: QUAD SPI D1 */
-#ifndef CYBSP_QSPI_D1
-#define CYBSP_QSPI_D1               (P11_5)
-#endif
-/** Pin: QUAD SPI D0 */
-#ifndef CYBSP_QSPI_D0
-#define CYBSP_QSPI_D0               (P11_6)
-#endif
-/** Pin: QUAD SPI SCK */
-#ifndef CYBSP_QSPI_SCK
-#define CYBSP_QSPI_SCK              (P11_7)
-#endif
-
-/** \} group_bsp_pins_comm */
-
-/** \} group_bsp_pins */
-
-#endif /* defined(CY_USING_HAL) */
-
-#if defined(__cplusplus)
-}
-#endif

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cyb06xx7_cm0plus.sct

@@ -1,307 +0,0 @@
-#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
-; The first line specifies a preprocessor command that the linker invokes
-; to pass a scatter file through a C preprocessor.
-
-;*******************************************************************************
-;* \file cyb06xx7_cm0plus.sct
-;* \version 2.70.1
-;*
-;* Linker file for the ARMCC.
-;*
-;* The main purpose of the linker script is to describe how the sections in the
-;* input files should be mapped into the output file, and to control the memory
-;* layout of the output file.
-;*
-;* \note The entry point location is fixed and starts at 0x10000000. The valid
-;* application image should be placed there.
-;*
-;* \note The linker files included with the PDL template projects must be
-;* generic and handle all common use cases. Your project may not use every
-;* section defined in the linker files. In that case you may see the warnings
-;* during the build process: L6314W (no section matches pattern) and/or L6329W
-;* (pattern only matches removed unused sections). In your project, you can
-;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
-;* the linker, simply comment out or remove the relevant code in the linker
-;* file.
-;*
-;*******************************************************************************
-;* \copyright
-;* Copyright 2016-2020 Cypress Semiconductor Corporation
-;* SPDX-License-Identifier: Apache-2.0
-;*
-;* Licensed under the Apache License, Version 2.0 (the "License");
-;* you may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at
-;*
-;*     http://www.apache.org/licenses/LICENSE-2.0
-;*
-;* Unless required by applicable law or agreed to in writing, software
-;* distributed under the License is distributed on an "AS IS" BASIS,
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;******************************************************************************/
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-;* MBED_APP_START is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_START
-;* is equal to MBED_ROM_START
-;*
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START    MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-;* MBED_APP_SIZE is being  used by the bootloader build script and
-;* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-;* is equal to MBED_ROM_SIZE
-;*
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE     MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-; The size of the stack section at the end of CM0+ SRAM
-#if !defined(MBED_BOOT_STACK_SIZE)
-  #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-#define STACK_SIZE MBED_BOOT_STACK_SIZE
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-; The defines below describe the location and size of blocks of memory in the target.
-; Use these defines to specify the memory regions available for allocation.
-
-; The following defines control RAM and flash memory allocation for the CM0+ core.
-; You can change the memory allocation by editing the RAM and Flash defines.
-; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
-; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
-; RAM
-#define RAM_START               MBED_RAM_START
-#define RAM_SIZE                MBED_RAM_SIZE
-; Public RAM
-#define PUBLIC_RAM_START        MBED_PUBLIC_RAM_START
-#define PUBLIC_RAM_SIZE         MBED_PUBLIC_RAM_SIZE
-; Flash
-#define FLASH_START             MBED_APP_START
-#define FLASH_SIZE              MBED_APP_SIZE
-
-; The size of the MCU boot header area at the start of FLASH
-#define BOOT_HEADER_SIZE        0x00000400
-
-; The following defines describe a 32K flash region used for EEPROM emulation.
-; This region can also be used as the general purpose flash.
-; You can assign sections to this memory region for only one of the cores.
-; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-; Therefore, repurposing this memory region will prevent such middleware from operation.
-#define EM_EEPROM_START         0x14000000
-#define EM_EEPROM_SIZE          0x8000
-
-; The following defines describe device specific memory regions and must not be changed.
-; Supervisory flash: User data
-#define SFLASH_USER_DATA_START  0x16000800
-#define SFLASH_USER_DATA_SIZE   0x00000800
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-#define SFLASH_NAR_START        0x16001A00
-#define SFLASH_NAR_SIZE         0x00000200
-
-; Supervisory flash: Public Key
-#define SFLASH_PUBLIC_KEY_START 0x16005A00
-#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
-
-; Supervisory flash: Table of Content # 2
-#define SFLASH_TOC_2_START      0x16007C00
-#define SFLASH_TOC_2_SIZE       0x00000200
-
-; Supervisory flash: Table of Content # 2 Copy
-#define SFLASH_RTOC_2_START     0x16007E00
-#define SFLASH_RTOC_2_SIZE      0x00000200
-
-; External memory
-#define XIP_START               0x18000000
-#define XIP_SIZE                0x08000000
-
-; eFuse
-#define EFUSE_START             0x90700000
-#define EFUSE_SIZE              0x100000
-
-
-; Cortex-M0+ application flash area
-LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE - 0x8000)
-{
-    ER_FLASH_VECTORS +0
-    {
-        * (RESET, +FIRST)
-    }
-
-    ER_FLASH_CODE +0 FIXED
-    {
-        * (InRoot$$Sections)
-        * (+RO)
-    }
-
-    ER_RAM_VECTORS RAM_START UNINIT
-    {
-        * (RESET_RAM, +FIRST)
-    }
-
-    RW_RAM_DATA +0
-    {
-        * (.cy_ramfunc)
-        * (+RW, +ZI)
-    }
-
-    ; Place variables in the section that should not be initialized during the
-    ; device startup.
-    RW_IRAM1 +0 UNINIT
-    {
-        * (.noinit)
-    }
-
-    RW_IRAM2 PUBLIC_RAM_START UNINIT
-    {
-        * (.cy_sharedmem)
-    }
-
-    ; Application heap area (HEAP)
-    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM2)
-    { 
-    }
-    
-    ; Stack region growing down
-    ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE 
-    {
-    }
-}
-
-
-; Emulated EEPROM Flash area
-LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
-{
-    .cy_em_eeprom +0
-    {
-        * (.cy_em_eeprom)
-    }
-}
-
-; Supervisory flash: User data
-LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
-{
-    .cy_sflash_user_data +0
-    {
-        * (.cy_sflash_user_data)
-    }
-}
-
-; Supervisory flash: Normal Access Restrictions (NAR)
-LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
-{
-    .cy_sflash_nar +0
-    {
-        * (.cy_sflash_nar)
-    }
-}
-
-; Supervisory flash: Public Key
-LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
-{
-    .cy_sflash_public_key +0
-    {
-        * (.cy_sflash_public_key)
-    }
-}
-
-; Supervisory flash: Table of Content # 2
-LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
-{
-    .cy_toc_part2 +0
-    {
-        * (.cy_toc_part2)
-    }
-}
-
-; Supervisory flash: Table of Content # 2 Copy
-LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
-{
-    .cy_rtoc_part2 +0
-    {
-        * (.cy_rtoc_part2)
-    }
-}
-
-
-; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
-LR_EROM XIP_START XIP_SIZE
-{
-    .cy_xip +0
-    {
-        * (.cy_xip)
-    }
-}
-
-
-; eFuse
-LR_EFUSE EFUSE_START EFUSE_SIZE
-{
-    .cy_efuse +0
-    {
-        * (.cy_efuse)
-    }
-}
-
-
-; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
-CYMETA 0x90500000
-{
-    .cymeta +0 { * (.cymeta) }
-}
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-#define __cy_memory_0_start 0x10000000
-#define __cy_memory_0_length  0x000D0000
-#define __cy_memory_0_row_size 0x200
-
-/* Emulated EEPROM Flash area */
-#define __cy_memory_1_start    0x14000000
-#define __cy_memory_1_length   0x8000
-#define __cy_memory_1_row_size 0x200
-
-/* Supervisory Flash */
-#define __cy_memory_2_start    0x16000000
-#define __cy_memory_2_length   0x8000
-#define __cy_memory_2_row_size 0x200
-
-/* XIP */
-#define __cy_memory_3_start    0x18000000
-#define __cy_memory_3_length   0x08000000
-#define __cy_memory_3_row_size 0x200
-
-/* eFuse */
-#define __cy_memory_4_start    0x90700000
-#define __cy_memory_4_length   0x100000
-#define __cy_memory_4_row_size 1
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_01_cm0plus.S

@@ -1,261 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     0x0000000D                ; NMI Handler located at ROM code
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External interrupts                           Description
-                DCD     NvicMux0_IRQHandler                   ; CM0+ NVIC Mux input 0 
-                DCD     NvicMux1_IRQHandler                   ; CM0+ NVIC Mux input 1 
-                DCD     NvicMux2_IRQHandler                   ; CM0+ NVIC Mux input 2 
-                DCD     NvicMux3_IRQHandler                   ; CM0+ NVIC Mux input 3 
-                DCD     NvicMux4_IRQHandler                   ; CM0+ NVIC Mux input 4 
-                DCD     NvicMux5_IRQHandler                   ; CM0+ NVIC Mux input 5 
-                DCD     NvicMux6_IRQHandler                   ; CM0+ NVIC Mux input 6 
-                DCD     NvicMux7_IRQHandler                   ; CM0+ NVIC Mux input 7 
-                DCD     NvicMux8_IRQHandler                   ; CM0+ NVIC Mux input 8 
-                DCD     NvicMux9_IRQHandler                   ; CM0+ NVIC Mux input 9 
-                DCD     NvicMux10_IRQHandler                  ; CM0+ NVIC Mux input 10 
-                DCD     NvicMux11_IRQHandler                  ; CM0+ NVIC Mux input 11 
-                DCD     NvicMux12_IRQHandler                  ; CM0+ NVIC Mux input 12 
-                DCD     NvicMux13_IRQHandler                  ; CM0+ NVIC Mux input 13 
-                DCD     NvicMux14_IRQHandler                  ; CM0+ NVIC Mux input 14 
-                DCD     NvicMux15_IRQHandler                  ; CM0+ NVIC Mux input 15 
-                DCD     NvicMux16_IRQHandler                  ; CM0+ NVIC Mux input 16 
-                DCD     NvicMux17_IRQHandler                  ; CM0+ NVIC Mux input 17 
-                DCD     NvicMux18_IRQHandler                  ; CM0+ NVIC Mux input 18 
-                DCD     NvicMux19_IRQHandler                  ; CM0+ NVIC Mux input 19 
-                DCD     NvicMux20_IRQHandler                  ; CM0+ NVIC Mux input 20 
-                DCD     NvicMux21_IRQHandler                  ; CM0+ NVIC Mux input 21 
-                DCD     NvicMux22_IRQHandler                  ; CM0+ NVIC Mux input 22 
-                DCD     NvicMux23_IRQHandler                  ; CM0+ NVIC Mux input 23 
-                DCD     NvicMux24_IRQHandler                  ; CM0+ NVIC Mux input 24 
-                DCD     NvicMux25_IRQHandler                  ; CM0+ NVIC Mux input 25 
-                DCD     NvicMux26_IRQHandler                  ; CM0+ NVIC Mux input 26 
-                DCD     NvicMux27_IRQHandler                  ; CM0+ NVIC Mux input 27 
-                DCD     NvicMux28_IRQHandler                  ; CM0+ NVIC Mux input 28 
-                DCD     NvicMux29_IRQHandler                  ; CM0+ NVIC Mux input 29 
-                DCD     NvicMux30_IRQHandler                  ; CM0+ NVIC Mux input 30 
-                DCD     NvicMux31_IRQHandler                  ; CM0+ NVIC Mux input 31 
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-                EXPORT __ramVectors
-                AREA    RESET_RAM, READWRITE, NOINIT
-__ramVectors    SPACE   __Vectors_Size
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Weak function for startup customization
-;
-; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks)
-; because this function is executed as the first instruction in the ResetHandler.
-; The PDL is also not initialized to use the proper register offsets.
-; The user of this function is responsible for initializing the PDL and resources before using them.
-;
-Cy_OnResetUser  PROC
-                EXPORT  Cy_OnResetUser            [WEAK]
-                BX      LR
-                ENDP
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  __main
-
-                ; Define strong function for startup customization
-                BL      Cy_OnResetUser
-
-                ; Copy vectors from ROM to RAM
-                LDR r1, =__Vectors
-                LDR r0, =__ramVectors
-                LDR r2, =__Vectors_Size
-Vectors_Copy
-                LDR r3, [r1]
-                STR r3, [r0]
-                ADDS r0, r0, #4
-                ADDS r1, r1, #4
-                SUBS r2, r2, #1
-                CMP r2, #0
-                BNE Vectors_Copy
-
-                ; Update Vector Table Offset Register. */
-                LDR r0, =__ramVectors
-                LDR r1, =0xE000ED08
-                STR r0, [r1]
-                dsb 0xF
-
-                LDR     R0, =__main
-                BLX     R0
-
-                ; Should never get here
-                B       .
-
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler         PROC
-                    EXPORT  NMI_Handler               [WEAK]
-                    B       .
-                    ENDP
-
-Cy_SysLib_FaultHandler PROC
-                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
-                    B       .
-                    ENDP
-
-HardFault_Handler   PROC
-                    EXPORT HardFault_Handler          [WEAK]
-                    movs r0, #4
-                    mov r1, LR
-                    tst r0, r1
-                    beq L_MSP
-                    mrs r0, PSP
-                    bl L_API_call
-L_MSP
-                    mrs r0, MSP
-L_API_call
-                    bl Cy_SysLib_FaultHandler
-                    ENDP
-
-SVC_Handler         PROC
-                    EXPORT  SVC_Handler               [WEAK]
-                    B       .
-                    ENDP
-PendSV_Handler      PROC
-                    EXPORT  PendSV_Handler            [WEAK]
-                    B       .
-                    ENDP
-SysTick_Handler     PROC
-                    EXPORT  SysTick_Handler           [WEAK]
-                    B       .
-                    ENDP
-
-Default_Handler     PROC
-                    EXPORT  Default_Handler                       [WEAK]
-                    EXPORT  NvicMux0_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux1_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux2_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux3_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux4_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux5_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux6_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux7_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux8_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux9_IRQHandler                   [WEAK]
-                    EXPORT  NvicMux10_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux11_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux12_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux13_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux14_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux15_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux16_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux17_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux18_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux19_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux20_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux21_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux22_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux23_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux24_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux25_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux26_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux27_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux28_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux29_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux30_IRQHandler                  [WEAK]
-                    EXPORT  NvicMux31_IRQHandler                  [WEAK]
-
-NvicMux0_IRQHandler
-NvicMux1_IRQHandler
-NvicMux2_IRQHandler
-NvicMux3_IRQHandler
-NvicMux4_IRQHandler
-NvicMux5_IRQHandler
-NvicMux6_IRQHandler
-NvicMux7_IRQHandler
-NvicMux8_IRQHandler
-NvicMux9_IRQHandler
-NvicMux10_IRQHandler
-NvicMux11_IRQHandler
-NvicMux12_IRQHandler
-NvicMux13_IRQHandler
-NvicMux14_IRQHandler
-NvicMux15_IRQHandler
-NvicMux16_IRQHandler
-NvicMux17_IRQHandler
-NvicMux18_IRQHandler
-NvicMux19_IRQHandler
-NvicMux20_IRQHandler
-NvicMux21_IRQHandler
-NvicMux22_IRQHandler
-NvicMux23_IRQHandler
-NvicMux24_IRQHandler
-NvicMux25_IRQHandler
-NvicMux26_IRQHandler
-NvicMux27_IRQHandler
-NvicMux28_IRQHandler
-NvicMux29_IRQHandler
-NvicMux30_IRQHandler
-NvicMux31_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-                END
-
-
-; [] END OF FILE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cyb06xx7_cm0plus.ld

@@ -1,471 +0,0 @@
-/***************************************************************************//**
-* \file cyb06xx7_cm0plus.ld
-* \version 2.70.1
-*
-* Linker file for the GNU C compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-ENTRY(Reset_Handler)
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-/* MBED_APP_START is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
-* is equal to MBED_ROM_START
-*/
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x80000
-#endif
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-* is equal to MBED_ROM_SIZE
-*/
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x00010000
-#endif
-
-#if !defined(MBED_PUBLIC_RAM_SIZE)
-  #define MBED_PUBLIC_RAM_SIZE     0x200
-#endif
-
-/* The size of the stack section at the end of CM0+ SRAM */
-#if !defined(MBED_BOOT_STACK_SIZE)
-    #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-STACK_SIZE = MBED_BOOT_STACK_SIZE;
-
-#if !defined(MBED_PUBLIC_RAM_START)
-  #define MBED_PUBLIC_RAM_START    (MBED_RAM_START + MBED_RAM_SIZE - STACK_SIZE - MBED_PUBLIC_RAM_SIZE)
-#endif
-
-/* The size of the MCU boot header area at the start of FLASH */
-BOOT_HEADER_SIZE = 0x400;
-
-/* Force symbol to be entered in the output file as an undefined symbol. Doing
-* this may, for example, trigger linking of additional modules from standard
-* libraries. You may list several symbols for each EXTERN, and you may use
-* EXTERN multiple times. This command has the same effect as the -u command-line
-* option.
-*/
-EXTERN(Reset_Handler)
-
-/* The MEMORY section below describes the location and size of blocks of memory in the target.
-* Use this section to specify the memory regions available for allocation.
-*/
-MEMORY
-{
-    /* The ram and flash regions control RAM and flash memory allocation for the CM0+ core.
-     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
-     * Your changes must be aligned with the corresponding memory regions for the CM4 core in 'xx_cm4_dual.ld',
-     * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.ld'.
-     */
-    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    public_ram        (rw)    : ORIGIN = MBED_PUBLIC_RAM_START, LENGTH = MBED_PUBLIC_RAM_SIZE
-    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = (MBED_APP_SIZE - 0x8000)
-
-    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
-     * You can assign sections to this memory region for only one of the cores.
-     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-     * Therefore, repurposing this memory region will prevent such middleware from operation.
-     */
-    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
-
-    /* The following regions define device specific memory regions and must not be changed. */
-    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
-    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
-    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
-    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
-    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
-    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
-    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-
-
-SECTIONS
-{
-    .cy_app_header :
-    {
-        KEEP(*(.cy_app_header))
-    } > flash
-
-    /* Cortex-M0+ application flash area */
-    .text ORIGIN(flash) + BOOT_HEADER_SIZE :
-    {
-        . = ALIGN(4);
-        __Vectors = . ;
-        KEEP(*(.vectors))
-        . = ALIGN(4);
-        __Vectors_End = .;
-        __Vectors_Size = __Vectors_End - __Vectors;
-        __end__ = .;
-
-        . = ALIGN(4);
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* Read-only code (constants). */
-        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
-
-        KEEP(*(.eh_frame*))
-    } > flash
-
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    __exidx_start = .;
-
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > flash
-    __exidx_end = .;
-
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm0plus.S */
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-
-        /* Copy interrupt vectors from flash to RAM */
-        LONG (__Vectors)                                    /* From */
-        LONG (__ram_vectors_start__)                        /* To   */
-        LONG (__Vectors_End - __Vectors)                    /* Size */
-
-        /* Copy data section to RAM */
-        LONG (__etext)                                      /* From */
-        LONG (__data_start__)                               /* To   */
-        LONG (__data_end__ - __data_start__)                /* Size */
-
-        __copy_table_end__ = .;
-    } > flash
-
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm0plus.S */
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        __zero_table_end__ = .;
-    } > flash
-
-    __etext =  . ;
-
-
-    .ramVectors (NOLOAD) : ALIGN(8)
-    {
-        __ram_vectors_start__ = .;
-        KEEP(*(.ram_vectors))
-        __ram_vectors_end__   = .;
-    } > ram
-
-
-    .data __ram_vectors_end__ : AT (__etext)
-    {
-        __data_start__ = .;
-
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        KEEP(*(.cy_ramfunc*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > ram
-
-
-    /* Place variables in the section that should not be initialized during the
-    *  device startup.
-    */
-    .noinit (NOLOAD) : ALIGN(8)
-    {
-      KEEP(*(.noinit))
-    } > ram
-
-
-    /* The uninitialized global or static variables are placed in this section.
-    *
-    * The NOLOAD attribute tells linker that .bss section does not consume
-    * any space in the image. The NOLOAD attribute changes the .bss type to
-    * NOBITS, and that  makes linker to A) not allocate section in memory, and
-    * A) put information to clear the section with all zeros during application
-    * loading.
-    *
-    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
-    * This  makes linker to A) allocate zeroed section in memory, and B) copy
-    * this section to RAM during application loading.
-    */
-    .bss (NOLOAD):
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram
-
-
-    .heap (NOLOAD):
-    {
-        __HeapBase = .;
-        __end__ = .;
-        end = __end__;
-        KEEP(*(.heap*))
-        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
-        __HeapLimit = .;
-    } > ram
-
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        KEEP(*(.stack*))
-    } > ram
-
-
-    /* Public RAM */
-    .cy_sharedmem (NOLOAD):
-    {
-        . = ALIGN(4);
-        KEEP(*(.cy_sharedmem))
-    } > public_ram
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(ram) + LENGTH(ram);
-    __StackLimit = __StackTop - STACK_SIZE;
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
-    /* Emulated EEPROM Flash area */
-    .cy_em_eeprom :
-    {
-        KEEP(*(.cy_em_eeprom))
-    } > em_eeprom
-
-
-    /* Supervisory Flash: User data */
-    .cy_sflash_user_data :
-    {
-        KEEP(*(.cy_sflash_user_data))
-    } > sflash_user_data
-
-
-    /* Supervisory Flash: Normal Access Restrictions (NAR) */
-    .cy_sflash_nar :
-    {
-        KEEP(*(.cy_sflash_nar))
-    } > sflash_nar
-
-
-    /* Supervisory Flash: Public Key */
-    .cy_sflash_public_key :
-    {
-        KEEP(*(.cy_sflash_public_key))
-    } > sflash_public_key
-
-
-    /* Supervisory Flash: Table of Content # 2 */
-    .cy_toc_part2 :
-    {
-        KEEP(*(.cy_toc_part2))
-    } > sflash_toc_2
-
-
-    /* Supervisory Flash: Table of Content # 2 Copy */
-    .cy_rtoc_part2 :
-    {
-        KEEP(*(.cy_rtoc_part2))
-    } > sflash_rtoc_2
-
-
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
-    /* eFuse */
-    .cy_efuse :
-    {
-        KEEP(*(.cy_efuse))
-    } > efuse
-
-
-    /* These sections are used for additional metadata (silicon revision,
-    *  Silicon/JTAG ID, etc.) storage.
-    */
-    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
-}
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x000D0000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start    = 0x14000000;
-__cy_memory_1_length   = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start    = 0x16000000;
-__cy_memory_2_length   = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start    = 0x18000000;
-__cy_memory_3_length   = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start    = 0x90700000;
-__cy_memory_4_length   = 0x100000;
-__cy_memory_4_row_size = 1;
-
-/* EOF */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm0plus.S

@@ -1,399 +0,0 @@
-/**************************************************************************//**
- * @file     startup_psoc6_01_cm0plus.S
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM0plus Device Series
- * @version  V5.00
- * @date     02. March 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-    /* Address of the NMI handler */
-    #define CY_NMI_HANLDER_ADDR         0x0000000D
-
-    /* The CPU VTOR register */
-    #define CY_CPU_VTOR_ADDR            0xE000ED08
-
-    /* Copy flash vectors and data section to RAM */
-    #define __STARTUP_COPY_MULTIPLE
-
-    /* Clear single BSS section */
-    #define __STARTUP_CLEAR_BSS
-
-    .syntax    unified
-    .arch    armv6-m
-
-    .section .stack
-    .align    3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x00001000
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size    __StackLimit, . - __StackLimit
-__StackTop:
-    .size    __StackTop, . - __StackTop
-
-    .section .heap
-    .align    3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x00000400
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size    __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size    __HeapLimit, . - __HeapLimit
-
-    .section .vectors
-    .align 2
-    .globl    __Vectors
-__Vectors:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-     /* External interrupts                             Description */
-    .long    NvicMux0_IRQHandler                     /* CM0+ NVIC Mux input 0 */
-    .long    NvicMux1_IRQHandler                     /* CM0+ NVIC Mux input 1 */
-    .long    NvicMux2_IRQHandler                     /* CM0+ NVIC Mux input 2 */
-    .long    NvicMux3_IRQHandler                     /* CM0+ NVIC Mux input 3 */
-    .long    NvicMux4_IRQHandler                     /* CM0+ NVIC Mux input 4 */
-    .long    NvicMux5_IRQHandler                     /* CM0+ NVIC Mux input 5 */
-    .long    NvicMux6_IRQHandler                     /* CM0+ NVIC Mux input 6 */
-    .long    NvicMux7_IRQHandler                     /* CM0+ NVIC Mux input 7 */
-    .long    NvicMux8_IRQHandler                     /* CM0+ NVIC Mux input 8 */
-    .long    NvicMux9_IRQHandler                     /* CM0+ NVIC Mux input 9 */
-    .long    NvicMux10_IRQHandler                    /* CM0+ NVIC Mux input 10 */
-    .long    NvicMux11_IRQHandler                    /* CM0+ NVIC Mux input 11 */
-    .long    NvicMux12_IRQHandler                    /* CM0+ NVIC Mux input 12 */
-    .long    NvicMux13_IRQHandler                    /* CM0+ NVIC Mux input 13 */
-    .long    NvicMux14_IRQHandler                    /* CM0+ NVIC Mux input 14 */
-    .long    NvicMux15_IRQHandler                    /* CM0+ NVIC Mux input 15 */
-    .long    NvicMux16_IRQHandler                    /* CM0+ NVIC Mux input 16 */
-    .long    NvicMux17_IRQHandler                    /* CM0+ NVIC Mux input 17 */
-    .long    NvicMux18_IRQHandler                    /* CM0+ NVIC Mux input 18 */
-    .long    NvicMux19_IRQHandler                    /* CM0+ NVIC Mux input 19 */
-    .long    NvicMux20_IRQHandler                    /* CM0+ NVIC Mux input 20 */
-    .long    NvicMux21_IRQHandler                    /* CM0+ NVIC Mux input 21 */
-    .long    NvicMux22_IRQHandler                    /* CM0+ NVIC Mux input 22 */
-    .long    NvicMux23_IRQHandler                    /* CM0+ NVIC Mux input 23 */
-    .long    NvicMux24_IRQHandler                    /* CM0+ NVIC Mux input 24 */
-    .long    NvicMux25_IRQHandler                    /* CM0+ NVIC Mux input 25 */
-    .long    NvicMux26_IRQHandler                    /* CM0+ NVIC Mux input 26 */
-    .long    NvicMux27_IRQHandler                    /* CM0+ NVIC Mux input 27 */
-    .long    NvicMux28_IRQHandler                    /* CM0+ NVIC Mux input 28 */
-    .long    NvicMux29_IRQHandler                    /* CM0+ NVIC Mux input 29 */
-    .long    NvicMux30_IRQHandler                    /* CM0+ NVIC Mux input 30 */
-    .long    NvicMux31_IRQHandler                    /* CM0+ NVIC Mux input 31 */
-
-    .size    __Vectors, . - __Vectors
-    .equ    __VectorsSize, . - __Vectors
-
-    .section .ram_vectors
-    .align 2
-    .globl __ramVectors
-__ramVectors:
-    .space  __VectorsSize
-    .size   __ramVectors, . - __ramVectors
-
-
-    .text
-    .thumb
-    .thumb_func
-    .align  2
-
-    /* 
-     * Device startup customization 
-     *
-     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-     * because this function is executed as the first instruction in the ResetHandler.
-     * The PDL is also not initialized to use the proper register offsets.
-     * The user of this function is responsible for initializing the PDL and resources before using them.
-     */
-    .weak   Cy_OnResetUser
-    .func   Cy_OnResetUser, Cy_OnResetUser
-    .type   Cy_OnResetUser, %function
-
-Cy_OnResetUser:
-    bx lr
-    .size   Cy_OnResetUser, . - Cy_OnResetUser
-    .endfunc
-
-    /* Reset handler */
-    .weak    Reset_Handler
-    .type    Reset_Handler, %function
-
-Reset_Handler:
-    bl Cy_OnResetUser
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r4, =__copy_table_start__
-    ldr    r5, =__copy_table_end__
-
-.L_loop0:
-    cmp    r4, r5
-    bge    .L_loop0_done
-    ldr    r1, [r4]
-    ldr    r2, [r4, #4]
-    ldr    r3, [r4, #8]
-
-.L_loop0_0:
-    subs    r3, #4
-    blt    .L_loop0_0_done
-    ldr    r0, [r1, r3]
-    str    r0, [r2, r3]
-    b    .L_loop0_0
-
-.L_loop0_0_done:
-    adds    r4, #12
-    b    .L_loop0
-
-.L_loop0_done:
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-    subs    r3, r2
-    ble    .L_loop1_done
-
-.L_loop1:
-    subs    r3, #4
-    ldr    r0, [r1,r3]
-    str    r0, [r2,r3]
-    bgt    .L_loop1
-
-.L_loop1_done:
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-    ldr    r3, =__zero_table_start__
-    ldr    r4, =__zero_table_end__
-
-.L_loop2:
-    cmp    r3, r4
-    bge    .L_loop2_done
-    ldr    r1, [r3]
-    ldr    r2, [r3, #4]
-    movs    r0, 0
-
-.L_loop2_0:
-    subs    r2, #4
-    blt    .L_loop2_0_done
-    str    r0, [r1, r2]
-    b    .L_loop2_0
-.L_loop2_0_done:
-
-    adds    r3, #8
-    b    .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__bss_start__
-    ldr    r2, =__bss_end__
-
-    movs    r0, 0
-
-    subs    r2, r1
-    ble    .L_loop3_done
-
-.L_loop3:
-    subs    r2, #4
-    str    r0, [r1, r2]
-    bgt    .L_loop3
-.L_loop3_done:
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-    /* Update Vector Table Offset Register. */
-    ldr r0, =__ramVectors
-    ldr r1, =CY_CPU_VTOR_ADDR
-    str r0, [r1]
-    dsb 0xF
-
-    bl  _start
-
-    /* Should never get here */
-    b   .
-
-    .pool
-    .size    Reset_Handler, . - Reset_Handler
-
-    .align    1
-    .thumb_func
-    .weak    Default_Handler
-    .type    Default_Handler, %function
-Default_Handler:
-    b    .
-    .size    Default_Handler, . - Default_Handler
-    .weak    Cy_SysLib_FaultHandler
-    .type    Cy_SysLib_FaultHandler, %function
-
-Cy_SysLib_FaultHandler:
-    b    .
-    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
-    .type Fault_Handler, %function
-
-Fault_Handler:
-    /* Storing LR content for Creator call stack trace */
-    push {LR}
-    movs r0, #4
-    mov r1, LR
-    tst r0, r1
-    beq .L_MSP
-    mrs r0, PSP
-    b .L_API_call
-.L_MSP:
-    mrs r0, MSP
-.L_API_call:
-    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
-    adds r0, r0, #4
-    bl Cy_SysLib_FaultHandler
-    b   .
-    .size    Fault_Handler, . - Fault_Handler
-
-.macro    def_fault_Handler    fault_handler_name
-    .weak    \fault_handler_name
-    .set    \fault_handler_name, Fault_Handler
-    .endm
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .weak    \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler    NMI_Handler
-
-    def_fault_Handler  HardFault_Handler
-
-    def_irq_handler    SVC_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
-
-    def_irq_handler  NvicMux0_IRQHandler                     /* CM0+ NVIC Mux input 0 */
-    def_irq_handler  NvicMux1_IRQHandler                     /* CM0+ NVIC Mux input 1 */
-    def_irq_handler  NvicMux2_IRQHandler                     /* CM0+ NVIC Mux input 2 */
-    def_irq_handler  NvicMux3_IRQHandler                     /* CM0+ NVIC Mux input 3 */
-    def_irq_handler  NvicMux4_IRQHandler                     /* CM0+ NVIC Mux input 4 */
-    def_irq_handler  NvicMux5_IRQHandler                     /* CM0+ NVIC Mux input 5 */
-    def_irq_handler  NvicMux6_IRQHandler                     /* CM0+ NVIC Mux input 6 */
-    def_irq_handler  NvicMux7_IRQHandler                     /* CM0+ NVIC Mux input 7 */
-    def_irq_handler  NvicMux8_IRQHandler                     /* CM0+ NVIC Mux input 8 */
-    def_irq_handler  NvicMux9_IRQHandler                     /* CM0+ NVIC Mux input 9 */
-    def_irq_handler  NvicMux10_IRQHandler                    /* CM0+ NVIC Mux input 10 */
-    def_irq_handler  NvicMux11_IRQHandler                    /* CM0+ NVIC Mux input 11 */
-    def_irq_handler  NvicMux12_IRQHandler                    /* CM0+ NVIC Mux input 12 */
-    def_irq_handler  NvicMux13_IRQHandler                    /* CM0+ NVIC Mux input 13 */
-    def_irq_handler  NvicMux14_IRQHandler                    /* CM0+ NVIC Mux input 14 */
-    def_irq_handler  NvicMux15_IRQHandler                    /* CM0+ NVIC Mux input 15 */
-    def_irq_handler  NvicMux16_IRQHandler                    /* CM0+ NVIC Mux input 16 */
-    def_irq_handler  NvicMux17_IRQHandler                    /* CM0+ NVIC Mux input 17 */
-    def_irq_handler  NvicMux18_IRQHandler                    /* CM0+ NVIC Mux input 18 */
-    def_irq_handler  NvicMux19_IRQHandler                    /* CM0+ NVIC Mux input 19 */
-    def_irq_handler  NvicMux20_IRQHandler                    /* CM0+ NVIC Mux input 20 */
-    def_irq_handler  NvicMux21_IRQHandler                    /* CM0+ NVIC Mux input 21 */
-    def_irq_handler  NvicMux22_IRQHandler                    /* CM0+ NVIC Mux input 22 */
-    def_irq_handler  NvicMux23_IRQHandler                    /* CM0+ NVIC Mux input 23 */
-    def_irq_handler  NvicMux24_IRQHandler                    /* CM0+ NVIC Mux input 24 */
-    def_irq_handler  NvicMux25_IRQHandler                    /* CM0+ NVIC Mux input 25 */
-    def_irq_handler  NvicMux26_IRQHandler                    /* CM0+ NVIC Mux input 26 */
-    def_irq_handler  NvicMux27_IRQHandler                    /* CM0+ NVIC Mux input 27 */
-    def_irq_handler  NvicMux28_IRQHandler                    /* CM0+ NVIC Mux input 28 */
-    def_irq_handler  NvicMux29_IRQHandler                    /* CM0+ NVIC Mux input 29 */
-    def_irq_handler  NvicMux30_IRQHandler                    /* CM0+ NVIC Mux input 30 */
-    def_irq_handler  NvicMux31_IRQHandler                    /* CM0+ NVIC Mux input 31 */
-
-    .end
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cyb06xx7_cm0plus.icf

@@ -1,288 +0,0 @@
-/*******************************************************************************
-* \file cyb06xx7_cm0plus.icf
-* \version 2.70.1
-*
-* Linker file for the IAR compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point is fixed and starts at 0x10000000. The valid application
-* image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-
-if (!isdefinedsymbol(MBED_ROM_START)) {
-  define symbol MBED_ROM_START = 0x10000000;
-}
-
-/* MBED_APP_START is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_START
- * is equal to MBED_ROM_START
- */
-if (!isdefinedsymbol(MBED_APP_START)) {
-  define symbol MBED_APP_START = MBED_ROM_START;
-}
-
-if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x80000;
-}
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
- * will be calculate by the system. Without bootloader the MBED_APP_SIZE
- * is equal to MBED_ROM_SIZE
- */
-if (!isdefinedsymbol(MBED_APP_SIZE)) {
-  define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
-}
-
-if (!isdefinedsymbol(MBED_RAM_START)) {
-  define symbol MBED_RAM_START = 0x08000000;
-}
-
-if (!isdefinedsymbol(MBED_RAM_SIZE)) {
-  define symbol MBED_RAM_SIZE = 0x00010000;
-}
-
-/*-Sizes-*/
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_SIZE)) {
-  define symbol MBED_PUBLIC_RAM_SIZE = 0x200;
-}
-if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
-
-    if (!isdefinedsymbol(__STACK_SIZE)) {
-      define symbol MBED_BOOT_STACK_SIZE = 0x0400;
-    } else {
-      define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE;
-    }
-}
-
-define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
-
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-
-/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
-if (!isdefinedsymbol(__HEAP_SIZE)) {
-    define symbol __ICFEDIT_size_heap__ = 0x0400;
-} else {
-  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
-}
-
-if (!isdefinedsymbol(MBED_PUBLIC_RAM_START)) {
-  define symbol MBED_PUBLIC_RAM_START = (MBED_RAM_START + MBED_RAM_SIZE - __ICFEDIT_size_cstack__ - MBED_PUBLIC_RAM_SIZE);
-}
-
-/* The symbols below define the location and size of blocks of memory in the target.
- * Use these symbols to specify the memory regions available for allocation.
- */
-
-/* The following symbols control RAM and flash memory allocation for the CM0+ core.
- * You can change the memory allocation by editing RAM and Flash symbols.
- * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
- * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'.
- */
-/* RAM */
-define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START;
-define symbol __ICFEDIT_region_IRAM1_end__   = (MBED_RAM_START + MBED_RAM_SIZE - 1);
-/* Public RAM */
-define symbol __ICFEDIT_region_IRAM2_start__ = MBED_PUBLIC_RAM_START;
-define symbol __ICFEDIT_region_IRAM2_end__   = (MBED_PUBLIC_RAM_START + MBED_PUBLIC_RAM_SIZE - 1);
-/* Flash */
-define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START;
-define symbol __ICFEDIT_region_IROM1_end__   = (MBED_APP_START + MBED_APP_SIZE - 0x8000 - 1);
-
-/* The following symbols define a 32K flash region used for EEPROM emulation.
- * This region can also be used as the general purpose flash.
- * You can assign sections to this memory region for only one of the cores.
- * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
- * Therefore, repurposing this memory region will prevent such middleware from operation.
- */
-define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
-
-/* The following symbols define device specific memory regions and must not be changed. */
-/* Supervisory FLASH - User Data */
-define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
-define symbol __ICFEDIT_region_IROM3_end__   = 0x160007FF;
-
-/* Supervisory FLASH - Normal Access Restrictions (NAR) */
-define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
-define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
-
-/* Supervisory FLASH - Public Key */
-define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
-define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
-
-/* Supervisory FLASH - Table of Content # 2 */
-define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
-define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
-
-/* Supervisory FLASH - Table of Content # 2 Copy */
-define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
-define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
-
-/* eFuse */
-define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
-define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
-
-/* XIP */
-define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
-
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-/**** End of ICF editor section. ###ICF###*/
-
-/* The size of the MCU boot header area at the start of FLASH */
-define symbol BOOT_HEADER_SIZE  = 0x400;
-
-
-define memory mem with size = 4G;
-define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
-define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
-define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
-define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
-define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
-define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
-define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
-define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
-define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
-define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
-define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
-
-define block RAM_DATA {readwrite section .data};
-define block RAM_OTHER {readwrite section * };
-define block RAM_NOINIT {readwrite section .noinit};
-define block RAM_BSS {readwrite section .bss};
-define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS};
-define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
-define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
-define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
-define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
-define block RO     {first section .intvec, readonly};
-
-/*-Initializations-*/
-initialize by copy { readwrite };
-do not initialize  { section .noinit, section .intvec_ram };
-
-/*-Placement-*/
-
-/* Flash - Cortex-M0+ application */
-".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
-place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO };
-
-/* Emulated EEPROM Flash area */
-".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
-
-/* Supervisory Flash - User Data */
-".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
-
-/* Supervisory Flash - NAR */
-".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
-
-/* Supervisory Flash - Public Key */
-".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
-
-/* Supervisory Flash - TOC2 */
-".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
-
-/* Supervisory Flash - RTOC2 */
-".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
-
-/* eFuse */
-".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
-
-/* Execute in Place (XIP). See the smif driver documentation for details. */
-".cy_xip" : place at start of EROM1_region  { section .cy_xip };
-
-/* RAM */
-place at start of IRAM1_region  { readwrite section .intvec_ram};
-place in IRAM1_region  { block RAM};
-place in IRAM1_region  { readwrite section .cy_ramfunc };
-place at end   of IRAM1_region  { block HSTACK };
-
-/* Public RAM */
-place at start of IRAM2_region  { section .cy_sharedmem };
-
-/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
-".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
-
-
-keep {  section .cy_app_header,
-        section .cy_em_eeprom,
-        section .cy_sflash_user_data,
-        section .cy_sflash_nar,
-        section .cy_sflash_public_key,
-        section .cy_toc_part2,
-        section .cy_rtoc_part2,
-        section .cy_efuse,
-        section .cy_xip,
-        section .cymeta,
-         };
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-define exported symbol __cy_memory_0_start    = 0x10000000;
-define exported symbol __cy_memory_0_length   = 0x000D0000;
-define exported symbol __cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-define exported symbol __cy_memory_1_start    = 0x14000000;
-define exported symbol __cy_memory_1_length   = 0x8000;
-define exported symbol __cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-define exported symbol __cy_memory_2_start    = 0x16000000;
-define exported symbol __cy_memory_2_length   = 0x8000;
-define exported symbol __cy_memory_2_row_size = 0x200;
-
-/* XIP */
-define exported symbol __cy_memory_3_start    = 0x18000000;
-define exported symbol __cy_memory_3_length   = 0x08000000;
-define exported symbol __cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-define exported symbol __cy_memory_4_start    = 0x90700000;
-define exported symbol __cy_memory_4_length   = 0x100000;
-define exported symbol __cy_memory_4_row_size = 1;
-
-/* EOF */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_01_cm0plus.S

@@ -1,413 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm0plus.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM0plus Device Series
-; * @version  V5.00
-; * @date     08. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-        SECTION .intvec_ram:DATA:NOROOT(2)
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        EXTERN __iar_data_init3
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-        PUBLIC  __ramVectors
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     0x0000000D      ; NMI_Handler is defined in ROM code
-        DCD     HardFault_Handler
-        DCD     0
-        DCD     0
-        DCD     0
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     0
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External interrupts                           Description
-        DCD     NvicMux0_IRQHandler                   ; CM0+ NVIC Mux input 0
-        DCD     NvicMux1_IRQHandler                   ; CM0+ NVIC Mux input 1
-        DCD     NvicMux2_IRQHandler                   ; CM0+ NVIC Mux input 2
-        DCD     NvicMux3_IRQHandler                   ; CM0+ NVIC Mux input 3
-        DCD     NvicMux4_IRQHandler                   ; CM0+ NVIC Mux input 4
-        DCD     NvicMux5_IRQHandler                   ; CM0+ NVIC Mux input 5
-        DCD     NvicMux6_IRQHandler                   ; CM0+ NVIC Mux input 6
-        DCD     NvicMux7_IRQHandler                   ; CM0+ NVIC Mux input 7
-        DCD     NvicMux8_IRQHandler                   ; CM0+ NVIC Mux input 8
-        DCD     NvicMux9_IRQHandler                   ; CM0+ NVIC Mux input 9
-        DCD     NvicMux10_IRQHandler                  ; CM0+ NVIC Mux input 10
-        DCD     NvicMux11_IRQHandler                  ; CM0+ NVIC Mux input 11
-        DCD     NvicMux12_IRQHandler                  ; CM0+ NVIC Mux input 12
-        DCD     NvicMux13_IRQHandler                  ; CM0+ NVIC Mux input 13
-        DCD     NvicMux14_IRQHandler                  ; CM0+ NVIC Mux input 14
-        DCD     NvicMux15_IRQHandler                  ; CM0+ NVIC Mux input 15
-        DCD     NvicMux16_IRQHandler                  ; CM0+ NVIC Mux input 16
-        DCD     NvicMux17_IRQHandler                  ; CM0+ NVIC Mux input 17
-        DCD     NvicMux18_IRQHandler                  ; CM0+ NVIC Mux input 18
-        DCD     NvicMux19_IRQHandler                  ; CM0+ NVIC Mux input 19
-        DCD     NvicMux20_IRQHandler                  ; CM0+ NVIC Mux input 20
-        DCD     NvicMux21_IRQHandler                  ; CM0+ NVIC Mux input 21
-        DCD     NvicMux22_IRQHandler                  ; CM0+ NVIC Mux input 22
-        DCD     NvicMux23_IRQHandler                  ; CM0+ NVIC Mux input 23
-        DCD     NvicMux24_IRQHandler                  ; CM0+ NVIC Mux input 24
-        DCD     NvicMux25_IRQHandler                  ; CM0+ NVIC Mux input 25
-        DCD     NvicMux26_IRQHandler                  ; CM0+ NVIC Mux input 26
-        DCD     NvicMux27_IRQHandler                  ; CM0+ NVIC Mux input 27
-        DCD     NvicMux28_IRQHandler                  ; CM0+ NVIC Mux input 28
-        DCD     NvicMux29_IRQHandler                  ; CM0+ NVIC Mux input 29
-        DCD     NvicMux30_IRQHandler                  ; CM0+ NVIC Mux input 30
-        DCD     NvicMux31_IRQHandler                  ; CM0+ NVIC Mux input 31
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size  EQU   __Vectors_End - __Vectors
-
-        SECTION .intvec_ram:DATA:REORDER:NOROOT(2)
-__ramVectors
-        DS32     __Vectors_Size
-
-
-        THUMB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default handlers
-;;
-        PUBWEAK Default_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Default_Handler
-        B Default_Handler
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Weak function for startup customization
-;;
-;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-;; because this function is executed as the first instruction in the ResetHandler.
-;; The PDL is also not initialized to use the proper register offsets.
-;; The user of this function is responsible for initializing the PDL and resources before using them.
-;;
-        PUBWEAK Cy_OnResetUser
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Cy_OnResetUser
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Define strong version to return zero for
-;; __iar_program_start to skip data sections
-;; initialization.
-;;
-        PUBLIC __low_level_init
-        SECTION .text:CODE:REORDER:NOROOT(2)
-__low_level_init
-        MOVS R0, #0
-        BX LR
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        ; Define strong function for startup customization
-        LDR     R0, =Cy_OnResetUser
-        BLX     R0
-
-        ; Copy vectors from ROM to RAM
-        LDR r1, =__vector_table
-        LDR r0, =__ramVectors
-        LDR r2, =__Vectors_Size
-intvec_copy
-        LDR r3, [r1]
-        STR r3, [r0]
-        ADDS r0, r0, #4
-        ADDS r1, r1, #4
-        SUBS r2, r2, #1
-        CMP r2, #0
-        BNE intvec_copy
-
-        ; Update Vector Table Offset Register
-        LDR r0, =__ramVectors
-        LDR r1, =0xE000ED08
-        STR r0, [r1]
-        dsb
-
-        LDR     R0, =__iar_program_start
-        BLX     R0
-
-; Should never get here
-Cy_Main_Exited
-        B Cy_Main_Exited
-
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-
-        PUBWEAK Cy_SysLib_FaultHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-Cy_SysLib_FaultHandler
-        B Cy_SysLib_FaultHandler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        IMPORT Cy_SysLib_FaultHandler
-        movs r0, #4
-        mov r1, LR
-        tst r0, r1
-        beq L_MSP
-        mrs r0, PSP
-        b L_API_call
-L_MSP
-        mrs r0, MSP
-L_API_call
-        ; Storing LR content for Creator call stack trace
-        push {LR}
-        bl Cy_SysLib_FaultHandler
-
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-
-        ; External interrupts
-        PUBWEAK NvicMux0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux0_IRQHandler
-        B       NvicMux0_IRQHandler
-
-        PUBWEAK NvicMux1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux1_IRQHandler
-        B       NvicMux1_IRQHandler
-
-        PUBWEAK NvicMux2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux2_IRQHandler
-        B       NvicMux2_IRQHandler
-
-        PUBWEAK NvicMux3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux3_IRQHandler
-        B       NvicMux3_IRQHandler
-
-        PUBWEAK NvicMux4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux4_IRQHandler
-        B       NvicMux4_IRQHandler
-
-        PUBWEAK NvicMux5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux5_IRQHandler
-        B       NvicMux5_IRQHandler
-
-        PUBWEAK NvicMux6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux6_IRQHandler
-        B       NvicMux6_IRQHandler
-
-        PUBWEAK NvicMux7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux7_IRQHandler
-        B       NvicMux7_IRQHandler
-
-        PUBWEAK NvicMux8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux8_IRQHandler
-        B       NvicMux8_IRQHandler
-
-        PUBWEAK NvicMux9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux9_IRQHandler
-        B       NvicMux9_IRQHandler
-
-        PUBWEAK NvicMux10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux10_IRQHandler
-        B       NvicMux10_IRQHandler
-
-        PUBWEAK NvicMux11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux11_IRQHandler
-        B       NvicMux11_IRQHandler
-
-        PUBWEAK NvicMux12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux12_IRQHandler
-        B       NvicMux12_IRQHandler
-
-        PUBWEAK NvicMux13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux13_IRQHandler
-        B       NvicMux13_IRQHandler
-
-        PUBWEAK NvicMux14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux14_IRQHandler
-        B       NvicMux14_IRQHandler
-
-        PUBWEAK NvicMux15_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux15_IRQHandler
-        B       NvicMux15_IRQHandler
-
-        PUBWEAK NvicMux16_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux16_IRQHandler
-        B       NvicMux16_IRQHandler
-
-        PUBWEAK NvicMux17_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux17_IRQHandler
-        B       NvicMux17_IRQHandler
-
-        PUBWEAK NvicMux18_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux18_IRQHandler
-        B       NvicMux18_IRQHandler
-
-        PUBWEAK NvicMux19_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux19_IRQHandler
-        B       NvicMux19_IRQHandler
-
-        PUBWEAK NvicMux20_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux20_IRQHandler
-        B       NvicMux20_IRQHandler
-
-        PUBWEAK NvicMux21_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux21_IRQHandler
-        B       NvicMux21_IRQHandler
-
-        PUBWEAK NvicMux22_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux22_IRQHandler
-        B       NvicMux22_IRQHandler
-
-        PUBWEAK NvicMux23_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux23_IRQHandler
-        B       NvicMux23_IRQHandler
-
-        PUBWEAK NvicMux24_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux24_IRQHandler
-        B       NvicMux24_IRQHandler
-
-        PUBWEAK NvicMux25_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux25_IRQHandler
-        B       NvicMux25_IRQHandler
-
-        PUBWEAK NvicMux26_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux26_IRQHandler
-        B       NvicMux26_IRQHandler
-
-        PUBWEAK NvicMux27_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux27_IRQHandler
-        B       NvicMux27_IRQHandler
-
-        PUBWEAK NvicMux28_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux28_IRQHandler
-        B       NvicMux28_IRQHandler
-
-        PUBWEAK NvicMux29_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux29_IRQHandler
-        B       NvicMux29_IRQHandler
-
-        PUBWEAK NvicMux30_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux30_IRQHandler
-        B       NvicMux30_IRQHandler
-
-        PUBWEAK NvicMux31_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NvicMux31_IRQHandler
-        B       NvicMux31_IRQHandler
-
-
-        END
-
-
-; [] END OF FILE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM0P/system_psoc6_cm0plus.c

@@ -1,526 +0,0 @@
-/***************************************************************************//**
-* \file system_psoc6_cm0plus.c
-* \version 2.70.1
-*
-* The device system-source file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-#include <stdbool.h>
-#include "system_psoc6.h"
-#include "cy_device.h"
-#include "cy_device_headers.h"
-#include "cy_syslib.h"
-#include "cy_sysclk.h"
-#include "cy_wdt.h"
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    #include "cy_ipc_sema.h"
-    #include "cy_ipc_pipe.h"
-    #include "cy_ipc_drv.h"
-
-    #if defined(CY_DEVICE_PSOC6ABLE2)
-        #include "cy_flash.h"
-    #endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate()
-*******************************************************************************/
-
-/** Default HFClk frequency in Hz */
-#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
-
-/** Default PeriClk frequency in Hz */
-#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (4000000UL)
-
-/** Default SlowClk system core frequency in Hz */
-#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (4000000UL)
-
-
-/**
-* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock,
-* which is the system clock frequency supplied to the SysTick timer and the
-* processor core clock.
-* This variable implements CMSIS Core global variable.
-* Refer to the [CMSIS documentation]
-* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
-* for more details.
-* This variable can be used by debuggers to query the frequency
-* of the debug timer or to configure the trace clock speed.
-*
-* \attention Compilers must be configured to avoid removing this variable in case
-* the application program is not using it. Debugging systems require the variable
-* to be physically present in memory so that it can be examined to configure the debugger. */
-uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT;
-
-/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_Hfclk0FreqHz  = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT;
-
-/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
-uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT;
-
-/** Holds the Alternate high frequency clock in Hz. Updated by \ref Cy_BLE_EcoConfigure(). */
-uint32_t cy_BleEcoClockFreqHz = 0UL;
-
-
-/*******************************************************************************
-* SystemInit()
-*******************************************************************************/
-
-/* CLK_FLL_CONFIG default values */
-#define CY_FB_CLK_FLL_CONFIG_VALUE      (0x01000000u)
-#define CY_FB_CLK_FLL_CONFIG2_VALUE     (0x00020001u)
-#define CY_FB_CLK_FLL_CONFIG3_VALUE     (0x00002800u)
-#define CY_FB_CLK_FLL_CONFIG4_VALUE     (0x000000FFu)
-
-
-/*******************************************************************************
-* SystemCoreClockUpdate (void)
-*******************************************************************************/
-
-/* Do not use these definitions directly in your application */
-#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
-#define CY_DELAY_1K_THRESHOLD           (1000u)
-#define CY_DELAY_1M_THRESHOLD           (1000000u)
-
-uint32_t cy_delayFreqKhz  = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
-
-uint8_t cy_delayFreqMhz  = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1M_THRESHOLD);
-
-uint32_t cy_delay32kMs    = CY_DELAY_MS_OVERFLOW_THRESHOLD *
-                            CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESHOLD);
-
-
-/*******************************************************************************
-* Cy_SysEnableCM4(), Cy_SysRetainCM4(), and Cy_SysResetCM4()
-*******************************************************************************/
-#define CY_SYS_CM4_PWR_CTL_KEY_OPEN  (0x05FAUL)
-#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
-#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR  (0x000003FFUL)
-
-
-/*******************************************************************************
-* Function Name: SystemInit
-****************************************************************************//**
-*
-* Initializes the system:
-* - Restores FLL registers to the default state.
-* - Unlocks and disables WDT.
-* - Calls Cy_PDL_Init() function to define the driver library.
-* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator.
-* - Calls \ref SystemCoreClockUpdate().
-*
-*******************************************************************************/
-void SystemInit(void)
-{
-    Cy_PDL_Init(CY_DEVICE_CFG);
-
-    /* Restore FLL registers to the default state as they are not restored by the ROM code */
-    uint32_t copy = SRSS->CLK_FLL_CONFIG;
-    copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk;
-    SRSS->CLK_FLL_CONFIG = copy;
-
-    copy = SRSS->CLK_ROOT_SELECT[0u];
-    copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/
-    SRSS->CLK_ROOT_SELECT[0u] = copy;
-
-    SRSS->CLK_FLL_CONFIG  = CY_FB_CLK_FLL_CONFIG_VALUE;
-    SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE;
-    SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE;
-    SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE;
-
-    /* Unlock and disable WDT */
-    Cy_WDT_Unlock();
-    Cy_WDT_Disable();
-
-    Cy_SystemInit();
-    SystemCoreClockUpdate();
-
-    /* Clear data register of IPC structure #7, reserved for the Deep-Sleep operations. */
-    REG_IPC_STRUCT_DATA(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
-
-    /* Release IPC structure #7 to avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering. */
-    REG_IPC_STRUCT_RELEASE(CY_IPC_STRUCT_PTR(CY_IPC_CHAN_DDFT)) = 0UL;
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-    /* Allocate and initialize semaphores for the system operations. */
-    CY_SECTION(".cy_sharedmem")
-    static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD];
-
-    (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray);
-
-
-    /********************************************************************************
-    *
-    * Initializes the system pipes. The system pipes are used by BLE and Flash.
-    *
-    * If the default startup file is not used, or SystemInit() is not called in your
-    * project, call the following three functions prior to executing any flash or
-    * EmEEPROM write or erase operation:
-    *  -# Cy_IPC_Sema_Init()
-    *  -# Cy_IPC_Pipe_Config()
-    *  -# Cy_IPC_Pipe_Init()
-    *  -# Cy_Flash_Init()
-    *
-    *******************************************************************************/
-
-    /* Create an array of endpoint structures */
-    static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS];
-
-    Cy_IPC_Pipe_Config(systemIpcPipeEpArray);
-
-    static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT];
-
-    static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm0 =
-    {
-    /* .ep0ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP0,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP0,
-            /* .ipcNotifierMuxNumber */  CY_SYS_INTR_CYPIPE_MUX_EP0,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM0_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP0
-        },
-    /* .ep1ConfigData */
-        {
-            /* .ipcNotifierNumber    */  CY_IPC_INTR_CYPIPE_EP1,
-            /* .ipcNotifierPriority  */  CY_SYS_INTR_CYPIPE_PRIOR_EP1,
-            /* .ipcNotifierMuxNumber */  0u,
-            /* .epAddress            */  CY_IPC_EP_CYPIPE_CM4_ADDR,
-            /* .epConfig             */  CY_SYS_CYPIPE_CONFIG_EP1
-        },
-    /* .endpointClientsCount     */  CY_SYS_CYPIPE_CLIENT_CNT,
-    /* .endpointsCallbacksArray  */  systemIpcPipeSysCbArray,
-    /* .userPipeIsrHandler       */  &Cy_SysIpcPipeIsrCm0
-    };
-
-    Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm0);
-
-#if defined(CY_DEVICE_PSOC6ABLE2)
-    Cy_Flash_Init();
-#endif /* defined(CY_DEVICE_PSOC6ABLE2) */
-
-#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SystemInit
-****************************************************************************//**
-*
-* The function is called during device startup. Once project compiled as part of
-* the PSoC Creator project, the Cy_SystemInit() function is generated by the
-* PSoC Creator.
-*
-* The function generated by PSoC Creator performs all of the necessary device
-* configuration based on the design settings.  This includes settings from the
-* Design Wide Resources (DWR) such as Clocks and Pins as well as any component
-* configuration that is necessary.
-*
-*******************************************************************************/
-__WEAK void Cy_SystemInit(void)
-{
-     /* Empty weak function. The actual implementation to be in the PSoC Creator
-      * generated strong function.
-     */
-}
-
-
-/*******************************************************************************
-* Function Name: SystemCoreClockUpdate
-****************************************************************************//**
-*
-* Gets core clock frequency and updates \ref SystemCoreClock.
-*
-* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
-* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
-*
-*******************************************************************************/
-void SystemCoreClockUpdate (void)
-{
-    uint32 locHf0Clock = Cy_SysClk_ClkHfGetFrequency(0UL);
-
-    if (0UL != locHf0Clock)
-    {
-        cy_Hfclk0FreqHz = locHf0Clock;
-        cy_PeriClkFreqHz = locHf0Clock / (1UL + (uint32_t)Cy_SysClk_ClkPeriGetDivider());
-        SystemCoreClock = cy_PeriClkFreqHz / (1UL + (uint32_t)Cy_SysClk_ClkSlowGetDivider());
-        
-        /* Sets clock frequency for Delay API */
-        cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD);
-        cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD);
-        cy_delay32kMs   = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz;
-    }
-}
-
-
-#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
-/*******************************************************************************
-* Function Name: Cy_SysGetCM4Status
-****************************************************************************//**
-*
-* Returns the Cortex-M4 core power mode.
-*
-* \return \ref group_system_config_cm4_status_macro
-*
-*******************************************************************************/
-uint32_t Cy_SysGetCM4Status(void)
-{
-    uint32_t regValue;
-
-    /* Get current power mode */
-    regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
-
-    return (regValue);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysEnableCM4
-****************************************************************************//**
-*
-* Sets vector table base address and enables the Cortex-M4 core.
-*
-* \note If the CPU is already enabled, it is reset and then enabled.
-*
-* \param vectorTableOffset The offset of the vector table base address from
-* memory address 0x00000000. The offset should be multiple to 1024 bytes.
-*
-*******************************************************************************/
-void Cy_SysEnableCM4(uint32_t vectorTableOffset)
-{
-    uint32_t regValue;
-    uint32_t interruptState;
-    uint32_t cpuState;
-
-    CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    cpuState = Cy_SysGetCM4Status();
-    if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
-    {
-        Cy_SysResetCM4();
-    }
-
-    CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_ENABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysDisableCM4
-****************************************************************************//**
-*
-* Disables the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
-* CPU.
-*
-*******************************************************************************/
-void Cy_SysDisableCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_DISABLED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysRetainCM4
-****************************************************************************//**
-*
-* Retains the Cortex-M4 core and exists without waiting for the mode to take
-* effect.
-*
-* \note The retained mode can be entered only from the enabled mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysRetainCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RETAINED;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-
-
-/*******************************************************************************
-* Function Name: Cy_SysResetCM4
-****************************************************************************//**
-*
-* Resets the Cortex-M4 core and waits for the mode to take the effect.
-*
-* \note The reset mode can not be entered from the retained mode.
-*
-* \warning Do not call the function while the Cortex-M4 is executing because
-* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
-* unexpected behavior in the system including a deadlock. Call the function
-* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
-* the \ref group_syspm Power Management (syspm) API to put the CPU into the
-* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
-*
-*******************************************************************************/
-void Cy_SysResetCM4(void)
-{
-    uint32_t interruptState;
-    uint32_t regValue;
-
-    interruptState = Cy_SysLib_EnterCriticalSection();
-
-    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
-    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
-    regValue |= CY_SYS_CM4_STATUS_RESET;
-    CPUSS->CM4_PWR_CTL = regValue;
-
-    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
-    {
-        /* Wait for the power mode to take effect */
-    }
-
-    Cy_SysLib_ExitCriticalSection(interruptState);
-}
-#endif /* #if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) */
-
-#if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
-/*******************************************************************************
-* Function Name: Cy_SysIpcPipeIsrCm0
-****************************************************************************//**
-*
-* This is the interrupt service routine for the system pipe.
-*
-*******************************************************************************/
-void Cy_SysIpcPipeIsrCm0(void)
-{
-    Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM0_ADDR);
-}
-#endif
-
-
-/*******************************************************************************
-* Function Name: Cy_MemorySymbols
-****************************************************************************//**
-*
-* The intention of the function is to declare boundaries of the memories for the
-* MDK compilers. For the rest of the supported compilers, this is done using
-* linker configuration files. The following symbols used by the cymcuelftool.
-*
-*******************************************************************************/
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
-__asm void Cy_MemorySymbols(void)
-{
-    /* Flash */
-    EXPORT __cy_memory_0_start
-    EXPORT __cy_memory_0_length
-    EXPORT __cy_memory_0_row_size
-
-    /* Working Flash */
-    EXPORT __cy_memory_1_start
-    EXPORT __cy_memory_1_length
-    EXPORT __cy_memory_1_row_size
-
-    /* Supervisory Flash */
-    EXPORT __cy_memory_2_start
-    EXPORT __cy_memory_2_length
-    EXPORT __cy_memory_2_row_size
-
-    /* XIP */
-    EXPORT __cy_memory_3_start
-    EXPORT __cy_memory_3_length
-    EXPORT __cy_memory_3_row_size
-
-    /* eFuse */
-    EXPORT __cy_memory_4_start
-    EXPORT __cy_memory_4_length
-    EXPORT __cy_memory_4_row_size
-
-    /* Flash */
-__cy_memory_0_start     EQU __cpp(CY_FLASH_BASE)
-__cy_memory_0_length    EQU __cpp(CY_FLASH_SIZE)
-__cy_memory_0_row_size  EQU 0x200
-
-    /* Flash region for EEPROM emulation */
-__cy_memory_1_start     EQU __cpp(CY_EM_EEPROM_BASE)
-__cy_memory_1_length    EQU __cpp(CY_EM_EEPROM_SIZE)
-__cy_memory_1_row_size  EQU 0x200
-
-    /* Supervisory Flash */
-__cy_memory_2_start     EQU __cpp(CY_SFLASH_BASE)
-__cy_memory_2_length    EQU __cpp(CY_SFLASH_SIZE)
-__cy_memory_2_row_size  EQU 0x200
-
-    /* XIP */
-__cy_memory_3_start     EQU __cpp(CY_XIP_BASE)
-__cy_memory_3_length    EQU __cpp(CY_XIP_SIZE)
-__cy_memory_3_row_size  EQU 0x200
-
-    /* eFuse */
-__cy_memory_4_start     EQU __cpp(0x90700000)
-__cy_memory_4_length    EQU __cpp(0x100000)
-__cy_memory_4_row_size  EQU __cpp(1)
-}
-#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_01_cm4.S

@@ -1,638 +0,0 @@
-;/**************************************************************************//**
-; * @file     startup_psoc6_01_cm4.S
-; * @brief    CMSIS Core Device Startup File for
-; *           ARMCM4 Device Series
-; * @version  V5.00
-; * @date     02. March 2016
-; ******************************************************************************/
-;/*
-; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
-; *
-; * SPDX-License-Identifier: Apache-2.0
-; *
-; * Licensed under the Apache License, Version 2.0 (the License); you may
-; * not use this file except in compliance with the License.
-; * You may obtain a copy of the License at
-; *
-; * www.apache.org/licenses/LICENSE-2.0
-; *
-; * Unless required by applicable law or agreed to in writing, software
-; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; * See the License for the specific language governing permissions and
-; * limitations under the License.
-; */
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-                IMPORT  |Image$$ARM_LIB_STACK$$ZI$$Limit|
-
-__Vectors       DCD     |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-
-                DCD     0x0000000D                            ; NMI Handler located at ROM code
-                DCD     HardFault_Handler                     ; Hard Fault Handler
-                DCD     MemManage_Handler                     ; MPU Fault Handler
-                DCD     BusFault_Handler                      ; Bus Fault Handler
-                DCD     UsageFault_Handler                    ; Usage Fault Handler
-                DCD     0                                     ; Reserved
-                DCD     0                                     ; Reserved
-                DCD     0                                     ; Reserved
-                DCD     0                                     ; Reserved
-                DCD     SVC_Handler                           ; SVCall Handler
-                DCD     DebugMon_Handler                      ; Debug Monitor Handler
-                DCD     0                                     ; Reserved
-                DCD     PendSV_Handler                        ; PendSV Handler
-                DCD     SysTick_Handler                       ; SysTick Handler
-
-                ; External interrupts                           Description
-                DCD     ioss_interrupts_gpio_0_IRQHandler     ; GPIO Port Interrupt #0 
-                DCD     ioss_interrupts_gpio_1_IRQHandler     ; GPIO Port Interrupt #1 
-                DCD     ioss_interrupts_gpio_2_IRQHandler     ; GPIO Port Interrupt #2 
-                DCD     ioss_interrupts_gpio_3_IRQHandler     ; GPIO Port Interrupt #3 
-                DCD     ioss_interrupts_gpio_4_IRQHandler     ; GPIO Port Interrupt #4 
-                DCD     ioss_interrupts_gpio_5_IRQHandler     ; GPIO Port Interrupt #5 
-                DCD     ioss_interrupts_gpio_6_IRQHandler     ; GPIO Port Interrupt #6 
-                DCD     ioss_interrupts_gpio_7_IRQHandler     ; GPIO Port Interrupt #7 
-                DCD     ioss_interrupts_gpio_8_IRQHandler     ; GPIO Port Interrupt #8 
-                DCD     ioss_interrupts_gpio_9_IRQHandler     ; GPIO Port Interrupt #9 
-                DCD     ioss_interrupts_gpio_10_IRQHandler    ; GPIO Port Interrupt #10 
-                DCD     ioss_interrupts_gpio_11_IRQHandler    ; GPIO Port Interrupt #11 
-                DCD     ioss_interrupts_gpio_12_IRQHandler    ; GPIO Port Interrupt #12 
-                DCD     ioss_interrupts_gpio_13_IRQHandler    ; GPIO Port Interrupt #13 
-                DCD     ioss_interrupts_gpio_14_IRQHandler    ; GPIO Port Interrupt #14 
-                DCD     ioss_interrupt_gpio_IRQHandler        ; GPIO All Ports 
-                DCD     ioss_interrupt_vdd_IRQHandler         ; GPIO Supply Detect Interrupt 
-                DCD     lpcomp_interrupt_IRQHandler           ; Low Power Comparator Interrupt 
-                DCD     scb_8_interrupt_IRQHandler            ; Serial Communication Block #8 (DeepSleep capable) 
-                DCD     srss_interrupt_mcwdt_0_IRQHandler     ; Multi Counter Watchdog Timer interrupt 
-                DCD     srss_interrupt_mcwdt_1_IRQHandler     ; Multi Counter Watchdog Timer interrupt 
-                DCD     srss_interrupt_backup_IRQHandler      ; Backup domain interrupt 
-                DCD     srss_interrupt_IRQHandler             ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) 
-                DCD     pass_interrupt_ctbs_IRQHandler        ; CTBm Interrupt (all CTBms) 
-                DCD     bless_interrupt_IRQHandler            ; Bluetooth Radio interrupt 
-                DCD     cpuss_interrupts_ipc_0_IRQHandler     ; CPUSS Inter Process Communication Interrupt #0 
-                DCD     cpuss_interrupts_ipc_1_IRQHandler     ; CPUSS Inter Process Communication Interrupt #1 
-                DCD     cpuss_interrupts_ipc_2_IRQHandler     ; CPUSS Inter Process Communication Interrupt #2 
-                DCD     cpuss_interrupts_ipc_3_IRQHandler     ; CPUSS Inter Process Communication Interrupt #3 
-                DCD     cpuss_interrupts_ipc_4_IRQHandler     ; CPUSS Inter Process Communication Interrupt #4 
-                DCD     cpuss_interrupts_ipc_5_IRQHandler     ; CPUSS Inter Process Communication Interrupt #5 
-                DCD     cpuss_interrupts_ipc_6_IRQHandler     ; CPUSS Inter Process Communication Interrupt #6 
-                DCD     cpuss_interrupts_ipc_7_IRQHandler     ; CPUSS Inter Process Communication Interrupt #7 
-                DCD     cpuss_interrupts_ipc_8_IRQHandler     ; CPUSS Inter Process Communication Interrupt #8 
-                DCD     cpuss_interrupts_ipc_9_IRQHandler     ; CPUSS Inter Process Communication Interrupt #9 
-                DCD     cpuss_interrupts_ipc_10_IRQHandler    ; CPUSS Inter Process Communication Interrupt #10 
-                DCD     cpuss_interrupts_ipc_11_IRQHandler    ; CPUSS Inter Process Communication Interrupt #11 
-                DCD     cpuss_interrupts_ipc_12_IRQHandler    ; CPUSS Inter Process Communication Interrupt #12 
-                DCD     cpuss_interrupts_ipc_13_IRQHandler    ; CPUSS Inter Process Communication Interrupt #13 
-                DCD     cpuss_interrupts_ipc_14_IRQHandler    ; CPUSS Inter Process Communication Interrupt #14 
-                DCD     cpuss_interrupts_ipc_15_IRQHandler    ; CPUSS Inter Process Communication Interrupt #15 
-                DCD     scb_0_interrupt_IRQHandler            ; Serial Communication Block #0 
-                DCD     scb_1_interrupt_IRQHandler            ; Serial Communication Block #1 
-                DCD     scb_2_interrupt_IRQHandler            ; Serial Communication Block #2 
-                DCD     scb_3_interrupt_IRQHandler            ; Serial Communication Block #3 
-                DCD     scb_4_interrupt_IRQHandler            ; Serial Communication Block #4 
-                DCD     scb_5_interrupt_IRQHandler            ; Serial Communication Block #5 
-                DCD     scb_6_interrupt_IRQHandler            ; Serial Communication Block #6 
-                DCD     scb_7_interrupt_IRQHandler            ; Serial Communication Block #7 
-                DCD     csd_interrupt_IRQHandler              ; CSD (Capsense) interrupt 
-                DCD     cpuss_interrupts_dw0_0_IRQHandler     ; CPUSS DataWire #0, Channel #0 
-                DCD     cpuss_interrupts_dw0_1_IRQHandler     ; CPUSS DataWire #0, Channel #1 
-                DCD     cpuss_interrupts_dw0_2_IRQHandler     ; CPUSS DataWire #0, Channel #2 
-                DCD     cpuss_interrupts_dw0_3_IRQHandler     ; CPUSS DataWire #0, Channel #3 
-                DCD     cpuss_interrupts_dw0_4_IRQHandler     ; CPUSS DataWire #0, Channel #4 
-                DCD     cpuss_interrupts_dw0_5_IRQHandler     ; CPUSS DataWire #0, Channel #5 
-                DCD     cpuss_interrupts_dw0_6_IRQHandler     ; CPUSS DataWire #0, Channel #6 
-                DCD     cpuss_interrupts_dw0_7_IRQHandler     ; CPUSS DataWire #0, Channel #7 
-                DCD     cpuss_interrupts_dw0_8_IRQHandler     ; CPUSS DataWire #0, Channel #8 
-                DCD     cpuss_interrupts_dw0_9_IRQHandler     ; CPUSS DataWire #0, Channel #9 
-                DCD     cpuss_interrupts_dw0_10_IRQHandler    ; CPUSS DataWire #0, Channel #10 
-                DCD     cpuss_interrupts_dw0_11_IRQHandler    ; CPUSS DataWire #0, Channel #11 
-                DCD     cpuss_interrupts_dw0_12_IRQHandler    ; CPUSS DataWire #0, Channel #12 
-                DCD     cpuss_interrupts_dw0_13_IRQHandler    ; CPUSS DataWire #0, Channel #13 
-                DCD     cpuss_interrupts_dw0_14_IRQHandler    ; CPUSS DataWire #0, Channel #14 
-                DCD     cpuss_interrupts_dw0_15_IRQHandler    ; CPUSS DataWire #0, Channel #15 
-                DCD     cpuss_interrupts_dw1_0_IRQHandler     ; CPUSS DataWire #1, Channel #0 
-                DCD     cpuss_interrupts_dw1_1_IRQHandler     ; CPUSS DataWire #1, Channel #1 
-                DCD     cpuss_interrupts_dw1_2_IRQHandler     ; CPUSS DataWire #1, Channel #2 
-                DCD     cpuss_interrupts_dw1_3_IRQHandler     ; CPUSS DataWire #1, Channel #3 
-                DCD     cpuss_interrupts_dw1_4_IRQHandler     ; CPUSS DataWire #1, Channel #4 
-                DCD     cpuss_interrupts_dw1_5_IRQHandler     ; CPUSS DataWire #1, Channel #5 
-                DCD     cpuss_interrupts_dw1_6_IRQHandler     ; CPUSS DataWire #1, Channel #6 
-                DCD     cpuss_interrupts_dw1_7_IRQHandler     ; CPUSS DataWire #1, Channel #7 
-                DCD     cpuss_interrupts_dw1_8_IRQHandler     ; CPUSS DataWire #1, Channel #8 
-                DCD     cpuss_interrupts_dw1_9_IRQHandler     ; CPUSS DataWire #1, Channel #9 
-                DCD     cpuss_interrupts_dw1_10_IRQHandler    ; CPUSS DataWire #1, Channel #10 
-                DCD     cpuss_interrupts_dw1_11_IRQHandler    ; CPUSS DataWire #1, Channel #11 
-                DCD     cpuss_interrupts_dw1_12_IRQHandler    ; CPUSS DataWire #1, Channel #12 
-                DCD     cpuss_interrupts_dw1_13_IRQHandler    ; CPUSS DataWire #1, Channel #13 
-                DCD     cpuss_interrupts_dw1_14_IRQHandler    ; CPUSS DataWire #1, Channel #14 
-                DCD     cpuss_interrupts_dw1_15_IRQHandler    ; CPUSS DataWire #1, Channel #15 
-                DCD     cpuss_interrupts_fault_0_IRQHandler   ; CPUSS Fault Structure Interrupt #0 
-                DCD     cpuss_interrupts_fault_1_IRQHandler   ; CPUSS Fault Structure Interrupt #1 
-                DCD     cpuss_interrupt_crypto_IRQHandler     ; CRYPTO Accelerator Interrupt 
-                DCD     cpuss_interrupt_fm_IRQHandler         ; FLASH Macro Interrupt 
-                DCD     cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 
-                DCD     cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 
-                DCD     cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 
-                DCD     cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 
-                DCD     tcpwm_0_interrupts_0_IRQHandler       ; TCPWM #0, Counter #0 
-                DCD     tcpwm_0_interrupts_1_IRQHandler       ; TCPWM #0, Counter #1 
-                DCD     tcpwm_0_interrupts_2_IRQHandler       ; TCPWM #0, Counter #2 
-                DCD     tcpwm_0_interrupts_3_IRQHandler       ; TCPWM #0, Counter #3 
-                DCD     tcpwm_0_interrupts_4_IRQHandler       ; TCPWM #0, Counter #4 
-                DCD     tcpwm_0_interrupts_5_IRQHandler       ; TCPWM #0, Counter #5 
-                DCD     tcpwm_0_interrupts_6_IRQHandler       ; TCPWM #0, Counter #6 
-                DCD     tcpwm_0_interrupts_7_IRQHandler       ; TCPWM #0, Counter #7 
-                DCD     tcpwm_1_interrupts_0_IRQHandler       ; TCPWM #1, Counter #0 
-                DCD     tcpwm_1_interrupts_1_IRQHandler       ; TCPWM #1, Counter #1 
-                DCD     tcpwm_1_interrupts_2_IRQHandler       ; TCPWM #1, Counter #2 
-                DCD     tcpwm_1_interrupts_3_IRQHandler       ; TCPWM #1, Counter #3 
-                DCD     tcpwm_1_interrupts_4_IRQHandler       ; TCPWM #1, Counter #4 
-                DCD     tcpwm_1_interrupts_5_IRQHandler       ; TCPWM #1, Counter #5 
-                DCD     tcpwm_1_interrupts_6_IRQHandler       ; TCPWM #1, Counter #6 
-                DCD     tcpwm_1_interrupts_7_IRQHandler       ; TCPWM #1, Counter #7 
-                DCD     tcpwm_1_interrupts_8_IRQHandler       ; TCPWM #1, Counter #8 
-                DCD     tcpwm_1_interrupts_9_IRQHandler       ; TCPWM #1, Counter #9 
-                DCD     tcpwm_1_interrupts_10_IRQHandler      ; TCPWM #1, Counter #10 
-                DCD     tcpwm_1_interrupts_11_IRQHandler      ; TCPWM #1, Counter #11 
-                DCD     tcpwm_1_interrupts_12_IRQHandler      ; TCPWM #1, Counter #12 
-                DCD     tcpwm_1_interrupts_13_IRQHandler      ; TCPWM #1, Counter #13 
-                DCD     tcpwm_1_interrupts_14_IRQHandler      ; TCPWM #1, Counter #14 
-                DCD     tcpwm_1_interrupts_15_IRQHandler      ; TCPWM #1, Counter #15 
-                DCD     tcpwm_1_interrupts_16_IRQHandler      ; TCPWM #1, Counter #16 
-                DCD     tcpwm_1_interrupts_17_IRQHandler      ; TCPWM #1, Counter #17 
-                DCD     tcpwm_1_interrupts_18_IRQHandler      ; TCPWM #1, Counter #18 
-                DCD     tcpwm_1_interrupts_19_IRQHandler      ; TCPWM #1, Counter #19 
-                DCD     tcpwm_1_interrupts_20_IRQHandler      ; TCPWM #1, Counter #20 
-                DCD     tcpwm_1_interrupts_21_IRQHandler      ; TCPWM #1, Counter #21 
-                DCD     tcpwm_1_interrupts_22_IRQHandler      ; TCPWM #1, Counter #22 
-                DCD     tcpwm_1_interrupts_23_IRQHandler      ; TCPWM #1, Counter #23 
-                DCD     udb_interrupts_0_IRQHandler           ; UDB Interrupt #0 
-                DCD     udb_interrupts_1_IRQHandler           ; UDB Interrupt #1 
-                DCD     udb_interrupts_2_IRQHandler           ; UDB Interrupt #2 
-                DCD     udb_interrupts_3_IRQHandler           ; UDB Interrupt #3 
-                DCD     udb_interrupts_4_IRQHandler           ; UDB Interrupt #4 
-                DCD     udb_interrupts_5_IRQHandler           ; UDB Interrupt #5 
-                DCD     udb_interrupts_6_IRQHandler           ; UDB Interrupt #6 
-                DCD     udb_interrupts_7_IRQHandler           ; UDB Interrupt #7 
-                DCD     udb_interrupts_8_IRQHandler           ; UDB Interrupt #8 
-                DCD     udb_interrupts_9_IRQHandler           ; UDB Interrupt #9 
-                DCD     udb_interrupts_10_IRQHandler          ; UDB Interrupt #10 
-                DCD     udb_interrupts_11_IRQHandler          ; UDB Interrupt #11 
-                DCD     udb_interrupts_12_IRQHandler          ; UDB Interrupt #12 
-                DCD     udb_interrupts_13_IRQHandler          ; UDB Interrupt #13 
-                DCD     udb_interrupts_14_IRQHandler          ; UDB Interrupt #14 
-                DCD     udb_interrupts_15_IRQHandler          ; UDB Interrupt #15 
-                DCD     pass_interrupt_sar_IRQHandler         ; SAR ADC interrupt 
-                DCD     audioss_interrupt_i2s_IRQHandler      ; I2S Audio interrupt 
-                DCD     audioss_interrupt_pdm_IRQHandler      ; PDM/PCM Audio interrupt 
-                DCD     profile_interrupt_IRQHandler          ; Energy Profiler interrupt 
-                DCD     smif_interrupt_IRQHandler             ; Serial Memory Interface interrupt 
-                DCD     usb_interrupt_hi_IRQHandler           ; USB Interrupt 
-                DCD     usb_interrupt_med_IRQHandler          ; USB Interrupt 
-                DCD     usb_interrupt_lo_IRQHandler           ; USB Interrupt 
-                DCD     pass_interrupt_dacs_IRQHandler        ; Consolidated interrrupt for all DACs 
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-                EXPORT __ramVectors
-                AREA    RESET_RAM, READWRITE, NOINIT
-__ramVectors    SPACE   __Vectors_Size
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Weak function for startup customization
-;
-; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-; because this function is executed as the first instruction in the ResetHandler.
-; The PDL is also not initialized to use the proper register offsets.
-; The user of this function is responsible for initializing the PDL and resources before using them.
-;
-Cy_OnResetUser  PROC
-                EXPORT  Cy_OnResetUser            [WEAK]
-                BX      LR
-                ENDP
-
-; Reset Handler
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  Cy_SystemInitFpuEnable
-                IMPORT  __main
-
-                ; Define strong function for startup customization
-                BL      Cy_OnResetUser
-
-                ; Disable global interrupts
-                CPSID I
-
-                ; Copy vectors from ROM to RAM
-                LDR r1, =__Vectors
-                LDR r0, =__ramVectors
-                LDR r2, =__Vectors_Size
-Vectors_Copy
-                LDR r3, [r1]
-                STR r3, [r0]
-                ADDS r0, r0, #4
-                ADDS r1, r1, #4
-                SUBS r2, r2, #1
-                CMP r2, #0
-                BNE Vectors_Copy
-
-                ; Update Vector Table Offset Register. */
-                LDR r0, =__ramVectors
-                LDR r1, =0xE000ED08
-                STR r0, [r1]
-                dsb 0xF
-
-                ; Enable the FPU if used
-                LDR     R0, =Cy_SystemInitFpuEnable
-                BLX     R0
-
-                LDR     R0, =__main
-                BLX     R0
-
-                ; Should never get here
-                B       .
-
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-NMI_Handler         PROC
-                    EXPORT  NMI_Handler               [WEAK]
-                    B       .
-                    ENDP
-
-Cy_SysLib_FaultHandler PROC
-                    EXPORT  Cy_SysLib_FaultHandler   [WEAK]
-                    B       .
-                    ENDP
-HardFault_Wrapper\
-                    PROC
-                    EXPORT HardFault_Wrapper         [WEAK]
-                    movs r0, #4
-                    mov r1, LR
-                    tst r0, r1
-                    beq L_MSP
-                    mrs r0, PSP
-                    bl L_API_call
-L_MSP
-                    mrs r0, MSP
-L_API_call
-                    bl Cy_SysLib_FaultHandler
-                    ENDP
-HardFault_Handler\
-                    PROC
-                    EXPORT  HardFault_Handler         [WEAK]
-                    B       HardFault_Wrapper
-                    ENDP
-MemManage_Handler\
-                    PROC
-                    EXPORT  MemManage_Handler         [WEAK]
-                    B       HardFault_Wrapper
-                    ENDP
-BusFault_Handler\
-                    PROC
-                    EXPORT  BusFault_Handler          [WEAK]
-                    B       HardFault_Wrapper
-                    ENDP
-UsageFault_Handler\
-                    PROC
-                    EXPORT  UsageFault_Handler        [WEAK]
-                    B       HardFault_Wrapper
-                    ENDP
-SVC_Handler         PROC
-                    EXPORT  SVC_Handler               [WEAK]
-                    B       .
-                    ENDP
-DebugMon_Handler\
-                    PROC
-                    EXPORT  DebugMon_Handler          [WEAK]
-                    B       .
-                    ENDP
-PendSV_Handler      PROC
-                    EXPORT  PendSV_Handler            [WEAK]
-                    B       .
-                    ENDP
-SysTick_Handler     PROC
-                    EXPORT  SysTick_Handler           [WEAK]
-                    B       .
-                    ENDP
-
-Default_Handler     PROC
-                    EXPORT  Default_Handler                       [WEAK]
-                    EXPORT  ioss_interrupts_gpio_0_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_1_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_2_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_3_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_4_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_5_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_6_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_7_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_8_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_9_IRQHandler     [WEAK]
-                    EXPORT  ioss_interrupts_gpio_10_IRQHandler    [WEAK]
-                    EXPORT  ioss_interrupts_gpio_11_IRQHandler    [WEAK]
-                    EXPORT  ioss_interrupts_gpio_12_IRQHandler    [WEAK]
-                    EXPORT  ioss_interrupts_gpio_13_IRQHandler    [WEAK]
-                    EXPORT  ioss_interrupts_gpio_14_IRQHandler    [WEAK]
-                    EXPORT  ioss_interrupt_gpio_IRQHandler        [WEAK]
-                    EXPORT  ioss_interrupt_vdd_IRQHandler         [WEAK]
-                    EXPORT  lpcomp_interrupt_IRQHandler           [WEAK]
-                    EXPORT  scb_8_interrupt_IRQHandler            [WEAK]
-                    EXPORT  srss_interrupt_mcwdt_0_IRQHandler     [WEAK]
-                    EXPORT  srss_interrupt_mcwdt_1_IRQHandler     [WEAK]
-                    EXPORT  srss_interrupt_backup_IRQHandler      [WEAK]
-                    EXPORT  srss_interrupt_IRQHandler             [WEAK]
-                    EXPORT  pass_interrupt_ctbs_IRQHandler        [WEAK]
-                    EXPORT  bless_interrupt_IRQHandler            [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_0_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_1_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_2_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_3_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_4_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_5_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_6_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_7_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_8_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_9_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_10_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_11_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_12_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_13_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_14_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_ipc_15_IRQHandler    [WEAK]
-                    EXPORT  scb_0_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_1_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_2_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_3_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_4_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_5_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_6_interrupt_IRQHandler            [WEAK]
-                    EXPORT  scb_7_interrupt_IRQHandler            [WEAK]
-                    EXPORT  csd_interrupt_IRQHandler              [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_0_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_1_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_2_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_3_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_4_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_5_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_6_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_7_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_8_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_9_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_10_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_11_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_12_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_13_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_14_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw0_15_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_0_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_1_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_2_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_3_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_4_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_5_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_6_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_7_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_8_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_9_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_10_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_11_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_12_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_13_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_14_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_dw1_15_IRQHandler    [WEAK]
-                    EXPORT  cpuss_interrupts_fault_0_IRQHandler   [WEAK]
-                    EXPORT  cpuss_interrupts_fault_1_IRQHandler   [WEAK]
-                    EXPORT  cpuss_interrupt_crypto_IRQHandler     [WEAK]
-                    EXPORT  cpuss_interrupt_fm_IRQHandler         [WEAK]
-                    EXPORT  cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK]
-                    EXPORT  cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK]
-                    EXPORT  cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK]
-                    EXPORT  cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK]
-                    EXPORT  tcpwm_0_interrupts_0_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_1_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_2_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_3_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_4_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_5_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_6_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_0_interrupts_7_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_0_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_1_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_2_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_3_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_4_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_5_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_6_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_7_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_8_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_9_IRQHandler       [WEAK]
-                    EXPORT  tcpwm_1_interrupts_10_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_11_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_12_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_13_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_14_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_15_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_16_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_17_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_18_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_19_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_20_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_21_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_22_IRQHandler      [WEAK]
-                    EXPORT  tcpwm_1_interrupts_23_IRQHandler      [WEAK]
-                    EXPORT  udb_interrupts_0_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_1_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_2_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_3_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_4_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_5_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_6_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_7_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_8_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_9_IRQHandler           [WEAK]
-                    EXPORT  udb_interrupts_10_IRQHandler          [WEAK]
-                    EXPORT  udb_interrupts_11_IRQHandler          [WEAK]
-                    EXPORT  udb_interrupts_12_IRQHandler          [WEAK]
-                    EXPORT  udb_interrupts_13_IRQHandler          [WEAK]
-                    EXPORT  udb_interrupts_14_IRQHandler          [WEAK]
-                    EXPORT  udb_interrupts_15_IRQHandler          [WEAK]
-                    EXPORT  pass_interrupt_sar_IRQHandler         [WEAK]
-                    EXPORT  audioss_interrupt_i2s_IRQHandler      [WEAK]
-                    EXPORT  audioss_interrupt_pdm_IRQHandler      [WEAK]
-                    EXPORT  profile_interrupt_IRQHandler          [WEAK]
-                    EXPORT  smif_interrupt_IRQHandler             [WEAK]
-                    EXPORT  usb_interrupt_hi_IRQHandler           [WEAK]
-                    EXPORT  usb_interrupt_med_IRQHandler          [WEAK]
-                    EXPORT  usb_interrupt_lo_IRQHandler           [WEAK]
-                    EXPORT  pass_interrupt_dacs_IRQHandler        [WEAK]
-
-ioss_interrupts_gpio_0_IRQHandler
-ioss_interrupts_gpio_1_IRQHandler
-ioss_interrupts_gpio_2_IRQHandler
-ioss_interrupts_gpio_3_IRQHandler
-ioss_interrupts_gpio_4_IRQHandler
-ioss_interrupts_gpio_5_IRQHandler
-ioss_interrupts_gpio_6_IRQHandler
-ioss_interrupts_gpio_7_IRQHandler
-ioss_interrupts_gpio_8_IRQHandler
-ioss_interrupts_gpio_9_IRQHandler
-ioss_interrupts_gpio_10_IRQHandler
-ioss_interrupts_gpio_11_IRQHandler
-ioss_interrupts_gpio_12_IRQHandler
-ioss_interrupts_gpio_13_IRQHandler
-ioss_interrupts_gpio_14_IRQHandler
-ioss_interrupt_gpio_IRQHandler
-ioss_interrupt_vdd_IRQHandler
-lpcomp_interrupt_IRQHandler
-scb_8_interrupt_IRQHandler
-srss_interrupt_mcwdt_0_IRQHandler
-srss_interrupt_mcwdt_1_IRQHandler
-srss_interrupt_backup_IRQHandler
-srss_interrupt_IRQHandler
-pass_interrupt_ctbs_IRQHandler
-bless_interrupt_IRQHandler
-cpuss_interrupts_ipc_0_IRQHandler
-cpuss_interrupts_ipc_1_IRQHandler
-cpuss_interrupts_ipc_2_IRQHandler
-cpuss_interrupts_ipc_3_IRQHandler
-cpuss_interrupts_ipc_4_IRQHandler
-cpuss_interrupts_ipc_5_IRQHandler
-cpuss_interrupts_ipc_6_IRQHandler
-cpuss_interrupts_ipc_7_IRQHandler
-cpuss_interrupts_ipc_8_IRQHandler
-cpuss_interrupts_ipc_9_IRQHandler
-cpuss_interrupts_ipc_10_IRQHandler
-cpuss_interrupts_ipc_11_IRQHandler
-cpuss_interrupts_ipc_12_IRQHandler
-cpuss_interrupts_ipc_13_IRQHandler
-cpuss_interrupts_ipc_14_IRQHandler
-cpuss_interrupts_ipc_15_IRQHandler
-scb_0_interrupt_IRQHandler
-scb_1_interrupt_IRQHandler
-scb_2_interrupt_IRQHandler
-scb_3_interrupt_IRQHandler
-scb_4_interrupt_IRQHandler
-scb_5_interrupt_IRQHandler
-scb_6_interrupt_IRQHandler
-scb_7_interrupt_IRQHandler
-csd_interrupt_IRQHandler
-cpuss_interrupts_dw0_0_IRQHandler
-cpuss_interrupts_dw0_1_IRQHandler
-cpuss_interrupts_dw0_2_IRQHandler
-cpuss_interrupts_dw0_3_IRQHandler
-cpuss_interrupts_dw0_4_IRQHandler
-cpuss_interrupts_dw0_5_IRQHandler
-cpuss_interrupts_dw0_6_IRQHandler
-cpuss_interrupts_dw0_7_IRQHandler
-cpuss_interrupts_dw0_8_IRQHandler
-cpuss_interrupts_dw0_9_IRQHandler
-cpuss_interrupts_dw0_10_IRQHandler
-cpuss_interrupts_dw0_11_IRQHandler
-cpuss_interrupts_dw0_12_IRQHandler
-cpuss_interrupts_dw0_13_IRQHandler
-cpuss_interrupts_dw0_14_IRQHandler
-cpuss_interrupts_dw0_15_IRQHandler
-cpuss_interrupts_dw1_0_IRQHandler
-cpuss_interrupts_dw1_1_IRQHandler
-cpuss_interrupts_dw1_2_IRQHandler
-cpuss_interrupts_dw1_3_IRQHandler
-cpuss_interrupts_dw1_4_IRQHandler
-cpuss_interrupts_dw1_5_IRQHandler
-cpuss_interrupts_dw1_6_IRQHandler
-cpuss_interrupts_dw1_7_IRQHandler
-cpuss_interrupts_dw1_8_IRQHandler
-cpuss_interrupts_dw1_9_IRQHandler
-cpuss_interrupts_dw1_10_IRQHandler
-cpuss_interrupts_dw1_11_IRQHandler
-cpuss_interrupts_dw1_12_IRQHandler
-cpuss_interrupts_dw1_13_IRQHandler
-cpuss_interrupts_dw1_14_IRQHandler
-cpuss_interrupts_dw1_15_IRQHandler
-cpuss_interrupts_fault_0_IRQHandler
-cpuss_interrupts_fault_1_IRQHandler
-cpuss_interrupt_crypto_IRQHandler
-cpuss_interrupt_fm_IRQHandler
-cpuss_interrupts_cm0_cti_0_IRQHandler
-cpuss_interrupts_cm0_cti_1_IRQHandler
-cpuss_interrupts_cm4_cti_0_IRQHandler
-cpuss_interrupts_cm4_cti_1_IRQHandler
-tcpwm_0_interrupts_0_IRQHandler
-tcpwm_0_interrupts_1_IRQHandler
-tcpwm_0_interrupts_2_IRQHandler
-tcpwm_0_interrupts_3_IRQHandler
-tcpwm_0_interrupts_4_IRQHandler
-tcpwm_0_interrupts_5_IRQHandler
-tcpwm_0_interrupts_6_IRQHandler
-tcpwm_0_interrupts_7_IRQHandler
-tcpwm_1_interrupts_0_IRQHandler
-tcpwm_1_interrupts_1_IRQHandler
-tcpwm_1_interrupts_2_IRQHandler
-tcpwm_1_interrupts_3_IRQHandler
-tcpwm_1_interrupts_4_IRQHandler
-tcpwm_1_interrupts_5_IRQHandler
-tcpwm_1_interrupts_6_IRQHandler
-tcpwm_1_interrupts_7_IRQHandler
-tcpwm_1_interrupts_8_IRQHandler
-tcpwm_1_interrupts_9_IRQHandler
-tcpwm_1_interrupts_10_IRQHandler
-tcpwm_1_interrupts_11_IRQHandler
-tcpwm_1_interrupts_12_IRQHandler
-tcpwm_1_interrupts_13_IRQHandler
-tcpwm_1_interrupts_14_IRQHandler
-tcpwm_1_interrupts_15_IRQHandler
-tcpwm_1_interrupts_16_IRQHandler
-tcpwm_1_interrupts_17_IRQHandler
-tcpwm_1_interrupts_18_IRQHandler
-tcpwm_1_interrupts_19_IRQHandler
-tcpwm_1_interrupts_20_IRQHandler
-tcpwm_1_interrupts_21_IRQHandler
-tcpwm_1_interrupts_22_IRQHandler
-tcpwm_1_interrupts_23_IRQHandler
-udb_interrupts_0_IRQHandler
-udb_interrupts_1_IRQHandler
-udb_interrupts_2_IRQHandler
-udb_interrupts_3_IRQHandler
-udb_interrupts_4_IRQHandler
-udb_interrupts_5_IRQHandler
-udb_interrupts_6_IRQHandler
-udb_interrupts_7_IRQHandler
-udb_interrupts_8_IRQHandler
-udb_interrupts_9_IRQHandler
-udb_interrupts_10_IRQHandler
-udb_interrupts_11_IRQHandler
-udb_interrupts_12_IRQHandler
-udb_interrupts_13_IRQHandler
-udb_interrupts_14_IRQHandler
-udb_interrupts_15_IRQHandler
-pass_interrupt_sar_IRQHandler
-audioss_interrupt_i2s_IRQHandler
-audioss_interrupt_pdm_IRQHandler
-profile_interrupt_IRQHandler
-smif_interrupt_IRQHandler
-usb_interrupt_hi_IRQHandler
-usb_interrupt_med_IRQHandler
-usb_interrupt_lo_IRQHandler
-pass_interrupt_dacs_IRQHandler
-
-                B       .
-                ENDP
-
-                ALIGN
-
-                END
-
-
-; [] END OF FILE

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4.ld

@@ -1,447 +0,0 @@
-/***************************************************************************//**
-* \file cyb06xx7_cm4.ld
-* \version 2.70.1
-*
-* Linker file for the GNU C compiler.
-*
-* The main purpose of the linker script is to describe how the sections in the
-* input files should be mapped into the output file, and to control the memory
-* layout of the output file.
-*
-* \note The entry point location is fixed and starts at 0x10000000. The valid
-* application image should be placed there.
-*
-* \note The linker files included with the PDL template projects must be generic
-* and handle all common use cases. Your project may not use every section
-* defined in the linker files. In that case you may see warnings during the
-* build process. In your project, you can simply comment out or remove the
-* relevant code in the linker file.
-*
-********************************************************************************
-* \copyright
-* Copyright 2016-2020 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-*******************************************************************************/
-
-OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-SEARCH_DIR(.)
-GROUP(-lgcc -lc -lnosys)
-ENTRY(Reset_Handler)
-
-#if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10000000
-#endif
-
-/* MBED_APP_START is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_START
-* is equal to MBED_ROM_START
-*/
-#if !defined(MBED_APP_START)
-  #define MBED_APP_START MBED_ROM_START
-#endif
-
-#if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x000D0000
-#endif
-
-/* MBED_APP_SIZE is being  used by the bootloader build script and
-* will be calculate by the system. Without bootloader the MBED_APP_SIZE
-* is equal to MBED_ROM_SIZE
-*/
-#if !defined(MBED_APP_SIZE)
-  #define MBED_APP_SIZE MBED_ROM_SIZE
-#endif
-
-#if !defined(MBED_RAM_START)
-  #define MBED_RAM_START    0x08000000
-#endif
-
-#if !defined(MBED_RAM_SIZE)
-  #define MBED_RAM_SIZE     0x0002A000
-#endif
-
-#if !defined(MBED_BOOT_STACK_SIZE)
-    #define MBED_BOOT_STACK_SIZE 0x400
-#endif
-
-/* The size of the stack section at the end of CM4 SRAM */
-STACK_SIZE = MBED_BOOT_STACK_SIZE;
-
-/* The size of the MCU boot header area at the start of FLASH */
-BOOT_HEADER_SIZE = 0x400;
-
-/* Force symbol to be entered in the output file as an undefined symbol. Doing
-* this may, for example, trigger linking of additional modules from standard
-* libraries. You may list several symbols for each EXTERN, and you may use
-* EXTERN multiple times. This command has the same effect as the -u command-line
-* option.
-*/
-EXTERN(Reset_Handler)
-
-/* The MEMORY section below describes the location and size of blocks of memory in the target.
-* Use this section to specify the memory regions available for allocation.
-*/
-MEMORY
-{
-    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
-     */
-    ram               (rwx)   : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
-    flash             (rx)    : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
-
-    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
-     * You can assign sections to this memory region for only one of the cores.
-     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
-     * Therefore, repurposing this memory region will prevent such middleware from operation.
-     */
-    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
-
-    /* The following regions define device specific memory regions and must not be changed. */
-    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
-    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
-    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
-    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
-    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
-    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
-    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
-}
-
-/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __copy_table_start__
- *   __copy_table_end__
- *   __zero_table_start__
- *   __zero_table_end__
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   __Vectors_End
- *   __Vectors_Size
- */
-
-
-SECTIONS
-{
-    /* Cortex-M4 application flash area */
-    .text ORIGIN(flash) + BOOT_HEADER_SIZE :
-    {
-        /* Cortex-M4 flash vector table */
-        . = ALIGN(4);
-        __Vectors = . ;
-        KEEP(*(.vectors))
-        . = ALIGN(4);
-        __Vectors_End = .;
-        __Vectors_Size = __Vectors_End - __Vectors;
-        __end__ = .;
-
-        . = ALIGN(4);
-        *(.text*)
-
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        /* Read-only code (constants). */
-        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
-
-        KEEP(*(.eh_frame*))
-    } > flash
-
-
-    .ARM.extab :
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > flash
-
-    __exidx_start = .;
-
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > flash
-    __exidx_end = .;
-
-
-    /* To copy multiple ROM to RAM sections,
-     * uncomment .copy.table section and,
-     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_01_cm4.S */
-    .copy.table :
-    {
-        . = ALIGN(4);
-        __copy_table_start__ = .;
-
-        /* Copy interrupt vectors from flash to RAM */
-        LONG (__Vectors)                                    /* From */
-        LONG (__ram_vectors_start__)                        /* To   */
-        LONG (__Vectors_End - __Vectors)                    /* Size */
-
-        /* Copy data section to RAM */
-        LONG (__etext)                                      /* From */
-        LONG (__data_start__)                               /* To   */
-        LONG (__data_end__ - __data_start__)                /* Size */
-
-        __copy_table_end__ = .;
-    } > flash
-
-
-    /* To clear multiple BSS sections,
-     * uncomment .zero.table section and,
-     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_01_cm4.S */
-    .zero.table :
-    {
-        . = ALIGN(4);
-        __zero_table_start__ = .;
-        LONG (__bss_start__)
-        LONG (__bss_end__ - __bss_start__)
-        __zero_table_end__ = .;
-    } > flash
-
-    __etext =  . ;
-
-
-    .ramVectors (NOLOAD) : ALIGN(8)
-    {
-        __ram_vectors_start__ = .;
-        KEEP(*(.ram_vectors))
-        __ram_vectors_end__   = .;
-    } > ram
-
-
-    .data __ram_vectors_end__ : AT (__etext)
-    {
-        __data_start__ = .;
-
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        KEEP(*(.cy_ramfunc*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > ram
-
-
-    /* Place variables in the section that should not be initialized during the
-    *  device startup.
-    */
-    .noinit (NOLOAD) : ALIGN(8)
-    {
-      KEEP(*(.noinit))
-    } > ram
-
-
-    /* The uninitialized global or static variables are placed in this section.
-    *
-    * The NOLOAD attribute tells linker that .bss section does not consume
-    * any space in the image. The NOLOAD attribute changes the .bss type to
-    * NOBITS, and that  makes linker to A) not allocate section in memory, and
-    * A) put information to clear the section with all zeros during application
-    * loading.
-    *
-    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
-    * This  makes linker to A) allocate zeroed section in memory, and B) copy
-    * this section to RAM during application loading.
-    */
-    .bss (NOLOAD):
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram
-
-
-    .heap (NOLOAD):
-    {
-        __HeapBase = .;
-        __end__ = .;
-        end = __end__;
-        KEEP(*(.heap*))
-        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
-        __HeapLimit = .;
-    } > ram
-
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(ram) + LENGTH(ram);
-    __StackLimit = __StackTop - STACK_SIZE;
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
-    /* Used for the digital signature of the secure application and the Bootloader SDK application.
-    * The size of the section depends on the required data size. */
-    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
-    {
-        KEEP(*(.cy_app_signature))
-    } > flash
-
-
-    /* Emulated EEPROM Flash area */
-    .cy_em_eeprom :
-    {
-        KEEP(*(.cy_em_eeprom))
-    } > em_eeprom
-
-
-    /* Supervisory Flash: User data */
-    .cy_sflash_user_data :
-    {
-        KEEP(*(.cy_sflash_user_data))
-    } > sflash_user_data
-
-
-    /* Supervisory Flash: Normal Access Restrictions (NAR) */
-    .cy_sflash_nar :
-    {
-        KEEP(*(.cy_sflash_nar))
-    } > sflash_nar
-
-
-    /* Supervisory Flash: Public Key */
-    .cy_sflash_public_key :
-    {
-        KEEP(*(.cy_sflash_public_key))
-    } > sflash_public_key
-
-
-    /* Supervisory Flash: Table of Content # 2 */
-    .cy_toc_part2 :
-    {
-        KEEP(*(.cy_toc_part2))
-    } > sflash_toc_2
-
-
-    /* Supervisory Flash: Table of Content # 2 Copy */
-    .cy_rtoc_part2 :
-    {
-        KEEP(*(.cy_rtoc_part2))
-    } > sflash_rtoc_2
-
-
-    /* Places the code in the Execute in Place (XIP) section. See the smif driver
-    *  documentation for details.
-    */
-    .cy_xip :
-    {
-        KEEP(*(.cy_xip))
-    } > xip
-
-
-    /* eFuse */
-    .cy_efuse :
-    {
-        KEEP(*(.cy_efuse))
-    } > efuse
-
-
-    /* These sections are used for additional metadata (silicon revision,
-    *  Silicon/JTAG ID, etc.) storage.
-    */
-    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
-}
-
-
-/* The following symbols used by the cymcuelftool. */
-/* Flash */
-__cy_memory_0_start    = 0x10000000;
-__cy_memory_0_length   = 0x000D0000;
-__cy_memory_0_row_size = 0x200;
-
-/* Emulated EEPROM Flash area */
-__cy_memory_1_start    = 0x14000000;
-__cy_memory_1_length   = 0x8000;
-__cy_memory_1_row_size = 0x200;
-
-/* Supervisory Flash */
-__cy_memory_2_start    = 0x16000000;
-__cy_memory_2_length   = 0x8000;
-__cy_memory_2_row_size = 0x200;
-
-/* XIP */
-__cy_memory_3_start    = 0x18000000;
-__cy_memory_3_length   = 0x08000000;
-__cy_memory_3_row_size = 0x200;
-
-/* eFuse */
-__cy_memory_4_start    = 0x90700000;
-__cy_memory_4_length   = 0x100000;
-__cy_memory_4_row_size = 1;
-
-/* EOF */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S

@@ -1,631 +0,0 @@
-/**************************************************************************//**
- * @file     startup_psoc6_01_cm4.S
- * @brief    CMSIS Core Device Startup File for
- *           ARMCM4 Device Series
- * @version  V5.00
- * @date     02. March 2016
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-    /* Address of the NMI handler */
-    #define CY_NMI_HANLDER_ADDR         0x0000000D
-
-    /* The CPU VTOR register */
-    #define CY_CPU_VTOR_ADDR            0xE000ED08
-
-    /* Copy flash vectors and data section to RAM */
-    #define __STARTUP_COPY_MULTIPLE
-
-    /* Clear single BSS section */
-    #define __STARTUP_CLEAR_BSS
-
-    .syntax    unified
-    .arch    armv7-m
-
-    .section .stack
-    .align    3
-#ifdef __STACK_SIZE
-    .equ    Stack_Size, __STACK_SIZE
-#else
-    .equ    Stack_Size, 0x00001000
-#endif
-    .globl    __StackTop
-    .globl    __StackLimit
-__StackLimit:
-    .space    Stack_Size
-    .size    __StackLimit, . - __StackLimit
-__StackTop:
-    .size    __StackTop, . - __StackTop
-
-    .section .heap
-    .align    3
-#ifdef __HEAP_SIZE
-    .equ    Heap_Size, __HEAP_SIZE
-#else
-    .equ    Heap_Size, 0x00000400
-#endif
-    .globl    __HeapBase
-    .globl    __HeapLimit
-__HeapBase:
-    .if    Heap_Size
-    .space    Heap_Size
-    .endif
-    .size    __HeapBase, . - __HeapBase
-__HeapLimit:
-    .size    __HeapLimit, . - __HeapLimit
-
-    .section .vectors
-    .align 2
-    .globl    __Vectors
-__Vectors:
-    .long    __StackTop            /* Top of Stack */
-    .long    Reset_Handler         /* Reset Handler */
-    .long    CY_NMI_HANLDER_ADDR   /* NMI Handler */
-    .long    HardFault_Handler     /* Hard Fault Handler */
-    .long    MemManage_Handler     /* MPU Fault Handler */
-    .long    BusFault_Handler      /* Bus Fault Handler */
-    .long    UsageFault_Handler    /* Usage Fault Handler */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    0                     /* Reserved */
-    .long    SVC_Handler           /* SVCall Handler */
-    .long    DebugMon_Handler      /* Debug Monitor Handler */
-    .long    0                     /* Reserved */
-    .long    PendSV_Handler        /* PendSV Handler */
-    .long    SysTick_Handler       /* SysTick Handler */
-
-     /* External interrupts                             Description */
-    .long    ioss_interrupts_gpio_0_IRQHandler       /* GPIO Port Interrupt #0 */
-    .long    ioss_interrupts_gpio_1_IRQHandler       /* GPIO Port Interrupt #1 */
-    .long    ioss_interrupts_gpio_2_IRQHandler       /* GPIO Port Interrupt #2 */
-    .long    ioss_interrupts_gpio_3_IRQHandler       /* GPIO Port Interrupt #3 */
-    .long    ioss_interrupts_gpio_4_IRQHandler       /* GPIO Port Interrupt #4 */
-    .long    ioss_interrupts_gpio_5_IRQHandler       /* GPIO Port Interrupt #5 */
-    .long    ioss_interrupts_gpio_6_IRQHandler       /* GPIO Port Interrupt #6 */
-    .long    ioss_interrupts_gpio_7_IRQHandler       /* GPIO Port Interrupt #7 */
-    .long    ioss_interrupts_gpio_8_IRQHandler       /* GPIO Port Interrupt #8 */
-    .long    ioss_interrupts_gpio_9_IRQHandler       /* GPIO Port Interrupt #9 */
-    .long    ioss_interrupts_gpio_10_IRQHandler      /* GPIO Port Interrupt #10 */
-    .long    ioss_interrupts_gpio_11_IRQHandler      /* GPIO Port Interrupt #11 */
-    .long    ioss_interrupts_gpio_12_IRQHandler      /* GPIO Port Interrupt #12 */
-    .long    ioss_interrupts_gpio_13_IRQHandler      /* GPIO Port Interrupt #13 */
-    .long    ioss_interrupts_gpio_14_IRQHandler      /* GPIO Port Interrupt #14 */
-    .long    ioss_interrupt_gpio_IRQHandler          /* GPIO All Ports */
-    .long    ioss_interrupt_vdd_IRQHandler           /* GPIO Supply Detect Interrupt */
-    .long    lpcomp_interrupt_IRQHandler             /* Low Power Comparator Interrupt */
-    .long    scb_8_interrupt_IRQHandler              /* Serial Communication Block #8 (DeepSleep capable) */
-    .long    srss_interrupt_mcwdt_0_IRQHandler       /* Multi Counter Watchdog Timer interrupt */
-    .long    srss_interrupt_mcwdt_1_IRQHandler       /* Multi Counter Watchdog Timer interrupt */
-    .long    srss_interrupt_backup_IRQHandler        /* Backup domain interrupt */
-    .long    srss_interrupt_IRQHandler               /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
-    .long    pass_interrupt_ctbs_IRQHandler          /* CTBm Interrupt (all CTBms) */
-    .long    bless_interrupt_IRQHandler              /* Bluetooth Radio interrupt */
-    .long    cpuss_interrupts_ipc_0_IRQHandler       /* CPUSS Inter Process Communication Interrupt #0 */
-    .long    cpuss_interrupts_ipc_1_IRQHandler       /* CPUSS Inter Process Communication Interrupt #1 */
-    .long    cpuss_interrupts_ipc_2_IRQHandler       /* CPUSS Inter Process Communication Interrupt #2 */
-    .long    cpuss_interrupts_ipc_3_IRQHandler       /* CPUSS Inter Process Communication Interrupt #3 */
-    .long    cpuss_interrupts_ipc_4_IRQHandler       /* CPUSS Inter Process Communication Interrupt #4 */
-    .long    cpuss_interrupts_ipc_5_IRQHandler       /* CPUSS Inter Process Communication Interrupt #5 */
-    .long    cpuss_interrupts_ipc_6_IRQHandler       /* CPUSS Inter Process Communication Interrupt #6 */
-    .long    cpuss_interrupts_ipc_7_IRQHandler       /* CPUSS Inter Process Communication Interrupt #7 */
-    .long    cpuss_interrupts_ipc_8_IRQHandler       /* CPUSS Inter Process Communication Interrupt #8 */
-    .long    cpuss_interrupts_ipc_9_IRQHandler       /* CPUSS Inter Process Communication Interrupt #9 */
-    .long    cpuss_interrupts_ipc_10_IRQHandler      /* CPUSS Inter Process Communication Interrupt #10 */
-    .long    cpuss_interrupts_ipc_11_IRQHandler      /* CPUSS Inter Process Communication Interrupt #11 */
-    .long    cpuss_interrupts_ipc_12_IRQHandler      /* CPUSS Inter Process Communication Interrupt #12 */
-    .long    cpuss_interrupts_ipc_13_IRQHandler      /* CPUSS Inter Process Communication Interrupt #13 */
-    .long    cpuss_interrupts_ipc_14_IRQHandler      /* CPUSS Inter Process Communication Interrupt #14 */
-    .long    cpuss_interrupts_ipc_15_IRQHandler      /* CPUSS Inter Process Communication Interrupt #15 */
-    .long    scb_0_interrupt_IRQHandler              /* Serial Communication Block #0 */
-    .long    scb_1_interrupt_IRQHandler              /* Serial Communication Block #1 */
-    .long    scb_2_interrupt_IRQHandler              /* Serial Communication Block #2 */
-    .long    scb_3_interrupt_IRQHandler              /* Serial Communication Block #3 */
-    .long    scb_4_interrupt_IRQHandler              /* Serial Communication Block #4 */
-    .long    scb_5_interrupt_IRQHandler              /* Serial Communication Block #5 */
-    .long    scb_6_interrupt_IRQHandler              /* Serial Communication Block #6 */
-    .long    scb_7_interrupt_IRQHandler              /* Serial Communication Block #7 */
-    .long    csd_interrupt_IRQHandler                /* CSD (Capsense) interrupt */
-    .long    cpuss_interrupts_dw0_0_IRQHandler       /* CPUSS DataWire #0, Channel #0 */
-    .long    cpuss_interrupts_dw0_1_IRQHandler       /* CPUSS DataWire #0, Channel #1 */
-    .long    cpuss_interrupts_dw0_2_IRQHandler       /* CPUSS DataWire #0, Channel #2 */
-    .long    cpuss_interrupts_dw0_3_IRQHandler       /* CPUSS DataWire #0, Channel #3 */
-    .long    cpuss_interrupts_dw0_4_IRQHandler       /* CPUSS DataWire #0, Channel #4 */
-    .long    cpuss_interrupts_dw0_5_IRQHandler       /* CPUSS DataWire #0, Channel #5 */
-    .long    cpuss_interrupts_dw0_6_IRQHandler       /* CPUSS DataWire #0, Channel #6 */
-    .long    cpuss_interrupts_dw0_7_IRQHandler       /* CPUSS DataWire #0, Channel #7 */
-    .long    cpuss_interrupts_dw0_8_IRQHandler       /* CPUSS DataWire #0, Channel #8 */
-    .long    cpuss_interrupts_dw0_9_IRQHandler       /* CPUSS DataWire #0, Channel #9 */
-    .long    cpuss_interrupts_dw0_10_IRQHandler      /* CPUSS DataWire #0, Channel #10 */
-    .long    cpuss_interrupts_dw0_11_IRQHandler      /* CPUSS DataWire #0, Channel #11 */
-    .long    cpuss_interrupts_dw0_12_IRQHandler      /* CPUSS DataWire #0, Channel #12 */
-    .long    cpuss_interrupts_dw0_13_IRQHandler      /* CPUSS DataWire #0, Channel #13 */
-    .long    cpuss_interrupts_dw0_14_IRQHandler      /* CPUSS DataWire #0, Channel #14 */
-    .long    cpuss_interrupts_dw0_15_IRQHandler      /* CPUSS DataWire #0, Channel #15 */
-    .long    cpuss_interrupts_dw1_0_IRQHandler       /* CPUSS DataWire #1, Channel #0 */
-    .long    cpuss_interrupts_dw1_1_IRQHandler       /* CPUSS DataWire #1, Channel #1 */
-    .long    cpuss_interrupts_dw1_2_IRQHandler       /* CPUSS DataWire #1, Channel #2 */
-    .long    cpuss_interrupts_dw1_3_IRQHandler       /* CPUSS DataWire #1, Channel #3 */
-    .long    cpuss_interrupts_dw1_4_IRQHandler       /* CPUSS DataWire #1, Channel #4 */
-    .long    cpuss_interrupts_dw1_5_IRQHandler       /* CPUSS DataWire #1, Channel #5 */
-    .long    cpuss_interrupts_dw1_6_IRQHandler       /* CPUSS DataWire #1, Channel #6 */
-    .long    cpuss_interrupts_dw1_7_IRQHandler       /* CPUSS DataWire #1, Channel #7 */
-    .long    cpuss_interrupts_dw1_8_IRQHandler       /* CPUSS DataWire #1, Channel #8 */
-    .long    cpuss_interrupts_dw1_9_IRQHandler       /* CPUSS DataWire #1, Channel #9 */
-    .long    cpuss_interrupts_dw1_10_IRQHandler      /* CPUSS DataWire #1, Channel #10 */
-    .long    cpuss_interrupts_dw1_11_IRQHandler      /* CPUSS DataWire #1, Channel #11 */
-    .long    cpuss_interrupts_dw1_12_IRQHandler      /* CPUSS DataWire #1, Channel #12 */
-    .long    cpuss_interrupts_dw1_13_IRQHandler      /* CPUSS DataWire #1, Channel #13 */
-    .long    cpuss_interrupts_dw1_14_IRQHandler      /* CPUSS DataWire #1, Channel #14 */
-    .long    cpuss_interrupts_dw1_15_IRQHandler      /* CPUSS DataWire #1, Channel #15 */
-    .long    cpuss_interrupts_fault_0_IRQHandler     /* CPUSS Fault Structure Interrupt #0 */
-    .long    cpuss_interrupts_fault_1_IRQHandler     /* CPUSS Fault Structure Interrupt #1 */
-    .long    cpuss_interrupt_crypto_IRQHandler       /* CRYPTO Accelerator Interrupt */
-    .long    cpuss_interrupt_fm_IRQHandler           /* FLASH Macro Interrupt */
-    .long    cpuss_interrupts_cm0_cti_0_IRQHandler   /* CM0+ CTI #0 */
-    .long    cpuss_interrupts_cm0_cti_1_IRQHandler   /* CM0+ CTI #1 */
-    .long    cpuss_interrupts_cm4_cti_0_IRQHandler   /* CM4 CTI #0 */
-    .long    cpuss_interrupts_cm4_cti_1_IRQHandler   /* CM4 CTI #1 */
-    .long    tcpwm_0_interrupts_0_IRQHandler         /* TCPWM #0, Counter #0 */
-    .long    tcpwm_0_interrupts_1_IRQHandler         /* TCPWM #0, Counter #1 */
-    .long    tcpwm_0_interrupts_2_IRQHandler         /* TCPWM #0, Counter #2 */
-    .long    tcpwm_0_interrupts_3_IRQHandler         /* TCPWM #0, Counter #3 */
-    .long    tcpwm_0_interrupts_4_IRQHandler         /* TCPWM #0, Counter #4 */
-    .long    tcpwm_0_interrupts_5_IRQHandler         /* TCPWM #0, Counter #5 */
-    .long    tcpwm_0_interrupts_6_IRQHandler         /* TCPWM #0, Counter #6 */
-    .long    tcpwm_0_interrupts_7_IRQHandler         /* TCPWM #0, Counter #7 */
-    .long    tcpwm_1_interrupts_0_IRQHandler         /* TCPWM #1, Counter #0 */
-    .long    tcpwm_1_interrupts_1_IRQHandler         /* TCPWM #1, Counter #1 */
-    .long    tcpwm_1_interrupts_2_IRQHandler         /* TCPWM #1, Counter #2 */
-    .long    tcpwm_1_interrupts_3_IRQHandler         /* TCPWM #1, Counter #3 */
-    .long    tcpwm_1_interrupts_4_IRQHandler         /* TCPWM #1, Counter #4 */
-    .long    tcpwm_1_interrupts_5_IRQHandler         /* TCPWM #1, Counter #5 */
-    .long    tcpwm_1_interrupts_6_IRQHandler         /* TCPWM #1, Counter #6 */
-    .long    tcpwm_1_interrupts_7_IRQHandler         /* TCPWM #1, Counter #7 */
-    .long    tcpwm_1_interrupts_8_IRQHandler         /* TCPWM #1, Counter #8 */
-    .long    tcpwm_1_interrupts_9_IRQHandler         /* TCPWM #1, Counter #9 */
-    .long    tcpwm_1_interrupts_10_IRQHandler        /* TCPWM #1, Counter #10 */
-    .long    tcpwm_1_interrupts_11_IRQHandler        /* TCPWM #1, Counter #11 */
-    .long    tcpwm_1_interrupts_12_IRQHandler        /* TCPWM #1, Counter #12 */
-    .long    tcpwm_1_interrupts_13_IRQHandler        /* TCPWM #1, Counter #13 */
-    .long    tcpwm_1_interrupts_14_IRQHandler        /* TCPWM #1, Counter #14 */
-    .long    tcpwm_1_interrupts_15_IRQHandler        /* TCPWM #1, Counter #15 */
-    .long    tcpwm_1_interrupts_16_IRQHandler        /* TCPWM #1, Counter #16 */
-    .long    tcpwm_1_interrupts_17_IRQHandler        /* TCPWM #1, Counter #17 */
-    .long    tcpwm_1_interrupts_18_IRQHandler        /* TCPWM #1, Counter #18 */
-    .long    tcpwm_1_interrupts_19_IRQHandler        /* TCPWM #1, Counter #19 */
-    .long    tcpwm_1_interrupts_20_IRQHandler        /* TCPWM #1, Counter #20 */
-    .long    tcpwm_1_interrupts_21_IRQHandler        /* TCPWM #1, Counter #21 */
-    .long    tcpwm_1_interrupts_22_IRQHandler        /* TCPWM #1, Counter #22 */
-    .long    tcpwm_1_interrupts_23_IRQHandler        /* TCPWM #1, Counter #23 */
-    .long    udb_interrupts_0_IRQHandler             /* UDB Interrupt #0 */
-    .long    udb_interrupts_1_IRQHandler             /* UDB Interrupt #1 */
-    .long    udb_interrupts_2_IRQHandler             /* UDB Interrupt #2 */
-    .long    udb_interrupts_3_IRQHandler             /* UDB Interrupt #3 */
-    .long    udb_interrupts_4_IRQHandler             /* UDB Interrupt #4 */
-    .long    udb_interrupts_5_IRQHandler             /* UDB Interrupt #5 */
-    .long    udb_interrupts_6_IRQHandler             /* UDB Interrupt #6 */
-    .long    udb_interrupts_7_IRQHandler             /* UDB Interrupt #7 */
-    .long    udb_interrupts_8_IRQHandler             /* UDB Interrupt #8 */
-    .long    udb_interrupts_9_IRQHandler             /* UDB Interrupt #9 */
-    .long    udb_interrupts_10_IRQHandler            /* UDB Interrupt #10 */
-    .long    udb_interrupts_11_IRQHandler            /* UDB Interrupt #11 */
-    .long    udb_interrupts_12_IRQHandler            /* UDB Interrupt #12 */
-    .long    udb_interrupts_13_IRQHandler            /* UDB Interrupt #13 */
-    .long    udb_interrupts_14_IRQHandler            /* UDB Interrupt #14 */
-    .long    udb_interrupts_15_IRQHandler            /* UDB Interrupt #15 */
-    .long    pass_interrupt_sar_IRQHandler           /* SAR ADC interrupt */
-    .long    audioss_interrupt_i2s_IRQHandler        /* I2S Audio interrupt */
-    .long    audioss_interrupt_pdm_IRQHandler        /* PDM/PCM Audio interrupt */
-    .long    profile_interrupt_IRQHandler            /* Energy Profiler interrupt */
-    .long    smif_interrupt_IRQHandler               /* Serial Memory Interface interrupt */
-    .long    usb_interrupt_hi_IRQHandler             /* USB Interrupt */
-    .long    usb_interrupt_med_IRQHandler            /* USB Interrupt */
-    .long    usb_interrupt_lo_IRQHandler             /* USB Interrupt */
-    .long    pass_interrupt_dacs_IRQHandler          /* Consolidated interrrupt for all DACs */
-
-
-    .size    __Vectors, . - __Vectors
-    .equ    __VectorsSize, . - __Vectors
-
-    .section .ram_vectors
-    .align 2
-    .globl __ramVectors
-__ramVectors:
-    .space  __VectorsSize
-    .size   __ramVectors, . - __ramVectors
-
-
-    .text
-    .thumb
-    .thumb_func
-    .align  2
-
-    /* 
-     * Device startup customization 
-     *
-     * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) 
-     * because this function is executed as the first instruction in the ResetHandler.
-     * The PDL is also not initialized to use the proper register offsets.
-     * The user of this function is responsible for initializing the PDL and resources before using them.
-     */
-    .weak   Cy_OnResetUser
-    .func   Cy_OnResetUser, Cy_OnResetUser
-    .type   Cy_OnResetUser, %function
-
-Cy_OnResetUser:
-    bx lr
-    .size   Cy_OnResetUser, . - Cy_OnResetUser
-    .endfunc
-
-    /* Reset handler */
-    .weak    Reset_Handler
-    .type    Reset_Handler, %function
-
-Reset_Handler:
-    bl Cy_OnResetUser
-    cpsid i
-
-/*  Firstly it copies data from read only memory to RAM. There are two schemes
- *  to copy. One can copy more than one sections. Another can only copy
- *  one section.  The former scheme needs more instructions and read-only
- *  data to implement than the latter.
- *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
-
-#ifdef __STARTUP_COPY_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of triplets, each of which specify:
- *    offset 0: LMA of start of a section to copy from
- *    offset 4: VMA of start of a section to copy to
- *    offset 8: size of the section to copy. Must be multiply of 4
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r4, =__copy_table_start__
-    ldr    r5, =__copy_table_end__
-
-.L_loop0:
-    cmp    r4, r5
-    bge    .L_loop0_done
-    ldr    r1, [r4]
-    ldr    r2, [r4, #4]
-    ldr    r3, [r4, #8]
-
-.L_loop0_0:
-    subs    r3, #4
-    ittt    ge
-    ldrge    r0, [r1, r3]
-    strge    r0, [r2, r3]
-    bge    .L_loop0_0
-
-    adds    r4, #12
-    b    .L_loop0
-
-.L_loop0_done:
-#else
-/*  Single section scheme.
- *
- *  The ranges of copy from/to are specified by following symbols
- *    __etext: LMA of start of the section to copy from. Usually end of text
- *    __data_start__: VMA of start of the section to copy to
- *    __data_end__: VMA of end of the section to copy to
- *
- *  All addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__etext
-    ldr    r2, =__data_start__
-    ldr    r3, =__data_end__
-
-.L_loop1:
-    cmp    r2, r3
-    ittt    lt
-    ldrlt    r0, [r1], #4
-    strlt    r0, [r2], #4
-    blt    .L_loop1
-#endif /*__STARTUP_COPY_MULTIPLE */
-
-/*  This part of work usually is done in C library startup code. Otherwise,
- *  define this macro to enable it in this startup.
- *
- *  There are two schemes too. One can clear multiple BSS sections. Another
- *  can only clear one section. The former is more size expensive than the
- *  latter.
- *
- *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
- *  Otherwise define macro __STARTUP_CLEAR_BSS to choose the later.
- */
-#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
-/*  Multiple sections scheme.
- *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
- *  there are array of tuples specifying:
- *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
- */
-    ldr    r3, =__zero_table_start__
-    ldr    r4, =__zero_table_end__
-
-.L_loop2:
-    cmp    r3, r4
-    bge    .L_loop2_done
-    ldr    r1, [r3]
-    ldr    r2, [r3, #4]
-    movs    r0, 0
-
-.L_loop2_0:
-    subs    r2, #4
-    itt    ge
-    strge    r0, [r1, r2]
-    bge    .L_loop2_0
-
-    adds    r3, #8
-    b    .L_loop2
-.L_loop2_done:
-#elif defined (__STARTUP_CLEAR_BSS)
-/*  Single BSS section scheme.
- *
- *  The BSS section is specified by following symbols
- *    __bss_start__: start of the BSS section.
- *    __bss_end__: end of the BSS section.
- *
- *  Both addresses must be aligned to 4 bytes boundary.
- */
-    ldr    r1, =__bss_start__
-    ldr    r2, =__bss_end__
-
-    movs    r0, 0
-.L_loop3:
-    cmp    r1, r2
-    itt    lt
-    strlt    r0, [r1], #4
-    blt    .L_loop3
-#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
-
-    /* Update Vector Table Offset Register. */
-    ldr r0, =__ramVectors
-    ldr r1, =CY_CPU_VTOR_ADDR
-    str r0, [r1]
-    dsb 0xF
-
-    /* Enable the FPU if used */
-    bl Cy_SystemInitFpuEnable
-
-    bl    _start
-
-    /* Should never get here */
-    b   .
-
-    .pool
-    .size    Reset_Handler, . - Reset_Handler
-
-    .align    1
-    .thumb_func
-    .weak    Default_Handler
-    .type    Default_Handler, %function
-
-Default_Handler:
-    b    .
-    .size    Default_Handler, . - Default_Handler
-
-
-    .weak    Cy_SysLib_FaultHandler
-    .type    Cy_SysLib_FaultHandler, %function
-    
-Cy_SysLib_FaultHandler:
-    b    .
-    .size    Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler
-    .type Fault_Handler, %function
-
-Fault_Handler:
-    /* Storing LR content for Creator call stack trace */
-    push {LR}
-    movs r0, #4
-    mov r1, LR
-    tst r0, r1
-    beq .L_MSP
-    mrs r0, PSP
-    b .L_API_call
-.L_MSP:
-    mrs r0, MSP
-.L_API_call:
-    /* Compensation of stack pointer address due to pushing 4 bytes of LR */
-    adds r0, r0, #4
-    bl Cy_SysLib_FaultHandler
-    b   .
-    .size    Fault_Handler, . - Fault_Handler
-
-.macro    def_fault_Handler    fault_handler_name
-    .weak    \fault_handler_name
-    .set    \fault_handler_name, Fault_Handler
-    .endm
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro    def_irq_handler    handler_name
-    .weak    \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler    NMI_Handler
-
-    def_fault_Handler HardFault_Handler
-    def_fault_Handler MemManage_Handler
-    def_fault_Handler BusFault_Handler
-    def_fault_Handler UsageFault_Handler
-
-    def_irq_handler    SVC_Handler
-    def_irq_handler    DebugMon_Handler
-    def_irq_handler    PendSV_Handler
-    def_irq_handler    SysTick_Handler
-
-    def_irq_handler  ioss_interrupts_gpio_0_IRQHandler       /* GPIO Port Interrupt #0 */
-    def_irq_handler  ioss_interrupts_gpio_1_IRQHandler       /* GPIO Port Interrupt #1 */
-    def_irq_handler  ioss_interrupts_gpio_2_IRQHandler       /* GPIO Port Interrupt #2 */
-    def_irq_handler  ioss_interrupts_gpio_3_IRQHandler       /* GPIO Port Interrupt #3 */
-    def_irq_handler  ioss_interrupts_gpio_4_IRQHandler       /* GPIO Port Interrupt #4 */
-    def_irq_handler  ioss_interrupts_gpio_5_IRQHandler       /* GPIO Port Interrupt #5 */
-    def_irq_handler  ioss_interrupts_gpio_6_IRQHandler       /* GPIO Port Interrupt #6 */
-    def_irq_handler  ioss_interrupts_gpio_7_IRQHandler       /* GPIO Port Interrupt #7 */
-    def_irq_handler  ioss_interrupts_gpio_8_IRQHandler       /* GPIO Port Interrupt #8 */
-    def_irq_handler  ioss_interrupts_gpio_9_IRQHandler       /* GPIO Port Interrupt #9 */
-    def_irq_handler  ioss_interrupts_gpio_10_IRQHandler      /* GPIO Port Interrupt #10 */
-    def_irq_handler  ioss_interrupts_gpio_11_IRQHandler      /* GPIO Port Interrupt #11 */
-    def_irq_handler  ioss_interrupts_gpio_12_IRQHandler      /* GPIO Port Interrupt #12 */
-    def_irq_handler  ioss_interrupts_gpio_13_IRQHandler      /* GPIO Port Interrupt #13 */
-    def_irq_handler  ioss_interrupts_gpio_14_IRQHandler      /* GPIO Port Interrupt #14 */
-    def_irq_handler  ioss_interrupt_gpio_IRQHandler          /* GPIO All Ports */
-    def_irq_handler  ioss_interrupt_vdd_IRQHandler           /* GPIO Supply Detect Interrupt */
-    def_irq_handler  lpcomp_interrupt_IRQHandler             /* Low Power Comparator Interrupt */
-    def_irq_handler  scb_8_interrupt_IRQHandler              /* Serial Communication Block #8 (DeepSleep capable) */
-    def_irq_handler  srss_interrupt_mcwdt_0_IRQHandler       /* Multi Counter Watchdog Timer interrupt */
-    def_irq_handler  srss_interrupt_mcwdt_1_IRQHandler       /* Multi Counter Watchdog Timer interrupt */
-    def_irq_handler  srss_interrupt_backup_IRQHandler        /* Backup domain interrupt */
-    def_irq_handler  srss_interrupt_IRQHandler               /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
-    def_irq_handler  pass_interrupt_ctbs_IRQHandler          /* CTBm Interrupt (all CTBms) */
-    def_irq_handler  bless_interrupt_IRQHandler              /* Bluetooth Radio interrupt */
-    def_irq_handler  cpuss_interrupts_ipc_0_IRQHandler       /* CPUSS Inter Process Communication Interrupt #0 */
-    def_irq_handler  cpuss_interrupts_ipc_1_IRQHandler       /* CPUSS Inter Process Communication Interrupt #1 */
-    def_irq_handler  cpuss_interrupts_ipc_2_IRQHandler       /* CPUSS Inter Process Communication Interrupt #2 */
-    def_irq_handler  cpuss_interrupts_ipc_3_IRQHandler       /* CPUSS Inter Process Communication Interrupt #3 */
-    def_irq_handler  cpuss_interrupts_ipc_4_IRQHandler       /* CPUSS Inter Process Communication Interrupt #4 */
-    def_irq_handler  cpuss_interrupts_ipc_5_IRQHandler       /* CPUSS Inter Process Communication Interrupt #5 */
-    def_irq_handler  cpuss_interrupts_ipc_6_IRQHandler       /* CPUSS Inter Process Communication Interrupt #6 */
-    def_irq_handler  cpuss_interrupts_ipc_7_IRQHandler       /* CPUSS Inter Process Communication Interrupt #7 */
-    def_irq_handler  cpuss_interrupts_ipc_8_IRQHandler       /* CPUSS Inter Process Communication Interrupt #8 */
-    def_irq_handler  cpuss_interrupts_ipc_9_IRQHandler       /* CPUSS Inter Process Communication Interrupt #9 */
-    def_irq_handler  cpuss_interrupts_ipc_10_IRQHandler      /* CPUSS Inter Process Communication Interrupt #10 */
-    def_irq_handler  cpuss_interrupts_ipc_11_IRQHandler      /* CPUSS Inter Process Communication Interrupt #11 */
-    def_irq_handler  cpuss_interrupts_ipc_12_IRQHandler      /* CPUSS Inter Process Communication Interrupt #12 */
-    def_irq_handler  cpuss_interrupts_ipc_13_IRQHandler      /* CPUSS Inter Process Communication Interrupt #13 */
-    def_irq_handler  cpuss_interrupts_ipc_14_IRQHandler      /* CPUSS Inter Process Communication Interrupt #14 */
-    def_irq_handler  cpuss_interrupts_ipc_15_IRQHandler      /* CPUSS Inter Process Communication Interrupt #15 */
-    def_irq_handler  scb_0_interrupt_IRQHandler              /* Serial Communication Block #0 */
-    def_irq_handler  scb_1_interrupt_IRQHandler              /* Serial Communication Block #1 */
-    def_irq_handler  scb_2_interrupt_IRQHandler              /* Serial Communication Block #2 */
-    def_irq_handler  scb_3_interrupt_IRQHandler              /* Serial Communication Block #3 */
-    def_irq_handler  scb_4_interrupt_IRQHandler              /* Serial Communication Block #4 */
-    def_irq_handler  scb_5_interrupt_IRQHandler              /* Serial Communication Block #5 */
-    def_irq_handler  scb_6_interrupt_IRQHandler              /* Serial Communication Block #6 */
-    def_irq_handler  scb_7_interrupt_IRQHandler              /* Serial Communication Block #7 */
-    def_irq_handler  csd_interrupt_IRQHandler                /* CSD (Capsense) interrupt */
-    def_irq_handler  cpuss_interrupts_dw0_0_IRQHandler       /* CPUSS DataWire #0, Channel #0 */
-    def_irq_handler  cpuss_interrupts_dw0_1_IRQHandler       /* CPUSS DataWire #0, Channel #1 */
-    def_irq_handler  cpuss_interrupts_dw0_2_IRQHandler       /* CPUSS DataWire #0, Channel #2 */
-    def_irq_handler  cpuss_interrupts_dw0_3_IRQHandler       /* CPUSS DataWire #0, Channel #3 */
-    def_irq_handler  cpuss_interrupts_dw0_4_IRQHandler       /* CPUSS DataWire #0, Channel #4 */
-    def_irq_handler  cpuss_interrupts_dw0_5_IRQHandler       /* CPUSS DataWire #0, Channel #5 */
-    def_irq_handler  cpuss_interrupts_dw0_6_IRQHandler       /* CPUSS DataWire #0, Channel #6 */
-    def_irq_handler  cpuss_interrupts_dw0_7_IRQHandler       /* CPUSS DataWire #0, Channel #7 */
-    def_irq_handler  cpuss_interrupts_dw0_8_IRQHandler       /* CPUSS DataWire #0, Channel #8 */
-    def_irq_handler  cpuss_interrupts_dw0_9_IRQHandler       /* CPUSS DataWire #0, Channel #9 */
-    def_irq_handler  cpuss_interrupts_dw0_10_IRQHandler      /* CPUSS DataWire #0, Channel #10 */
-    def_irq_handler  cpuss_interrupts_dw0_11_IRQHandler      /* CPUSS DataWire #0, Channel #11 */
-    def_irq_handler  cpuss_interrupts_dw0_12_IRQHandler      /* CPUSS DataWire #0, Channel #12 */
-    def_irq_handler  cpuss_interrupts_dw0_13_IRQHandler      /* CPUSS DataWire #0, Channel #13 */
-    def_irq_handler  cpuss_interrupts_dw0_14_IRQHandler      /* CPUSS DataWire #0, Channel #14 */
-    def_irq_handler  cpuss_interrupts_dw0_15_IRQHandler      /* CPUSS DataWire #0, Channel #15 */
-    def_irq_handler  cpuss_interrupts_dw1_0_IRQHandler       /* CPUSS DataWire #1, Channel #0 */
-    def_irq_handler  cpuss_interrupts_dw1_1_IRQHandler       /* CPUSS DataWire #1, Channel #1 */
-    def_irq_handler  cpuss_interrupts_dw1_2_IRQHandler       /* CPUSS DataWire #1, Channel #2 */
-    def_irq_handler  cpuss_interrupts_dw1_3_IRQHandler       /* CPUSS DataWire #1, Channel #3 */
-    def_irq_handler  cpuss_interrupts_dw1_4_IRQHandler       /* CPUSS DataWire #1, Channel #4 */
-    def_irq_handler  cpuss_interrupts_dw1_5_IRQHandler       /* CPUSS DataWire #1, Channel #5 */
-    def_irq_handler  cpuss_interrupts_dw1_6_IRQHandler       /* CPUSS DataWire #1, Channel #6 */
-    def_irq_handler  cpuss_interrupts_dw1_7_IRQHandler       /* CPUSS DataWire #1, Channel #7 */
-    def_irq_handler  cpuss_interrupts_dw1_8_IRQHandler       /* CPUSS DataWire #1, Channel #8 */
-    def_irq_handler  cpuss_interrupts_dw1_9_IRQHandler       /* CPUSS DataWire #1, Channel #9 */
-    def_irq_handler  cpuss_interrupts_dw1_10_IRQHandler      /* CPUSS DataWire #1, Channel #10 */
-    def_irq_handler  cpuss_interrupts_dw1_11_IRQHandler      /* CPUSS DataWire #1, Channel #11 */
-    def_irq_handler  cpuss_interrupts_dw1_12_IRQHandler      /* CPUSS DataWire #1, Channel #12 */
-    def_irq_handler  cpuss_interrupts_dw1_13_IRQHandler      /* CPUSS DataWire #1, Channel #13 */
-    def_irq_handler  cpuss_interrupts_dw1_14_IRQHandler      /* CPUSS DataWire #1, Channel #14 */
-    def_irq_handler  cpuss_interrupts_dw1_15_IRQHandler      /* CPUSS DataWire #1, Channel #15 */
-    def_irq_handler  cpuss_interrupts_fault_0_IRQHandler     /* CPUSS Fault Structure Interrupt #0 */
-    def_irq_handler  cpuss_interrupts_fault_1_IRQHandler     /* CPUSS Fault Structure Interrupt #1 */
-    def_irq_handler  cpuss_interrupt_crypto_IRQHandler       /* CRYPTO Accelerator Interrupt */
-    def_irq_handler  cpuss_interrupt_fm_IRQHandler           /* FLASH Macro Interrupt */
-    def_irq_handler  cpuss_interrupts_cm0_cti_0_IRQHandler   /* CM0+ CTI #0 */
-    def_irq_handler  cpuss_interrupts_cm0_cti_1_IRQHandler   /* CM0+ CTI #1 */
-    def_irq_handler  cpuss_interrupts_cm4_cti_0_IRQHandler   /* CM4 CTI #0 */
-    def_irq_handler  cpuss_interrupts_cm4_cti_1_IRQHandler   /* CM4 CTI #1 */
-    def_irq_handler  tcpwm_0_interrupts_0_IRQHandler         /* TCPWM #0, Counter #0 */
-    def_irq_handler  tcpwm_0_interrupts_1_IRQHandler         /* TCPWM #0, Counter #1 */
-    def_irq_handler  tcpwm_0_interrupts_2_IRQHandler         /* TCPWM #0, Counter #2 */
-    def_irq_handler  tcpwm_0_interrupts_3_IRQHandler         /* TCPWM #0, Counter #3 */
-    def_irq_handler  tcpwm_0_interrupts_4_IRQHandler         /* TCPWM #0, Counter #4 */
-    def_irq_handler  tcpwm_0_interrupts_5_IRQHandler         /* TCPWM #0, Counter #5 */
-    def_irq_handler  tcpwm_0_interrupts_6_IRQHandler         /* TCPWM #0, Counter #6 */
-    def_irq_handler  tcpwm_0_interrupts_7_IRQHandler         /* TCPWM #0, Counter #7 */
-    def_irq_handler  tcpwm_1_interrupts_0_IRQHandler         /* TCPWM #1, Counter #0 */
-    def_irq_handler  tcpwm_1_interrupts_1_IRQHandler         /* TCPWM #1, Counter #1 */
-    def_irq_handler  tcpwm_1_interrupts_2_IRQHandler         /* TCPWM #1, Counter #2 */
-    def_irq_handler  tcpwm_1_interrupts_3_IRQHandler         /* TCPWM #1, Counter #3 */
-    def_irq_handler  tcpwm_1_interrupts_4_IRQHandler         /* TCPWM #1, Counter #4 */
-    def_irq_handler  tcpwm_1_interrupts_5_IRQHandler         /* TCPWM #1, Counter #5 */
-    def_irq_handler  tcpwm_1_interrupts_6_IRQHandler         /* TCPWM #1, Counter #6 */
-    def_irq_handler  tcpwm_1_interrupts_7_IRQHandler         /* TCPWM #1, Counter #7 */
-    def_irq_handler  tcpwm_1_interrupts_8_IRQHandler         /* TCPWM #1, Counter #8 */
-    def_irq_handler  tcpwm_1_interrupts_9_IRQHandler         /* TCPWM #1, Counter #9 */
-    def_irq_handler  tcpwm_1_interrupts_10_IRQHandler        /* TCPWM #1, Counter #10 */
-    def_irq_handler  tcpwm_1_interrupts_11_IRQHandler        /* TCPWM #1, Counter #11 */
-    def_irq_handler  tcpwm_1_interrupts_12_IRQHandler        /* TCPWM #1, Counter #12 */
-    def_irq_handler  tcpwm_1_interrupts_13_IRQHandler        /* TCPWM #1, Counter #13 */
-    def_irq_handler  tcpwm_1_interrupts_14_IRQHandler        /* TCPWM #1, Counter #14 */
-    def_irq_handler  tcpwm_1_interrupts_15_IRQHandler        /* TCPWM #1, Counter #15 */
-    def_irq_handler  tcpwm_1_interrupts_16_IRQHandler        /* TCPWM #1, Counter #16 */
-    def_irq_handler  tcpwm_1_interrupts_17_IRQHandler        /* TCPWM #1, Counter #17 */
-    def_irq_handler  tcpwm_1_interrupts_18_IRQHandler        /* TCPWM #1, Counter #18 */
-    def_irq_handler  tcpwm_1_interrupts_19_IRQHandler        /* TCPWM #1, Counter #19 */
-    def_irq_handler  tcpwm_1_interrupts_20_IRQHandler        /* TCPWM #1, Counter #20 */
-    def_irq_handler  tcpwm_1_interrupts_21_IRQHandler        /* TCPWM #1, Counter #21 */
-    def_irq_handler  tcpwm_1_interrupts_22_IRQHandler        /* TCPWM #1, Counter #22 */
-    def_irq_handler  tcpwm_1_interrupts_23_IRQHandler        /* TCPWM #1, Counter #23 */
-    def_irq_handler  udb_interrupts_0_IRQHandler             /* UDB Interrupt #0 */
-    def_irq_handler  udb_interrupts_1_IRQHandler             /* UDB Interrupt #1 */
-    def_irq_handler  udb_interrupts_2_IRQHandler             /* UDB Interrupt #2 */
-    def_irq_handler  udb_interrupts_3_IRQHandler             /* UDB Interrupt #3 */
-    def_irq_handler  udb_interrupts_4_IRQHandler             /* UDB Interrupt #4 */
-    def_irq_handler  udb_interrupts_5_IRQHandler             /* UDB Interrupt #5 */
-    def_irq_handler  udb_interrupts_6_IRQHandler             /* UDB Interrupt #6 */
-    def_irq_handler  udb_interrupts_7_IRQHandler             /* UDB Interrupt #7 */
-    def_irq_handler  udb_interrupts_8_IRQHandler             /* UDB Interrupt #8 */
-    def_irq_handler  udb_interrupts_9_IRQHandler             /* UDB Interrupt #9 */
-    def_irq_handler  udb_interrupts_10_IRQHandler            /* UDB Interrupt #10 */
-    def_irq_handler  udb_interrupts_11_IRQHandler            /* UDB Interrupt #11 */
-    def_irq_handler  udb_interrupts_12_IRQHandler            /* UDB Interrupt #12 */
-    def_irq_handler  udb_interrupts_13_IRQHandler            /* UDB Interrupt #13 */
-    def_irq_handler  udb_interrupts_14_IRQHandler            /* UDB Interrupt #14 */
-    def_irq_handler  udb_interrupts_15_IRQHandler            /* UDB Interrupt #15 */
-    def_irq_handler  pass_interrupt_sar_IRQHandler           /* SAR ADC interrupt */
-    def_irq_handler  audioss_interrupt_i2s_IRQHandler        /* I2S Audio interrupt */
-    def_irq_handler  audioss_interrupt_pdm_IRQHandler        /* PDM/PCM Audio interrupt */
-    def_irq_handler  profile_interrupt_IRQHandler            /* Energy Profiler interrupt */
-    def_irq_handler  smif_interrupt_IRQHandler               /* Serial Memory Interface interrupt */
-    def_irq_handler  usb_interrupt_hi_IRQHandler             /* USB Interrupt */
-    def_irq_handler  usb_interrupt_med_IRQHandler            /* USB Interrupt */
-    def_irq_handler  usb_interrupt_lo_IRQHandler             /* USB Interrupt */
-    def_irq_handler  pass_interrupt_dacs_IRQHandler          /* Consolidated interrrupt for all DACs */
-
-    .end
-
-
-/* [] END OF FILE */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/secure_image_parameters.json

@@ -1,17 +0,0 @@
-{   
-    "boot0" : { 
-        "VERSION" : "0.1",
-        "ROLLBACK_COUNTER" : "0"
-    },
-    
-    "boot1" : {
-        "VERSION" : "0.1",
-        "ROLLBACK_COUNTER" : "0"
-    },
-    
-    "sdk_path" : "targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/",
-    "priv_key_file": "keys/USERAPP_CM4_KEY_PRIV.pem",
-    "aes_key_file": "keys/image-aes-128.key",
-    "dev_pub_key_file": "keys/dev_pub_key.pem",
-    "policy_file": "policy/policy_single_stage_CM4.json"
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -1,36 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg.c
-*
-* Description:
-* Wrapper function to initialize all generated code.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg.h"
-
-void init_cycfg_all(void)
-{
-	init_cycfg_system();
-	init_cycfg_clocks();
-	init_cycfg_routing();
-	init_cycfg_peripherals();
-	init_cycfg_pins();
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -1,49 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg.h
-*
-* Description:
-* Simple wrapper header containing all generated files.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_H)
-#define CYCFG_H
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#include "cycfg_notices.h"
-#include "cycfg_system.h"
-#include "cycfg_clocks.h"
-#include "cycfg_routing.h"
-#include "cycfg_peripherals.h"
-#include "cycfg_pins.h"
-
-void init_cycfg_all(void);
-
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -1,26 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg.timestamp
-*
-* Description:
-* Sentinel file for determining if generated source is up to date.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -1,32 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_notices.h
-*
-* Description:
-* Contains warnings and errors that occurred while generating code for the
-* design.
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_NOTICES_H)
-#define CYCFG_NOTICES_H
-
-
-#endif /* CYCFG_NOTICES_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -1,38 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_peripherals.c
-*
-* Description:
-* Peripheral Hardware Block configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_peripherals.h"
-
-cy_stc_csd_context_t cy_csd_0_context = 
-{
-	.lockKey = CY_CSD_NONE_KEY,
-};
-
-
-void init_cycfg_peripherals(void)
-{
-	Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -1,485 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.c
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_pins.h"
-
-const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_WCO_IN_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_WCO_IN_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_WCO_IN_PORT_NUM,
-		.channel_num = CYBSP_WCO_IN_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_WCO_OUT_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_WCO_OUT_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_WCO_OUT_PORT_NUM,
-		.channel_num = CYBSP_WCO_OUT_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_RX_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_RX_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_RX_PORT_NUM,
-		.channel_num = CYBSP_CSD_RX_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWO_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-	.hsiom = CYBSP_SWO_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SWO_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_SWO_PORT_NUM,
-		.channel_num = CYBSP_SWO_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLUP,
-	.hsiom = CYBSP_SWDIO_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SWDIO_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_SWDIO_PORT_NUM,
-		.channel_num = CYBSP_SWDIO_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_PULLDOWN,
-	.hsiom = CYBSP_SWDCK_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_SWDCK_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_SWDCK_PORT_NUM,
-		.channel_num = CYBSP_SWDCK_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CINA_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CINA_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CINA_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CINA_PORT_NUM,
-		.channel_num = CYBSP_CINA_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CINB_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CINB_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CINB_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CINB_PORT_NUM,
-		.channel_num = CYBSP_CINB_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CMOD_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CMOD_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CMOD_PORT_NUM,
-		.channel_num = CYBSP_CMOD_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_BTN0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_BTN0_PORT_NUM,
-		.channel_num = CYBSP_CSD_BTN0_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_BTN1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_BTN1_PORT_NUM,
-		.channel_num = CYBSP_CSD_BTN1_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_SLD0_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_SLD0_PORT_NUM,
-		.channel_num = CYBSP_CSD_SLD0_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_SLD1_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_SLD1_PORT_NUM,
-		.channel_num = CYBSP_CSD_SLD1_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_SLD2_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_SLD2_PORT_NUM,
-		.channel_num = CYBSP_CSD_SLD2_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_SLD3_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_SLD3_PORT_NUM,
-		.channel_num = CYBSP_CSD_SLD3_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
-{
-	.outVal = 1,
-	.driveMode = CY_GPIO_DM_ANALOG,
-	.hsiom = CYBSP_CSD_SLD4_HSIOM,
-	.intEdge = CY_GPIO_INTR_DISABLE,
-	.intMask = 0UL,
-	.vtrip = CY_GPIO_VTRIP_CMOS,
-	.slewRate = CY_GPIO_SLEW_FAST,
-	.driveSel = CY_GPIO_DRIVE_1_2,
-	.vregEn = 0UL,
-	.ibufMode = 0UL,
-	.vtripSel = 0UL,
-	.vrefSel = 0UL,
-	.vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-	const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
-	{
-		.type = CYHAL_RSC_GPIO,
-		.block_num = CYBSP_CSD_SLD4_PORT_NUM,
-		.channel_num = CYBSP_CSD_SLD4_PIN,
-	};
-#endif //defined (CY_USING_HAL)
-
-
-void init_cycfg_pins(void)
-{
-	Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
-#endif //defined (CY_USING_HAL)
-
-	Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
-#endif //defined (CY_USING_HAL)
-
-#if defined (CY_USING_HAL)
-	cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
-#endif //defined (CY_USING_HAL)
-}

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -1,498 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_pins.h
-*
-* Description:
-* Pin configuration
-* This file was automatically generated and should not be modified.
-* Device Configurator: 2.0.0.1483
-* Device Support Library (../../../psoc6pdl): 1.4.1.2240
-*
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#if !defined(CYCFG_PINS_H)
-#define CYCFG_PINS_H
-
-#include "cycfg_notices.h"
-#include "cy_gpio.h"
-#if defined (CY_USING_HAL)
-	#include "cyhal_hwmgr.h"
-#endif //defined (CY_USING_HAL)
-#include "cycfg_routing.h"
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-#define CYBSP_WCO_IN_ENABLED 1U
-#define CYBSP_WCO_IN_PORT GPIO_PRT0
-#define CYBSP_WCO_IN_PORT_NUM 0U
-#define CYBSP_WCO_IN_PIN 0U
-#define CYBSP_WCO_IN_NUM 0U
-#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_0_HSIOM
-	#define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
-#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_WCO_OUT_ENABLED 1U
-#define CYBSP_WCO_OUT_PORT GPIO_PRT0
-#define CYBSP_WCO_OUT_PORT_NUM 0U
-#define CYBSP_WCO_OUT_PIN 1U
-#define CYBSP_WCO_OUT_NUM 1U
-#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_0_pin_1_HSIOM
-	#define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
-#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_RX_ENABLED 1U
-#define CYBSP_CSD_RX_PORT GPIO_PRT1
-#define CYBSP_CSD_RX_PORT_NUM 1U
-#define CYBSP_CSD_RX_PIN 0U
-#define CYBSP_CSD_RX_NUM 0U
-#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_RX_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_1_pin_0_HSIOM
-	#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM
-#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_RX_HAL_PORT_PIN P1_0
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_SWO_ENABLED 1U
-#define CYBSP_SWO_PORT GPIO_PRT6
-#define CYBSP_SWO_PORT_NUM 6U
-#define CYBSP_SWO_PIN 4U
-#define CYBSP_SWO_NUM 4U
-#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SWO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_4_HSIOM
-	#define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
-#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_PORT_PIN P6_4
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_SWDIO_ENABLED 1U
-#define CYBSP_SWDIO_PORT GPIO_PRT6
-#define CYBSP_SWDIO_PORT_NUM 6U
-#define CYBSP_SWDIO_PIN 6U
-#define CYBSP_SWDIO_NUM 6U
-#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
-#define CYBSP_SWDIO_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_6_HSIOM
-	#define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
-#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_PORT_PIN P6_6
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
-#endif //defined (CY_USING_HAL)
-#define CYBSP_SWDCK_ENABLED 1U
-#define CYBSP_SWDCK_PORT GPIO_PRT6
-#define CYBSP_SWDCK_PORT_NUM 6U
-#define CYBSP_SWDCK_PIN 7U
-#define CYBSP_SWDCK_NUM 7U
-#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
-#define CYBSP_SWDCK_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_6_pin_7_HSIOM
-	#define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
-#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDCK_HAL_PORT_PIN P6_7
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CINA_ENABLED 1U
-#define CYBSP_CINA_PORT GPIO_PRT7
-#define CYBSP_CINA_PORT_NUM 7U
-#define CYBSP_CINA_PIN 1U
-#define CYBSP_CINA_NUM 1U
-#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINA_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_1_HSIOM
-	#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
-#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINA_HAL_PORT_PIN P7_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CINB_ENABLED 1U
-#define CYBSP_CINB_PORT GPIO_PRT7
-#define CYBSP_CINB_PORT_NUM 7U
-#define CYBSP_CINB_PIN 2U
-#define CYBSP_CINB_NUM 2U
-#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CINB_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_2_HSIOM
-	#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
-#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINB_HAL_PORT_PIN P7_2
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CMOD_ENABLED 1U
-#define CYBSP_CMOD_PORT GPIO_PRT7
-#define CYBSP_CMOD_PORT_NUM 7U
-#define CYBSP_CMOD_PIN 7U
-#define CYBSP_CMOD_NUM 7U
-#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CMOD_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_7_pin_7_HSIOM
-	#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
-#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CMOD_HAL_PORT_PIN P7_7
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN0_PORT_NUM 8U
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_1_HSIOM
-	#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_BTN1_ENABLED 1U
-#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
-#define CYBSP_CSD_BTN1_PORT_NUM 8U
-#define CYBSP_CSD_BTN1_PIN 2U
-#define CYBSP_CSD_BTN1_NUM 2U
-#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_2_HSIOM
-	#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
-#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_SLD0_ENABLED 1U
-#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD0_PORT_NUM 8U
-#define CYBSP_CSD_SLD0_PIN 3U
-#define CYBSP_CSD_SLD0_NUM 3U
-#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_3_HSIOM
-	#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
-#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_SLD1_ENABLED 1U
-#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD1_PORT_NUM 8U
-#define CYBSP_CSD_SLD1_PIN 4U
-#define CYBSP_CSD_SLD1_NUM 4U
-#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_4_HSIOM
-	#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
-#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_SLD2_ENABLED 1U
-#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD2_PORT_NUM 8U
-#define CYBSP_CSD_SLD2_PIN 5U
-#define CYBSP_CSD_SLD2_NUM 5U
-#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_5_HSIOM
-	#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
-#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_SLD3_ENABLED 1U
-#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD3_PORT_NUM 8U
-#define CYBSP_CSD_SLD3_PIN 6U
-#define CYBSP_CSD_SLD3_NUM 6U
-#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_6_HSIOM
-	#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
-#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_SLD4_ENABLED 1U
-#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
-#define CYBSP_CSD_SLD4_PORT_NUM 8U
-#define CYBSP_CSD_SLD4_PIN 7U
-#define CYBSP_CSD_SLD4_NUM 7U
-#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
-#ifndef ioss_0_port_8_pin_7_HSIOM
-	#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
-#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-#endif //defined (CY_USING_HAL)
-#if defined (CY_USING_HAL)
-	#define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-#endif //defined (CY_USING_HAL)
-
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SWO_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CINA_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CINB_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
-#if defined (CY_USING_HAL)
-	extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
-#endif //defined (CY_USING_HAL)
-
-void init_cycfg_pins(void);
-
-#if defined(__cplusplus)
-}
-#endif
-
-
-#endif /* CYCFG_PINS_H */

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -1,265 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_qspi_memslot.c
-*
-* Description:
-* Provides definitions of the SMIF-driver memory configuration.
-* This file was automatically generated and should not be modified.
-* 
-********************************************************************************
-* Copyright 2017-2019 Cypress Semiconductor Corporation
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-
-#include "cycfg_qspi_memslot.h"
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xECU,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_QUAD,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0x01U,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_QUAD,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 4U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_QUAD
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x06U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x04U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0xDCU,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x60U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_programCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x34U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_QUAD,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_QUAD
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x35U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x05U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_cmd_t S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd =
-{
-    /* The 8-bit command. 1 x I/O read command. */
-    .command = 0x01U,
-    /* The width of the command transfer. */
-    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The width of the address transfer. */
-    .addrWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
-    .mode = 0xFFFFFFFFU,
-    /* The width of the mode command transfer. */
-    .modeWidth = CY_SMIF_WIDTH_SINGLE,
-    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
-    .dummyCycles = 0U,
-    /* The width of the data transfer. */
-    .dataWidth = CY_SMIF_WIDTH_SINGLE
-};
-
-const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0 =
-{
-    /* Specifies the number of address bytes used by the memory slave device. */
-    .numOfAddrBytes = 0x04U,
-    /* The size of the memory. */
-    .memSize = 0x04000000U,
-    /* Specifies the Read command. */
-    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readCmd,
-    /* Specifies the Write Enable command. */
-    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeEnCmd,
-    /* Specifies the Write Disable command. */
-    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeDisCmd,
-    /* Specifies the Erase command. */
-    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_eraseCmd,
-    /* Specifies the sector size of each erase. */
-    .eraseSize = 0x00040000U,
-    /* Specifies the Chip Erase command. */
-    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_chipEraseCmd,
-    /* Specifies the Program command. */
-    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_programCmd,
-    /* Specifies the page size for programming. */
-    .programSize = 0x00000200U,
-    /* Specifies the command to read the QE-containing status register. */
-    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegQeCmd,
-    /* Specifies the command to read the WIP-containing status register. */
-    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_readStsRegWipCmd,
-    /* Specifies the command to write into the QE-containing status register. */
-    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_4byteaddr_SlaveSlot_0_writeStsRegQeCmd,
-    /* The mask for the status register. */
-    .stsRegBusyMask = 0x01U,
-    /* The mask for the status register. */
-    .stsRegQuadEnableMask = 0x02U,
-    /* The max time for the erase type-1 cycle-time in ms. */
-    .eraseTime = 2600U,
-    /* The max time for the chip-erase cycle-time in ms. */
-    .chipEraseTime = 460000U,
-    /* The max time for the page-program cycle-time in us. */
-    .programTime = 1300U
-};
-
-const cy_stc_smif_mem_config_t S25FL512S_4byteaddr_SlaveSlot_0 =
-{
-    /* Determines the slot number where the memory device is placed. */
-    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
-    /* Flags. */
-    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
-    /* The data-line selection options for a slave device. */
-    .dataSelect = CY_SMIF_DATA_SEL0,
-    /* The base address the memory slave is mapped to in the PSoC memory map.
-    Valid when the memory-mapped mode is enabled. */
-    .baseAddress = 0x18000000U,
-    /* The size allocated in the PSoC memory map, for the memory slave device.
-    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
-    .memMappedSize = 0x4000000U,
-    /* If this memory device is one of the devices in the dual quad SPI configuration.
-    Valid when the memory mapped mode is enabled. */
-    .dualQuadSlots = 0,
-    /* The configuration of the device. */
-    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_4byteaddr_SlaveSlot_0
-};
-
-const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
-   &S25FL512S_4byteaddr_SlaveSlot_0
-};
-
-const cy_stc_smif_block_config_t smifBlockConfig =
-{
-    /* The number of SMIF memories defined. */
-    .memCount = CY_SMIF_DEVICE_NUM,
-    /* The pointer to the array of memory config structures of size memCount. */
-    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
-    /* The version of the SMIF driver. */
-    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
-    /* The version of the SMIF driver. */
-    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
-};
-