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Merge pull request #13165 from MarceloSalazar/musca_a1 

Remove Musca A1 target
pull/13173/head
Martin Kojtal 2020-06-22 16:32:01 +02:00 committed by GitHub
parent 107d9bbf8a dbbdb3f5bd
commit b4389c7805
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GPG Key ID: 4AEE18F83AFDEB23
51 changed files with 0 additions and 8304 deletions
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2
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/LICENSE
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Unless specifically indicated otherwise in a file, MUSCA_A1 files in this directory are licensed under the BSD-3-Clause license,
as can be found in: LICENSE-bsd-3-clause.txt

26
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/LICENSE-BSD-3-Clause
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Copyright 2020 Arm Limited and affiliates.
SPDX-License-Identifier: BSD-3-Clause
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.

49
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/LICENSE-permissive-binary-license-1.0.txt
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Permissive Binary License
Version 1.0, December 2018
Redistribution. Redistribution and use in binary form, without
modification, are permitted provided that the following conditions are
met:
1) Redistributions must reproduce the above copyright notice and the
following disclaimer in the documentation and/or other materials
provided with the distribution.
2) Unless to the extent explicitly permitted by law, no reverse
engineering, decompilation, or disassembly of this software is
permitted.
3) Redistribution as part of a software development kit must include the
accompanying file named DEPENDENCIES and any dependencies listed in
that file.
4) Neither the name of the copyright holder nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
Limited patent license. The copyright holders (and contributors) grant a
worldwide, non-exclusive, no-charge, royalty-free patent license to
make, have made, use, offer to sell, sell, import, and otherwise
transfer this software, where such license applies only to those patent
claims licensable by the copyright holders (and contributors) that are
necessarily infringed by this software. This patent license shall not
apply to any combinations that include this software. No hardware is
licensed hereunder.
If you institute patent litigation against any entity (including a
cross-claim or counterclaim in a lawsuit) alleging that the software
itself infringes your patent(s), then your rights granted under this
license shall terminate as of the date such litigation is filed.
DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

48
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PORTNUM_0 = 0
} PortName;
typedef enum {
UART_0 = 0,
UART_1
} UARTName;
#define STDIO_UART_TX UART1_TX
#define STDIO_UART_RX UART1_RX
#define STDIO_UART UART_1
#define USBTX STDIO_UART_TX
#define USBRX STDIO_UART_RX
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
PA0 = 0,
PA1 = 1,
PA2 = 2,
PA3 = 3,
PA4 = 4,
PA5 = 5,
PA6 = 6,
PA7 = 7,
PA8 = 8,
PA9 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
/* Arduino Connector Namings */
D0 = PA0,
D1 = PA1,
D2 = PA2,
D3 = PA3,
D4 = PA4,
D5 = PA5,
D6 = PA6,
D7 = PA7,
D8 = PA8,
D9 = PA9,
D10 = PA10,
D11 = PA11,
D12 = PA12,
D13 = PA13,
D14 = PA14,
D15 = PA15,
/* UART pins */
UART0_RX = PA0, /* Alternate Function - 1 */
UART0_TX = PA1, /* Alternate Function - 1 */
UART1_RX = PA16,
UART1_TX = PA17,
LED1 = PA2,
LED2 = PA3,
LED3 = PA4,
/* Not connected */
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PRIMARY_FUNC = 0,
ALTERNATE_FUNC_1 = 1,
ALTERNATE_FUNC_2 = 2,
ALTERNATE_FUNC_3 = 3
} PinFunction;
typedef enum {
PullNone = 0,
PullUp,
PullDown,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/README.md
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# MUSCA_A1_NS prebuilt secure binaries
This directory tree contains Secure images released under Permissive Binary License.
Built by mbed-cli using GNU Arm Embedded - version 6.3.1
These images were compiled by the following command:
## mcuboot.bin
### Repository
https://github.com/ARMmbed/trusted-firmware-m.git
### Commit SHA
Contained in `features/FEATURE_PSA/TARGET_TFM/VERSION.txt`
```sh
cmake ../ -G"Unix Makefiles" -DTARGET_PLATFORM=MUSCA_A -DCOMPILER=ARMCLANG -DCMAKE_BUILD_TYPE=Debug
make
```
## tfm.bin
```sh
mbed compile -t GCC_ARM -m ARM_MUSCA_A1_S --app-config tools/psa/tfm/mbed_app.json --profile release
```
To update the prebuilt binaries run the previous commands.

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device.h
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_ARMC6/musca_ns.sct
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#! armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -xc
/*
* Copyright (c) 2019 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "../../partition/region_defs.h"
#include "../cmsis_nvic.h"
#if !defined(MBED_ROM_START)
#define MBED_ROM_START NS_CODE_START // 0x000a0400
#endif
#if !defined(MBED_ROM_SIZE)
#define MBED_ROM_SIZE NS_CODE_SIZE // 0x5f800
#endif
#if !defined(MBED_RAM_START)
#define MBED_RAM_START NS_DATA_START
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE NS_DATA_SIZE
#endif
#define VECTOR_SIZE NVIC_RAM_VECTOR_SIZE
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_CODE MBED_ROM_START MBED_ROM_SIZE {
ER_CODE MBED_ROM_START MBED_ROM_SIZE {
*.o (VECTOR +First)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) {
* (+RW) ; RW data that gets copied from Flash to SRAM
* (+ZI) ; ZI data that gets initialised to zero in SRAM
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

240
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_ARMC6/startup_cmsdk_musca_ns.S
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;/*
; * Copyright (c) 2019 ARM Limited
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;
; This file is derivative of CMSIS V5.01 startup_ARMv8MML.s
; Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; Vector Table Mapped to Address 0 at Reset
AREA VECTOR, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors ;Core Interrupts
DCD |Image$$ARM_LIB_STACK$$ZI$$Limit|; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
;SSE-200 Interrupts
DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
DCD 0 ; 9: Reserved
DCD 0 ; 10: Reserved
DCD 0 ; 11: Reserved
DCD 0 ; 12: Reserved
DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
DCD 0 ; 14: Reserved
DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
DCD 0 ; 21: Reserved
DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
DCD 0 ; 27: Reserved
DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
DCD 0 ; 30: Reserved
DCD 0 ; 31: Reserved
;Expansion Interrupts
DCD 0 ; 32: Reserved
DCD GpTimer_IRQHandler ; 33: General Purpose Timer
DCD I2C0_IRQHandler ; 34: I2C0
DCD I2C1_IRQHandler ; 35: I2C1
DCD I2S_IRQHandler ; 36: I2S
DCD SPI_IRQHandler ; 37: SPI
DCD QSPI_IRQHandler ; 38: QSPI
DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
DCD UART0_IRQHandler ; 44: UART0 interrupt
DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
DCD UART1_IRQHandler ; 50: UART0 interrupt
DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
DCD Combined_IRQHandler ; 67: Combined interrupt
DCD PVT_IRQHandler ; 68: PVT sensor interrupt
DCD 0 ; 69: Reserved
DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
DCD RTC_IRQHandler ; 71: RTC interrupt
DCD GpTimer1_IRQHandler ; 72: General Purpose Timer1
DCD GpTimer0_IRQHandler ; 73: General Purpose Timer0
DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
; Reset Handler
AREA RESET, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
End_Of_Main
B .
; Dummy Exception Handlers (infinite loops which can be modified)
MACRO
Default_Handler $handler_name
$handler_name PROC
EXPORT $handler_name [WEAK]
B .
ENDP
MEND
Default_Handler NMI_Handler
Default_Handler HardFault_Handler
Default_Handler MemManage_Handler
Default_Handler BusFault_Handler
Default_Handler UsageFault_Handler
Default_Handler SVC_Handler
Default_Handler DebugMon_Handler
Default_Handler PendSV_Handler
Default_Handler SysTick_Handler
Default_Handler NS_WATCHDOG_RESET_IRQHandler
Default_Handler NS_WATCHDOG_IRQHandler
Default_Handler S32K_TIMER_IRQHandler
Default_Handler TIMER0_IRQHandler
Default_Handler TIMER1_IRQHandler
Default_Handler DUALTIMER_IRQHandler
Default_Handler MHU0_IRQHandler
Default_Handler MHU1_IRQHandler
Default_Handler CRYPTOCELL_IRQHandler
Default_Handler I_CACHE_INV_ERR_IRQHandler
Default_Handler SYS_PPU_IRQHandler
Default_Handler CPU0_PPU_IRQHandler
Default_Handler CPU1_PPU_IRQHandler
Default_Handler CPU0_DGB_PPU_IRQHandler
Default_Handler CPU1_DGB_PPU_IRQHandler
Default_Handler CRYPTOCELL_PPU_IRQHandler
Default_Handler RAM0_PPU_IRQHandler
Default_Handler RAM1_PPU_IRQHandler
Default_Handler RAM2_PPU_IRQHandler
Default_Handler RAM3_PPU_IRQHandler
Default_Handler DEBUG_PPU_IRQHandler
Default_Handler CPU0_CTI_IRQHandler
Default_Handler CPU1_CTI_IRQHandler
Default_Handler GpTimer_IRQHandler
Default_Handler I2C0_IRQHandler
Default_Handler I2C1_IRQHandler
Default_Handler I2S_IRQHandler
Default_Handler SPI_IRQHandler
Default_Handler QSPI_IRQHandler
Default_Handler UARTRX0_Handler
Default_Handler UARTTX0_Handler
Default_Handler UART0_RxTimeout_IRQHandler
Default_Handler UART0_ModemStatus_IRQHandler
Default_Handler UART0_Error_IRQHandler
Default_Handler UART0_IRQHandler
Default_Handler UARTRX1_Handler
Default_Handler UARTTX1_Handler
Default_Handler UART1_RxTimeout_IRQHandler
Default_Handler UART1_ModemStatus_IRQHandler
Default_Handler UART1_Error_IRQHandler
Default_Handler UART1_IRQHandler
Default_Handler GPIO_0_IRQHandler
Default_Handler GPIO_1_IRQHandler
Default_Handler GPIO_2_IRQHandler
Default_Handler GPIO_3_IRQHandler
Default_Handler GPIO_4_IRQHandler
Default_Handler GPIO_5_IRQHandler
Default_Handler GPIO_6_IRQHandler
Default_Handler GPIO_7_IRQHandler
Default_Handler GPIO_8_IRQHandler
Default_Handler GPIO_9_IRQHandler
Default_Handler GPIO_10_IRQHandler
Default_Handler GPIO_11_IRQHandler
Default_Handler GPIO_12_IRQHandler
Default_Handler GPIO_13_IRQHandler
Default_Handler GPIO_14_IRQHandler
Default_Handler GPIO_15_IRQHandler
Default_Handler Combined_IRQHandler
Default_Handler PVT_IRQHandler
Default_Handler PWM_0_IRQHandler
Default_Handler RTC_IRQHandler
Default_Handler GpTimer1_IRQHandler
Default_Handler GpTimer0_IRQHandler
Default_Handler PWM_1_IRQHandler
Default_Handler PWM_2_IRQHandler
Default_Handler IOMUX_IRQHandler
ALIGN
END

197
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_GCC_ARM/musca_ns.ld
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;/*
; * Copyright (c) 2019 ARM Limited
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; *
; * This file is derivative of CMSIS V5.00 gcc_arm.ld
; */
/* Linker script to configure memory regions. */
/* This file will be run trough the pre-processor. */
#include "../../partition/region_defs.h"
#include "../cmsis_nvic.h"
/* Stack size is 1K for Mbed-OS */
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
MEMORY
{
FLASH (rx) : ORIGIN = NS_CODE_START, LENGTH = NS_CODE_SIZE
/* Vector table is copied to RAM, so RAM address needs to be adjusted */
RAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_LIMIT, LENGTH = (NS_DATA_SIZE - NVIC_RAM_VECTOR_SIZE)
}
__stack_size__ = MBED_BOOT_STACK_SIZE;
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.vectors))
__Vectors_End = .;
__Vectors_Size = __Vectors_End - __Vectors;
__end__ = .;
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
* define etext2/data2_start/data2_end and
* define __STARTUP_COPY_MULTIPLE in startup_cmsdk_musca_ns.S */
.copy.table :
{
. = ALIGN(4);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (DEFINED(__etext2) ? __etext2 : 0)
LONG (DEFINED(__data2_start__) ? __data2_start__ : 0)
LONG (DEFINED(__data2_start__) ? __data2_end__ - __data2_start__ : 0)
__copy_table_end__ = .;
} > FLASH
/* To clear multiple BSS sections,
* uncomment .zero.table section and,
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_cmsdk_musca_ns.S */
.zero.table :
{
. = ALIGN(4);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (DEFINED(__bss2_start__) ? __bss2_start__ : 0)
LONG (DEFINED(__bss2_start__) ? __bss2_end__ - __bss2_start__ : 0)
__zero_table_end__ = .;
} > FLASH
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
bss_size = __bss_end__ - __bss_start__;
.stack :
{
. = ALIGN(8);
__StackLimit = .;
KEEP(*(.stack*))
. += __stack_size__;
__StackTop = .;
} > RAM
PROVIDE(__stack = __StackTop);
.heap (COPY):
{
. = ALIGN(8);
__HeapBase = .;
__end__ = .;
end = __end__;
KEEP(*(.heap*))
. += (ORIGIN(RAM) + LENGTH(RAM) - .);
__HeapLimit = .;
__heap_limit = .; /* Add for _sbrk */
} > RAM
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackTop <= (NS_DATA_START + NS_DATA_SIZE), "RAM region overflowed")
}

355
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_GCC_ARM/startup_cmsdk_musca_ns.S
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@ -1,355 +0,0 @@
;/*
; * Copyright (c) 2019 ARM Limited
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the "License");
; * you may not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * http://www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an "AS IS" BASIS,
; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; *
; * This file is derivative of CMSIS V5.00 startup_ARMCM33.S
; */
.syntax unified
.arch armv8-m.main
.section .vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* Core interrupts */
.long NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
.long NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
.long S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
.long TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
.long TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
.long DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
.long MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
.long MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
.long CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
.long 0 /* 9: Reserved */
.long 0 /* 10: Reserved */
.long 0 /* 11: Reserved */
.long 0 /* 12: Reserved */
.long I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
.long 0 /* 14: Reserved */
.long SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
.long CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
.long CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
.long CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
.long CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
.long CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
.long 0 /* 21: Reserved */
.long RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
.long RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
.long RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
.long RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
.long DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
.long 0 /* 27: Reserved */
.long CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
.long CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
.long 0 /* 30: Reserved */
.long 0 /* 31: Reserved */
/* External interrupts */
.long 0 /* 32: Reserved */
.long GpTimer_IRQHandler /* 33: General Purpose Timer */
.long I2C0_IRQHandler /* 34: I2C0 */
.long I2C1_IRQHandler /* 35: I2C1 */
.long I2S_IRQHandler /* 36: I2S */
.long SPI_IRQHandler /* 37: SPI */
.long QSPI_IRQHandler /* 38: QSPI */
.long UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
.long UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
.long UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
.long UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
.long UART0_Error_IRQHandler /* 43: UART0 error interrupt */
.long UART0_IRQHandler /* 44: UART0 interrupt */
.long UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
.long UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
.long UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
.long UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
.long UART1_Error_IRQHandler /* 49: UART0 error interrupt */
.long UART1_IRQHandler /* 50: UART0 interrupt */
.long GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
.long GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
.long GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
.long GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
.long GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
.long GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
.long GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
.long GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
.long GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
.long GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
.long GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
.long GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
.long GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
.long GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
.long GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
.long GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
.long Combined_IRQHandler /* 67: Combined interrupt */
.long PVT_IRQHandler /* 68: PVT sensor interrupt */
.long 0 /* 69: Reserved */
.long PWM_0_IRQHandler /* 70: PWM0 interrupt */
.long RTC_IRQHandler /* 71: RTC interrupt */
.long GpTimer1_IRQHandler /* 72: General Purpose Timer0 */
.long GpTimer0_IRQHandler /* 73: General Purpose Timer1 */
.long PWM_1_IRQHandler /* 74: PWM1 interrupt */
.long PWM_2_IRQHandler /* 75: PWM2 interrupt */
.long IOMUX_IRQHandler /* 76: IOMUX interrupt */
.size __Vectors, . - __Vectors
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Firstly it copies data from read only memory to RAM. There are two schemes
* to copy. One can copy more than one sections. Another can only copy
* one section. The former scheme needs more instructions and read-only
* data to implement than the latter.
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
#ifdef __STARTUP_COPY_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of triplets, each of which specify:
* offset 0: LMA of start of a section to copy from
* offset 4: VMA of start of a section to copy to
* offset 8: size of the section to copy. Must be multiply of 4
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
#else
/* Single section scheme.
*
* The ranges of copy from/to are specified by following symbols
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to
* __data_end__: VMA of end of the section to copy to
*
* All addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
.L_loop1:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
blt .L_loop1
#endif /*__STARTUP_COPY_MULTIPLE */
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* There are two schemes too. One can clear multiple BSS sections. Another
* can only clear one section. The former is more size expensive than the
* latter.
*
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
*/
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
/* Multiple sections scheme.
*
* Between symbol address __copy_table_start__ and __copy_table_end__,
* there are array of tuples specifying:
* offset 0: Start of a BSS section
* offset 4: Size of this BSS section. Must be multiply of 4
*/
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
#elif defined (__STARTUP_CLEAR_BSS)
/* Single BSS section scheme.
*
* The BSS section is specified by following symbols
* __bss_start__: start of the BSS section.
* __bss_end__: end of the BSS section.
*
* Both addresses must be aligned to 4 bytes boundary.
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
movs r0, 0
.L_loop3:
cmp r1, r2
itt lt
strlt r0, [r1], #4
blt .L_loop3
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
#ifndef __NO_SYSTEM_INIT
bl SystemInit
#endif
#ifndef __START
#define __START _start
#endif
bl __START
.pool
.size Reset_Handler, . - Reset_Handler
/* Macro to define default handlers. */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
\handler_name:
b \handler_name
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler MemManage_Handler
def_irq_handler BusFault_Handler
def_irq_handler UsageFault_Handler
def_irq_handler SVC_Handler
def_irq_handler DebugMon_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
/* Core interrupts */
def_irq_handler NS_WATCHDOG_RESET_IRQHandler /* 0: Non-Secure Watchdog Reset Request Interrupt */
def_irq_handler NS_WATCHDOG_IRQHandler /* 1: Non-Secure Watchdog Interrupt */
def_irq_handler S32K_TIMER_IRQHandler /* 2: S32K Timer Interrupt */
def_irq_handler TIMER0_IRQHandler /* 3: CMSDK Timer 0 Interrupt */
def_irq_handler TIMER1_IRQHandler /* 4: CMSDK Timer 1 Interrupt */
def_irq_handler DUALTIMER_IRQHandler /* 5: CMSDK Dual Timer Interrupt */
def_irq_handler MHU0_IRQHandler /* 6: Message Handling Unit 0 Interrupt */
def_irq_handler MHU1_IRQHandler /* 7: Message Handling Unit 1 Interrupt */
def_irq_handler CRYPTOCELL_IRQHandler /* 8: CryptoCell-312 Interrupt */
def_irq_handler I_CACHE_INV_ERR_IRQHandler /* 13: Intsruction Cache Invalidation Interrupt */
def_irq_handler SYS_PPU_IRQHandler /* 15: System PPU Interrupt */
def_irq_handler CPU0_PPU_IRQHandler /* 16: CPU0 PPU Interrupt */
def_irq_handler CPU1_PPU_IRQHandler /* 17: CPU1 PPU Interrupt */
def_irq_handler CPU0_DGB_PPU_IRQHandler /* 18: CPU0 Debug PPU Interrupt */
def_irq_handler CPU1_DGB_PPU_IRQHandler /* 19: CPU1 Debug PPU Interrupt */
def_irq_handler CRYPTOCELL_PPU_IRQHandler /* 20: CryptoCell PPU Interrupt */
def_irq_handler RAM0_PPU_IRQHandler /* 22: RAM 0 PPU Interrupt */
def_irq_handler RAM1_PPU_IRQHandler /* 23: RAM 1 PPU Interrupt */
def_irq_handler RAM2_PPU_IRQHandler /* 24: RAM 2 PPU Interrupt */
def_irq_handler RAM3_PPU_IRQHandler /* 25: RAM 3 PPU Interrupt */
def_irq_handler DEBUG_PPU_IRQHandler /* 26: Debug PPU Interrupt */
def_irq_handler CPU0_CTI_IRQHandler /* 28: CPU0 CTI Interrupt */
def_irq_handler CPU1_CTI_IRQHandler /* 29: CPU1 CTI Interrupt */
/* External interrupts */
def_irq_handler GpTimer_IRQHandler /* 33: General Purpose Timer */
def_irq_handler I2C0_IRQHandler /* 34: I2C0 */
def_irq_handler I2C1_IRQHandler /* 35: I2C1 */
def_irq_handler I2S_IRQHandler /* 36: I2S */
def_irq_handler SPI_IRQHandler /* 37: SPI */
def_irq_handler QSPI_IRQHandler /* 38: QSPI */
def_irq_handler UARTRX0_Handler /* 39: UART0 receive FIFO interrupt */
def_irq_handler UARTTX0_Handler /* 40: UART0 transmit FIFO interrupt */
def_irq_handler UART0_RxTimeout_IRQHandler /* 41: UART0 receive timeout interrupt */
def_irq_handler UART0_ModemStatus_IRQHandler /* 42: UART0 modem status interrupt */
def_irq_handler UART0_Error_IRQHandler /* 43: UART0 error interrupt */
def_irq_handler UART0_IRQHandler /* 44: UART0 interrupt */
def_irq_handler UARTRX1_Handler /* 45: UART0 receive FIFO interrupt */
def_irq_handler UARTTX1_Handler /* 46: UART0 transmit FIFO interrupt */
def_irq_handler UART1_RxTimeout_IRQHandler /* 47: UART0 receive timeout interrupt */
def_irq_handler UART1_ModemStatus_IRQHandler /* 48: UART0 modem status interrupt */
def_irq_handler UART1_Error_IRQHandler /* 49: UART0 error interrupt */
def_irq_handler UART1_IRQHandler /* 50: UART0 interrupt */
def_irq_handler GPIO_0_IRQHandler /* 51: GPIO 0 interrupt */
def_irq_handler GPIO_1_IRQHandler /* 52: GPIO 1 interrupt */
def_irq_handler GPIO_2_IRQHandler /* 53: GPIO 2 interrupt */
def_irq_handler GPIO_3_IRQHandler /* 54: GPIO 3 interrupt */
def_irq_handler GPIO_4_IRQHandler /* 55: GPIO 4 interrupt */
def_irq_handler GPIO_5_IRQHandler /* 56: GPIO 5 interrupt */
def_irq_handler GPIO_6_IRQHandler /* 57: GPIO 6 interrupt */
def_irq_handler GPIO_7_IRQHandler /* 58: GPIO 7 interrupt */
def_irq_handler GPIO_8_IRQHandler /* 59: GPIO 8 interrupt */
def_irq_handler GPIO_9_IRQHandler /* 60: GPIO 9 interrupt */
def_irq_handler GPIO_10_IRQHandler /* 61: GPIO 10 interrupt */
def_irq_handler GPIO_11_IRQHandler /* 62: GPIO 11 interrupt */
def_irq_handler GPIO_12_IRQHandler /* 63: GPIO 12 interrupt */
def_irq_handler GPIO_13_IRQHandler /* 64: GPIO 13 interrupt */
def_irq_handler GPIO_14_IRQHandler /* 65: GPIO 14 interrupt */
def_irq_handler GPIO_15_IRQHandler /* 66: GPIO 15 interrupt */
def_irq_handler Combined_IRQHandler /* 67: Combined interrupt */
def_irq_handler PVT_IRQHandler /* 68: PVT sensor interrupt */
def_irq_handler PWM_0_IRQHandler /* 70: PWM0 interrupt */
def_irq_handler RTC_IRQHandler /* 71: RTC interrupt */
def_irq_handler GpTimer1_IRQHandler /* 72: General Purpose Timer0 */
def_irq_handler GpTimer0_IRQHandler /* 73: General Purpose Timer1 */
def_irq_handler PWM_1_IRQHandler /* 74: PWM1 interrupt */
def_irq_handler PWM_2_IRQHandler /* 75: PWM2 interrupt */
def_irq_handler IOMUX_IRQHandler /* 76: IOMUX interrupt */
.end

112
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_IAR/musca_ns.icf
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@ -1,112 +0,0 @@
/*
* Copyright (c) 2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License) you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
define symbol NS_CODE_START = 0x000a0400;
define symbol NS_CODE_SIZE = 0x0005f800;
define symbol NS_DATA_START = 0x20011000;
define symbol NS_DATA_SIZE = 0x0000f000;
define symbol __ram_vector_table__ = 1;
if (!isdefinedsymbol(MBED_ROM_START)) {
define symbol MBED_ROM_START = NS_CODE_START;
}
if (!isdefinedsymbol(MBED_APP_START)) {
define symbol MBED_APP_START = MBED_ROM_START;
}
if (!isdefinedsymbol(MBED_ROM_SIZE)) {
define symbol MBED_ROM_SIZE = NS_CODE_SIZE;
}
if (!isdefinedsymbol(MBED_APP_SIZE)) {
define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
}
if (!isdefinedsymbol(MBED_RAM_START)) {
define symbol MBED_RAM_START = NS_DATA_START;
}
if (!isdefinedsymbol(MBED_RAM_SIZE)) {
define symbol MBED_RAM_SIZE = NS_DATA_SIZE;
}
if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
define symbol MBED_BOOT_STACK_SIZE = 0x400;
}
define symbol __stack_size__ = MBED_BOOT_STACK_SIZE;
define symbol __heap_size__ = 0x4000;
define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000200 : 0;
define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000001FF : 0;
/* Stack and Heap Sizes */
if (isdefinedsymbol(__stack_size__)) {
define symbol __size_cstack__ = __stack_size__;
} else {
define symbol __size_cstack__ = 0x0400;
}
if (isdefinedsymbol(__heap_size__)) {
define symbol __size_heap__ = __heap_size__;
} else {
define symbol __size_heap__ = 0x0400;
}
define symbol m_interrupts_start = MBED_APP_START;
define symbol m_interrupts_end = (MBED_APP_START + 0x16F);
define symbol m_text_start = (MBED_APP_START + 0x170);
define symbol m_text_end = (MBED_APP_START + MBED_APP_SIZE - 1);
define symbol m_interrupts_ram_start = MBED_RAM_START;
define symbol m_interrupts_ram_end = (MBED_RAM_START + __ram_vector_table_size__ - 1);
define symbol m_data_start = (m_interrupts_ram_start + __ram_vector_table_size__);
define symbol m_data_end = (MBED_RAM_START + MBED_RAM_SIZE - 1);
define exported symbol __VECTOR_TABLE = m_interrupts_start;
define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
| mem:[from m_text_start to m_text_end];
define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block RW { readwrite };
define block ZI { zi };
initialize by copy { readwrite, section .textrw };
do not initialize { section .noinit };
place at address mem: m_interrupts_start { readonly section .intvec };
place in TEXT_region { readonly };
place in DATA_region { block RW };
place in DATA_region { block ZI };
place in DATA_region { last block HEAP };
place in CSTACK_region { block CSTACK };
place in m_interrupts_ram_region { section m_interrupts_ram };

736
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/TOOLCHAIN_IAR/startup_cmsdk_musca_ns.S
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; mbed Microcontroller Library
; Copyright (c) 2019 ARM Limited
; SPDX-License-Identifier: Apache-2.0
;
; Licensed under the Apache License, Version 2.0 (the "License");
; you may not use this file except in compliance with the License.
; You may obtain a copy of the License at
;
; http://www.apache.org/licenses/LICENSE-2.0
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
PUBLIC __vector_table_0x1c
PUBLIC __Vectors
PUBLIC __Vectors_End
PUBLIC __Vectors_Size
DATA
__vector_table
; Core Interrupts
DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
__vector_table_0x1c
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; SSE-200 Interrupts
DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
DCD 0 ; 9: Reserved
DCD 0 ; 10: Reserved
DCD 0 ; 11: Reserved
DCD 0 ; 12: Reserved
DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
DCD 0 ; 14: Reserved
DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
DCD 0 ; 21: Reserved
DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
DCD 0 ; 27: Reserved
DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
DCD 0 ; 30: Reserved
DCD 0 ; 31: Reserved
;Expansion Interrupts
DCD 0 ; 32: Reserved
DCD GpTimer_IRQHandler ; 33: General Purpose Timer
DCD I2C0_IRQHandler ; 34: I2C0
DCD I2C1_IRQHandler ; 35: I2C1
DCD I2S_IRQHandler ; 36: I2S
DCD SPI_IRQHandler ; 37: SPI
DCD QSPI_IRQHandler ; 38: QSPI
DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
DCD UART0_IRQHandler ; 44: UART0 interrupt
DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
DCD UART1_IRQHandler ; 50: UART0 interrupt
DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
DCD Combined_IRQHandler ; 67: Combined interrupt
DCD PVT_IRQHandler ; 68: PVT sensor interrupt
DCD 0 ; 69: Reserved
DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
DCD RTC_IRQHandler ; 71: RTC interrupt
DCD GpTimer1_IRQHandler ; 72: General Purpose Timer1
DCD GpTimer0_IRQHandler ; 73: General Purpose Timer0
DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
__Vectors_End
__Vectors EQU __vector_table
__Vectors_Size EQU __Vectors_End - __Vectors
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
CPSID I ; Mask interrupts
LDR R0, =sfb(CSTACK)
MSR MSPLIM, R0
LDR R0, =SystemInit
BLX R0
CPSIE I ; Unmask interrupts
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B .
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B .
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B .
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B .
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B .
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B .
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B .
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B .
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B .
PUBWEAK NS_WATCHDOG_RESET_IRQHandler
PUBWEAK NS_WATCHDOG_RESET_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
NS_WATCHDOG_RESET_IRQHandler
LDR R0, =NS_WATCHDOG_RESET_DriverIRQHandler
BX R0
PUBWEAK NS_WATCHDOG_IRQHandler
PUBWEAK NS_WATCHDOG_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
NS_WATCHDOG_IRQHandler
LDR R0, =NS_WATCHDOG_DriverIRQHandler
BX R0
PUBWEAK S32K_TIMER_IRQHandler
PUBWEAK S32K_TIMER_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
S32K_TIMER_IRQHandler
LDR R0, =S32K_TIMER_DriverIRQHandler
BX R0
PUBWEAK TIMER0_IRQHandler
PUBWEAK TIMER0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
TIMER0_IRQHandler
LDR R0, =TIMER0_DriverIRQHandler
BX R0
PUBWEAK TIMER1_IRQHandler
PUBWEAK TIMER1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
TIMER1_IRQHandler
LDR R0, =TIMER1_DriverIRQHandler
BX R0
PUBWEAK DUALTIMER_IRQHandler
PUBWEAK DUALTIMER_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DUALTIMER_IRQHandler
LDR R0, =DUALTIMER_DriverIRQHandler
BX R0
PUBWEAK MHU0_IRQHandler
PUBWEAK MHU0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
MHU0_IRQHandler
LDR R0, =MHU0_DriverIRQHandler
BX R0
PUBWEAK MHU1_IRQHandler
PUBWEAK MHU1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
MHU1_IRQHandler
LDR R0, =MHU1_DriverIRQHandler
BX R0
PUBWEAK CRYPTOCELL_IRQHandler
PUBWEAK CRYPTOCELL_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CRYPTOCELL_IRQHandler
LDR R0, =CRYPTOCELL_DriverIRQHandler
BX R0
PUBWEAK I_CACHE_INV_ERR_IRQHandler
PUBWEAK I_CACHE_INV_ERR_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I_CACHE_INV_ERR_IRQHandler
LDR R0, =I_CACHE_INV_ERR_DriverIRQHandler
BX R0
PUBWEAK SYS_PPU_IRQHandler
PUBWEAK SYS_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SYS_PPU_IRQHandler
LDR R0, =SYS_PPU_DriverIRQHandler
BX R0
PUBWEAK CPU0_PPU_IRQHandler
PUBWEAK CPU0_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CPU0_PPU_IRQHandler
LDR R0, =CPU0_PPU_DriverIRQHandler
BX R0
PUBWEAK CPU1_PPU_IRQHandler
PUBWEAK CPU1_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CPU1_PPU_IRQHandler
LDR R0, =CPU1_PPU_DriverIRQHandler
BX R0
PUBWEAK CPU0_DGB_PPU_IRQHandler
PUBWEAK CPU0_DGB_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CPU0_DGB_PPU_IRQHandler
LDR R0, =CPU0_DGB_PPU_DriverIRQHandler
BX R0
PUBWEAK CPU1_DGB_PPU_IRQHandler
PUBWEAK CPU1_DGB_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CPU1_DGB_PPU_IRQHandler
LDR R0, =CPU1_DGB_PPU_DriverIRQHandler
BX R0
PUBWEAK CRYPTOCELL_PPU_IRQHandler
PUBWEAK CRYPTOCELL_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CRYPTOCELL_PPU_IRQHandler
LDR R0, =CRYPTOCELL_PPU_DriverIRQHandler
BX R0
PUBWEAK RAM0_PPU_IRQHandler
PUBWEAK RAM0_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
RAM0_PPU_IRQHandler
LDR R0, =RAM0_PPU_DriverIRQHandler
BX R0
PUBWEAK RAM1_PPU_IRQHandler
PUBWEAK RAM1_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
RAM1_PPU_IRQHandler
LDR R0, =RAM1_PPU_DriverIRQHandler
BX R0
PUBWEAK RAM2_PPU_IRQHandler
PUBWEAK RAM2_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
RAM2_PPU_IRQHandler
LDR R0, =RAM2_PPU_DriverIRQHandler
BX R0
PUBWEAK RAM3_PPU_IRQHandler
PUBWEAK RAM3_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
RAM3_PPU_IRQHandler
LDR R0, =RAM3_PPU_DriverIRQHandler
BX R0
PUBWEAK DEBUG_PPU_IRQHandler
PUBWEAK DEBUG_PPU_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
DEBUG_PPU_IRQHandler
LDR R0, =DEBUG_PPU_DriverIRQHandler
BX R0
PUBWEAK CPU0_CTI_IRQHandler
PUBWEAK CPU0_CTI_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CPU0_CTI_IRQHandler
LDR R0, =CPU0_CTI_DriverIRQHandler
BX R0
PUBWEAK CPU1_CTI_IRQHandler
PUBWEAK CPU1_CTI_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
CPU1_CTI_IRQHandler
LDR R0, =CPU1_CTI_DriverIRQHandler
BX R0
PUBWEAK GpTimer_IRQHandler
PUBWEAK GpTimer_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GpTimer_IRQHandler
LDR R0, =GpTimer_DriverIRQHandler
BX R0
PUBWEAK I2C0_IRQHandler
PUBWEAK I2C0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C0_IRQHandler
LDR R0, =I2C0_DriverIRQHandler
BX R0
PUBWEAK I2C1_IRQHandler
PUBWEAK I2C1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2C1_IRQHandler
LDR R0, =I2C1_DriverIRQHandler
BX R0
PUBWEAK I2S_IRQHandler
PUBWEAK I2S_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
I2S_IRQHandler
LDR R0, =I2S_DriverIRQHandler
BX R0
PUBWEAK SPI_IRQHandler
PUBWEAK SPI_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
SPI_IRQHandler
LDR R0, =SPI_DriverIRQHandler
BX R0
PUBWEAK QSPI_IRQHandler
PUBWEAK QSPI_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
QSPI_IRQHandler
LDR R0, =QSPI_DriverIRQHandler
BX R0
PUBWEAK UARTRX0_Handler
PUBWEAK UARTRX0_DriverHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UARTRX0_Handler
LDR R0, =UARTRX0_DriverHandler
BX R0
PUBWEAK UARTTX0_Handler
PUBWEAK UARTTX0_DriverHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UARTTX0_Handler
LDR R0, =UARTTX0_DriverHandler
BX R0
PUBWEAK UART0_RxTimeout_IRQHandler
PUBWEAK UART0_RxTimeout_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART0_RxTimeout_IRQHandler
LDR R0, =UART0_RxTimeout_DriverIRQHandler
BX R0
PUBWEAK UART0_ModemStatus_IRQHandler
PUBWEAK UART0_ModemStatus_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART0_ModemStatus_IRQHandler
LDR R0, =UART0_ModemStatus_DriverIRQHandler
BX R0
PUBWEAK UART0_Error_IRQHandler
PUBWEAK UART0_Error_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART0_Error_IRQHandler
LDR R0, =UART0_Error_DriverIRQHandler
BX R0
PUBWEAK UART0_IRQHandler
PUBWEAK UART0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART0_IRQHandler
LDR R0, =UART0_DriverIRQHandler
BX R0
PUBWEAK UARTRX1_Handler
PUBWEAK UARTRX1_DriverHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UARTRX1_Handler
LDR R0, =UARTRX1_DriverHandler
BX R0
PUBWEAK UARTTX1_Handler
PUBWEAK UARTTX1_DriverHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UARTTX1_Handler
LDR R0, =UARTTX1_DriverHandler
BX R0
PUBWEAK UART1_RxTimeout_IRQHandler
PUBWEAK UART1_RxTimeout_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART1_RxTimeout_IRQHandler
LDR R0, =UART1_RxTimeout_DriverIRQHandler
BX R0
PUBWEAK UART1_ModemStatus_IRQHandler
PUBWEAK UART1_ModemStatus_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART1_ModemStatus_IRQHandler
LDR R0, =UART1_ModemStatus_DriverIRQHandler
BX R0
PUBWEAK UART1_Error_IRQHandler
PUBWEAK UART1_Error_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART1_Error_IRQHandler
LDR R0, =UART1_Error_DriverIRQHandler
BX R0
PUBWEAK UART1_IRQHandler
PUBWEAK UART1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
UART1_IRQHandler
LDR R0, =UART1_DriverIRQHandler
BX R0
PUBWEAK GPIO_0_IRQHandler
PUBWEAK GPIO_0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_0_IRQHandler
LDR R0, =GPIO_0_DriverIRQHandler
BX R0
PUBWEAK GPIO_1_IRQHandler
PUBWEAK GPIO_1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_1_IRQHandler
LDR R0, =GPIO_1_DriverIRQHandler
BX R0
PUBWEAK GPIO_2_IRQHandler
PUBWEAK GPIO_2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_2_IRQHandler
LDR R0, =GPIO_2_DriverIRQHandler
BX R0
PUBWEAK GPIO_3_IRQHandler
PUBWEAK GPIO_3_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_3_IRQHandler
LDR R0, =GPIO_3_DriverIRQHandler
BX R0
PUBWEAK GPIO_4_IRQHandler
PUBWEAK GPIO_4_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_4_IRQHandler
LDR R0, =GPIO_4_DriverIRQHandler
BX R0
PUBWEAK GPIO_5_IRQHandler
PUBWEAK GPIO_5_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_5_IRQHandler
LDR R0, =GPIO_5_DriverIRQHandler
BX R0
PUBWEAK GPIO_6_IRQHandler
PUBWEAK GPIO_6_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_6_IRQHandler
LDR R0, =GPIO_6_DriverIRQHandler
BX R0
PUBWEAK GPIO_7_IRQHandler
PUBWEAK GPIO_7_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_7_IRQHandler
LDR R0, =GPIO_7_DriverIRQHandler
BX R0
PUBWEAK GPIO_8_IRQHandler
PUBWEAK GPIO_8_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_8_IRQHandler
LDR R0, =GPIO_8_DriverIRQHandler
BX R0
PUBWEAK GPIO_9_IRQHandler
PUBWEAK GPIO_9_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_9_IRQHandler
LDR R0, =GPIO_9_DriverIRQHandler
BX R0
PUBWEAK GPIO_10_IRQHandler
PUBWEAK GPIO_10_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_10_IRQHandler
LDR R0, =GPIO_10_DriverIRQHandler
BX R0
PUBWEAK GPIO_11_IRQHandler
PUBWEAK GPIO_11_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_11_IRQHandler
LDR R0, =GPIO_11_DriverIRQHandler
BX R0
PUBWEAK GPIO_12_IRQHandler
PUBWEAK GPIO_12_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_12_IRQHandler
LDR R0, =GPIO_12_DriverIRQHandler
BX R0
PUBWEAK GPIO_13_IRQHandler
PUBWEAK GPIO_13_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_13_IRQHandler
LDR R0, =GPIO_13_DriverIRQHandler
BX R0
PUBWEAK GPIO_14_IRQHandler
PUBWEAK GPIO_14_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_14_IRQHandler
LDR R0, =GPIO_14_DriverIRQHandler
BX R0
PUBWEAK GPIO_15_IRQHandler
PUBWEAK GPIO_15_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GPIO_15_IRQHandler
LDR R0, =GPIO_15_DriverIRQHandler
BX R0
PUBWEAK Combined_IRQHandler
PUBWEAK Combined_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
Combined_IRQHandler
LDR R0, =Combined_DriverIRQHandler
BX R0
PUBWEAK PVT_IRQHandler
PUBWEAK PVT_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
PVT_IRQHandler
LDR R0, =PVT_DriverIRQHandler
BX R0
PUBWEAK PWM_0_IRQHandler
PUBWEAK PWM_0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
PWM_0_IRQHandler
LDR R0, =PWM_0_DriverIRQHandler
BX R0
PUBWEAK RTC_IRQHandler
PUBWEAK RTC_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
RTC_IRQHandler
LDR R0, =RTC_DriverIRQHandler
BX R0
PUBWEAK GpTimer1_IRQHandler
PUBWEAK GpTimer1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GpTimer1_IRQHandler
LDR R0, =GpTimer1_DriverIRQHandler
BX R0
PUBWEAK GpTimer0_IRQHandler
PUBWEAK GpTimer0_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
GpTimer0_IRQHandler
LDR R0, =GpTimer0_DriverIRQHandler
BX R0
PUBWEAK PWM_1_IRQHandler
PUBWEAK PWM_1_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
PWM_1_IRQHandler
LDR R0, =PWM_1_DriverIRQHandler
BX R0
PUBWEAK PWM_2_IRQHandler
PUBWEAK PWM_2_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
PWM_2_IRQHandler
LDR R0, =PWM_2_DriverIRQHandler
BX R0
PUBWEAK IOMUX_IRQHandler
PUBWEAK IOMUX_DriverIRQHandler
SECTION .text:CODE:REORDER:NOROOT(2)
IOMUX_IRQHandler
LDR R0, =IOMUX_DriverIRQHandler
BX R0
NS_WATCHDOG_RESET_DriverIRQHandler
NS_WATCHDOG_DriverIRQHandler
S32K_TIMER_DriverIRQHandler
TIMER0_DriverIRQHandler
TIMER1_DriverIRQHandler
DUALTIMER_DriverIRQHandler
MHU0_DriverIRQHandler
MHU1_DriverIRQHandler
CRYPTOCELL_DriverIRQHandler
I_CACHE_INV_ERR_DriverIRQHandler
SYS_PPU_DriverIRQHandler
CPU0_PPU_DriverIRQHandler
CPU1_PPU_DriverIRQHandler
CPU0_DGB_PPU_DriverIRQHandler
CPU1_DGB_PPU_DriverIRQHandler
CRYPTOCELL_PPU_DriverIRQHandler
RAM0_PPU_DriverIRQHandler
RAM1_PPU_DriverIRQHandler
RAM2_PPU_DriverIRQHandler
RAM3_PPU_DriverIRQHandler
DEBUG_PPU_DriverIRQHandler
CPU0_CTI_DriverIRQHandler
CPU1_CTI_DriverIRQHandler
GpTimer_DriverIRQHandler
I2C0_DriverIRQHandler
I2C1_DriverIRQHandler
I2S_DriverIRQHandler
SPI_DriverIRQHandler
QSPI_DriverIRQHandler
UARTRX0_DriverHandler
UARTTX0_DriverHandler
UART0_RxTimeout_DriverIRQHandler
UART0_ModemStatus_DriverIRQHandler
UART0_Error_DriverIRQHandler
UART0_DriverIRQHandler
UARTRX1_DriverHandler
UARTTX1_DriverHandler
UART1_RxTimeout_DriverIRQHandler
UART1_ModemStatus_DriverIRQHandler
UART1_Error_DriverIRQHandler
UART1_DriverIRQHandler
GPIO_0_DriverIRQHandler
GPIO_1_DriverIRQHandler
GPIO_2_DriverIRQHandler
GPIO_3_DriverIRQHandler
GPIO_4_DriverIRQHandler
GPIO_5_DriverIRQHandler
GPIO_6_DriverIRQHandler
GPIO_7_DriverIRQHandler
GPIO_8_DriverIRQHandler
GPIO_9_DriverIRQHandler
GPIO_10_DriverIRQHandler
GPIO_11_DriverIRQHandler
GPIO_12_DriverIRQHandler
GPIO_13_DriverIRQHandler
GPIO_14_DriverIRQHandler
GPIO_15_DriverIRQHandler
Combined_DriverIRQHandler
PVT_DriverIRQHandler
PWM_0_DriverIRQHandler
RTC_DriverIRQHandler
GpTimer1_DriverIRQHandler
GpTimer0_DriverIRQHandler
PWM_1_DriverIRQHandler
PWM_2_DriverIRQHandler
IOMUX_DriverIRQHandler
DefaultISR
B .
END

32
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/cmsis.h
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@ -1,32 +0,0 @@
/*
* Copyright (c) 2019 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __MUSCA_CMSIS_H__
#define __MUSCA_CMSIS_H__
/* CMSIS wrapper for Musca board */
#include "system_cmsdk_musca.h"
#include "platform_regs.h" /* Platform registers */
#include "platform_retarget.h" /* Peripherals base addresses */
#if defined(TARGET_MUSCA_A1_NS)
#include "cmsis_nvic.h"
#endif
#endif /*__MUSCA_CMSIS_H__ */

25
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/cmsis_cpu.h
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@ -1,25 +0,0 @@
/*
* Copyright (c) 2018 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_CPU_H__
#define __CMSIS_CPU_H__
#include "system_core_musca.h"
#include "core_cm33.h"
#endif /* __CMSIS_CPU_H__ */

35
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/cmsis_nvic.h
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@ -1,35 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is included from the linker script,
* limited set of C constructs can be used here
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "../partition/region_defs.h"
#define NVIC_NUM_VECTORS (16 + 76)
/** Location of vectors to move in RAM */
#define NVIC_RAM_VECTOR_ADDRESS NS_DATA_START
#define NVIC_RAM_VECTOR_SIZE (NVIC_NUM_VECTORS * 4)
#define NVIC_RAM_VECTOR_LIMIT (NVIC_RAM_VECTOR_ADDRESS + NVIC_RAM_VECTOR_SIZE)
#endif

85
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/device_cfg.h
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@ -1,85 +0,0 @@
/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __ARM_LTD_DEVICE_CFG_H__
#define __ARM_LTD_DEVICE_CFG_H__
/**
* \file device_cfg.h
* \brief Configuration file native driver re-targeting
*
* \details This file can be used to add native driver specific macro
* definitions to select which peripherals are available in the build.
*
* This is a default device configuration file with all peripherals enabled.
*/
/* ARM SCC */
#define MUSCA_A1_SCC_NS
#define MUSCA_A1_SCC_DEV MUSCA_A1_SCC_DEV_NS
/*ARM UART Controller PL011*/
#define UART0_PL011_NS
#define UART0_PL011_DEV UART0_PL011_DEV_NS
#define uart0_tx_irq_handler UARTTX0_Handler
#define uart0_rx_irq_handler UARTRX0_Handler
#define uart0_rx_timeout_irq_handler UART0_RxTimeout_IRQHandler
#define UART1_PL011_NS
#define UART1_PL011_DEV UART1_PL011_DEV_NS
#define uart1_tx_irq_handler UARTTX1_Handler
#define uart1_rx_irq_handler UARTRX1_Handler
#define uart1_rx_timeout_irq_handler UART1_RxTimeout_IRQHandler
/* CMSDK Timers */
#define CMSDK_TIMER0_NS
#define CMSDK_TIMER0_DEV CMSDK_TIMER0_DEV_NS
#define CMSDK_TIMER1_NS
/* GP Timer */
#define GP_TIMER_NS
#define GP_TIMER_DEV GP_TIMER_DEV_NS
#define GP_TIMER_ALARM0_IRQ GpTimer0_IRQn
#define GP_TIMER_IRQ0_HANDLER GpTimer0_IRQHandler
#define GP_TIMER_ALARM_NR TIMER_GP_READ_ALARM_0
#define GP_TIMER_FREQ_HZ 32768UL /* System Ref Clock */
#define GP_TIMER_BIT_WIDTH 32U
/**
* mbed usec high-resolution ticker configuration
*/
#define USEC_TIMER_DEV CMSDK_TIMER0_DEV_NS
#define usec_interval_irq_handler TIMER0_IRQHandler
#define USEC_INTERVAL_IRQ TIMER0_IRQn
/** Timer frequency is equal to SYSTEM_CLOCK, defined in system_cmsdk_musca.c */
#define TIMER_FREQ_HZ 50000000U
/** The us Ticker uses CMSDK Timer, that does not have HW prescaler.
* The reported shift define is necessary for the software emulated
* prescaler behavior, so the ticker works as if it was ticking on a
* virtually slower frequency. The value 5 sets up the ticker to work
* properly in the specified frequency interval.
*/
#define USEC_REPORTED_SHIFT 6
#define USEC_REPORTED_FREQ_HZ (TIMER_FREQ_HZ >> USEC_REPORTED_SHIFT)
#define USEC_REPORTED_BITS (32 - USEC_REPORTED_SHIFT)
#define DEFAULT_UART_BAUDRATE 9600U
#endif /* __ARM_LTD_DEVICE_CFG_H__ */

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/drivers/musca_a1_scc_drv.c
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/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "musca_a1_scc_drv.h"
struct musca_a1_scc_reg_map_t {
volatile uint32_t reset_ctrl; /* 0x00 RW Reset Control Register */
volatile uint32_t clk_ctrl; /* 0x04 RW Clock Control Register*/
volatile uint32_t pwr_ctrl; /* 0x08 RW Power Control Register*/
volatile uint32_t pll_ctrl; /* 0x0C RW Power Control Register */
volatile uint32_t dbg_ctrl; /* 0x10 RW Debug Control Register */
volatile uint32_t sram_ctrl; /* 0x14 RW SRAM Control Register */
volatile uint32_t intr_ctrl; /* 0x18 RW Interupt Control Register */
volatile uint32_t reserved1; /* 0x1C RW reserved */
volatile uint32_t cpu0_vtor_sram; /* 0x20 RW Reset vector for CPU0 Secure Mode */
volatile uint32_t cpu0_vtor_flash; /* 0x24 RW Reset vector for CPU0 Secure Mode */
volatile uint32_t cpu1_vtor_sram; /* 0x28 RW Reset vector for CPU1 Secure Mode */
volatile uint32_t cpu1_vtor_flash; /* 0x2C RW Reset vector for CPU0 Secure Mode */
volatile uint32_t iomux_main_insel; /* 0x30 RW Main function in data select */
volatile uint32_t iomux_main_outsel; /* 0x34 RW Main function out data select */
volatile uint32_t iomux_main_oensel; /* 0x38 RW Main function out enable select */
volatile uint32_t iomux_main_default_in; /* 0x3C RW Main function default in select */
volatile uint32_t iomux_altf1_insel; /* 0x40 RW Alt function 1 in data select */
volatile uint32_t iomux_altf1_outsel; /* 0x44 RW Alt function 1 out data select */
volatile uint32_t iomux_altf1_oensel; /* 0x48 RW Alt function 1 out enable select */
volatile uint32_t iomux_altf1_default_in; /* 0x4C RW Alt function 1 default in select */
volatile uint32_t iomux_altf2_insel; /* 0x50 RW Alt function 2 in data select */
volatile uint32_t iomux_altf2_outsel; /* 0x54 RW Alt function 2 out data select */
volatile uint32_t iomux_altf2_oensel; /* 0x58 RW Alt function 2 out enable select */
volatile uint32_t iomux_altf2_default_in; /* 0x5C RW Alt function 2 default in select */
volatile uint32_t pvt_ctrl; /* 0x60 RW PVT control register */
volatile uint32_t spare0; /* 0x64 RW reserved */
volatile uint32_t iopad_ds0; /* 0x68 RW Drive Select 0 */
volatile uint32_t iopad_ds1; /* 0x6C RW Drive Select 1 */
volatile uint32_t iopad_pe; /* 0x70 RW Pull Enable */
volatile uint32_t iopad_ps; /* 0x74 RW Pull Select */
volatile uint32_t iopad_sr; /* 0x78 RW Slew Select */
volatile uint32_t iopad_is; /* 0x7C RW Input Select */
volatile uint32_t sram_rw_margine; /* 0x80 RW reserved */
volatile uint32_t static_conf_sig0; /* 0x84 RW Static configuration */
volatile uint32_t static_conf_sig1; /* 0x88 RW Static configuration */
volatile uint32_t req_set; /* 0x8C RW External Event Enable */
volatile uint32_t req_clear; /* 0x90 RW External Event Clear */
volatile uint32_t iomux_altf3_insel; /* 0x94 RW Alt function 3 in data select */
volatile uint32_t iomux_altf3_outsel; /* 0x98 RW Alt function 3 out data select */
volatile uint32_t iomux_altf3_oensel; /* 0x9C RW Alt function 3 out enable select */
volatile uint32_t iomux_altf3_default_in; /* 0xA0 RW Alt function 3 default in select */
volatile uint32_t pcsm_ctrl_override; /* 0xA4 RW Q-Channels QACTIVE Override */
volatile uint32_t pd_cpu0_iso_override; /* 0xA8 RW CPU0 Isolation Override */
volatile uint32_t pd_cpu1_iso_override; /* 0xAC RW CPU1 Isolation Override */
volatile uint32_t sys_sram_rw_assist0; /* 0xB0 RW CPU0 icache sram ldata */
volatile uint32_t sys_sram_rw_assist1; /* 0xB4 RW CPU0 icache sram tag */
volatile uint32_t sys_sram_rw_assist2; /* 0xB8 RW CPU1 icache sram ldata */
volatile uint32_t sys_sram_rw_assist3; /* 0xBC RW CPU1 icache sram tag */
volatile uint32_t sys_sram_rw_assist4; /* 0xC0 RW System sram */
volatile uint32_t sys_sram_rw_assist5; /* 0xC4 RW System sram */
volatile uint32_t reserved2[3]; /* reserved */
volatile uint32_t crypto_sram_rw_assist0; /* 0xD4 RW Crypto ram */
volatile uint32_t crypto_sram_rw_assist1; /* 0xD8 RW Crypto sec sram */
volatile uint32_t crypto_sram_rw_assist2; /* 0xDC RW Reserved */
volatile uint32_t req_edge_sel; /* 0xC0 RW Power clock request edge select */
volatile uint32_t req_enable; /* 0xC4 RW Power clock request enable */
volatile uint32_t reserved3[28]; /* reserved */
volatile uint32_t chip_id; /* 0x100 RO Chip ID 0x0797_0477 */
volatile uint32_t clock_status; /* 0x104 RO Clock status */
volatile uint32_t io_in_status; /* 0x108 RO I/O in status */
};
/**
* \brief Clears selected alternate functions for selected pins
*
* \param[in] dev SCC registers base address \ref musca_a1_scc_reg_map_t
* \param[in] func_mask Bitmask of alternate functions to clear
* \ref gpio_altfunc_mask_t
* \param[in] pin_mask Pin mask for the alternate functions
*/
static void scc_clear_alt_func(struct musca_a1_scc_reg_map_t* scc_regs,
enum gpio_altfunc_mask_t func_mask,
uint32_t pin_mask)
{
if (func_mask & GPIO_MAIN_FUNC_MASK) {
scc_regs->iomux_main_insel &= ~pin_mask;
scc_regs->iomux_main_outsel &= ~pin_mask;
scc_regs->iomux_main_oensel &= ~pin_mask;
}
if (func_mask & GPIO_ALTFUNC_1_MASK) {
scc_regs->iomux_altf1_insel &= ~pin_mask;
scc_regs->iomux_altf1_outsel &= ~pin_mask;
scc_regs->iomux_altf1_oensel &= ~pin_mask;
}
if (func_mask & GPIO_ALTFUNC_2_MASK) {
scc_regs->iomux_altf2_insel &= ~pin_mask;
scc_regs->iomux_altf2_outsel &= ~pin_mask;
scc_regs->iomux_altf2_oensel &= ~pin_mask;
}
if (func_mask & GPIO_ALTFUNC_3_MASK) {
scc_regs->iomux_altf3_insel &= ~pin_mask;
scc_regs->iomux_altf3_outsel &= ~pin_mask;
scc_regs->iomux_altf3_oensel &= ~pin_mask;
}
}
void musca_a1_scc_set_alt_func(struct musca_a1_scc_dev_t* dev,
enum gpio_altfunc_t altfunc, uint32_t pin_mask)
{
struct musca_a1_scc_reg_map_t* scc_regs =
(struct musca_a1_scc_reg_map_t*) dev->cfg->base;
enum gpio_altfunc_mask_t altfunc_to_clear = GPIO_ALTFUNC_NONE;
volatile uint32_t *insel = NULL;
volatile uint32_t *outsel = NULL;
volatile uint32_t *oensel = NULL;
if (altfunc >= GPIO_ALTFUNC_MAX) {
/* If no altfunction is selected, then nothing to do.
* This is possible during init and we do not
* want to change the reset values set by the HW
*/
return;
}
switch (altfunc) {
case GPIO_MAIN_FUNC:
insel = &scc_regs->iomux_main_insel;
outsel = &scc_regs->iomux_main_outsel;
oensel = &scc_regs->iomux_main_oensel;
altfunc_to_clear = GPIO_MAIN_FUNC_NEG_MASK;
break;
case GPIO_ALTFUNC_1:
insel = &scc_regs->iomux_altf1_insel;
outsel = &scc_regs->iomux_altf1_outsel;
oensel = &scc_regs->iomux_altf1_oensel;
altfunc_to_clear = GPIO_ALTFUNC_1_NEG_MASK;
break;
case GPIO_ALTFUNC_2:
insel = &scc_regs->iomux_altf2_insel;
outsel = &scc_regs->iomux_altf2_outsel;
oensel = &scc_regs->iomux_altf2_oensel;
altfunc_to_clear = GPIO_ALTFUNC_2_NEG_MASK;
break;
case GPIO_ALTFUNC_3:
insel = &scc_regs->iomux_altf3_insel;
outsel = &scc_regs->iomux_altf3_outsel;
oensel = &scc_regs->iomux_altf3_oensel;
altfunc_to_clear = GPIO_ALTFUNC_3_NEG_MASK;
break;
default:
break;
}
/* Select the wanted function's output enable bit first.
* This way the output won't be disabled which is desired
* if we switch from output to output function
*/
*oensel |= pin_mask;
/* Clear all alternate function registers which are not selected */
scc_clear_alt_func(scc_regs, altfunc_to_clear, pin_mask);
/* Enable input and output data line */
*insel |= pin_mask;
*outsel |= pin_mask;
}
void musca_a1_scc_set_pinmode(struct musca_a1_scc_dev_t* dev, uint32_t pin_mask,
enum pinmode_select_t mode)
{
struct musca_a1_scc_reg_map_t* scc_regs =
(struct musca_a1_scc_reg_map_t*) dev->cfg->base;
switch (mode) {
case PINMODE_NONE:
scc_regs->iopad_pe &= ~pin_mask;
break;
case PINMODE_PULL_DOWN:
/* If the pull select bit is set to 0 it means pull down */
scc_regs->iopad_ps &= ~pin_mask;
scc_regs->iopad_pe |= pin_mask;
break;
case PINMODE_PULL_UP:
/* If the pull select bit is set to 1 it means pull up */
scc_regs->iopad_ps |= pin_mask;
scc_regs->iopad_pe |= pin_mask;
break;
default:
break;
}
}
void musca_a1_scc_set_default_in(struct musca_a1_scc_dev_t* dev,
enum gpio_altfunc_t altfunc,
uint32_t default_in_mask,
uint32_t default_in_value)
{
struct musca_a1_scc_reg_map_t* scc_regs =
(struct musca_a1_scc_reg_map_t*) dev->cfg->base;
uint32_t iomux_value = 0;
if (altfunc >= GPIO_ALTFUNC_MAX) {
/* If no altfunction is selected, then nothing to do */
return;
}
switch (altfunc) {
case GPIO_MAIN_FUNC:
iomux_value = scc_regs->iomux_main_default_in & ~default_in_mask;
iomux_value |= (default_in_value & default_in_mask);
scc_regs->iomux_main_default_in = iomux_value;
scc_regs->iomux_main_insel = (scc_regs->iomux_main_insel & ~default_in_mask);
break;
case GPIO_ALTFUNC_1:
iomux_value = scc_regs->iomux_altf1_default_in & ~default_in_mask;
iomux_value |= (default_in_value & default_in_mask);
scc_regs->iomux_altf1_default_in = iomux_value;
scc_regs->iomux_altf1_insel = (scc_regs->iomux_altf1_insel & ~default_in_mask);
break;
case GPIO_ALTFUNC_2:
iomux_value = scc_regs->iomux_altf2_default_in & ~default_in_mask;
iomux_value |= (default_in_value & default_in_mask);
scc_regs->iomux_altf2_default_in = iomux_value;
scc_regs->iomux_altf2_insel = (scc_regs->iomux_altf2_insel & ~default_in_mask);
break;
case GPIO_ALTFUNC_3:
iomux_value = scc_regs->iomux_altf3_default_in & ~default_in_mask;
iomux_value |= (default_in_value & default_in_mask);
scc_regs->iomux_altf3_default_in = iomux_value;
scc_regs->iomux_altf3_insel = (scc_regs->iomux_altf3_insel & ~default_in_mask);
break;
default:
break;
}
}

111
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/drivers/musca_a1_scc_drv.h
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/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __MUSCA_A1_SCC_DRV_H__
#define __MUSCA_A1_SCC_DRV_H__
#include <stdint.h>
#include <stddef.h>
/**
* \brief Enum to store alternate function values.
* They are used as shift operand, must be unsigned.
*/
enum gpio_altfunc_t {
GPIO_MAIN_FUNC = 0UL,
GPIO_ALTFUNC_1,
GPIO_ALTFUNC_2,
GPIO_ALTFUNC_3,
GPIO_ALTFUNC_MAX
};
#define GPIO_ALTFUNC_ALL_MASK ((1U << GPIO_ALTFUNC_MAX) - 1)
/**
* \brief Enum to store alternate function mask values.
*/
enum gpio_altfunc_mask_t {
GPIO_ALTFUNC_NONE = 0,
GPIO_MAIN_FUNC_MASK = (1UL << GPIO_MAIN_FUNC),
GPIO_ALTFUNC_1_MASK = (1UL << GPIO_ALTFUNC_1),
GPIO_ALTFUNC_2_MASK = (1UL << GPIO_ALTFUNC_2),
GPIO_ALTFUNC_3_MASK = (1UL << GPIO_ALTFUNC_3),
GPIO_MAIN_FUNC_NEG_MASK = (~GPIO_MAIN_FUNC_MASK & GPIO_ALTFUNC_ALL_MASK),
GPIO_ALTFUNC_1_NEG_MASK = (~GPIO_ALTFUNC_1_MASK & GPIO_ALTFUNC_ALL_MASK),
GPIO_ALTFUNC_2_NEG_MASK = (~GPIO_ALTFUNC_2_MASK & GPIO_ALTFUNC_ALL_MASK),
GPIO_ALTFUNC_3_NEG_MASK = (~GPIO_ALTFUNC_3_MASK & GPIO_ALTFUNC_ALL_MASK)
};
enum pinmode_select_t {
PINMODE_NONE,
PINMODE_PULL_DOWN,
PINMODE_PULL_UP
};
/* MUSCA SCC device configuration structure */
struct musca_a1_scc_dev_cfg_t {
const uint32_t base; /*!< SCC base address */
};
/* MUSCA SCC device structure */
struct musca_a1_scc_dev_t {
const struct musca_a1_scc_dev_cfg_t* const cfg; /*!< SCC configuration */
};
/**
* \brief Sets selected alternate functions for selected pins
*
* \param[in] dev SCC device pointer \ref musca_a1_scc_dev_t
* \param[in] altfunc Alternate function to set \ref gpio_altfunc_t
* \param[in] pin_mask Pin mask for the alternate functions
*
* \note This function doesn't check if scc dev is NULL.
* \note If no alternate function is selected then the function won't do anything
*/
void musca_a1_scc_set_alt_func(struct musca_a1_scc_dev_t* dev,
enum gpio_altfunc_t altfunc, uint32_t pin_mask);
/**
* \brief Sets pinmode for the given pins
*
* \param[in] dev SCC device pointer \ref musca_a1_scc_dev_t
* \param[in] pin_mask Pin mask for the alternate functions
* \param[in] mode Pin mode to set \ref pinmode_select_t
*
* \note This function doesn't check if scc dev is NULL.
*/
void musca_a1_scc_set_pinmode(struct musca_a1_scc_dev_t* dev, uint32_t pin_mask,
enum pinmode_select_t mode);
/**
* \brief Sets default input values for the selected pins
*
* \param[in] dev SCC device pointer \ref musca_a1_scc_dev_t
* \param[in] altfunc The selected alternate function that is set the
* specified default in value \ref gpio_altfunc_t
* \param[in] default_in_mask Pin mask for selecting pins
* \param[in] default_in_value Pin values for the selected pins
*
* \note This function doesn't check if scc_base is NULL.
* \note If no alternate function is selected, the function won't do anything
*/
void musca_a1_scc_set_default_in(struct musca_a1_scc_dev_t* dev,
enum gpio_altfunc_t altfunc,
uint32_t default_in_mask,
uint32_t default_in_value);
#endif /* __MUSCA_A1_SCC_DRV_H__ */

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/drivers/timer_cmsdk_drv.c
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/*
* Copyright (c) 2016-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file timer_cmsdk_drv.c
* \brief Generic driver for CMSDK APB Timers.
* The timer is a 32-bit down-counter with the following features:
* - optional programmable external clock source
* - programmable interrupt source, triggered if counter reaches 0
* - automatic reload if counter reaches 0
*/
#include "timer_cmsdk_drv.h"
/** Setter bit manipulation macro */
#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
/** Clearing bit manipulation macro */
#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
/** Getter bit manipulation macro */
#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
/**
* \brief Timer register map structure
*
*/
struct timer_cmsdk_reg_map_t {
volatile uint32_t ctrl; /* Offset: 0x000 (R/W) control register */
volatile uint32_t value; /* Offset: 0x004 (R/W) current value register */
volatile uint32_t reload; /* Offset: 0x008 (R/W) reload value register */
union {
volatile uint32_t intstatus; /* Offset: 0x00C (R/ ) interrupt
* status register */
volatile uint32_t intclear; /* Offset: 0x00C ( /W) interrupt
* clear register */
}intreg;
};
/**
* \brief CTRL register bit definitions
*
*/
enum ctrl_reg_bits_t{
CTRL_REG_ENUM_ENABLE_INDEX = 0,
CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1,
CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2,
CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3
};
/**
* \brief INTSTATUS/INTCLEAR register bit definitions
*
*/
enum interrupt_reg_bits_t{
INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0
};
void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
if (dev->data->is_initialized == 0) {
register_map->ctrl = 0;
register_map->reload = TIMER_CMSDK_DEFAULT_RELOAD;
dev->data->is_initialized = 1;
}
}
bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev)
{
return dev->data->is_initialized;
}
void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
}
void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
}
bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->ctrl,
CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
}
void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
}
void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
}
bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->ctrl,
CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
}
void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
}
void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
}
bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
}
void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
}
void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
}
bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
}
bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->intreg.intstatus,
INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
}
void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->intreg.intclear,
INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
}
uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return register_map->value;
}
void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev,
uint32_t reload)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
register_map->reload = reload;
}
void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
register_map->value = register_map->reload;
}
uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return register_map->reload;
}
uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev)
{
struct timer_cmsdk_reg_map_t* register_map =
(struct timer_cmsdk_reg_map_t*)dev->cfg->base;
return register_map->reload - register_map->value;
}

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/*
* Copyright (c) 2016-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file timer_cmsdk_drv.h
* \brief Generic driver for CMSDK APB Timers.
* The timer is a 32-bit down-counter with the following features:
* - optional programmable external clock source
* - programmable interrupt source, triggered if counter reaches 0
* - automatic reload if counter reaches 0
*/
#ifndef __TIMER_CMSDK_DRV_H__
#define __TIMER_CMSDK_DRV_H__
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Maximum reload value */
#define TIMER_CMSDK_MAX_RELOAD UINT32_MAX /* max of 32-bit */
#define TIMER_CMSDK_DEFAULT_RELOAD TIMER_CMSDK_MAX_RELOAD
/** CMSDK timer device configuration structure */
struct timer_cmsdk_dev_cfg_t {
const uintptr_t base; /*!< Timer base address */
};
/** CMSDK timer device data structure */
struct timer_cmsdk_dev_data_t {
bool is_initialized; /*!< Indicates if the timer is initialized */
};
/* CMSDK timer device structure */
struct timer_cmsdk_dev_t {
const struct timer_cmsdk_dev_cfg_t* const cfg; /*!< Timer configuration */
struct timer_cmsdk_dev_data_t* const data; /*!< Timer data */
};
/**
* \brief Initializes timer to a known default state, which is:
* - timer disabled
* - timer interrupt disabled
* - clock source set to internal
* - external input disabled
* - reload value maxed out
* Init should be called prior to any other process and
* it's the caller's responsibility to follow proper call order.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Checks if a timer is initialized.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return true if initialized, false otherwise
*/
bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Enables external input, which could be used as clock source
* by calling \ref timer_cmsdk_set_clock_to_external.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Disables external input.
* Make sure if the timer is explicitly wanted to be stopped or set
* the clock source to internal by \ref timer_cmsdk_set_clock_to_internal.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Checks if external input is enabled.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return true if enabled, false otherwise
*/
bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Sets the clock source to internal.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Sets the clock source to external.
* Make sure external input is enabled correspondingly
* by \ref timer_cmsdk_enable_external_input.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Checks if clock source is external input.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return true if external, false if internal
*/
bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Enables timer operation.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Disables the given hardware timer.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Checks if a timer is enabled.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return true if enabled, false otherwise
*/
bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Enables timer interrupt.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Disables timer interrupt.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Checks if a timer interrupt is enabled.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return true if enabled, false otherwise
*/
bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Gets timer interrupt status
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* * \return true if active, false otherwise
*/
bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Clears timer interrupt
* The interrupt request is held until it is cleared.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Reads timer current value.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return Timer value
*/
uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Sets the reload value of the selected timer.
*
* New reload value takes effect when:
* - timer is restarted
* - on timer underflow
* - when timer_cmsdk_reset is called
*
* \note In r1p0 technical reference manual it's incorrectly stated
* writing the reload value automatically sets the current value also.
* r1p1 technical reference manual includes the fix.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
* \param[in] reload Timer reload value to set.
* This is the start value of the 32-bit down counter,
* which automatically reloaded if 0 is reached.
*/
void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev,
uint32_t reload);
/**
* \brief Resets the timer counter to the reload value instantly
* (i.e. without waiting for underflow).
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*/
void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Gets the reload value of the selected timer.
* This is the start value of the 32-bit down counter,
* which is automatically reloaded if 0 is reached by the counter.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return Reload value of the selected timer.
*/
uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev);
/**
* \brief Reads the number of ticks elapsed in the current cycle.
*
* \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
*
* \return Get elapsed number of ticks since last reload was set.
* Elapsed = (Reload value - Current value)
*/
uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev);
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_CMSDK_DRV_H__ */

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/*
* Copyright (c) 2018-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file timer_gp_drv.c
*
* \brief Generic driver for general purpose timer.
*/
#include "timer_gp_drv.h"
/** Setter bit manipulation macro */
#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
/** Clearing bit manipulation macro */
#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
/** Getter bit manipulation macro */
#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
/**
* \brief Timer register map structure
*
*/
struct timer_gp_reg_map_t {
volatile uint32_t reset; /*!< Offset: 0x000 (R/W) Control Reset */
volatile uint32_t irq_mask; /*!< Offset: 0x004 (R/W) Masked Interrupt */
volatile uint32_t irq_clear; /*!< Offset: 0x008 (R/W) Interrupt Clear */
volatile uint32_t reserved; /*!< Offset: 0x00C Reserved */
volatile uint32_t alarm0; /*!< Offset: 0x010 (R/W) Alarm0 data value */
volatile uint32_t alarm1; /*!< Offset: 0x014 (R/W) Alarm1 data value */
volatile uint32_t irq_status; /*!< Offset: 0x018 (R) Raw Interrupt status */
volatile uint32_t counter; /*!< Offset: 0x01C (R) Counter data value */
};
/**
* \brief Reset control register bit identifiers
*
*/
enum reset_reg_bits_t{
RESET_REG_INDEX = 0
/* 1-31: Reserved. Read as zero. Do No Modify (DNM). */
};
void timer_gp_init(const struct timer_gp_dev_t* dev)
{
if (dev->data->is_initialized == false) {
timer_gp_interrupt_disable(dev, TIMER_GP_ALARM_0);
timer_gp_interrupt_clear(dev, TIMER_GP_ALARM_0);
timer_gp_interrupt_disable(dev, TIMER_GP_ALARM_1);
timer_gp_interrupt_clear(dev, TIMER_GP_ALARM_1);
timer_gp_set_alarm_value(dev, TIMER_GP_ALARM_0, dev->data->alarm0_init);
timer_gp_set_alarm_value(dev, TIMER_GP_ALARM_1, dev->data->alarm1_init);
timer_gp_counter_reset(dev);
dev->data->is_initialized = true;
}
}
void timer_gp_counter_reset(const struct timer_gp_dev_t* dev)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->reset, RESET_REG_INDEX);
/* Reset bit is not self-clearing and some pulse width is required
* for successful reset, so we have to check whether the
* timer counter is set to reset value. Until this bit is asserted
* the timer won't be started.
* The timer is running only if the reset bit is cleared.*/
while (timer_gp_get_counter(dev) != TIMER_GP_DEFAULT_RESET)
;
CLR_BIT(register_map->reset, RESET_REG_INDEX);
}
uint32_t timer_gp_get_counter(const struct timer_gp_dev_t* dev)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
return register_map->counter;
}
void timer_gp_interrupt_enable(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
SET_BIT(register_map->irq_mask, alarm);
}
void timer_gp_interrupt_disable(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
CLR_BIT(register_map->irq_mask, alarm);
}
bool timer_gp_interrupt_is_enabled(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->irq_mask, alarm);
}
bool timer_gp_interrupt_is_active(const struct timer_gp_dev_t* dev,
const enum timer_gp_read_alarm_identifier_t alarm)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
return GET_BIT(register_map->irq_status, alarm);
}
void timer_gp_interrupt_clear(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
enum timer_gp_read_alarm_identifier_t read_alarm =
((alarm == TIMER_GP_ALARM_0) ?
(TIMER_GP_READ_ALARM_0) :
(TIMER_GP_READ_ALARM_1));
SET_BIT(register_map->irq_clear, alarm);
/* Clear bit is not self-clearing and some pulse width is required
* for successful interrupt clear, so we have to check whether the
* interrupt is cleared. */
while(timer_gp_interrupt_is_active(dev, read_alarm))
;
CLR_BIT(register_map->irq_clear, alarm);
}
void timer_gp_set_alarm_value(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm,
const uint32_t value)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
if (alarm == TIMER_GP_ALARM_0) {
register_map->alarm0 = value;
} else {
register_map->alarm1 = value;
}
}
uint32_t timer_gp_get_alarm_value(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm)
{
struct timer_gp_reg_map_t* const register_map =
(struct timer_gp_reg_map_t*)dev->cfg->base;
if (alarm == TIMER_GP_ALARM_0) {
return register_map->alarm0;
} else {
return register_map->alarm1;
}
}

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/*
* Copyright (c) 2018-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file timer_gp_drv.h
*
* \brief Generic driver for general purpose timer.
*
* \details
* The free running counter is a 32 bit size counter that counts
* up to 0xFFFFFFFF.
* At this maximum value it wraps around to 0x00000000 and continues
* incrementing.
* Software can reset the counter to default 1 by calling
* \ref timer_gp_counter_reset.
* The counter implements two compare interrupts. When the counter
* reaches compare value "alarm0" or "alarm1" value it can trigger a
* corresponding interrupt.
*/
#ifndef __TIMER_GP_DRV_H__
#define __TIMER_GP_DRV_H__
#include <stdbool.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define TIMER_GP_MAX_VALUE UINT32_MAX /*!< max of 32-bit */
#define TIMER_GP_DEFAULT_RESET 1U
/*!< Counter's reset value will be set at HW level if reset bit is asserted */
/** GP timer device structure */
struct timer_gp_dev_cfg_t {
const uintptr_t base; /*!< Timer base address */
};
/** GP timer device data structure */
struct timer_gp_dev_data_t {
bool is_initialized;
uint32_t alarm0_init; /*!< Alarm0 value will be set by init */
uint32_t alarm1_init; /*!< Alarm1 value will be set by init */
};
/** GP timer device structure */
struct timer_gp_dev_t {
const struct timer_gp_dev_cfg_t* const cfg; /*!< Timer configuration */
struct timer_gp_dev_data_t* const data; /*!< Timer data */
};
/**
* \brief GP Timer alarm number identifiers
*
*/
enum timer_gp_alarm_identifier_t{
TIMER_GP_ALARM_0 = 0,
TIMER_GP_ALARM_1 = 1
};
/**
* \brief GP Timer read alarm number identifiers
*
*/
enum timer_gp_read_alarm_identifier_t{
TIMER_GP_READ_ALARM_0 = 0,
TIMER_GP_READ_ALARM_1 = 1,
TIMER_GP_READ_ALARM_COMBINED = 2
/*!< Combined is asserted if Alarm1 OR Alarm2 is asserted */
};
/**
* \brief Initializes timer to a known default state, which is:
* - interrupts disabled
* - alarm0 and alarm1 set to init value in \ref timer_gp_dev_data_t
* - timer reset to default reset value \ref TIMER_GP_DEFAULT_RESET
* Init should be called prior to any other process and
* it's the caller's responsibility to follow proper call order.
* More than one call results fall through.
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
*/
void timer_gp_init(const struct timer_gp_dev_t* dev);
/**
* \brief Resets the timer counter to 1.
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
*/
void timer_gp_counter_reset(const struct timer_gp_dev_t* dev);
/**
* \brief Read the 32bit free runnning counter's current value
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
*
* \return 32bit counter current value
*/
uint32_t timer_gp_get_counter(const struct timer_gp_dev_t* dev);
/**
* \brief Enable alarm interrupt of the given source
* Note: This function is not interrupt safe.
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source of the interrupt
* \ref timer_gp_alarm_identifier_t
*
*/
void timer_gp_interrupt_enable(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm);
/**
* \brief Disable alarm interrupt of the given source
* Note: This function is not interrupt safe.
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source of the interrupt
* \ref timer_gp_alarm_identifier_t
*
*/
void timer_gp_interrupt_disable(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm);
/**
* \brief Get alarm interrupt enabled status of the given source
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source of the interrupt
* \ref timer_gp_alarm_identifier_t
*
* \return true if enabled, false if not
*/
bool timer_gp_interrupt_is_enabled(const struct timer_gp_dev_t* dev,
const enum
timer_gp_alarm_identifier_t alarm);
/**
* \brief Get alarm interrupt pending status of the given source
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source of the interrupt
* \ref timer_gp_read_alarm_identifier_t
*
* \return true if active, false if not
*/
bool timer_gp_interrupt_is_active(const struct timer_gp_dev_t* dev,
const enum timer_gp_read_alarm_identifier_t alarm);
/**
* \brief Clear alarm interrupt of the given source
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source of the interrupt
* \ref timer_gp_alarm_identifier_t
*
*/
void timer_gp_interrupt_clear(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm);
/**
* \brief Set alarm value of the given source
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source \ref timer_gp_alarm_identifier_t
* \param[in] value When the counter reaches this tick value
* corresponding interrupt status will be asserted.
*/
void timer_gp_set_alarm_value(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm,
const uint32_t value);
/**
* \brief Get alarm value of the given source
*
* \param[in] dev Timer device struct \ref timer_gp_dev_t
* \param[in] alarm Alarm source \ref timer_gp_alarm_identifier_t
*
* \return value Counter value when the alarm is asserted.
*/
uint32_t timer_gp_get_alarm_value(const struct timer_gp_dev_t* dev,
const enum timer_gp_alarm_identifier_t alarm);
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_GP_DRV_H__ */

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/*
* Copyright (c) 2016-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file uart_pl011_drv.h
* \brief Driver for ARM UART PL011.
*/
#ifndef __UART_PL011_DRV_H__
#define __UART_PL011_DRV_H__
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ARM UART PL011 state types
*/
enum uart_pl011_state_t {
UART_PL011_UNINITIALIZED = 0x0u,
UART_PL011_INITIALIZED = 0x1u,
};
#define UART_PL011_UARTRSR_FE_ERR_OFF 0x0u
/*!< Receive Status Register Frame Error bit field offset */
#define UART_PL011_UARTRSR_PE_ERR_OFF 0x1u
/*!< Receive Status Register Parity Error bit field offset */
#define UART_PL011_UARTRSR_BE_ERR_OFF 0x2u
/*!< Receive Status Register Break Error bit field offset */
#define UART_PL011_UARTRSR_OE_ERR_OFF 0x3u
/*!< Receive Status Register Overrun Error bit field offset */
#define UART_PL011_RX_ERR_MASK ( \
0x1u<<UART_PL011_UARTRSR_FE_ERR_OFF \
| 0x1u<<UART_PL011_UARTRSR_PE_ERR_OFF \
| 0x1u<<UART_PL011_UARTRSR_BE_ERR_OFF \
| 0x1u<<UART_PL011_UARTRSR_OE_ERR_OFF)
/*!< Receive Status Register Error Mask */
#define UART_PL011_UARTFR_CTS_OFF 0x0u
/*!< Flag Register Clear to send bit field offset */
#define UART_PL011_UARTFR_DSR_OFF 0x1u
/*!< Flag Register Data set ready bit field offset */
#define UART_PL011_UARTFR_DCD_OFF 0x2u
/*!< Flag Register Data carrier detect bit field offset */
#define UART_PL011_UARTFR_BUSYBIT_OFF 0x3u
/*!< Flag Register Busy bit field offset */
#define UART_PL011_UARTFR_RX_FIFO_EMPTY_OFF 0x4u
/*!< Flag Register Receive fifo empty bit field offset */
#define UART_PL011_UARTFR_TX_FIFO_FULL_OFF 0x5u
/*!< Flag Register Transmit fifo full bit field offset */
#define UART_PL011_UARTFR_RX_FIFO_FULL_OFF 0x6u
/*!< Flag Register Receive fifo full bit field offset */
#define UART_PL011_UARTFR_TX_FIFO_EMPTY_OFF 0x7u
/*!< Flag Register Transmit fifo empty bit field offset */
#define UART_PL011_UARTFR_RI_OFF 0x8u
/*!< Flag Register Ring indicator bit field offset */
#define UART_PL011_UARTLCR_H_BRK_OFF 0x0u
/*!< Line Control Register Break bit field offset */
#define UART_PL011_UARTLCR_H_PEN_OFF 0x1u
/*!< Line Control Register Parity enable bit field offset */
#define UART_PL011_UARTLCR_H_EPS_OFF 0x2u
/*!< Line Control Register Even parity select bit field offset */
#define UART_PL011_UARTLCR_H_STP2_OFF 0x3u
/*!< Line Control Register 2 stop bit select bit field offset */
#define UART_PL011_UARTLCR_H_FEN_OFF 0x4u
/*!< Line Control Register Fifo enable bit field offset */
#define UART_PL011_UARTLCR_H_WLEN_OFF 0x5u
/*!< Line Control Register Word length bit field offset */
#define UART_PL011_UARTLCR_H_SPS_OFF 0x7u
/*!< Line Control Register Stick parity select bit field offset */
/**
* \brief Allowed word length options UART PL011
*/
enum uart_pl011_wlen_t {
UART_PL011_WLEN_5 = (0x0u<<UART_PL011_UARTLCR_H_WLEN_OFF),
UART_PL011_WLEN_6 = (0x1u<<UART_PL011_UARTLCR_H_WLEN_OFF),
UART_PL011_WLEN_7 = (0x2u<<UART_PL011_UARTLCR_H_WLEN_OFF),
UART_PL011_WLEN_8 = (0x3u<<UART_PL011_UARTLCR_H_WLEN_OFF),
};
/**
* \brief Allowed parity options UART PL011
*/
enum uart_pl011_parity_t {
UART_PL011_PARITY_DISABLED = (0x0u<<UART_PL011_UARTLCR_H_PEN_OFF),
UART_PL011_PARITY_ODD = (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
| 0x0u<<UART_PL011_UARTLCR_H_EPS_OFF
| 0x0u<<UART_PL011_UARTLCR_H_SPS_OFF),
UART_PL011_PARITY_EVEN = (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
| 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF
| 0x0u<<UART_PL011_UARTLCR_H_SPS_OFF),
UART_PL011_PARITY_STICKY_ONE= (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
| 0x0u<<UART_PL011_UARTLCR_H_EPS_OFF
| 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF),
UART_PL011_PARITY_STICKY_ZERO= (0x1u<<UART_PL011_UARTLCR_H_PEN_OFF
| 0x1u<<UART_PL011_UARTLCR_H_EPS_OFF
| 0x1u<<UART_PL011_UARTLCR_H_SPS_OFF),
};
/**
* \brief Allowed stop bits options UART PL011
*/
enum uart_pl011_stopbit_t {
UART_PL011_STOPBIT_1 = (0x0u<<UART_PL011_UARTLCR_H_STP2_OFF),
UART_PL011_STOPBIT_2 = (0x1u<<UART_PL011_UARTLCR_H_STP2_OFF),
};
#define UART_PL011_UARTCR_UARTEN_OFF 0x0u
/*!< Control Register Uart enable bit field offset */
#define UART_PL011_UARTCR_SIREN_OFF 0x1u
/*!< Control Register Sir enable bit field offset */
#define UART_PL011_UARTCR_SIRLP_OFF 0x2u
/*!< Control Register Sir low power bit field offset */
#define UART_PL011_UARTCR_LBE_OFF 0x7u
/*!< Control Register Loop back enable bit field offset */
#define UART_PL011_UARTCR_TXE_OFF 0x8u
/*!< Control Register Transmit enable bit field offset */
#define UART_PL011_UARTCR_RXE_OFF 0x9u
/*!< Control Register Receive enable bit field offset */
#define UART_PL011_UARTCR_DTR_OFF 0xAu
/*!< Control Register Data transmit ready bit field offset */
#define UART_PL011_UARTCR_RTS_OFF 0xBu
/*!< Control Register Request to send bit field offset */
#define UART_PL011_UARTCR_OUT1_OFF 0xCu
/*!< Control Register Out1 bit field offset */
#define UART_PL011_UARTCR_OUT2_OFF 0xDu
/*!< Control Register Out2 bit field offset */
#define UART_PL011_UARTCR_RTSE_OFF 0xEu
/*!< Control Register RTS hardware flow control enable bit field offset */
#define UART_PL011_UARTCR_CTSE_OFF 0xFu
/*!< Control Register CTS hardware flow control enable bit field offset */
#define UART_PL011_UARTIFLS_TX_OFF 0x0u
/*!< Interrupt FIFO Level Select Register Transmit bit field offset */
#define UART_PL011_UARTIFLS_RX_OFF 0x3u
/*!< Interrupt FIFO Level Select Register Receive bit field offset */
/**
* \brief UART Receive fifo levels
*/
enum uart_pl011_rx_fifo_lvl_t {
UART_PL011_RX_FIFO_LVL_1_8 = (0x0u<<UART_PL011_UARTIFLS_RX_OFF),
UART_PL011_RX_FIFO_LVL_1_4 = (0x1u<<UART_PL011_UARTIFLS_RX_OFF),
UART_PL011_RX_FIFO_LVL_1_2 = (0x2u<<UART_PL011_UARTIFLS_RX_OFF),
UART_PL011_RX_FIFO_LVL_3_4 = (0x3u<<UART_PL011_UARTIFLS_RX_OFF),
UART_PL011_RX_FIFO_LVL_7_8 = (0x4u<<UART_PL011_UARTIFLS_RX_OFF),
};
/**
* \brief UART Transmit fifo levels
*/
enum uart_pl011_tx_fifo_lvl_t {
UART_PL011_TX_FIFO_LVL_1_8 = (0x0u<<UART_PL011_UARTIFLS_TX_OFF),
UART_PL011_TX_FIFO_LVL_1_4 = (0x1u<<UART_PL011_UARTIFLS_TX_OFF),
UART_PL011_TX_FIFO_LVL_1_2 = (0x2u<<UART_PL011_UARTIFLS_TX_OFF),
UART_PL011_TX_FIFO_LVL_3_4 = (0x3u<<UART_PL011_UARTIFLS_TX_OFF),
UART_PL011_TX_FIFO_LVL_7_8 = (0x4u<<UART_PL011_UARTIFLS_TX_OFF),
};
#define UART_PL011_UARTDMACR_RXEN_OFF 0x0u
/*!< DMA Control Register Receive DMA enable bit field offset */
#define UART_PL011_UARTDMACR_TXEN_OFF 0x1u
/*!< DMA Control Register Transmit DMA enable bit field offset */
#define UART_PL011_UARTDMACR_ON_ERR_OFF 0x2u
/*!< DMA Control Register DMA on error bit field offset */
/**
* \brief Transmit DMA Enable
*/
enum uart_pl011_tx_dma_t {
UART_PL011_TX_DMA_DISABLE = (0x0u<<UART_PL011_UARTDMACR_TXEN_OFF),
UART_PL011_TX_DMA_ENABLE = (0x1u<<UART_PL011_UARTDMACR_TXEN_OFF),
};
/**
* \brief Receive DMA Enable
*/
enum uart_pl011_rx_dma_t {
UART_PL011_RX_DMA_DISABLE = (0x0u<<UART_PL011_UARTDMACR_RXEN_OFF),
UART_PL011_RX_DMA_ENABLE = (0x1u<<UART_PL011_UARTDMACR_RXEN_OFF),
UART_PL011_RX_DMA_ON_ERR_EN= (0x1u<<UART_PL011_UARTDMACR_RXEN_OFF
| 0x1u<<UART_PL011_UARTDMACR_ON_ERR_OFF),
};
#define UART_PL011_INTR_RI_OFF 0x0u
/*!< Ring indicator interrupt bit field offset */
#define UART_PL011_INTR_CTS_OFF 0x1u
/*!< Clear to send interrupt bit field offset */
#define UART_PL011_INTR_DCD_OFF 0x2u
/*!< Data carrier detect interrupt bit field offset */
#define UART_PL011_INTR_DSR_OFF 0x3u
/*!< Data set ready interrupt bit field offset */
#define UART_PL011_INTR_RX_OFF 0x4u
/*!< Receive interrupt bit field offset */
#define UART_PL011_INTR_TX_OFF 0x5u
/*!< Transmit interrupt bit field offset */
#define UART_PL011_INTR_RT_OFF 0x6u
/*!< Receive timeout interrupt bit field offset */
#define UART_PL011_INTR_FE_OFF 0x7u
/*!< Frame error interrupt bit field offset */
#define UART_PL011_INTR_PE_OFF 0x8u
/*!< Parity error interrupt bit field offset */
#define UART_PL011_INTR_BE_OFF 0x9u
/*!< Break error interrupt bit field offset */
#define UART_PL011_INTR_OE_OFF 0xAu
/*!< Overrun error interrupt bit field offset */
/**
* \brief ARM UART PL011 Interrupt data structure
*/
enum uart_pl011_intr_t {
UART_PL011_RI_INTR_MASK = (0x1u<<UART_PL011_INTR_RI_OFF),
UART_PL011_CTS_INTR_MASK = (0x1u<<UART_PL011_INTR_CTS_OFF),
UART_PL011_DCD_INTR_MASK = (0x1u<<UART_PL011_INTR_DCD_OFF),
UART_PL011_DSR_INTR_MASK = (0x1u<<UART_PL011_INTR_DSR_OFF),
UART_PL011_RX_INTR_MASK = (0x1u<<UART_PL011_INTR_RX_OFF),
UART_PL011_TX_INTR_MASK = (0x1u<<UART_PL011_INTR_TX_OFF),
UART_PL011_RT_INTR_MASK = (0x1u<<UART_PL011_INTR_RT_OFF),
UART_PL011_FE_INTR_MASK = (0x1u<<UART_PL011_INTR_FE_OFF),
UART_PL011_PE_INTR_MASK = (0x1u<<UART_PL011_INTR_PE_OFF),
UART_PL011_BE_INTR_MASK = (0x1u<<UART_PL011_INTR_BE_OFF),
UART_PL011_OE_INTR_MASK = (0x1u<<UART_PL011_INTR_OE_OFF),
};
/**
* \brief ARM UART PL011 error enumeration types
*/
enum uart_pl011_error_t {
UART_PL011_ERR_NONE = (0x0u),
UART_PL011_ERR_RX_FRAME = (0x1u<<UART_PL011_UARTRSR_FE_ERR_OFF),
UART_PL011_ERR_RX_PARITY = (0x1u<<UART_PL011_UARTRSR_PE_ERR_OFF),
UART_PL011_ERR_RX_BREAK = (0x1u<<UART_PL011_UARTRSR_BE_ERR_OFF),
UART_PL011_ERR_RX_OVERFLOW = (0x1u<<UART_PL011_UARTRSR_OE_ERR_OFF),
UART_PL011_ERR_INVALID_ARG = (UART_PL011_RX_ERR_MASK + 1),
UART_PL011_ERR_NOT_READY,
UART_PL011_ERR_INVALID_BAUD,
UART_PL011_ERR_NOT_INIT,
};
/**
* \brief ARM UART PL011 device configuration structure
*/
struct uart_pl011_dev_cfg_t {
const uint32_t base; /*!< UART PL011 base address */
const uint32_t def_baudrate; /*!< Default baudrate */
const enum uart_pl011_wlen_t def_wlen; /*!< Default word length */
const enum uart_pl011_parity_t def_parity; /*!< Default parity */
const enum uart_pl011_stopbit_t def_stopbit; /*!< Default stop bits */
};
/**
* \brief ARM UART PL011 device data structure
*/
struct uart_pl011_dev_data_t {
enum uart_pl011_state_t state; /*!< UART State */
uint32_t uart_clk; /*!< UART clock */
uint32_t baudrate; /*!< Baudrate */
};
/**
* \brief ARM UART PL011 device structure
*/
struct uart_pl011_dev_t {
const struct uart_pl011_dev_cfg_t* const cfg;
/*!< UART PL011 configuration */
struct uart_pl011_dev_data_t* const data;
/*!< UART PL011 data */
};
/**
* \brief Initializes UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
* \param[in] uart_clk UART clock used by the device.
*
* It uses the default baudrate to configure UART.
*
* \return Returns error code as specified in \ref uart_pl011_error_t
*
* \note This API should be called before calling any of the below UART APIs.
* \note This function doesn't check if dev is NULL.
*/
enum uart_pl011_error_t uart_pl011_init(struct uart_pl011_dev_t* dev,
uint32_t uart_clk);
/**
* \brief Uninitializes UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_uninit(struct uart_pl011_dev_t* dev);
/**
* \brief Returns the UART PL011 operational state.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \return Returns the UART operational state
*
* \note This function doesn't check if dev is NULL.
*/
enum uart_pl011_state_t uart_pl011_get_state(struct uart_pl011_dev_t* dev);
/**
* \brief Sets the UART baudrate.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] baudrate New baudrate.
*
* \return Returns error code as specified in \ref uart_pl011_error_t
*
* \note This function doesn't check if dev is NULL.
*/
enum uart_pl011_error_t uart_pl011_set_baudrate(
struct uart_pl011_dev_t* dev, uint32_t baudrate);
/**
* \brief Gets the UART baudrate.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \return Returns the UART baudrate.
*
* \note The UART should be in valid state before calling this API
* \ref uart_pl011_get_state should return UART_PL011_INITIALIZED
* \note This function doesn't check if dev is NULL.
*/
uint32_t uart_pl011_get_baudrate(struct uart_pl011_dev_t* dev);
/**
* \brief Enables UART interrupts
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] mask Bit mask for enabling/disabling interrupts
* \ref uart_pl011_intr_t
*
* \note User is responsible to configure the interrupt vector and
* the interrupt controller.
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_intr(struct uart_pl011_dev_t* dev,
enum uart_pl011_intr_t mask);
/**
* \brief Disables UART interrupts
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] mask Bit mask for enabling/disabling interrupts
* \ref uart_pl011_intr_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_intr(struct uart_pl011_dev_t* dev,
enum uart_pl011_intr_t mask);
/**
* \brief Clears UART Interrupt
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] mask Bit mask for clearing interrupts \ref uart_pl011_intr_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_clear_intr(struct uart_pl011_dev_t* dev,
enum uart_pl011_intr_t mask);
/**
* \brief Returns the UART Masked interrupt status
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \return Masked interrupt status \ref uart_pl011_intr_t
*
* \note This function doesn't check if dev is NULL.
*/
enum uart_pl011_intr_t uart_pl011_get_masked_intr_status(
struct uart_pl011_dev_t* dev);
/**
* \brief Returns the UART Raw interrupt status
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \return Raw interrupt status \ref uart_pl011_intr_t
*
* \note This function doesn't check if dev is NULL.
*/
enum uart_pl011_intr_t uart_pl011_get_raw_intr_status(
struct uart_pl011_dev_t* dev);
/**
* \brief Sets receive fifo levels
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] rx_lvl Receive fifo levels \ref uart_pl011_rx_fifo_lvl_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_set_rx_fifo_lvl(struct uart_pl011_dev_t* dev,
enum uart_pl011_rx_fifo_lvl_t rx_lvl);
/**
* \brief Sets transmit fifo levels
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] tx_lvl Transmit fifo levels \ref uart_pl011_tx_fifo_lvl_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_set_tx_fifo_lvl(struct uart_pl011_dev_t* dev,
enum uart_pl011_tx_fifo_lvl_t tx_lvl);
/**
* \brief Enables/Disables transmit UART DMA
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] enable To enable/disable the UART transmit DMA
* \ref uart_pl011_tx_dma_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_set_tx_dma(struct uart_pl011_dev_t* dev,
enum uart_pl011_tx_dma_t enable);
/**
* \brief Enables/Disables receive UART DMA
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] enable To enable/disable the UART receive DMA
* \ref uart_pl011_rx_dma_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_set_rx_dma(struct uart_pl011_dev_t* dev,
enum uart_pl011_rx_dma_t enable);
/**
* \brief Check if the UART dev is readable
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \return Returns bool, true if UART is readable, false otherwise
*
* \note This function doesn't check if dev is NULL.
*/
bool uart_pl011_is_readable(struct uart_pl011_dev_t* dev);
/**
* \brief Reads one byte from UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[out] byte Pointer to byte that is populated with the data to be read
*
* \return Error status (if any) as specified in
* \ref uart_pl011_error_t
*
* \note This API should only be called when the device is readable
* \ref uart_pl011_is_readable
* \note For better performance, this function doesn't check if dev and byte
* pointer are NULL, and if the driver is initialized.
*/
enum uart_pl011_error_t uart_pl011_read(struct uart_pl011_dev_t* dev,
uint8_t* byte);
/**
* \brief Check if the UART dev is writable
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \return Returns bool, true if UART is writable, false otherwise
*
* \note This function doesn't check if dev is NULL.
*/
bool uart_pl011_is_writable(struct uart_pl011_dev_t* dev);
/**
* \brief Writes a byte to UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] byte One byte to write.
*
* \note This API should only be called when the device is writable
* \ref uart_pl011_is_writable
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_write(struct uart_pl011_dev_t* dev, uint8_t byte);
/**
* \brief Sets the UART format.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] word_len UART word length \ref uart_pl011_wlen_t
* \param[in] parity UART parity \ref uart_pl011_parity_t
* \param[in] stop_bits UART stop bits \ref uart_pl011_stopbit_t
*
* \return Returns error code as specified in \ref uart_pl011_error_t
*
* \note This function doesn't check if dev is NULL.
*/
enum uart_pl011_error_t uart_pl011_set_format(struct uart_pl011_dev_t* dev,
enum uart_pl011_wlen_t word_len,
enum uart_pl011_parity_t parity,
enum uart_pl011_stopbit_t stop_bits);
/**
* \brief Enables the UART fifo.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_fifo(struct uart_pl011_dev_t* dev);
/**
* \brief Disables the UART fifo.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_fifo(struct uart_pl011_dev_t* dev);
/**
* \brief Enables break transmission from UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_enable_break(struct uart_pl011_dev_t* dev);
/**
* \brief Disables break transmission from UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_disable_break(struct uart_pl011_dev_t* dev);
/**
* \brief Enables CTS flow control in UART PL011
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_cts_flowcontrol(struct uart_pl011_dev_t* dev);
/**
* \brief Disables CTS flow control in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_cts_flowcontrol(struct uart_pl011_dev_t* dev);
/**
* \brief Enables RTS flow control in UART PL011
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_rts_flowcontrol(struct uart_pl011_dev_t* dev);
/**
* \brief Disables RTS flow control in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_rts_flowcontrol(struct uart_pl011_dev_t* dev);
/**
* \brief Enables Data carrier detect in UART PL011
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \note For DTE nUARTOut1 can be used as Data carrier detect (DCD).
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_dcd(struct uart_pl011_dev_t* dev);
/**
* \brief Disables Data carrier detect in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \note For DTE nUARTOut1 can be used as Data carrier detect (DCD).
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_dcd(struct uart_pl011_dev_t* dev);
/**
* \brief Enables RTS signal for UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_set_rts(struct uart_pl011_dev_t* dev);
/**
* \brief Disables RTS signal for UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_clear_rts(struct uart_pl011_dev_t* dev);
/**
* \brief Enables DTR signal for UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_set_dtr(struct uart_pl011_dev_t* dev);
/**
* \brief Disables DTR signal for UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_clear_dtr(struct uart_pl011_dev_t* dev);
/**
* \brief Enables reception in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_receive(struct uart_pl011_dev_t* dev);
/**
* \brief Disables reception in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_receive(struct uart_pl011_dev_t* dev);
/**
* \brief Enables transmission in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable_transmit(struct uart_pl011_dev_t* dev);
/**
* \brief Disables transmission in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable_transmit(struct uart_pl011_dev_t* dev);
/**
* \brief Enables loopback in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_set_loopback(struct uart_pl011_dev_t* dev);
/**
* \brief Disables loopback in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_clear_loopback(struct uart_pl011_dev_t* dev);
/**
* \brief Enables IrDA Sir low power mode in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_enable_sirlp(struct uart_pl011_dev_t* dev);
/**
* \brief Disables IrDA Sir in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_disable_sirlp(struct uart_pl011_dev_t* dev);
/**
* \brief Enables IrDA Sir in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_enable_sir(struct uart_pl011_dev_t* dev);
/**
* \brief Disables IrDA Sir in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
*
* \note For better performance, this function doesn't check if dev is NULL and
* if the driver is initialized to have better performance.
*/
void uart_pl011_disable_sir(struct uart_pl011_dev_t* dev);
/**
* \brief Enables in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_enable(struct uart_pl011_dev_t* dev);
/**
* \brief Disables in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
*
* \note This function doesn't check if dev is NULL.
*/
void uart_pl011_disable(struct uart_pl011_dev_t* dev);
/**
* \brief Gets the Clear to send status in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \return Returns bool, true when the modem status input is 0, false otherwise
*
* \note This bit is the complement of the UART clear to send (nUARTCTS) modem
* status input.
* \note This function doesn't check if dev is NULL.
*/
bool uart_pl011_get_cts_status(struct uart_pl011_dev_t* dev);
/**
* \brief Gets the Data set ready status in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \return Returns bool, true when the modem status input is 0, false otherwise
*
* \note This bit is the complement of the UART UART data set ready (nUARTDSR)
* modem status input.
* \note This function doesn't check if dev is NULL.
*/
bool uart_pl011_get_dsr_status(struct uart_pl011_dev_t* dev);
/**
* \brief Gets the Data carrier detect status in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \return Returns bool, true when the modem status input is 0, false otherwise
*
* \note This bit is the complement of the UART data carrier detect (nUARTDCD)
* modem status input.
* \note This function doesn't check if dev is NULL.
*/
bool uart_pl011_get_dcd_status(struct uart_pl011_dev_t* dev);
/**
* \brief Gets the Ring indicator status in UART PL011.
*
* \param[in] dev UART PL011 device struct \ref uart_pl011_dev_t
*
* \return Returns bool, true when the modem status input is 0, false otherwise
*
* \note This bit is the complement of the UART ring indicator (nUARTRI) modem
* status input.
* \note This function doesn't check if dev is NULL.
*/
bool uart_pl011_get_ri_status(struct uart_pl011_dev_t* dev);
/**
* \brief Sets the Low power Divisor in UART dev.
*
* \param[in] dev UART device struct \ref uart_pl011_dev_t
* \param[in] value Low power divisor value to be set
*
* \return Returns error code as specified in \ref uart_pl011_error_t
*
* \note For better performance, this function doesn't check if dev is NULL
*/
enum uart_pl011_error_t uart_pl011_set_sirlp_divisor(
struct uart_pl011_dev_t* dev, uint32_t value);
#ifdef __cplusplus
}
#endif
#endif /* __UART_PL011_DRV_H__ */

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/*
* Copyright (c) 2016-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __ARM_LTD_MUSCA_REGS_H__
#define __ARM_LTD_MUSCA_REGS_H__
#include <stdint.h>
#include "platform_retarget.h"
/* sysinfo memory mapped register access structure */
struct sysinfo_t {
volatile uint32_t sysversion; /* (R/ ) System version */
volatile uint32_t sysconfig; /* (R/ ) System configuration */
volatile uint32_t reserved0[1008];
volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
volatile uint32_t reserved1[3];
volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
};
/* Secure System Control (SYSCTRL) Alias */
#define CMSDK_SYSCTRL_BASE_S MUSCA_SYSTEM_CTRL_S_BASE
/* sysctrl memory mapped register access structure */
struct sysctrl_t {
volatile uint32_t secdbgstat; /* (R/ ) Secure Debug Configuration
* Status Register*/
volatile uint32_t secdbgset; /* ( /W) Secure Debug Configuration
* Set Register */
volatile uint32_t secdbgclr; /* ( /W) Secure Debug Configuration
* Clear Register */
volatile uint32_t scsecctrl; /* (R/W) System Control Security
* Control Register */
volatile uint32_t fclk_div; /* (R/W) Fast Clock Divider
* Configuration Register */
volatile uint32_t sysclk_div; /* (R/W) System Clock Divider
* Configuration Register */
volatile uint32_t clockforce; /* (R/W) Clock Forces */
volatile uint32_t reserved0[57];
volatile uint32_t resetsyndrome; /* (R/W) Reset syndrome */
volatile uint32_t resetmask; /* (R/W) Reset MASK */
volatile uint32_t swreset; /* ( /W) Software Reset */
volatile uint32_t gretreg; /* (R/W) General Purpose Retention
* Register */
volatile uint32_t initsvtor0; /* (R/W) Initial Secure Reset Vector
* Register For CPU 0 */
volatile uint32_t initsvtor1; /* (R/W) Initial Secure Reset
* Vector Register For CPU 1*/
volatile uint32_t cpuwait; /* (R/W) CPU Boot wait control
* after reset */
volatile uint32_t reserved1;
volatile uint32_t wicctrl; /* (R/W) CPU WIC Request and
* Acknowledgement */
volatile uint32_t ewctrl; /* (R/W) External Wakeup Control */
volatile uint32_t reserved2[54];
volatile uint32_t pdcm_pd_sys_sense; /* (R/W) Power Control Dependency
* Matrix PD_SYS
* Power Domain Sensitivity.*/
volatile uint32_t pdcm_pd_cpu0core_sense; /* (R/W) Power Control Dependency
* Matrix PD_CPU0CORE
* Power Domain Sensitivity.*/
volatile uint32_t pdcm_pd_cpu1core_sense; /* (R/W) Power Control Dependency
* Matrix PD_CPU1CORE
* Power Domain Sensitivity.*/
volatile uint32_t pdcm_pd_sram0_sense; /* (R/W) Power Control Dependency
* Matrix PD_SRAM0 Power
* Domain Sensitivity.*/
volatile uint32_t pdcm_pd_sram1_sense; /* (R/W) Power Control Dependency
* Matrix PD_SRAM1 Power
* Domain Sensitivity.*/
volatile uint32_t pdcm_pd_sram2_sense; /* (R/W) Power Control Dependency
* Matrix PD_SRAM2 Power
* Domain Sensitivity.*/
volatile uint32_t pdcm_pd_sram3_sense; /* (R/W) Power Control Dependency
* Matrix PD_SRAM3 Power
* Domain Sensitivity.*/
volatile uint32_t reserved3[5];
volatile uint32_t pdcm_pd_cc_sense; /* (R/W) Power Control Dependency
* Matrix PD_CC
* Power Domain Sensitivity.*/
volatile uint32_t pdcm_pd_exp0_out_sense; /* (R/W) Power Control Dependency
* Matrix PD_EXP0 Sensitivity. */
volatile uint32_t pdcm_pd_exp1_out_sense; /* (R/W) Power Control Dependency
* Matrix PD_EXP1 Sensitivity. */
volatile uint32_t pdcm_pd_exp2_out_sense; /* (R/W) Power Control Dependency
* Matrix PD_EXP2 Sensitivity. */
volatile uint32_t pdcm_pd_exp3_out_sense; /* (R/W) Power Control Dependency
* Matrix PD_EXP3 Sensitivity. */
volatile uint32_t reserved4[864];
volatile uint32_t pidr4; /* (R/ ) Peripheral ID 4 */
volatile uint32_t reserved5[3];
volatile uint32_t pidr0; /* (R/ ) Peripheral ID 0 */
volatile uint32_t pidr1; /* (R/ ) Peripheral ID 1 */
volatile uint32_t pidr2; /* (R/ ) Peripheral ID 2 */
volatile uint32_t pidr3; /* (R/ ) Peripheral ID 3 */
volatile uint32_t cidr0; /* (R/ ) Component ID 0 */
volatile uint32_t cidr1; /* (R/ ) Component ID 1 */
volatile uint32_t cidr2; /* (R/ ) Component ID 2 */
volatile uint32_t cidr3; /* (R/ ) Component ID 3 */
};
/* Secure Privilege Control */
#define CMSDK_SPCTRL ((struct spctrl_def*)MUSCA_SPCTRL_S_BASE)
/* SPCTRL memory mapped register access structure */
struct spctrl_def {
volatile uint32_t spcsecctrl; /* (R/W) Secure Configuration Control
Register */
volatile uint32_t buswait; /* (R/W) Bus Access wait control after reset.*/
volatile uint32_t reserved[2];
volatile uint32_t secrespcfg; /* (R/W) Security Violation Response
* Configuration register.*/
volatile uint32_t nsccfg; /* (R/W) Non Secure Callable Configuration
* for IDAU. */
volatile uint32_t reserved2;
volatile uint32_t secmpcintstat; /* (R/W) Secure MPC Interrupt Status. */
volatile uint32_t secppcintstat; /* (R/W) Secure PPC Interrupt Status. */
volatile uint32_t secppcintclr; /* (R/W) Secure PPC Interrupt Clear. */
volatile uint32_t secppcinten; /* (R/W) Secure PPC Interrupt Enable. */
volatile uint32_t reserved3;
volatile uint32_t secmscintstat; /* (R/W) Secure MSC Interrupt Status. */
volatile uint32_t secmscintclr; /* (R/W) Secure MSC Interrupt Clear. */
volatile uint32_t secmscinten; /* (R/W) Secure MSC Interrupt Enable. */
volatile uint32_t reserved4;
volatile uint32_t brgintstat; /* (R/W) Bridge Buffer Error Interrupt Status. */
volatile uint32_t brgintclr; /* (R/W) Bridge Buffer Error Interrupt Clear. */
volatile uint32_t brginten; /* (R/W) Bridge Buffer Error Interrupt Enable. */
volatile uint32_t reserved5;
volatile uint32_t ahbnsppc0; /* (R/W) Non-Secure Access AHB slave Peripheral
* Protection Control #0 */
volatile uint32_t reserved6[3];
volatile uint32_t ahbnsppcexp0; /* (R/W) Expansion 0 Non_Secure Access AHB slave
* Peripheral Protection Control */
volatile uint32_t ahbnsppcexp1; /* (R/W) Expansion 1 Non_Secure Access AHB slave
* Peripheral Protection Control */
volatile uint32_t ahbnsppcexp2; /* (R/W) Expansion 2 Non_Secure Access AHB slave
* Peripheral Protection Control */
volatile uint32_t ahbnsppcexp3; /* (R/W) Expansion 3 Non_Secure Access AHB slave
* Peripheral Protection Control */
volatile uint32_t apbnsppc0; /* (R/W) Non-Secure Access APB slave Peripheral
* Protection Control #0 */
volatile uint32_t apbnsppc1; /* (R/W) Non-Secure Access APB slave Peripheral
* Protection Control #1 */
volatile uint32_t reserved7[2];
volatile uint32_t apbnsppcexp0; /* (R/W) Expansion 0 Non_Secure Access APB slave
* Peripheral Protection Control */
volatile uint32_t apbnsppcexp1; /* (R/W) Expansion 1 Non_Secure Access APB slave
* Peripheral Protection Control */
volatile uint32_t apbnsppcexp2; /* (R/W) Expansion 2 Non_Secure Access APB slave
* Peripheral Protection Control */
volatile uint32_t apbnsppcexp3; /* (R/W) Expansion 3 Non_Secure Access APB slave
* Peripheral Protection Control */
volatile uint32_t ahbspppc0; /* (R/W) Secure Unprivileged Access AHB slave
* Peripheral Protection Control #0. */
volatile uint32_t reserved8[3];
volatile uint32_t ahbspppcexp0; /* (R/W) Expansion 0 Secure Unprivileged Access
* AHB slave Peripheral Protection Control. */
volatile uint32_t ahbspppcexp1; /* (R/W) Expansion 1 Secure Unprivileged Access
* AHB slave Peripheral Protection Control. */
volatile uint32_t ahbspppcexp2; /* (R/W) Expansion 2 Secure Unprivileged Access
* AHB slave Peripheral Protection Control. */
volatile uint32_t ahbspppcexp3; /* (R/W) Expansion 3 Secure Unprivileged Access
* AHB slave Peripheral Protection Control. */
volatile uint32_t apbspppc0; /* (R/W) Secure Unprivileged Access APB slave
* Peripheral Protection Control #0 */
volatile uint32_t apbspppc1; /* (R/W) Secure Unprivileged Access APB slave
* Peripheral Protection Control #1 */
volatile uint32_t reserved9[2];
volatile uint32_t apbspppcexp0; /* (R/W) Expansion 0 Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t apbspppcexp1; /* (R/W) Expansion 1 Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t apbspppcexp2; /* (R/W) Expansion 2 Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t apbspppcexp3; /* (R/W) Expansion 3 Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t nsmscexp; /* (R/W) Expansion MSC Non-Secure Configuration */
volatile uint32_t reserved10[959];
volatile uint32_t pid4; /* (R/W) Peripheral ID 4 */
volatile uint32_t pid5; /* (R/W) Peripheral ID 5 */
volatile uint32_t pid6; /* (R/W) Peripheral ID 6 */
volatile uint32_t pid7; /* (R/W) Peripheral ID 7 */
volatile uint32_t pid0; /* (R/W) Peripheral ID 0 */
volatile uint32_t pid1; /* (R/W) Peripheral ID 1 */
volatile uint32_t pid2; /* (R/W) Peripheral ID 2 */
volatile uint32_t pid3; /* (R/W) Peripheral ID 3 */
volatile uint32_t cid0; /* (R/W) Component ID 0 */
volatile uint32_t cid1; /* (R/W) Component ID 1 */
volatile uint32_t cid2; /* (R/W) Component ID 2 */
volatile uint32_t cid3; /* (R/W) Component ID 3 */
};
/* Secure PPC interrupt position mask */
#define CMSDK_APB_PPC0_INT_POS_MASK (1UL << 0)
#define CMSDK_APB_PPC1_INT_POS_MASK (1UL << 1)
#define CMSDK_APB_PPCEXP0_INT_POS_MASK (1UL << 4)
#define CMSDK_APB_PPCEXP1_INT_POS_MASK (1UL << 5)
#define CMSDK_APB_PPCEXP2_INT_POS_MASK (1UL << 6)
#define CMSDK_APB_PPCEXP3_INT_POS_MASK (1UL << 7)
#define CMSDK_AHB_PPCEXP0_INT_POS_MASK (1UL << 20)
#define CMSDK_AHB_PPCEXP1_INT_POS_MASK (1UL << 21)
#define CMSDK_AHB_PPCEXP2_INT_POS_MASK (1UL << 22)
#define CMSDK_AHB_PPCEXP3_INT_POS_MASK (1UL << 23)
/* Non-Secure Privilege Control */
#define CMSDK_NSPCTRL ((struct nspctrl_def*)MUSCA_NSPCTRL_NS_BASE)
/* NSPCTRL memory mapped register access structure */
struct nspctrl_def {
volatile uint32_t reserved[36];
volatile uint32_t ahbnspppc0; /* (R/W) Non-Secure Unprivileged Access AHB slave
* Peripheral Protection Control #0 */
volatile uint32_t reserved3[3];
volatile uint32_t ahbnspppcexp0; /* (R/W) Expansion 0 Non-Secure Unprivileged Access
* AHB slave Peripheral Protection Control */
volatile uint32_t ahbnspppcexp1; /* (R/W) Expansion 1 Non-Secure Unprivileged Access
* AHB slave Peripheral Protection Control */
volatile uint32_t ahbnspppcexp2; /* (R/W) Expansion 2 Non-Secure Unprivileged Access
* AHB slave Peripheral Protection Control */
volatile uint32_t ahbnspppcexp3; /* (R/W) Expansion 3 Non-Secure Unprivileged Access
* AHB slave Peripheral Protection Control */
volatile uint32_t apbnspppc0; /* (R/W) Non-Secure Unprivileged Access APB slave
* Peripheral Protection Control #0 */
volatile uint32_t apbnspppc1; /* (R/W) Non-Secure Unprivileged Access APB slave
* Peripheral Protection Control #1 */
volatile uint32_t reserved4[2];
volatile uint32_t apbnspppcexp0; /* (R/W) Expansion 0 Non-Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t apbnspppcexp1; /* (R/W) Expansion 1 Non-Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t apbnspppcexp2; /* (R/W) Expansion 2 Non-Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t apbnspppcexp3; /* (R/W) Expansion 3 Non-Secure Unprivileged Access
* APB slave Peripheral Protection Control */
volatile uint32_t reserved5[960];
volatile uint32_t pidr4; /* (R/W) Peripheral ID 3 */
volatile uint32_t reserved7;
volatile uint32_t reserved8;
volatile uint32_t reserved9;
volatile uint32_t pidr0; /* (R/W) Peripheral ID 0 */
volatile uint32_t pidr1; /* (R/W) Peripheral ID 1 */
volatile uint32_t pidr2; /* (R/W) Peripheral ID 2 */
volatile uint32_t pidr3; /* (R/W) Peripheral ID 3 */
volatile uint32_t cidr0; /* (R/W) Component ID 0 */
volatile uint32_t cidr2; /* (R/W) Component ID 1 */
volatile uint32_t cidr1; /* (R/W) Component ID 2 */
volatile uint32_t cidr3; /* (R/W) Component ID 3 */
};
/* ARM APB PPC0 peripherals definition */
#define CMSDK_TIMER0_APB_PPC_POS 0U
#define CMSDK_TIMER1_APB_PPC_POS 1U
#define CMSDK_DTIMER_APB_PPC_POS 2U
#define CMSDK_MHU0_APB_PPC_POS 3U
#define CMSDK_MHU1_APB_PPC_POS 4U
/* The bits 31:5 are reserved */
/* End ARM APB PPC0 peripherals definition */
/* ARM APB PPC1 peripherals definition */
#define CMSDK_S32K_TIMER_PPC_POS 0U
/* The bits 31:1 are reserved */
/* End ARM APB PPC1 peripherals definition */
/* ARM AHB PPC0 peripherals definition */
/* The bits 31:0 are reserved */
/* End of ARM AHB PPC0 peripherals definition */
/* ARM AHB PPCEXP0 peripherals definition */
#define MUSCA_PERIPHS_AHB_PPC_POS 0U
/* The bits 31:1 are reserved */
/* End of ARM AHB PPCEXP0 peripherals definition */
/* ARM AHB PPCEXP1 peripherals definition */
/* The bits 31:0 are reserved */
/* End of ARM AHB PPCEXP1 peripherals definition */
/* ARM AHB PPCEXP2 peripherals definition */
/* The bits 31:0 are reserved */
/* End of ARM AHB PPCEXP2 peripherals definition */
/* ARM AHB PPCEXP3 peripherals definition */
/* The bits 31:0 are reserved */
/* End of ARM AHB PPCEXP3 peripherals definition */
#endif /* __ARM_LTD_MUSCA_REGS_H__ */

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/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_retarget.h
* \brief This file defines all the peripheral base addresses for Musca platform.
*/
#ifndef __ARM_LTD_MUSCA_RETARGET_H__
#define __ARM_LTD_MUSCA_RETARGET_H__
#include "platform_regs.h" /* Platform registers */
#include "system_cmsdk_musca.h"
/* SRAM MPC ranges and limits */
/* Internal memory */
#define MPC_ISRAM0_RANGE_BASE_NS 0x20000000
#define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF
#define MPC_ISRAM0_RANGE_BASE_S 0x30000000
#define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF
#define MPC_ISRAM1_RANGE_BASE_NS 0x20008000
#define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF
#define MPC_ISRAM1_RANGE_BASE_S 0x30008000
#define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF
#define MPC_ISRAM2_RANGE_BASE_NS 0x20010000
#define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF
#define MPC_ISRAM2_RANGE_BASE_S 0x30010000
#define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF
#define MPC_ISRAM3_RANGE_BASE_NS 0x20018000
#define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF
#define MPC_ISRAM3_RANGE_BASE_S 0x30018000
#define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF
/* Code SRAM memory */
#define MPC_CODE_SRAM_RANGE_BASE_NS (0x00000000)
#define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x00200000)
#define MPC_CODE_SRAM_RANGE_BASE_S (0x10000000)
#define MPC_CODE_SRAM_RANGE_LIMIT_S (0x10200000)
/* QSPI Flash memory */
#define MPC_QSPI_RANGE_BASE_NS (0x00200000)
#define MPC_QSPI_RANGE_LIMIT_NS (0x00240000)
#define MPC_QSPI_RANGE_BASE_S (0x10200000)
#define MPC_QSPI_RANGE_LIMIT_S (0x10240000)
#endif /* __ARM_LTD_MUSCA_RETARGET_H__ */

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/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_retarget_dev.c
* \brief This file defines exports the structures based on the peripheral
* definitions from device_cfg.h.
* This retarget file is meant to be used as a helper for baremetal
* applications and/or as an example of how to configure the generic
* driver structures.
*/
#include "platform_retarget_dev.h"
#include "platform_retarget.h"
#include "system_cmsdk_musca.h"
/* ======= Peripheral configuration structure definitions ======= */
/* MUSCA A1 SCC driver structures */
#ifdef MUSCA_A1_SCC_S
static const struct musca_a1_scc_dev_cfg_t MUSCA_A1_SCC_DEV_CFG_S = {
.base = MUSCA_SCC_S_BASE};
struct musca_a1_scc_dev_t MUSCA_A1_SCC_DEV_S = {&(MUSCA_A1_SCC_DEV_CFG_S)};
#endif
#ifdef MUSCA_A1_SCC_NS
static const struct musca_a1_scc_dev_cfg_t MUSCA_A1_SCC_DEV_CFG_NS = {
.base = MUSCA_SCC_NS_BASE};
struct musca_a1_scc_dev_t MUSCA_A1_SCC_DEV_NS = {&(MUSCA_A1_SCC_DEV_CFG_NS)};
#endif
/* ARM PPC SSE 200 driver structures */
#ifdef AHB_PPC0_S
static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t AHB_PPC0_DEV_S = {
&AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S };
#endif
#ifdef AHB_PPCEXP0_S
static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = {
&AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S };
#endif
#ifdef AHB_PPCEXP1_S
static struct ppc_sse200_dev_cfg_t AHB_PPCEXP1_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t AHB_PPCEXP1_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t AHB_PPCEXP1_DEV_S = {
&AHB_PPCEXP1_DEV_CFG_S, &AHB_PPCEXP1_DEV_DATA_S };
#endif
#ifdef AHB_PPCEXP2_S
static struct ppc_sse200_dev_cfg_t AHB_PPCEXP2_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t AHB_PPCEXP2_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S = {
&AHB_PPCEXP2_DEV_CFG_S, &AHB_PPCEXP2_DEV_DATA_S };
#endif
#ifdef AHB_PPCEXP3_S
static struct ppc_sse200_dev_cfg_t AHB_PPCEXP3_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t AHB_PPCEXP3_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S = {
&AHB_PPCEXP3_DEV_CFG_S, &AHB_PPCEXP3_DEV_DATA_S };
#endif
#ifdef APB_PPC0_S
static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t APB_PPC0_DEV_S = {
&APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S };
#endif
#ifdef APB_PPC1_S
static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t APB_PPC1_DEV_S = {
&APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S};
#endif
#ifdef APB_PPCEXP0_S
static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = {
&APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S };
#endif
#ifdef APB_PPCEXP1_S
static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = {
&APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S };
#endif
#ifdef APB_PPCEXP2_S
static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = {
&APB_PPCEXP2_DEV_CFG, &APB_PPCEXP2_DEV_DATA_S };
#endif
#ifdef APB_PPCEXP3_S
static struct ppc_sse200_dev_cfg_t APB_PPCEXP3_DEV_CFG = {
.spctrl_base = MUSCA_SPCTRL_S_BASE,
.nspctrl_base = MUSCA_NSPCTRL_NS_BASE };
static struct ppc_sse200_dev_data_t APB_PPCEXP3_DEV_DATA_S = {
.p_ns_ppc = 0,
.p_sp_ppc = 0,
.p_nsp_ppc = 0,
.int_bit_mask = 0,
.state = 0 };
struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S = {
&APB_PPCEXP3_DEV_CFG, &APB_PPCEXP3_DEV_DATA_S };
#endif
/* ARM MPC SIE 200 driver structures */
#ifdef MPC_ISRAM0_S
static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = {
.base = MUSCA_MPC_SRAM0_S_BASE};
static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = {
&(MPC_ISRAM0_DEV_CFG_S),
&(MPC_ISRAM0_DEV_DATA_S)};
#endif
#ifdef MPC_ISRAM1_S
static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = {
.base = MUSCA_MPC_SRAM1_S_BASE};
static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = {
&(MPC_ISRAM1_DEV_CFG_S),
&(MPC_ISRAM1_DEV_DATA_S)};
#endif
#ifdef MPC_ISRAM2_S
static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = {
.base = MUSCA_MPC_SRAM2_S_BASE};
static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = {
&(MPC_ISRAM2_DEV_CFG_S),
&(MPC_ISRAM2_DEV_DATA_S)};
#endif
#ifdef MPC_ISRAM3_S
static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = {
.base = MUSCA_MPC_SRAM3_S_BASE};
static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = {
&(MPC_ISRAM3_DEV_CFG_S),
&(MPC_ISRAM3_DEV_DATA_S)};
#endif
#ifdef MPC_CODE_SRAM_NS
static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM_DEV_CFG_NS = {
.base = MUSCA_CODE_SRAM_MPC_NS_BASE};
static struct mpc_sie200_dev_data_t MPC_CODE_SRAM_DEV_DATA_NS = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_NS = {
&(MPC_CODE_SRAM_DEV_CFG_NS),
&(MPC_CODE_SRAM_DEV_DATA_NS)};
#endif
#ifdef MPC_CODE_SRAM_S
static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM_DEV_CFG_S = {
.base = MUSCA_CODE_SRAM_MPC_S_BASE};
static struct mpc_sie200_dev_data_t MPC_CODE_SRAM_DEV_DATA_S = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_S = {
&(MPC_CODE_SRAM_DEV_CFG_S),
&(MPC_CODE_SRAM_DEV_DATA_S)};
#endif
#ifdef MPC_QSPI_S
static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_S = {
.base = MUSCA_QSPI_MPC_S_BASE};
static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_S = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_QSPI_DEV_S = {
&(MPC_QSPI_DEV_CFG_S),
&(MPC_QSPI_DEV_DATA_S)};
#endif
#ifdef MPC_QSPI_NS
static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_NS = {
.base = MUSCA_QSPI_MPC_NS_BASE};
static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_NS = {
.range_list = 0,
.nbr_of_ranges = 0,
.state = 0,
.reserved = 0};
struct mpc_sie200_dev_t MPC_QSPI_DEV_NS = {
&(MPC_QSPI_DEV_CFG_NS),
&(MPC_QSPI_DEV_DATA_NS)};
#endif
/* CMSDK Timers driver structures */
#ifdef CMSDK_TIMER0_S
static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S = {
.base = MUSCA_CMSDK_TIMER0_S_BASE};
static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S = {
.is_initialized = 0};
struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S = {&(CMSDK_TIMER0_DEV_CFG_S),
&(CMSDK_TIMER0_DEV_DATA_S)};
#endif
#ifdef CMSDK_TIMER0_NS
static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = {
.base = MUSCA_CMSDK_TIMER0_NS_BASE};
static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = {
.is_initialized = 0};
struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS),
&(CMSDK_TIMER0_DEV_DATA_NS)};
#endif
#ifdef CMSDK_TIMER1_S
static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = {
.base = MUSCA_CMSDK_TIMER1_S_BASE};
static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = {
.is_initialized = 0};
struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S),
&(CMSDK_TIMER1_DEV_DATA_S)};
#endif
#ifdef CMSDK_TIMER1_NS
static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = {
.base = MUSCA_CMSDK_TIMER1_NS_BASE};
static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = {
.is_initialized = 0};
struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS),
&(CMSDK_TIMER1_DEV_DATA_NS)};
#endif
/* General-Purpose Timer driver structures */
#ifdef GP_TIMER_S
static const struct timer_gp_dev_cfg_t GP_TIMER_DEV_CFG_S = {
.base = MUSCA_TIMER_S_BASE};
static struct timer_gp_dev_data_t GP_TIMER_DEV_DATA_S = {
.is_initialized = false,
.alarm0_init = 0,
.alarm1_init = 0};
struct timer_gp_dev_t GP_TIMER_DEV_S = {
&(GP_TIMER_DEV_CFG_S),
&(GP_TIMER_DEV_DATA_S)};
#endif
#ifdef GP_TIMER_NS
static const struct timer_gp_dev_cfg_t GP_TIMER_DEV_CFG_NS = {
.base = MUSCA_TIMER_NS_BASE};
static struct timer_gp_dev_data_t GP_TIMER_DEV_DATA_NS = {
.is_initialized = false,
.alarm0_init = 0,
.alarm1_init = 0};
struct timer_gp_dev_t GP_TIMER_DEV_NS = {
&(GP_TIMER_DEV_CFG_NS),
&(GP_TIMER_DEV_DATA_NS)};
#endif
/* ARM UART PL011 driver structures */
#ifdef UART0_PL011_S
static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_S = {
.base = MUSCA_UART0_S_BASE,
.def_baudrate = 115200,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_S = {
.state = 0,
.uart_clk = 0,
.baudrate = 0};
struct uart_pl011_dev_t UART0_PL011_DEV_S = {&(UART0_PL011_DEV_CFG_S),
&(UART0_PL011_DEV_DATA_S)};
#endif
#ifdef UART0_PL011_NS
static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_NS = {
.base = MUSCA_UART0_NS_BASE,
.def_baudrate = 115200,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_NS = {
.state = 0,
.uart_clk = 0,
.baudrate = 0};
struct uart_pl011_dev_t UART0_PL011_DEV_NS = {&(UART0_PL011_DEV_CFG_NS),
&(UART0_PL011_DEV_DATA_NS)};
#endif
#ifdef UART1_PL011_S
static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_S = {
.base = MUSCA_UART1_S_BASE,
.def_baudrate = 115200,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
static struct uart_pl011_dev_data_t UART1_PL011_DEV_DATA_S = {
.state = 0,
.uart_clk = 0,
.baudrate = 0};
struct uart_pl011_dev_t UART1_PL011_DEV_S = {&(UART1_PL011_DEV_CFG_S),
&(UART1_PL011_DEV_DATA_S)};
#endif
#ifdef UART1_PL011_NS
static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_NS = {
.base = MUSCA_UART1_NS_BASE,
.def_baudrate = 115200,
.def_wlen = UART_PL011_WLEN_8,
.def_parity = UART_PL011_PARITY_DISABLED,
.def_stopbit = UART_PL011_STOPBIT_1};
static struct uart_pl011_dev_data_t UART1_PL011_DEV_DATA_NS = {
.state = 0,
.uart_clk = 0,
.baudrate = 0};
struct uart_pl011_dev_t UART1_PL011_DEV_NS = {&(UART1_PL011_DEV_CFG_NS),
&(UART1_PL011_DEV_DATA_NS)};
#endif
/* QSPI IP6514E driver structures */
#ifdef QSPI_IP6514E_S
static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_S = {
.base = MUSCA_QSPI_REG_S_BASE,
/*
* On Musca-A1, only the 18 first address bits are used for any AHB
* address in a request coming to the QSPI Flash controller.
* It means that direct accesses are limited to the first 256 KiB of the
* Flash memory (if the Remap register is not used) and that the Indirect
* Trigger zone needs to be inside the first 256 KiB as well.
*/
.addr_mask = (1U << 18) - 1, /* 256 KiB minus 1 byte */
};
struct qspi_ip6514e_dev_t QSPI_DEV_S = {
&QSPI_DEV_CFG_S
};
#endif
#ifdef QSPI_IP6514E_NS
static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_NS = {
.base = MUSCA_QSPI_REG_NS_BASE,
/*
* On Musca-A1, only the 18 first address bits are used for any AHB
* address in a request coming to the QSPI Flash controller.
* It means that direct accesses are limited to the first 256 KiB of the
* Flash memory (if the Remap register is not used) and that the Indirect
* Trigger zone needs to be inside the first 256 KiB as well.
*/
.addr_mask = (1U << 18) - 1, /* 256 KiB minus 1 byte */
};
struct qspi_ip6514e_dev_t QSPI_DEV_NS = {
&QSPI_DEV_CFG_NS
};
#endif
/* ======= External peripheral configuration structure definitions ======= */
/* MT25QL Flash memory library structures */
#if (defined(MT25QL_S) && defined(QSPI_IP6514E_S))
struct mt25ql_dev_t MT25QL_DEV_S = {
.controller = &QSPI_DEV_S,
.direct_access_start_addr = MUSCA_QSPI_FLASH_S_BASE,
.baud_rate_div = 4U,
/*
* 8 MiB flash memory are advertised in the Arm Musca-A Test Chip and Board
* Technical Reference Manual. The MT25QL Flash device may however contain
* more.
*/
.size = 0x00800000U, /* 8 MiB */
.func_state = MT25QL_FUNC_STATE_DEFAULT,
};
#endif
#if (defined(MT25QL_NS) && defined(QSPI_IP6514E_NS))
struct mt25ql_dev_t MT25QL_DEV_NS = {
.controller = &QSPI_DEV_NS,
.direct_access_start_addr = MUSCA_QSPI_FLASH_NS_BASE,
.baud_rate_div = 4U,
/*
* 8 MiB flash memory are advertised in the Arm Musca-A Test Chip and Board
* Technical Reference Manual. The MT25QL Flash device may however contain
* more.
*/
.size = 0x00800000U, /* 8 MiB */
.func_state = MT25QL_FUNC_STATE_DEFAULT,
};
#endif

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/platform_retarget_dev.h
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@ -1,205 +0,0 @@
/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_retarget_dev.h
* \brief The structure definitions in this file are exported based on the peripheral
* definitions from device_cfg.h.
* This retarget file is meant to be used as a helper for baremetal
* applications and/or as an example of how to configure the generic
* driver structures.
*/
#ifndef __ARM_LTD_MUSCA_A1_RETARGET_DEV_H__
#define __ARM_LTD_MUSCA_A1_RETARGET_DEV_H__
#include "device_cfg.h"
/* ======= Peripheral configuration structure declarations ======= */
/* ARM SCC driver structures */
#ifdef MUSCA_A1_SCC_S
#include "musca_a1_scc_drv.h"
extern struct musca_a1_scc_dev_t MUSCA_A1_SCC_DEV_S;
#endif
#ifdef MUSCA_A1_SCC_NS
#include "musca_a1_scc_drv.h"
extern struct musca_a1_scc_dev_t MUSCA_A1_SCC_DEV_NS;
#endif
/* ARM MPC SIE 200 driver structures */
#ifdef MPC_ISRAM0_S
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S;
#endif
#ifdef MPC_ISRAM1_S
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S;
#endif
#ifdef MPC_ISRAM2_S
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S;
#endif
#ifdef MPC_ISRAM3_S
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S;
#endif
#ifdef MPC_CODE_SRAM_S
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_S;
#endif
#ifdef MPC_CODE_SRAM_NS
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_NS;
#endif
#ifdef MPC_QSPI_S
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_QSPI_DEV_S;
#endif
#ifdef MPC_QSPI_NS
#include "mpc_sie200_drv.h"
extern struct mpc_sie200_dev_t MPC_QSPI_DEV_NS;
#endif
/* ARM UART PL011 driver structures */
#ifdef UART0_PL011_S
#include "uart_pl011_drv.h"
extern struct uart_pl011_dev_t UART0_PL011_DEV_S;
#endif
#ifdef UART0_PL011_NS
#include "uart_pl011_drv.h"
extern struct uart_pl011_dev_t UART0_PL011_DEV_NS;
#endif
#ifdef UART1_PL011_S
#include "uart_pl011_drv.h"
extern struct uart_pl011_dev_t UART1_PL011_DEV_S;
#endif
#ifdef UART1_PL011_NS
#include "uart_pl011_drv.h"
extern struct uart_pl011_dev_t UART1_PL011_DEV_NS;
#endif
/* CMSDK Timer driver structures */
#ifdef CMSDK_TIMER0_S
#include "timer_cmsdk_drv.h"
extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S;
#endif
#ifdef CMSDK_TIMER0_NS
#include "timer_cmsdk_drv.h"
extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS;
#endif
#ifdef CMSDK_TIMER1_S
#include "timer_cmsdk_drv.h"
extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S;
#endif
#ifdef CMSDK_TIMER1_NS
#include "timer_cmsdk_drv.h"
extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS;
#endif
/* General-Purpose Timer driver structures */
#ifdef GP_TIMER_S
#include "timer_gp_drv.h"
extern struct timer_gp_dev_t GP_TIMER_DEV_S;
#endif
#ifdef GP_TIMER_NS
#include "timer_gp_drv.h"
extern struct timer_gp_dev_t GP_TIMER_DEV_NS;
#endif
/* QSPI Flash Controller driver structures */
#ifdef QSPI_IP6514E_S
#include "qspi_ip6514e_drv.h"
extern struct qspi_ip6514e_dev_t QSPI_DEV_S;
#endif
#ifdef QSPI_IP6514E_NS
#include "qspi_ip6514e_drv.h"
extern struct qspi_ip6514e_dev_t QSPI_DEV_NS;
#endif
/* ARM PPC driver structures */
#ifdef AHB_PPC0_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t AHB_PPC0_DEV_S;
#endif
#ifdef AHB_PPCEXP0_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S;
#endif
#ifdef AHB_PPCEXP1_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t AHB_PPCEXP1_DEV_S;
#endif
#ifdef AHB_PPCEXP2_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S;
#endif
#ifdef AHB_PPCEXP3_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S;
#endif
#ifdef APB_PPC0_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t APB_PPC0_DEV_S;
#endif
#ifdef APB_PPC1_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t APB_PPC1_DEV_S;
#endif
#ifdef APB_PPCEXP0_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S;
#endif
#ifdef APB_PPCEXP1_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S;
#endif
#ifdef APB_PPCEXP2_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S;
#endif
#ifdef APB_PPCEXP3_S
#include "ppc_sse200_drv.h"
extern struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S;
#endif
/* ======= External peripheral configuration structure declarations ======= */
/* MT25QL Flash memory library structures */
#if (defined(MT25QL_S) && defined(QSPI_IP6514E_S))
#include "Libraries/mt25ql_flash_lib.h"
extern struct mt25ql_dev_t MT25QL_DEV_S;
#endif
#if (defined(MT25QL_NS) && defined(QSPI_IP6514E_NS))
#include "Libraries/mt25ql_flash_lib.h"
extern struct mt25ql_dev_t MT25QL_DEV_NS;
#endif
#endif /* __ARM_LTD_MUSCA_A1_RETARGET_DEV_H__ */

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/platform_retarget_pins.h
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/*
* Copyright (c) 2016-2019 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing software
* distributed under the License is distributed on an "AS IS" BASIS
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* \file platform_retarget_pins.h
* \brief This file defines all the pins for this platform.
*/
#ifndef __ARM_LTD_MUSCA_RETARGET_PINS_H__
#define __ARM_LTD_MUSCA_RETARGET_PINS_H__
/* AHB GPIO pin names */
enum arm_gpio_pin_name_t {
AHB_GPIO0_0 = 0U,
AHB_GPIO0_1,
AHB_GPIO0_2,
AHB_GPIO0_3,
AHB_GPIO0_4,
AHB_GPIO0_5,
AHB_GPIO0_6,
AHB_GPIO0_7,
AHB_GPIO0_8,
AHB_GPIO0_9,
AHB_GPIO0_10,
AHB_GPIO0_11,
AHB_GPIO0_12,
AHB_GPIO0_13,
AHB_GPIO0_14,
AHB_GPIO0_15,
};
#endif /* __ARM_LTD_MUSCA_RETARGET_PINS_H__ */

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/system_cmsdk_musca.c
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/*
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Source\system_ARMCM33.c
* https://github.com/ARM-software/CMSIS_5/tree/5.0.1
* Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
*/
#include "system_cmsdk_musca.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (50000000UL)
#define SYSTEM_CLOCK (XTAL)
#define SYSTEM_REFCLK (32768UL)
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK;
uint32_t PeripheralClock = SYSTEM_CLOCK;
uint32_t RefClock = SYSTEM_REFCLK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
PeripheralClock = SYSTEM_CLOCK;
RefClock = SYSTEM_REFCLK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* set CP10 Full Access */
(3U << 11U*2U) ); /* set CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/system_cmsdk_musca.h
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/*
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h
*/
#ifndef SYSTEM_CMSDK_MUSCA_H
#define SYSTEM_CMSDK_MUSCA_H
#ifdef __cplusplus
extern "C" {
#endif
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum IRQn
{
/* =========================================== Core Specific Interrupt Numbers ============================================= */
NonMaskableInt_IRQn = -14, /* -14 Non Maskable Interrupt */
HardFault_IRQn = -13, /* -13 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* -12 Memory Management Interrupt */
BusFault_IRQn = -11, /* -11 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* -10 Usage Fault Interrupt */
SecureFault_IRQn = -9, /* -9 Secure Fault Interrupt */
SVCall_IRQn = -5, /* -5 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* -4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* -2 Pend SV Interrupt */
SysTick_IRQn = -1, /* -1 System Tick Interrupt */
/* ======================================== Musca Specific SSE-200 Interrupt Numbers ====================================== */
NS_WATCHDOG_RESET_IRQn = 0, /* Non-Secure Watchdog Reset Request Interrupt */
NS_WATCHDOG_IRQn = 1, /* Non-Secure Watchdog Interrupt */
S32K_TIMER_IRQn = 2, /* S32K Timer Interrupt */
TIMER0_IRQn = 3, /* CMSDK Timer 0 Interrupt */
TIMER1_IRQn = 4, /* CMSDK Timer 1 Interrupt */
DUALTIMER_IRQn = 5, /* CMSDK Dual Timer Interrupt */
MHU0_IRQn = 6, /* Message Handling Unit 0 Interrupt */
MHU1_IRQn = 7, /* Message Handling Unit 1 Interrupt */
CRYPTOCELL_IRQn = 8, /* CryptoCell-312 Interrupt */
S_MPC_COMBINED_IRQn = 9, /* Secure Combined MPC Interrupt */
S_PPC_COMBINED_IRQn = 10, /* Secure Combined PPC Interrupt */
S_MSC_COMBINED_IRQn = 11, /* Secure Combined MSC Interrupt */
S_BRIDGE_ERR_IRQn = 12, /* Secure Bridge Error Combined Interrupt */
I_CACHE_INV_ERR_IRQn = 13, /* Instruction Cache Invalidation Interrupt */
/* Reserved = 14, Reserved */
SYS_PPU_IRQn = 15, /* System PPU Interrupt */
CPU0_PPU_IRQn = 16, /* CPU0 PPU Interrupt */
CPU1_PPU_IRQn = 17, /* CPU1 PPU Interrupt */
CPU0_DGB_PPU_IRQn = 18, /* CPU0 Debug PPU Interrupt */
CPU1_DGB_PPU_IRQn = 19, /* CPU1 Debug PPU Interrupt */
CRYPTOCELL_PPU_IRQn = 20, /* CryptoCell PPU Interrupt */
/* Reserved = 21, Reserved */
RAM0_PPU_IRQn = 22, /* RAM 0 PPU Interrupt */
RAM1_PPU_IRQn = 23, /* RAM 1 PPU Interrupt */
RAM2_PPU_IRQn = 24, /* RAM 2 PPU Interrupt */
RAM3_PPU_IRQn = 25, /* RAM 3 PPU Interrupt */
DEBUG_PPU_IRQn = 26, /* Debug PPU Interrupt */
/* Reserved = 27, Reserved */
CPU0_CTI_IRQn = 28, /* CPU0 CTI Interrupt */
CPU1_CTI_IRQn = 29, /* CPU1 CTI Interrupt */
/* Reserved = 30, Reserved */
/* Reserved = 31, Reserved */
/* ========================================== Musca Specific Expansion Interrupt Numbers =================================== */
/* None = 32, Not used. Tied to 0 */
GpTimer_IRQn = 33, /* General Purpose Timer Interrupt */
I2C0_IRQn = 34, /* I2C0 Interrupt */
I2C1_IRQn = 35, /* I2C1 Interrupt */
I2S_IRQn = 36, /* I2S Interrupt */
SPI_IRQn = 37, /* SPI Interrupt */
QSPI_IRQn = 38, /* QSPI Interrupt */
UART0_Rx_IRQn = 39, /* UART0 receive FIFO interrupt */
UART0_Tx_IRQn = 40, /* UART0 transmit FIFO interrupt */
UART0_RxTimeout_IRQn = 41, /* UART0 receive timeout interrupt */
UART0_ModemStatus_IRQn = 42, /* UART0 modem status interrupt */
UART0_Error_IRQn = 43, /* UART0 error interrupt */
UART0_IRQn = 44, /* UART0 interrupt */
UART1_Rx_IRQn = 45, /* UART1 receive FIFO interrupt */
UART1_Tx_IRQn = 46, /* UART1 transmit FIFO interrupt */
UART1_RxTimeout_IRQn = 47, /* UART1 receive timeout interrupt */
UART1_ModemStatus_IRQn = 48, /* UART1 modem status interrupt */
UART1_Error_IRQn = 49, /* UART1 error interrupt */
UART1_IRQn = 50, /* UART1 interrupt */
GPIO_0_IRQn = 51, /* GPIO 0 interrupt */
GPIO_1_IRQn = 52, /* GPIO 1 interrupt */
GPIO_2_IRQn = 53, /* GPIO 2 interrupt */
GPIO_3_IRQn = 54, /* GPIO 3 interrupt */
GPIO_4_IRQn = 55, /* GPIO 4 interrupt */
GPIO_5_IRQn = 56, /* GPIO 5 interrupt */
GPIO_6_IRQn = 57, /* GPIO 6 interrupt */
GPIO_7_IRQn = 58, /* GPIO 7 interrupt */
GPIO_8_IRQn = 59, /* GPIO 8 interrupt */
GPIO_9_IRQn = 60, /* GPIO 9 interrupt */
GPIO_10_IRQn = 61, /* GPIO 10 interrupt */
GPIO_11_IRQn = 62, /* GPIO 11 interrupt */
GPIO_12_IRQn = 63, /* GPIO 12 interrupt */
GPIO_13_IRQn = 64, /* GPIO 13 interrupt */
GPIO_14_IRQn = 65, /* GPIO 14 interrupt */
GPIO_15_IRQn = 66, /* GPIO 15 interrupt */
Combined_IRQn = 67, /* Combined interrupt */
PVT_IRQn = 68, /* PVT sensor interrupt */
/* Reserved = 69, Reserved */
PWM_0_IRQn = 70, /* PWM0 interrupt */
RTC_IRQn = 71, /* RTC interrupt */
GpTimer1_IRQn = 72, /* General Purpose Timer1 Interrupt */
GpTimer0_IRQn = 73, /* General Purpose Timer0 Interrupt */
PWM_1_IRQn = 74, /* PWM1 interrupt */
PWM_2_IRQn = 75, /* PWM2 interrupt */
IOMUX_IRQn = 76, /* IOMUX interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
#include "system_core_musca.h"
/** @} */ /* End of group Configuration_of_CMSIS */
#include <core_cm33.h> /*!< ARM Cortex-M33 processor and core peripherals */
#include "system_musca.h" /*!< Musca System */
/* ======================================== Start of section using anonymous unions ======================================== */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripherals
* @{
*/
/*@}*/ /* end of group <Device>_Peripherals */
/* ========================================= End of section using anonymous unions ========================================= */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_peripheralAddr
* @{
*/
/* Non-Secure Peripheral and SRAM base address */
#define MUSCA_CODE_SRAM_NS_BASE (0x00000000UL) /*!< (Non-Secure Code SRAM ) Base Address */
#define MUSCA_QSPI_FLASH_NS_BASE (0x00200000UL) /*!< (Non-Secure QSPI FLASH ) Base Address */
#define MUSCA_OTP_NS_BASE (0x0E000000UL) /*!< (Non-Secure OTP ) Base Address */
#define MUSCA_SRAM_NS_BASE (0x20000000UL) /*!< (Non-Secure Internal SRAM ) Base Address */
#define MUSCA_BASE_ELEMENT_NS_BASE (0x40000000UL) /*!< (Non-Secure Base Peripherals ) Base Address */
#define MUSCA_CMSDK_TIMER0_NS_BASE (0x40000000UL) /*!< (Non-Secure CMSDK Timer0 ) Base Address */
#define MUSCA_CMSDK_TIMER1_NS_BASE (0x40001000UL) /*!< (Non-Secure CMSDK Timer1 ) Base Address */
#define MUSCA_CMSDK_DUALTIMER_NS_BASE (0x40002000UL) /*!< (Non-Secure CMSDK Dual Timer ) Base Address */
#define MUSCA_MHU0_NS_BASE (0x40003000UL) /*!< (Non-Secure MHU0 ) Base Address */
#define MUSCA_MHU1_NS_BASE (0x40004000UL) /*!< (Non-Secure MHU1 ) Base Address */
#define MUSCA_CPU_ELEMENT_NS_BASE (0x40010000UL) /*!< (Non-Secure CPU Peripherals ) Base Address */
#define MUSCA_SYSTEM_INFO_NS_BASE (0x40020000UL) /*!< (Non-Secure System Info ) Base Address */
#define MUSCA_CMSDK_S32KTIMER_NS_BASE (0x4002F000UL) /*!< (Non-Secure CMSDK S32K Timer ) Base Address */
#define MUSCA_NSPCTRL_NS_BASE (0x40080000UL) /*!< (Non-Secure Privilege Ctrl Blk) Base Address */
#define MUSCA_CMSDK_WATCHDOG_NS_BASE (0x40081000UL) /*!< (Non-Secure CMSDK Watchdog ) Base Address */
#define MUSCA_UART0_NS_BASE (0x40101000UL) /*!< (Non-Secure UART0 ) Base Address */
#define MUSCA_UART1_NS_BASE (0x40102000UL) /*!< (Non-Secure UART1 ) Base Address */
#define MUSCA_SPI0_NS_BASE (0x40103000UL) /*!< (Non-Secure SPI0 ) Base Address */
#define MUSCA_I2C0_NS_BASE (0x40104000UL) /*!< (Non-Secure I2C0 ) Base Address */
#define MUSCA_I2C1_NS_BASE (0x40105000UL) /*!< (Non-Secure I2C1 ) Base Address */
#define MUSCA_I2S_NS_BASE (0x40106000UL) /*!< (Non-Secure I2S ) Base Address */
#define MUSCA_PWM0_NS_BASE (0x40107000UL) /*!< (Non-Secure PWM0 ) Base Address */
#define MUSCA_RTC_NS_BASE (0x40108000UL) /*!< (Non-Secure RTC ) Base Address */
#define MUSCA_PVT_NS_BASE (0x40109000UL) /*!< (Non-Secure PVT sensors ) Base Address */
#define MUSCA_QSPI_REG_NS_BASE (0x4010A000UL) /*!< (Non-Secure QSPI registers ) Base Address */
#define MUSCA_TIMER_NS_BASE (0x4010B000UL) /*!< (Non-Secure Timer ) Base Address */
#define MUSCA_SCC_NS_BASE (0x4010C000UL) /*!< (Non-Secure SCC ) Base Address */
#define MUSCA_PWM1_NS_BASE (0x4010E000UL) /*!< (Non-Secure PWM1 ) Base Address */
#define MUSCA_PWM2_NS_BASE (0x4010F000UL) /*!< (Non-Secure PWM2 ) Base Address */
#define MUSCA_GPIO_NS_BASE (0x40110000UL) /*!< (Non-Secure GPIO ) Base Address */
#define MUSCA_QSPI_MPC_NS_BASE (0x40120000UL) /*!< (Non-Secure QSPI MPC ) Base Address */
#define MUSCA_CODE_SRAM_MPC_NS_BASE (0x40130000UL) /*!< (Non-Secure Code SRAM MPC ) Base Address */
#define MUSCA_DEFAULT_SLAVE_NS_BASE (0x60000000UL) /*!< (Non-Secure Unused AHB ) Base Address */
/* Secure Peripheral and SRAM base address */
#define MUSCA_CODE_SRAM_S_BASE (0x10000000UL) /*!< (Secure Code SRAM ) Base Address */
#define MUSCA_QSPI_FLASH_S_BASE (0x10200000UL) /*!< (Secure QSPI FLASH ) Base Address */
#define MUSCA_OTP_S_BASE (0x1E000000UL) /*!< (Secure OTP ) Base Address */
#define MUSCA_SRAM_S_BASE (0x30000000UL) /*!< (Secure Internal SRAM ) Base Address */
#define MUSCA_BASE_ELEMENT_S_BASE (0x50000000UL) /*!< (Secure Base Peripherals ) Base Address */
#define MUSCA_MHU0_S_BASE (0x50003000UL) /*!< (Secure MHU0 ) Base Address */
#define MUSCA_MHU1_S_BASE (0x50004000UL) /*!< (Secure MHU1 ) Base Address */
#define MUSCA_CPU_ELEMENT_S_BASE (0x50010000UL) /*!< (Secure CPU Peripherals ) Base Address */
#define MUSCA_SYSTEM_INFO_S_BASE (0x50020000UL) /*!< (Secure System Info ) Base Address */
#define MUSCA_SYSTEM_CTRL_S_BASE (0x50021000UL) /*!< (Secure System Control ) Base Address */
#define MUSCA_CMSDK_S32KTIMER_S_BASE (0x5002F000UL) /*!< (Secure CMSDK S32K Timer ) Base Address */
#define MUSCA_CMSDK_TIMER0_S_BASE (0x50000000UL) /*!< (Secure CMSDK Timer0 ) Base Address */
#define MUSCA_CMSDK_TIMER1_S_BASE (0x50001000UL) /*!< (Secure CMSDK Timer1 ) Base Address */
#define MUSCA_CMSDK_DUALTIMER_S_BASE (0x50002000UL) /*!< (Secure CMSDK Dual Timer ) Base Address */
#define MUSCA_SPCTRL_S_BASE (0x50080000UL) /*!< (Secure Privilege Ctrl Blk) Base Address */
#define MUSCA_CMSDK_WATCHDOG_S_BASE (0x50081000UL) /*!< (Secure CMSDK Watchdog ) Base Address */
#define MUSCA_MPC_SRAM0_S_BASE (0x50083000UL) /*!< (Secure MPC SRAM Bank 0 ) Base Address */
#define MUSCA_MPC_SRAM1_S_BASE (0x50084000UL) /*!< (Secure MPC SRAM Bank 1 ) Base Address */
#define MUSCA_MPC_SRAM2_S_BASE (0x50085000UL) /*!< (Secure MPC SRAM Bank 2 ) Base Address */
#define MUSCA_MPC_SRAM3_S_BASE (0x50086000UL) /*!< (Secure MPC SRAM Bank 3 ) Base Address */
#define MUSCA_UART0_S_BASE (0x50101000UL) /*!< (Secure UART0 ) Base Address */
#define MUSCA_UART1_S_BASE (0x50102000UL) /*!< (Secure UART1 ) Base Address */
#define MUSCA_SPI0_S_BASE (0x50103000UL) /*!< (Secure SPI0 ) Base Address */
#define MUSCA_I2C0_S_BASE (0x50104000UL) /*!< (Secure I2C0 ) Base Address */
#define MUSCA_I2C1_S_BASE (0x50105000UL) /*!< (Secure I2C1 ) Base Address */
#define MUSCA_I2S_S_BASE (0x50106000UL) /*!< (Secure I2S ) Base Address */
#define MUSCA_PWM0_S_BASE (0x50107000UL) /*!< (Secure PWM0 ) Base Address */
#define MUSCA_RTC_S_BASE (0x50108000UL) /*!< (Secure RTC ) Base Address */
#define MUSCA_PVT_S_BASE (0x50109000UL) /*!< (Secure PVT sensors ) Base Address */
#define MUSCA_QSPI_REG_S_BASE (0x5010A000UL) /*!< (Secure QSPI registers ) Base Address */
#define MUSCA_TIMER_S_BASE (0x5010B000UL) /*!< (Secure Timer ) Base Address */
#define MUSCA_SCC_S_BASE (0x5010C000UL) /*!< (Secure SCC ) Base Address */
#define MUSCA_PWM1_S_BASE (0x5010E000UL) /*!< (Secure PWM1 ) Base Address */
#define MUSCA_PWM2_S_BASE (0x5010F000UL) /*!< (Secure PWM2 ) Base Address */
#define MUSCA_GPIO_S_BASE (0x50110000UL) /*!< (Secure GPIO ) Base Address */
#define MUSCA_QSPI_MPC_S_BASE (0x50120000UL) /*!< (Secure QSPI MPC ) Base Address */
#define MUSCA_CODE_SRAM_MPC_S_BASE (0x50130000UL) /*!< (Secure Code SRAM MPC ) Base Address */
#define MUSCA_DEFAULT_SLAVE_S_BASE (0x70000000UL) /*!< (Secure Unused AHB ) Base Address */
/* Peripheral memory map */
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup Device_Peripheral_declaration
* @{
*/
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_MUSCA_H */

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/*
* Copyright (c) 2018-2019 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef SYSTEM_CORE_MUSCA_H
#define SYSTEM_CORE_MUSCA_H
#ifdef DUAL_CORE
/* Both cores are used */
/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
#define __CM33_REV 0x0001U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#if defined CORE0
#define __FPU_PRESENT 0U /* no FPU present */
#define __DSP_PRESENT 0U /* no DSP extension present */
#elif defined CORE1
#define __FPU_PRESENT 1U /* FPU present */
#define __DSP_PRESENT 1U /* DSP extension present */
#else
#error "Either CORE0 or CORE1 must be defined"
#endif /* CORE0/1 */
#else /* DUAL_CORE */
/* Single core is used */
/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
#define __CM33_REV 0x0000U /* Core revision r0p1 */
#define __SAUREGION_PRESENT 1U /* SAU regions present */
#define __MPU_PRESENT 1U /* MPU present */
#define __VTOR_PRESENT 1U /* VTOR present */
#define __NVIC_PRIO_BITS 3U /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 0U /* no FPU present */
#define __DSP_PRESENT 0U /* no DSP extension present */
#endif /* DUAL_CORE */
#endif /* SYSTEM_CORE_MUSCA_H */

56
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/system_musca.h
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/*
* Copyright (c) 2017-2019 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Include\system_ARMCM33.h
* Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
*
*/
#ifndef SYSTEM_MUSCA_H
#define SYSTEM_MUSCA_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */
extern uint32_t RefClock; /*!< External Reference Clock Frequency */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
It should be called from Reset Handler within the first few steps.
The minimal feature set should be initialised for successful exit
from Reset Handler to main entry point.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_MUSCA_H */

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/gpio_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file implements APIS defined in hal/gpio_api.h
* Note: Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
#include <stddef.h>
#include "gpio_api.h"
#include "pinmap.h"
#include "objects.h"
#include "mbed_error.h"
uint32_t gpio_set(PinName pin)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
return 0;
}
void gpio_init(gpio_t *obj, PinName pin)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
int gpio_is_connected(const gpio_t *obj)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
return 0;
}
void gpio_write(gpio_t *obj, int value)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
int gpio_read(gpio_t *obj)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
return 0;
}

65
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/gpio_irq_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* This file implements APIS defined in hal/gpio_irq_api.h
* Note: Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
#include <stddef.h>
#include "gpio_irq_api.h"
#include "objects.h"
#include "mbed_error.h"
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler,
uint32_t id)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
return 0;
}
void gpio_irq_free(gpio_irq_t *obj)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
void gpio_irq_enable(gpio_irq_t *obj)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}
void gpio_irq_disable(gpio_irq_t *obj)
{
/* Due to a HW limitation, GPIO in Musca-A1 is Secure only, so secure
* service should be used for GPIO in NS domain.
*/
}

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/gpio_object.h
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Object to store GPIO specific data through the configuration
*/
typedef struct gpio_s {
/** GPIO is not available in Musca-A1 in non-secure domain, so this dummy
* structure is needed for successful build.
*/
uint32_t dummy;
} gpio_t;
struct gpio_irq_s {
/** GPIO is not available in Musca-A1 in non-secure domain, so this dummy
* structure is needed for successful build.
*/
uint32_t dummy;
};
#ifdef __cplusplus
}
#endif
#endif

89
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/lp_ticker.c
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* Low-power elapsed time measure and interval ticker,
* using General Purpose Timer \ref timer_gp_dev_t.
*/
#include "cmsis.h"
#include "device_cfg.h"
#include "timer_gp_drv.h"
#include "lp_ticker_api.h"
/* Check if the module configuration is right. These definitions
are usually located in device_cfg.h */
#ifndef GP_TIMER_DEV
#error "Configuration macro GP_TIMER_DEV is undefined!"
#endif
void lp_ticker_init(void)
{
timer_gp_init(&GP_TIMER_DEV);
NVIC_EnableIRQ(GP_TIMER_ALARM0_IRQ);
timer_gp_interrupt_disable(&GP_TIMER_DEV, GP_TIMER_ALARM_NR);
}
void lp_ticker_free(void)
{
/* This function should stop the ticker from counting, but GP Timer cannot
* be stopped.
*/
timer_gp_interrupt_disable(&GP_TIMER_DEV, GP_TIMER_ALARM_NR);
}
uint32_t lp_ticker_read(void)
{
return timer_gp_get_counter(&GP_TIMER_DEV);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
timer_gp_set_alarm_value(&GP_TIMER_DEV, GP_TIMER_ALARM_NR, (uint32_t)timestamp);
timer_gp_interrupt_enable(&GP_TIMER_DEV, GP_TIMER_ALARM_NR);
}
void lp_ticker_disable_interrupt(void)
{
timer_gp_interrupt_disable(&GP_TIMER_DEV, GP_TIMER_ALARM_NR);
}
void lp_ticker_clear_interrupt(void)
{
timer_gp_interrupt_clear(&GP_TIMER_DEV, GP_TIMER_ALARM_NR);
}
void lp_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(GP_TIMER_ALARM0_IRQ);
}
const ticker_info_t* lp_ticker_get_info(void)
{
static const ticker_info_t info = {
GP_TIMER_FREQ_HZ,
GP_TIMER_BIT_WIDTH
};
return &info;
}
#ifndef GP_TIMER_IRQ0_HANDLER
#error "GP_TIMER_IRQ0_HANDLER should be defined, check device_cfg.h!"
#endif
void GP_TIMER_IRQ0_HANDLER(void)
{
lp_ticker_irq_handler();
}

BIN
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/mcuboot.bin
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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/objects.h
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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "platform_retarget_dev.h"
#include "gpio_object.h"
#ifdef __cplusplus
extern "C" {
#endif
struct serial_s {
struct uart_pl011_dev_t *uart_dev;
UARTName uart_index; /* UART device number */
IRQn_Type tx_irq;
IRQn_Type rx_irq;
IRQn_Type rx_timeout_irq;
};
#if DEVICE_FLASH
struct flash_s {
uint8_t dummy;
};
#endif // DEVICE_FLASH
#if DEVICE_TRNG
struct trng_s {
/* nothing to be stored for now */
void *dummy;
};
#endif // DEVICE_TRNG
#ifdef __cplusplus
}
#endif
#endif

241
targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/partition/flash_layout.h
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/*
* Copyright (c) 2018-2019 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __FLASH_LAYOUT_H__
#define __FLASH_LAYOUT_H__
/* Flash layout on Musca with BL2 (single image boot, mandatory):
*
* 0x0020_0000 BL2 - MCUBoot (128 KB)
* 0x0022_0000 Primary image area (1 MB):
* 0x0022_0000 Secure image primary
* 0x002A_0000 Non-secure image primary
* 0x0032_0000 Secondary image area (1 MB):
* 0x0032_0000 Secure image secondary
* 0x003A_0000 Non-secure image secondary
* 0x0042_0000 Secure Storage Area (8 KB)
* 0x0042_2000 Internal Trusted Storage Area (8 KB)
* 0x0042_4000 NV counters area (4 KB)
* 0x0042_5000 Unused
*/
/* Code SRAM layout on Musca (with BL2, which is mandatory) after the newest
* image has been copied to SRAM:
* 0x0000_0000 BL2 - MCUBoot (128 KB)
* 0x0002_0000 Flash_area_newest_image (1 MB)
* 0x0002_0000 Secure image primary
* 0x000A_0000 Non-secure image primary
* 0x0012_00000 Unused
*/
/* This header file is included from linker scatter file as well, where only a
* limited C constructs are allowed. Therefore it is not possible to include
* here the platform_base_address.h to access flash related defines. To resolve
* this some of the values are redefined here with different names, these are
* marked with comment.
*/
/* Size of a Secure and of a Non-secure image */
#define FLASH_S_PARTITION_SIZE (0x80000) /* S partition: 512 KB */
#define FLASH_NS_PARTITION_SIZE (0x80000) /* NS partition: 512 KB */
#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \
FLASH_NS_PARTITION_SIZE) ? \
FLASH_S_PARTITION_SIZE : \
FLASH_NS_PARTITION_SIZE)
/* Sector size of the flash hardware */
#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x1000) /* 4 KB */
#define FLASH_TOTAL_SIZE (0x800000) /* 8 MB */
/* Flash layout info for BL2 bootloader */
/* Same as MPC_QSPI_RANGE_BASE_S */
#define FLASH_BASE_ADDRESS (0x10200000)
/* Offset and size definitions of the flash partitions that are handled by the
* bootloader. The image swapping is done between IMAGE_PRIMARY and
* IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image
* swapping.
*/
#define FLASH_AREA_BL2_OFFSET (0x0)
#define FLASH_AREA_BL2_SIZE (0x20000) /* 128KB */
#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1)
/* Secure + Non-secure image primary slot */
#define FLASH_AREA_0_ID (1)
#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)
#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
/* Secure + Non-secure secondary slot */
#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1)
#define FLASH_AREA_2_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
/* Not used, only the RAM loading firmware upgrade operation
* is supported on Musca-A.
*/
#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1)
#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
#define FLASH_AREA_SCRATCH_SIZE (0)
/* Maximum number of image sectors supported by the bootloader. */
#define BOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE) / \
FLASH_AREA_IMAGE_SECTOR_SIZE)
#elif (MCUBOOT_IMAGE_NUMBER == 2)
/* Secure image primary slot */
#define FLASH_AREA_0_ID (1)
#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE)
#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE)
/* Non-secure image primary slot */
#define FLASH_AREA_1_ID (FLASH_AREA_0_ID + 1)
#define FLASH_AREA_1_OFFSET (FLASH_AREA_0_OFFSET + FLASH_AREA_0_SIZE)
#define FLASH_AREA_1_SIZE (FLASH_NS_PARTITION_SIZE)
/* Secure image secondary slot */
#define FLASH_AREA_2_ID (FLASH_AREA_1_ID + 1)
#define FLASH_AREA_2_OFFSET (FLASH_AREA_1_OFFSET + FLASH_AREA_1_SIZE)
#define FLASH_AREA_2_SIZE (FLASH_S_PARTITION_SIZE)
/* Non-secure image secondary slot */
#define FLASH_AREA_3_ID (FLASH_AREA_2_ID + 1)
#define FLASH_AREA_3_OFFSET (FLASH_AREA_2_OFFSET + FLASH_AREA_2_SIZE)
#define FLASH_AREA_3_SIZE (FLASH_NS_PARTITION_SIZE)
/* Not used, only the RAM loading firmware upgrade operation
* is supported on Musca-A.
*/
#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_3_ID + 1)
#define FLASH_AREA_SCRATCH_OFFSET (FLASH_AREA_3_OFFSET + FLASH_AREA_3_SIZE)
#define FLASH_AREA_SCRATCH_SIZE (0)
/* Maximum number of image sectors supported by the bootloader. */
#define BOOT_MAX_IMG_SECTORS (FLASH_MAX_PARTITION_SIZE / \
FLASH_AREA_IMAGE_SECTOR_SIZE)
#else /* MCUBOOT_IMAGE_NUMBER > 2 */
#error "Only MCUBOOT_IMAGE_NUMBER 1 and 2 are supported!"
#endif /* MCUBOOT_IMAGE_NUMBER */
/* Not used, only the RAM loading firmware upgrade operation
* is supported on Musca-A. The maximum number of status entries
* supported by the bootloader.
*/
#define BOOT_STATUS_MAX_ENTRIES (0)
/* Secure Storage (SST) Service definitions */
#define FLASH_SST_AREA_OFFSET (FLASH_AREA_SCRATCH_OFFSET + \
FLASH_AREA_SCRATCH_SIZE)
#define FLASH_SST_AREA_SIZE (0x2000) /* 8 KB */
/* Internal Trusted Storage (ITS) Service definitions */
#define FLASH_ITS_AREA_OFFSET (FLASH_SST_AREA_OFFSET + \
FLASH_SST_AREA_SIZE)
#define FLASH_ITS_AREA_SIZE (0x2000) /* 8 KB */
/* NV Counters definitions */
#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \
FLASH_ITS_AREA_SIZE)
#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE)
/* Offset and size definition in flash area used by assemble.py */
#define SECURE_IMAGE_OFFSET (0x0)
#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE
#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \
SECURE_IMAGE_MAX_SIZE)
#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE
/* Image load address used by imgtool.py */
#define IMAGE_LOAD_ADDRESS (S_SRAM_ALIAS_BASE + \
FLASH_AREA_BL2_SIZE)
/* Define where executable memory for the images starts and ends */
#define IMAGE_EXECUTABLE_RAM_START (IMAGE_LOAD_ADDRESS)
#define IMAGE_EXECUTABLE_RAM_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
#define S_QSPI_ALIAS_BASE (0x10200000)
#define NS_QSPI_ALIAS_BASE (0x00200000)
#define S_SRAM_ALIAS_BASE (0x10000000)
#define NS_SRAM_ALIAS_BASE (0x00000000)
/* Flash device name used by BL2
* Name is defined in flash driver file: Driver_Flash.c
*/
#define FLASH_DEV_NAME Driver_FLASH0
/* Secure Storage (SST) Service definitions
* Note: Further documentation of these definitions can be found in the
* TF-M SST Integration Guide.
*/
#define SST_FLASH_DEV_NAME Driver_FLASH0
/* In this target the CMSIS driver requires only the offset from the base
* address instead of the full memory address.
*/
#define SST_FLASH_AREA_ADDR FLASH_SST_AREA_OFFSET
/* Dedicated flash area for SST */
#define SST_FLASH_AREA_SIZE FLASH_SST_AREA_SIZE
#define SST_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
/* Number of SST_SECTOR_SIZE per block */
#define SST_SECTORS_PER_BLOCK (0x1)
/* Specifies the smallest flash programmable unit in bytes */
#define SST_FLASH_PROGRAM_UNIT (0x1)
/* The maximum asset size to be stored in the SST area */
#define SST_MAX_ASSET_SIZE (512)
/* The maximum number of assets to be stored in the SST area */
#define SST_NUM_ASSETS (10)
/* Internal Trusted Storage (ITS) Service definitions
* Note: Further documentation of these definitions can be found in the
* TF-M ITS Integration Guide. The ITS should be in the internal flash, but is
* allocated in the external flash just for development platforms that don't
* have internal flash available.
*/
#define ITS_FLASH_DEV_NAME Driver_FLASH0
/* In this target the CMSIS driver requires only the offset from the base
* address instead of the full memory address.
*/
#define ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET
/* Dedicated flash area for ITS */
#define ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE
#define ITS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
/* Number of ITS_SECTOR_SIZE per block */
#define ITS_SECTORS_PER_BLOCK (0x1)
/* Specifies the smallest flash programmable unit in bytes */
#define ITS_FLASH_PROGRAM_UNIT (0x1)
/* The maximum asset size to be stored in the ITS area */
#define ITS_MAX_ASSET_SIZE (512)
/* The maximum number of assets to be stored in the ITS area */
#define ITS_NUM_ASSETS (10)
/* NV Counters definitions */
#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
#define TFM_NV_COUNTERS_AREA_SIZE (0x18) /* 24 Bytes */
#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET
#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE
/* Use QSPI Flash memory to store Code data */
#define S_ROM_ALIAS_BASE (0x10200000)
#define NS_ROM_ALIAS_BASE (0x00200000)
/* FIXME: Use SRAM2 memory to store RW data */
#define S_RAM_ALIAS_BASE (0x30000000)
#define NS_RAM_ALIAS_BASE (0x20000000)
#define TOTAL_ROM_SIZE (0x200000) /* 2 MB */
#define TOTAL_RAM_SIZE (0x20000) /* 128 KB */
#endif /* __FLASH_LAYOUT_H__ */

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targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/partition/image_macros_preprocessed.c
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/*
* Copyright (c) 2020 Arm Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
enum image_attributes {
RE_SECURE_IMAGE_OFFSET = (0x0),
RE_SECURE_IMAGE_MAX_SIZE = (0x80000),
RE_NON_SECURE_IMAGE_OFFSET = ((0x0) + (0x80000)),
RE_NON_SECURE_IMAGE_MAX_SIZE = (0x80000),
RE_IMAGE_LOAD_ADDRESS = ((0x10000000) + (0x20000)),
RE_SIGN_BIN_SIZE = ((0x80000) + (0x80000)),
};

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/*
* Copyright (c) 2017-2019 ARM Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __REGION_DEFS_H__
#define __REGION_DEFS_H__
#include "flash_layout.h"
#define BL2_HEAP_SIZE (0x0001000)
#define BL2_MSP_STACK_SIZE (0x0001800)
#define S_HEAP_SIZE (0x0001000)
#define S_MSP_STACK_SIZE_INIT (0x0000400)
#define S_MSP_STACK_SIZE (0x0000800)
#define S_PSP_STACK_SIZE (0x0000800)
#define NS_HEAP_SIZE (0x0001000)
#define NS_MSP_STACK_SIZE (0x0000400)
#define NS_PSP_STACK_SIZE (0x0000C00)
/* This size of buffer is big enough to store an attestation
* token produced by initial attestation service
*/
#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250)
/* MPC granularity is 128 KB on Musca_A. Alignment
* of partitions is defined in accordance with this constraint.
*/
#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET)
#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_2_OFFSET)
#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET \
+ FLASH_S_PARTITION_SIZE)
/*
* Boot partition structure if MCUBoot is used:
* 0x0_0000 Bootloader header
* 0x0_0400 Image area
* 0x1_FC00 Trailer
*/
/* IMAGE_CODE_SIZE is the space available for the software binary image.
* It is less than the FLASH_PARTITION_SIZE because we reserve space
* for the image header and trailer introduced by the bootloader.
*/
#define BL2_HEADER_SIZE (0x400)
#define BL2_TRAILER_SIZE (0x400)
#define IMAGE_S_CODE_SIZE \
(FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
#define IMAGE_NS_CODE_SIZE \
(FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE)
/*
* Since we enable/disable flash during s/ns code copy to code sram we cannot
* access bl2 code from flash, hence we need to copy the bl2 code to code sram
*/
/* Use QSPI Flash memory to store Code data */
#define CMSE_VENEER_REGION_SIZE (0x300)
/* Alias definitions for secure and non-secure areas*/
#define S_ROM_ALIAS(x) (S_SRAM_ALIAS_BASE + (x))
#define NS_ROM_ALIAS(x) (NS_SRAM_ALIAS_BASE + (x))
#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x))
#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x))
/* Secure regions */
#define S_IMAGE_PRIMARY_AREA_OFFSET \
(S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET))
#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE)
#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1)
#define S_DATA_START (S_RAM_ALIAS(0x0))
/* Reserve 96 KB of RAM to the SPE to meet worst case scenario
* requirements which are encountered in IPC mode and regression
* tests enabled. Leave the remaining 32 KB to the NSPE.
*/
#define S_DATA_SIZE ((TOTAL_RAM_SIZE / 4) * 3)
#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1)
/* CMSE Veneers region */
#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1)
/* Non-secure regions */
#define NS_IMAGE_PRIMARY_AREA_OFFSET \
(NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE)
#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET))
#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE - FLASH_AREA_BL2_SIZE)
#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1)
#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE))
#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE)
#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1)
/* NS partition information is used for MPC and SAU configuration */
#define NS_PARTITION_START \
(NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET))
#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE)
/* Secondary partition for new images in case of firmware upgrade */
#define SECONDARY_PARTITION_START \
(NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET))
#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \
FLASH_NS_PARTITION_SIZE)
/* Code SRAM area */
#define TOTAL_CODE_SRAM_SIZE (TOTAL_ROM_SIZE)
#define S_CODE_SRAM_ALIAS_BASE (0x10000000)
#define NS_CODE_SRAM_ALIAS_BASE (0x00000000)
#define BL2_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
#define S_CODE_SRAM_EXEC_BASE (S_CODE_SRAM_ALIAS_BASE)
#define S_CODE_SRAM_EXEC_LIMIT (S_CODE_SRAM_EXEC_BASE + \
(TOTAL_CODE_SRAM_SIZE / 2) - 1)
#define NS_CODE_SRAM_EXEC_BASE (NS_CODE_SRAM_ALIAS_BASE + \
(TOTAL_CODE_SRAM_SIZE / 2))
#define NS_CODE_SRAM_EXEC_LIMIT (NS_CODE_SRAM_EXEC_BASE + \
(TOTAL_CODE_SRAM_SIZE / 2) - 1)
/* Since we enable/disable flash during s/ns code copy to code sram we cannot
* access bl2 code from flash, hence we need to copy the bl2 code to code sram
*/
#define BL2_CODE_SRAM_ALIAS_BASE (S_SRAM_ALIAS_BASE)
#define BL2_CODE_SRAM_ALIAS(x) (BL2_CODE_SRAM_ALIAS_BASE + x)
#define BL2_CODE_SRAM_BASE (BL2_CODE_SRAM_ALIAS(FLASH_AREA_BL2_OFFSET))
/* Bootloader regions */
#define BL2_CODE_START (S_QSPI_ALIAS_BASE)
#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE)
#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1)
#define BL2_DATA_START (S_RAM_ALIAS(0x0))
#define BL2_DATA_SIZE (TOTAL_RAM_SIZE)
#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1)
/* Shared data area between bootloader and runtime firmware.
* Shared data area is allocated at the beginning of the RAM, it is overlapping
* with TF-M Secure code's MSP stack
*/
#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE
#define BOOT_TFM_SHARED_DATA_SIZE (0x400)
#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + \
BOOT_TFM_SHARED_DATA_SIZE - 1)
#endif /* __REGION_DEFS_H__ */

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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "mbed_error.h"
#include "pinmap.h"
#include "objects.h"
#include "musca_a1_scc_drv.h"
#if TARGET_MUSCA_A1_NS
const PinMap PinMap_UART_TX[] = {
{UART0_TX, UART_0, ALTERNATE_FUNC_1},
{UART1_TX, UART_1, PRIMARY_FUNC},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{UART0_RX, UART_0, ALTERNATE_FUNC_1},
{UART1_RX, UART_1, PRIMARY_FUNC},
{NC, NC, 0}
};
/**
* \brief Configures the GPIO pin and sets the alternate function
*
* \param[in] pin GPIO pin number \ref PinName
* \param[in] function Alternate function to set \ref PinFunction
*/
void pin_function(PinName pin, int function)
{
enum gpio_altfunc_t flags;
MBED_ASSERT(pin != NC);
/* The pin has to be a GPIO pin */
if (pin >= PA0 && pin <= PA15) {
switch (function) {
case PRIMARY_FUNC:
flags = GPIO_MAIN_FUNC;
break;
case ALTERNATE_FUNC_1:
flags = GPIO_ALTFUNC_1;
break;
case ALTERNATE_FUNC_2:
flags = GPIO_ALTFUNC_2;
break;
case ALTERNATE_FUNC_3:
flags = GPIO_ALTFUNC_3;
break;
default:
return;
}
#ifdef MUSCA_A1_SCC_DEV
musca_a1_scc_set_alt_func(&MUSCA_A1_SCC_DEV, flags, (1u<<pin));
#endif /* MUSCA_A1_SCC_DEV */
}
}
/**
* \brief Translates between different pin mode enums
*
* \param[in] mode Pin mode to translate \ref PinMode
*
* \return Translated pin mode \ref pinmode_select_t
*/
static enum pinmode_select_t translate_pinmode(PinMode mode)
{
switch (mode) {
case PullNone:
return PINMODE_NONE;
case PullDown:
return PINMODE_PULL_DOWN;
case PullUp:
return PINMODE_PULL_UP;
default:
return PINMODE_NONE;
}
}
/**
* \brief Sets pin mode for the given GPIO pin
*
* \param[in] pin GPIO pin number \ref PinName
* \param[in] mode Pin mode to set \ref PinMode
*/
void pin_mode(PinName pin, PinMode mode)
{
MBED_ASSERT(pin != NC);
#ifdef MUSCA_A1_SCC_DEV
musca_a1_scc_set_pinmode(&MUSCA_A1_SCC_DEV, (1u<<pin), translate_pinmode(mode));
#endif /* MUSCA_A1_SCC_DEV */
}
#else // TARGET_MUSCA_A1_NS
void pin_function(PinName pin, int function)
{
}
void pin_mode(PinName pin, PinMode mode)
{
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
/* Use memcpy */
#include <string.h>
#include "serial_api.h"
#include "pinmap.h"
#include "objects.h"
/* Use error(...) function */
#include "mbed_error.h"
#define STDIO_UART_NOT_INITED 0
#define STDIO_UART_INITED 1
#define UART_DEVICES_NUMBER 2
struct uart_irq_t {
uart_irq_handler handler;
uint32_t id;
};
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
/* Handlers registered */
static struct uart_irq_t uart_irq[UART_DEVICES_NUMBER];
/* Global variables needed for mbed */
int stdio_uart_inited = STDIO_UART_NOT_INITED;
serial_t stdio_uart;
#ifdef UART0_PL011_DEV
#ifndef uart0_tx_irq_handler
#error "uart0_tx_irq_handler should be defined, check device_cfg.h!"
#endif
void uart0_tx_irq_handler(void)
{
uart_pl011_clear_intr(&UART0_PL011_DEV, UART_PL011_TX_INTR_MASK);
if(uart_irq[UART_0].handler != 0) {
uart_irq[UART_0].handler(uart_irq[UART_0].id, TxIrq);
}
}
#ifndef uart0_rx_irq_handler
#error "uart0_rx_irq_handler should be defined, check device_cfg.h!"
#endif
void uart0_rx_irq_handler(void)
{
uart_pl011_clear_intr(&UART0_PL011_DEV, UART_PL011_RX_INTR_MASK);
if(uart_irq[UART_0].handler != 0) {
uart_irq[UART_0].handler(uart_irq[UART_0].id, RxIrq);
}
}
#ifndef uart0_rx_timeout_irq_handler
#error "uart0_rx_timeout_irq_handler should be defined, check device_cfg.h!"
#endif
void uart0_rx_timeout_irq_handler(void)
{
if(uart_irq[UART_0].handler != 0) {
uart_irq[UART_0].handler(uart_irq[UART_0].id, RxIrq);
}
}
#endif
#ifdef UART1_PL011_DEV
#ifndef uart1_tx_irq_handler
#error "uart1_tx_irq_handler should be defined, check device_cfg.h!"
#endif
void uart1_tx_irq_handler(void)
{
uart_pl011_clear_intr(&UART1_PL011_DEV, UART_PL011_TX_INTR_MASK);
if(uart_irq[UART_1].handler != 0) {
uart_irq[UART_1].handler(uart_irq[UART_1].id, TxIrq);
}
}
#ifndef uart1_rx_irq_handler
#error "uart1_rx_irq_handler should be defined, check device_cfg.h!"
#endif
void uart1_rx_irq_handler(void)
{
uart_pl011_clear_intr(&UART1_PL011_DEV, UART_PL011_RX_INTR_MASK);
if(uart_irq[UART_1].handler != 0) {
uart_irq[UART_1].handler(uart_irq[UART_1].id, RxIrq);
}
}
#ifndef uart1_rx_timeout_irq_handler
#error "uart1_rx_timeout_irq_handler should be defined, check device_cfg.h!"
#endif
void uart1_rx_timeout_irq_handler(void)
{
if(uart_irq[UART_1].handler != 0) {
uart_irq[UART_1].handler(uart_irq[UART_1].id, RxIrq);
}
}
#endif
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
/* Determine the UART to use */
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
if (uart == (UARTName)NC) {
error("Serial pinout mapping failed");
}
switch (uart) {
#ifdef UART0_PL011_DEV
case UART_0:
obj->uart_dev = &UART0_PL011_DEV;
obj->tx_irq = UART0_Tx_IRQn;
obj->rx_irq = UART0_Rx_IRQn;
obj->rx_timeout_irq = UART0_RxTimeout_IRQn;
break;
#endif
#ifdef UART1_PL011_DEV
case UART_1:
obj->uart_dev = &UART1_PL011_DEV;
obj->tx_irq = UART1_Tx_IRQn;
obj->rx_irq = UART1_Rx_IRQn;
obj->rx_timeout_irq = UART1_RxTimeout_IRQn;
break;
#endif
default:
error("serial_init: No uart selected");
}
obj->uart_index = uart;
/* Pinout the chosen uart */
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
uart_pl011_init(obj->uart_dev, SystemCoreClock);
uart_pl011_set_baudrate(obj->uart_dev,
MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE);
uart_pl011_enable(obj->uart_dev);
if (uart == STDIO_UART) {
stdio_uart_inited = STDIO_UART_INITED;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
uart_pl011_uninit(obj->uart_dev);
}
void serial_baud(serial_t *obj, int baudrate)
{
if(uart_pl011_set_baudrate(obj->uart_dev,baudrate) != UART_PL011_ERR_NONE) {
error("serial_baud: invalid baudrate");
}
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity,
int stop_bits)
{
enum uart_pl011_wlen_t uart_word_len = UART_PL011_WLEN_8;
enum uart_pl011_parity_t uart_parity = UART_PL011_PARITY_DISABLED;
enum uart_pl011_stopbit_t uart_stop_bits = UART_PL011_STOPBIT_1;
switch (data_bits) {
case 5:
uart_word_len = UART_PL011_WLEN_5;
break;
case 6:
uart_word_len = UART_PL011_WLEN_6;
break;
case 7:
uart_word_len = UART_PL011_WLEN_7;
break;
case 8:
uart_word_len = UART_PL011_WLEN_8;
break;
default:
error("serial_format: unexpected data bits");
}
switch (parity) {
case ParityNone:
uart_parity = UART_PL011_PARITY_DISABLED;
break;
case ParityOdd:
uart_parity = UART_PL011_PARITY_ODD;
break;
case ParityEven:
uart_parity = UART_PL011_PARITY_EVEN;
break;
case ParityForced1:
uart_parity = UART_PL011_PARITY_STICKY_ONE;
break;
case ParityForced0:
uart_parity = UART_PL011_PARITY_STICKY_ZERO;
break;
default:
error("serial_format: unexpected parity");
}
switch (stop_bits) {
case 1:
uart_stop_bits = UART_PL011_STOPBIT_1;
break;
case 2:
uart_stop_bits = UART_PL011_STOPBIT_2;
break;
default:
error("serial_format: unexpected stop bit");
}
(void)uart_pl011_set_format(obj->uart_dev,
uart_word_len, uart_parity, uart_stop_bits);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
uart_irq[obj->uart_index].handler = handler;
uart_irq[obj->uart_index].id = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
switch(irq) {
case RxIrq:
if (enable) {
NVIC_EnableIRQ(obj->rx_irq);
uart_pl011_enable_intr(obj->uart_dev, UART_PL011_RX_INTR_MASK);
NVIC_EnableIRQ(obj->rx_timeout_irq);
uart_pl011_enable_intr(obj->uart_dev, UART_PL011_RT_INTR_MASK);
} else {
uart_pl011_disable_intr(obj->uart_dev, UART_PL011_RX_INTR_MASK);
NVIC_DisableIRQ(obj->rx_irq);
uart_pl011_disable_intr(obj->uart_dev, UART_PL011_RT_INTR_MASK);
NVIC_DisableIRQ(obj->rx_timeout_irq);
}
break;
case TxIrq:
if (enable) {
NVIC_EnableIRQ(obj->tx_irq);
uart_pl011_enable_intr(obj->uart_dev, UART_PL011_TX_INTR_MASK);
} else {
uart_pl011_disable_intr(obj->uart_dev, UART_PL011_TX_INTR_MASK);
NVIC_DisableIRQ(obj->tx_irq);
}
break;
default : return;
}
}
int serial_readable(serial_t *obj)
{
return (int)uart_pl011_is_readable(obj->uart_dev);
}
int serial_writable(serial_t *obj)
{
return (int)uart_pl011_is_writable(obj->uart_dev);
}
int serial_getc(serial_t *obj)
{
uint8_t byte = 0;
while(!uart_pl011_is_readable(obj->uart_dev));
(void)uart_pl011_read(obj->uart_dev, &byte);
return byte;
}
void serial_putc(serial_t *obj, int c)
{
while(!uart_pl011_is_writable(obj->uart_dev));
uart_pl011_write(obj->uart_dev, (uint8_t)c);
}
void serial_clear(serial_t *obj)
{
uart_pl011_write(obj->uart_dev, (uint8_t)0);
}
void serial_pinout_tx(PinName tx)
{
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
uart_pl011_enable_break(obj->uart_dev);
}
void serial_break_clear(serial_t *obj)
{
uart_pl011_disable_break(obj->uart_dev);
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow,
PinName txflow)
{
error("serial_set_flow_control: Flow control is not supported in MUSCA");
}
const PinMap *serial_tx_pinmap()
{
return PinMap_UART_TX;
}
const PinMap *serial_rx_pinmap()
{
return PinMap_UART_RX;
}

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/* mbed Microcontroller Library
* Copyright (c) 2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device_cfg.h"
#include "sleep_api.h"
#include "timer_cmsdk_drv.h"
#if DEVICE_SLEEP
void hal_sleep(void)
{
__WFI();
}
/* Since there is no power management implemented in Musca-A, Deep Sleep could
* be supported only by additional software components, registering and managing
* the currently configured IPs. This would also mean a huge implementation
* overhead, that is not intended to be added. Therefore, Deep Sleep is almost
* identical to Sleep, representing a "Waiting For Interrupt" state, and
* disabling the Microsec ticker in addition.
*/
void hal_deepsleep(void)
{
#ifdef USEC_TIMER_DEV
timer_cmsdk_disable(&USEC_TIMER_DEV);
#endif
__WFI();
#ifdef USEC_TIMER_DEV
timer_cmsdk_enable(&USEC_TIMER_DEV);
#endif
}
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2017-2019 Arm Limited
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* Supports the High-resolution Ticker for mbed by implementing
* \ref us_ticker_api.h, using a CMSDK Timer \ref timer_cmsdk_dev_t.
*/
#include "device.h"
#include "mbed_critical.h"
#include "timer_cmsdk_drv.h"
#include "us_ticker_api.h"
static uint64_t total_ticks = 0;
/* Stores the last reload value, or the last tick value read when a read API
* call occurs from the upper layer, needed to keep total_ticks
* accumulated properly.
*/
static uint32_t previous_ticks = 0;
static void restart_timer(uint32_t new_reload)
{
timer_cmsdk_disable(&USEC_TIMER_DEV);
timer_cmsdk_set_reload_value(&USEC_TIMER_DEV,
new_reload);
timer_cmsdk_reset(&USEC_TIMER_DEV);
timer_cmsdk_clear_interrupt(&USEC_TIMER_DEV);
timer_cmsdk_enable_interrupt(&USEC_TIMER_DEV);
timer_cmsdk_enable(&USEC_TIMER_DEV);
}
static void update_ticker(void)
{
if (timer_cmsdk_is_interrupt_active(&USEC_TIMER_DEV)) {
total_ticks += previous_ticks;
previous_ticks = TIMER_CMSDK_MAX_RELOAD;
restart_timer(previous_ticks);
} else {
uint32_t tick = timer_cmsdk_get_current_value(&USEC_TIMER_DEV);
if (tick < previous_ticks) {
uint32_t delta = previous_ticks - tick;
total_ticks += delta;
previous_ticks = tick;
}
}
}
void us_ticker_init(void)
{
timer_cmsdk_init(&USEC_TIMER_DEV);
previous_ticks = TIMER_CMSDK_MAX_RELOAD;
NVIC_EnableIRQ(USEC_INTERVAL_IRQ);
restart_timer(previous_ticks);
}
void us_ticker_free(void)
{
timer_cmsdk_disable(&USEC_TIMER_DEV);
}
uint32_t us_ticker_read(void)
{
core_util_critical_section_enter();
update_ticker();
core_util_critical_section_exit();
return (uint32_t)(total_ticks >> USEC_REPORTED_SHIFT);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t reload = (timestamp - us_ticker_read()) << USEC_REPORTED_SHIFT;
previous_ticks = reload;
restart_timer(previous_ticks);
}
void us_ticker_disable_interrupt(void)
{
timer_cmsdk_disable_interrupt(&USEC_TIMER_DEV);
}
void us_ticker_clear_interrupt(void)
{
timer_cmsdk_clear_interrupt(&USEC_TIMER_DEV);
}
void us_ticker_fire_interrupt(void)
{
NVIC_SetPendingIRQ(USEC_INTERVAL_IRQ);
}
const ticker_info_t* us_ticker_get_info()
{
static const ticker_info_t info = {
USEC_REPORTED_FREQ_HZ,
USEC_REPORTED_BITS
};
return &info;
}
#ifndef usec_interval_irq_handler
#error "usec_interval_irq_handler should be defined, check device_cfg.h!"
#endif
void usec_interval_irq_handler(void)
{
update_ticker();
us_ticker_irq_handler();
}

54
targets/targets.json
View File

@ -4639,60 +4639,6 @@
"5004"
]
},
"ARM_MUSCA_A1": {
"inherits": [
"PSA_V8_M"
],
"default_toolchain": "ARMC6",
"features_add": [
"EXPERIMENTAL_API"
],
"forced_reset_timeout": 7,
"release_versions": [
"5"
],
"core": "Cortex-M33-NS",
"supported_toolchains": [
"ARMC6",
"GCC_ARM"
],
"device_has_add": [
"INTERRUPTIN",
"LPTICKER",
"SERIAL",
"SLEEP",
"USTICKER"
],
"macros_add": [
"__STARTUP_CLEAR_BSS",
"MBED_FAULT_HANDLER_DISABLED",
"CMSIS_NVIC_VIRTUAL",
"LPTICKER_DELAY_TICKS=1",
"MBED_MPU_CUSTOM"
],
"extra_labels_add": [
"ARM_SSG",
"MUSCA_A1",
"MUSCA_A1_NS"
],
"post_binary_hook": {
"function": "ArmMuscaA1Code.binary_hook"
},
"secure_image_filename": "tfm_s.bin",
"tfm_target_name": "MUSCA_A",
"tfm_bootloader_supported": true,
"tfm_default_toolchain": "ARMCLANG",
"tfm_supported_toolchains": [
"ARMCLANG",
"GNUARM"
],
"tfm_delivery_dir": "TARGET_ARM_SSG/TARGET_MUSCA_A1"
},
"ARM_MUSCA_A1_NS": {
"inherits": [
"ARM_MUSCA_A1"
]
},
"ARM_MUSCA_B1": {
"inherits": [
"PSA_V8_M"